Manufacturing method for semiconductor devices

Abstract

To improve the performance of semiconductor devices. [Solution] The semiconductor device manufacturing method includes a lead frame preparation step, a sealing step, a half-dicing step, a metal film formation step (plating step), and a piece-forming step. Each of the leads LD1 and LD2 of the lead frame LF prepared in the lead frame preparation step includes a portion LDP1 which is partially removed by a first blade in the half-dicing step, and a portion LDP2 which is not removed in the half-dicing step. In the piece-forming step, the tie bar LFtb is cut by inserting a second blade between the remaining portion LDP1 of lead LD1 and the remaining portion LDP1 of lead LD2.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device.

Background Art

[0002] JP 2014-007287 A (Patent Document 1) describes a semiconductor device in which a step surface is provided on the lower surface of a lead.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of Invention

Problems to be Solved by the Invention

[0004] As a package aspect of a semiconductor device, there is a package in which leads serving as external terminals are exposed from the lower surface of a sealing body. An example of such a package is a QFN (Quad Flat Non-leaded package) type. When mounting a package in which leads are exposed from the lower surface of a sealing body onto a mounting substrate, the package is mounted by bonding a bonding material such as solder to the exposed surfaces of the leads. In addition, from the viewpoint of improving the visibility of solder in inspection after the package is mounted, as in the above Patent Document 1, there is a method in which a stepped portion is provided at the tip of a lead, thereby forming a solder fillet at the tip of the lead.

[0005] However, as the size of semiconductor devices is reduced, for example, and the interval between two adjacent leads becomes smaller, there arises a concern that these two leads may be short-circuited to each other via solder. For example, when each lead is cut with a dicing blade that is a rotary blade, metal burrs are formed on the cut surface by the blade (particularly, the portion located between two adjacent leads). If the length of the metal burr is large, there is a possibility that two adjacent leads are short-circuited via this metal burr.

[0006] Therefore, in order to improve the performance of semiconductor devices, a technology is needed that can prevent short circuits between adjacent leads.

[0007] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0008] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: (a) preparing a lead frame comprising: a first lead provided in a first device formation section; a second lead provided in a second device formation section located adjacent to the first device formation section; and tie bars provided in a dicing section between the first device formation section and the second device formation section, and connected to the first lead and the second lead respectively; (b) After step (a) above, a step of mounting the first semiconductor chip in the first device formation section and mounting the second semiconductor chip in the second device formation section, (c) After step (b) above, the first lead and the first semiconductor chip are electrically connected to each other via a first conductive member, and the second lead and the second semiconductor chip are electrically connected to each other via a second conductive member. (d) After step (c) above, a step of forming a encapsulant that encapsulates the first lead, the second lead, the tie bar, the first semiconductor chip, the second semiconductor chip, the first conductive member, and the second conductive member together, such that the lower surfaces of the first lead and the second lead are exposed. (e) After step (d) above, a step of removing a portion of the first lead and the second lead using a first blade having a first width greater than the width of the tie bar, (f) After step (e) above, a step of forming a metal film on the exposed surface of the lead frame that is exposed from the seal by a plating method, (g) After step (f) above, a second blade having a second width smaller than the first width is used to remove the tie bar and the sealant, thereby separating the first device forming section and the second device forming section from each other. The tie bar of the lead frame prepared in step (a) above has a lead connecting portion extending in a first direction from the first lead toward the second lead in a plan view, and a support portion extending in a second direction intersecting the first direction in a plan view. In step (a) above, with the upper surfaces of the first lead and the second lead as reference planes, the height difference between the lower surface of the tie bar and the reference plane is smaller than the height difference between the lower surfaces of the first lead and the second lead and the reference plane. Each of the first lead and the second lead includes a first portion which is partially removed by the first blade in step (e) above, and a second portion which is not removed in step (e). In step (g) above, the tie bar is cut by inserting the second blade between the remaining portion of the first portion of the first lead and the remaining portion of the first portion of the second lead. [Effects of the Invention]

[0009] According to the above embodiment, the performance of the semiconductor device can be improved. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a top view of a semiconductor device according to one embodiment. [Figure 2] Figure 2 is a bottom view of the semiconductor device shown in Figure 1. [Figure 3] Figure 3 is a cross-sectional view along line AA in Figure 1. [Figure 4] Figure 4 is a perspective plan view showing the internal structure of the semiconductor device with the encapsulant shown in Figure 1 removed. [Figure 5] Figure 5 is an enlarged cross-sectional view along line BB in Figure 2. [Figure 6] Figure 6 is an enlarged cross-sectional view along the CC line in Figure 4. [Figure 7] FIG. 7 is a flowchart showing an example of the manufacturing process of the semiconductor device shown in FIG. 1 to FIG. 5. [Figure 8] FIG. 8 is a plan view of the lead frame prepared in the lead frame preparation step shown in FIG. 7. [Figure 9] FIG. 9 is an enlarged bottom view of two of the plurality of device forming portions shown in FIG. 8. [Figure 10] FIG. 10 is an enlarged bottom view of part D in FIG. 9. [Figure 11] FIG. 11 is an enlarged cross-sectional view taken along line E-E in FIG. 10. [Figure 12] FIG. 12 is an enlarged top view showing a state in which a semiconductor chip is mounted on each of the plurality of device forming portions shown in FIG. 9. [Figure 13] FIG. 13 is an enlarged top view showing a state in which the semiconductor chip and the leads shown in FIG. 12 are electrically connected via wires. [Figure 14] FIG. 14 is a plan view showing a sealing body formed in the sealing step shown in FIG. 7. [Figure 15] FIG. 15 is an enlarged cross-sectional view showing a state in which the lead frame is arranged in the cavity of a molding die in the enlarged cross-section taken along line F-F in FIG. 14. [Figure 16] FIG. 16 is an enlarged bottom view showing a state in which the sealing body covering the tie bar is removed after the half dicing step shown in FIG. 7 is completed. [Figure 17] FIG. 17 is an enlarged cross-sectional view showing a state in the middle of cutting with a blade in the cross-section taken along line G-G in FIG. 16. [Figure 18] FIG. 18 is an explanatory view schematically showing an example of the metal film forming step shown in FIG. 7. [Figure 19] FIG. 19 is an enlarged bottom view showing a state where two adjacent device forming portions are separated after the singulation step shown in FIG. 7 is completed. [Figure 20] FIG. 20 is an enlarged cross-sectional view showing the singulation step shown in FIG. 7. [Figure 21] FIG. 21 is an enlarged bottom view showing a modification of FIG. 10. [Figure 22] Figure 22 is an enlarged bottom view showing the leads of a semiconductor device manufactured using the lead frame shown in Figure 21. [Figure 23] Figure 23 is an enlarged bottom view showing another modification of Figure 10. [Modes for carrying out the invention]

[0011] (Explanation of format, basic terminology, and usage in this application) In this application, the descriptions of the embodiments are divided into multiple sections for convenience. These are not independent of each other, but rather one is a detail of the other, or one is a variation of the other. In principle, similar parts will be omitted from repeated explanations. Furthermore, each component in the embodiments is not essential unless it is explicitly indicated as an essential component, its number is theoretically limited, or it is clearly essential from the context.

[0012] Similarly, in descriptions of the implementation, etc., even if it says "X consisting of A" regarding materials, composition, etc., unless it is clearly limited or clearly limited from the context, elements other than A are not excluded. For example, in terms of components, it means "X containing A as the main component." For example, even if it says "silicon component," it is not limited to pure silicon, but also includes components containing SiGe (silicon-germanium) alloys, other multi-component alloys with silicon as the main component, and other additives. Also, even if it says gold plating, Cu layer, nickel plating, etc., unless it is specifically stated otherwise, it is meant to include not only pure materials but also components with gold, Cu, nickel, etc. as the main components, respectively.

[0013] Furthermore, when specific numbers or quantities are mentioned, unless explicitly limited or clearly limited by the context, those numbers are listed as examples only.

[0014] Furthermore, in each figure of the embodiment, identical or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions are generally not repeated.

[0015] Furthermore, in attached drawings, hatching or similar markings may be omitted even in cross-sections if it would make the drawing unnecessarily complicated or if the distinction from voids is clear. In connection with this, background contour lines may be omitted even for holes that are closed in plan view, if it is clear from the explanation, etc. Moreover, hatching or dot patterns may be added even to areas that are not voids or to indicate the boundaries of an area, even if they are not cross-sections.

[0016] <Semiconductor device> Figure 1 is a top view of the semiconductor device of this embodiment, Figure 2 is a bottom view of the semiconductor device shown in Figure 1, and Figure 3 is a cross-sectional view along line AA in Figure 1. Figure 4 is a perspective plan view showing the internal structure of the semiconductor device with the encapsulant shown in Figure 1 removed. Figure 5 is an enlarged cross-sectional view along line BB in Figure 2. Figure 6 is an enlarged cross-sectional view along line CC in Figure 4.

[0017] Figures 1 through 5 show either the X direction (see Figures 1, 2, 3, and 4), the Y direction (see Figures 1, 2, 4, and 5), or the Z direction (see Figures 3 and 5). The Y direction is the edge that intersects the X direction, and in the following explanation, the X and Y directions are orthogonal to each other. The Z direction is the direction orthogonal to both the X and Y directions. In other words, the Z direction is the normal direction (or perpendicular direction) to the XY plane, which contains the X and Y directions. In the following explanation, "thickness" generally refers to the length in the Z direction. Also, in the following explanation, "plan view" generally refers to a plan view of the XY plane.

[0018] The semiconductor device PKG1 of this embodiment comprises a die pad DP (see Figures 3 and 4) and a semiconductor chip CP (see Figures 3 and 4) mounted on the die pad DP via a die bond material DB (see Figures 3 and 4). The semiconductor device PKG1 also has a plurality of leads LD arranged around the semiconductor chip CP (die pad DP). The semiconductor device PKG1 has a plurality of wires (conductive members) BW (see Figures 3 and 4) that electrically connect the plurality of pads PD (see Figures 3 and 4) of the semiconductor chip CP and the plurality of leads LD, respectively. A plurality of suspension leads TL (see Figure 4) are also connected to the die pad DP. The semiconductor device PKG1 also comprises a encapsulant (resin body) MR that encapsulates the semiconductor chip CP, the plurality of wires BW, and a portion of the plurality of leads LD.

[0019] The planar shape of the encapsulant (resin body) MR shown in Figure 1 is a rectangle. The encapsulant MR has an upper surface MRt, a lower surface (back surface, mounting surface) MRb (see Figure 2) located opposite the upper surface MRt, and side surfaces MRs located between the upper surface MRt and the lower surface MRb. In the example shown in Figure 3, the side surfaces MRs intersect with the upper surface MRt and the lower surface MRb. More specifically, in the example shown in Figure 3, the side surfaces MRs are perpendicular to the upper surface MRt and the lower surface MRb.

[0020] Furthermore, as shown in Figure 2, in the semiconductor device PKG1, multiple lead LDs are arranged along the side MRs of the encapsulant MR. The multiple lead LDs are made of a metallic material, and in this embodiment, they are made of, for example, copper (Cu) or a copper alloy.

[0021] As shown in Figure 4, multiple lead LDs are arranged around the semiconductor chip CP (in other words, around the die pad DP). Each of the multiple lead LDs is positioned away from the die pad DP. Furthermore, each of the multiple lead LDs is positioned away from each other.

[0022] Multiple pads PD formed on the surface CPt of a semiconductor chip CP are electrically connected to multiple leads LD via multiple wires BW. The wires BW are made of, for example, gold (Au) or copper (Cu). A portion of the wire BW (e.g., one end) is joined to the pad PD, and the other portion (e.g., the other end) is joined to the upper surface LDt of the wire joint LDm of the lead LD. Although not shown in the diagram, a plating film may be formed on the surface (upper surface LDt) of the wire joint LDm of the lead LD. The plating film is made of, for example, silver (Ag) or gold (Au). By forming a plating film made of silver or gold on the surface (upper surface LDt) of the wire joint LDm of the lead LD, the bonding strength with the wires BW made of gold or copper can be improved.

[0023] As shown in Figure 2, a portion of each lead LD (the lower LDb) is exposed from the lower surface MRb of the encapsulant MR. A metal film SD is formed on the exposed portion of the lead LD from the encapsulant MR, and the lower LDb is covered by the metal film SD. The metal film SD is a plating film formed, for example, by a plating method. The metal film SD is made of, for example, solder material and functions as a bonding material when joining the lead LD to the terminals on the mounting substrate side, as described later.

[0024] The metal film SD (solder material) of this embodiment consists of so-called lead-free solder, which is substantially free of lead (Pb). The metal film SD consists of, for example, only tin (Sn), tin-bismuth (Sn-Bi), or tin-copper-silver (Sn-Cu-Ag). Here, lead-free solder means that the lead (Pb) content is 0.1 wt% or less. The lead content is defined as a standard in the RoHS (Restriction of Hazardous Materials) directive. Hereafter in this embodiment, when describing solder material or solder components, it refers to lead-free solder unless otherwise specified.

[0025] Each of the multiple leads LD has a wire joint (part) LDm as shown in Figure 4, and a stepped portion (part, end) LDe (see Figure 2) located further from the die pad DP than the wire joint LDm. The wire joint LDm is the planned area for joining the wire BW. The wire BW is joined to one of the positions on the upper surface LDt of the wire joint LDm.

[0026] As shown in Figure 3, the wire joint LDm has an upper surface LDt and a lower surface LDb located opposite the upper surface LDt. The wire BW is connected to the upper surface LDt of the wire joint LDm. The wire joint LDm includes a side surface LDs3, which is the leading edge surface of the lead LD on the die pad DP side.

[0027] The stepped portion LDe has an upper surface LDt and a lower surface (stepped surface) LDb2 located opposite the upper surface LDt. The distance from the upper surface LDt to the lower surface LDb2 is shorter than the distance from the upper surface LDt to the lower surface LDb. In other words, if the upper surface LDt is taken as the reference surface, the height difference between the upper surface LDt and the lower surface LDb2 is smaller than the height difference between the upper surface LDt and the lower surface LDb. The thickness of the stepped portion LDe is thinner than the thickness of the wire joint portion LDm. For example, the thickness of the wire joint portion LDm shown in Figure 3 (the thickness of the main body portion LDZ shown in Figure 6, which will be described in more detail later) is about 150 to 200 μm. On the other hand, the thickness of the stepped portion LDe is about 75 to 100 μm.

[0028] The presence of a stepped portion LDe on each of the multiple lead LDs at the periphery of the lower surface (mounting surface) of the semiconductor device PKG1 improves visibility during post-mounting inspection. Specifically, when the semiconductor device PKG1 is mounted on a mounting board (not shown), each of the multiple lead LDs is connected to a terminal on the mounting board via solder.

[0029] One way to check the connection status of each of the multiple lead LDs is to check the shape of the solder fillet connecting the lead LD to the terminal on the mounting board. A solder fillet is a slanted surface formed on the periphery of the solder. Solder fillets are formed when the solder wets and spreads on the terminal on the mounting board. Therefore, if an abnormality such as a solder melting failure occurs during the process of mounting the semiconductor device PKG1, the shape of the solder fillet will become abnormal.

[0030] Furthermore, solder fillets are formed on the periphery of the solder. Therefore, even after the semiconductor device PKG1 is mounted on the substrate, the shape of the solder fillets can be easily confirmed by viewing the semiconductor device PKG1 from above.

[0031] Therefore, the method of checking the shape of the solder fillet during visual inspection after mounting the semiconductor device PKG1 to a mounting substrate (not shown) is effective. Furthermore, in order to form a solder fillet that is easily visible during visual inspection, it is preferable that the height difference between the lower surface LDb and the lower surface LDb2 shown in Figure 3 is large. For example, in the example shown in Figure 3, the thickness of the stepped portion LDe is less than half the thickness of the main body portion LDZ of the lead LD.

[0032] The wire connection portion LDm of the lead LD has a side (lead side) LDs3 that faces the die pad DP (more specifically, the side DPs of the die pad DP). In other words, the main body LDZ of the lead LD has a side LDs3 that faces the die pad DP. The side LDs3 is connected to the upper surface LDt and the lower surface LDb.

[0033] The lower surface LDb of the wire joint LDm is connected to the side (lead side) LDs2, which is located opposite the side (lead side) LDs3. In other words, the lower surface LDb of the main body LDZ is connected to the side (lead side) LDs2, which is located opposite the side LDs3. The side LDs2 is connected to the lower surface LDb2 of the stepped portion LDe.

[0034] The stepped portion LDe has a side surface (lead side surface) LDs1 located at the position furthest from the wire joint portion LDm. Of the multiple lead side surfaces that each of the multiple lead LDs has, side surface LDs1 is located at the position furthest from the die pad DP. Side surface LDs1 is connected to the upper surface LDt and the lower surface LDb2. As will be described in detail later, the semiconductor device PKG1 is a so-called MAP (Mold Allay Package) type semiconductor device. In the individualization process described later, the lead LDs are cut together with the encapsulant MR in a MAP type semiconductor device. For this reason, as shown in Figure 3, side surface LDs1 is located on the extension of the side surface MRs of the encapsulant MR. In other words, side surface MRs and side surface LDs1 are located in the same plane. To put it another way, in the Z direction, the position of side surface LDs1 and the position of side surface MRs coincide. This state is called "side surface LDs1 and side surface MRs being flush."

[0035] As shown in Figure 5, a metal burr LDBL is connected to the stepped portion LDe of the lead LD. The metal burr LDBL is cutting debris formed when the stepped portion LDe is formed using a blade (dicing blade) in the half-dicing process described later. The metal burr LDBL is formed to extend along the direction of rotation of the blade.

[0036] Incidentally, with the increasing demand for higher functionality in semiconductor devices, the number of lead LDs (lead diodes) is on the rise. On the other hand, it is necessary to suppress the increase in the mounting area of ​​semiconductor devices. As a result, it is necessary to reduce the arrangement pitch (center-to-center distance) of adjacent lead LDs.

[0037] When the spacing between adjacent lead LDs becomes small, the handling of metal burrs (LDBLs) becomes crucial from the perspective of improving product reliability. For example, even when the spacing between adjacent lead LDs is small, it is necessary to prevent short circuits between adjacent lead LDs via metal burrs (LDBLs).

[0038] From the viewpoint of preventing adjacent lead LDs from short-circuiting via metal burrs LDBL, it is preferable that the width of the multiple lead LDs in the alignment direction be narrow. If the width of the multiple lead LDs in the alignment direction is narrow, the spacing between the lead LDs can be increased. As a result, even if metal burrs LDBL are formed, short-circuiting of adjacent lead LDs can be prevented.

[0039] However, if the width of the lead LD is extremely narrow, the following problems arise in the wire joining process for joining the wire BW shown in Figure 3. Specifically, due to the positional accuracy of the wire joining, the difficulty of wire joining increases when the width of the area where the wires are to be joined becomes narrow. Therefore, from the viewpoint of improving the connection reliability of the wire BW, the area where the wires BW are to be joined needs to have a certain width.

[0040] As shown in Figure 6, the width WLDt of the upper surface LDt of the wire joint LDm is greater than the width WLDb of the lower surface LDb. Also, the width WLDb of the lower surface LDb of the wire joint LDm shown in Figure 6 is equal to the width WLDb2 of the lower surface LDb2 of the stepped portion LDe shown in Figure 5. Therefore, the width WLDt of the upper surface LDt of the wire joint LDm shown in Figure 6 is greater than the width WLDb2 of the lower surface LDb2 of the stepped portion LDe shown in Figure 5.

[0041] By increasing the width WLDt of the upper surface LDt of the wire joint LDm, the wire BW can be reliably joined to the upper surface LDt of the wire joint LDm during the wire joining process.

[0042] On the other hand, since the width WLDb2 in the Y direction of the lower surface LDb2 of the stepped portion LDe shown in Figure 5 is narrow, the distance between adjacent lead LDs can be increased. Therefore, even if the metal burr LDBL shown in Figure 5 is formed, short circuits between adjacent lead LDs can be suppressed.

[0043] Regarding short circuits caused by metal burrs (LDBL), in addition to the above countermeasures, there is also a measure to shorten the length of the metal burr LDBL in the Y direction. The latter countermeasure will be described later in the section explaining the manufacturing method of semiconductor devices.

[0044] The wire joint LDm shown in Figure 6 includes a main body LDZ and a thin-walled portion (half-etched portion) LFhf, which is thinner than the main body LDZ. In the example shown in Figure 6, the main body LDZ of the wire joint LDm is positioned between two spaced-apart thin-walled portions LFhf. As shown in Figure 3, the main body LDZ is the portion of the lead LD other than the stepped portion LDe. The main body LDZ has a portion included in the wire joint LDm and a portion positioned between the wire joint LDm and the stepped portion LDe.

[0045] The thickness of the thin-walled section LFhf is thinner than the thickness of the main body LDZ. For example, the thickness of the main body LDZ shown in Figure 6 is approximately 150 to 200 μm. On the other hand, the thickness of the thin-walled section LFhf is approximately 75 to 100 μm.

[0046] As will be explained in more detail later, the stepped portion LDe shown in Figure 3 is obtained by further machining the lower surface of the thin-walled portion of the lead frame, which will be described later. Therefore, the thickness of the stepped portion LDe is thinner than the thickness of the thin-walled portion LFhf shown in Figure 6. In other words, the length from the upper surface LDt to the lower surface LDb2 shown in Figure 3 is shorter than the length from the upper surface LDt to the lower surface LDb3 shown in Figure 6.

[0047] The thin-walled portion LFhf is formed by half-etching from the underside of the lead frame. Therefore, if the upper surface LDt of the lead LD is used as the reference plane, the height difference between the lower surface LDb3 and the upper surface LDt of the thin-walled portion LFhf of the wire joint LDm is smaller than the height difference between the lower surface LDb and the upper surface LDt of the main body LDZ of the wire joint LDm.

[0048] Furthermore, as shown in Figure 2, the lower surface DPb of the die pad (chip mounting portion, tab) DP is exposed from the sealant MR on the lower surface MRb of the sealant MR. The die pad DP is made of a metal material with a higher thermal conductivity than the sealant MR, and in this embodiment, it is made of, for example, copper (Cu) or a copper alloy. In the examples shown in Figures 2 and 3, a metal film SD that functions as a bonding material during mounting is formed on the lower surface DPb of the die pad DP and covers the lower surface of the substrate. As described above, the metal film SD is a plated film (solder film) formed, for example, by a plating method.

[0049] As shown in Figures 2 and 4, the top surface (chip mounting surface) DPt of the die pad DP has a planar shape consisting of a quadrilateral. In the example shown in Figure 4, the outer size (planar size) of the die pad DP is larger than the outer size (planar size of the back surface CPb) of the semiconductor chip CP. By mounting the semiconductor chip CP on a die pad DP with an area larger than its outer size, and exposing the bottom surface DPb of the die pad DP from the encapsulant MR, heat dissipation can be improved.

[0050] Furthermore, as shown in Figures 3 and 4, a semiconductor chip CP is mounted on the die pad DP. The semiconductor chip CP is mounted in the center (including the center region) of the die pad DP. As shown in Figure 3, the semiconductor chip CP is mounted on the die pad DP via a die bond material (adhesive) DB with its back surface CPb facing the top surface DPt of the die pad DP. In other words, it is mounted using a so-called face-up mounting method, where the opposite side (back surface CPb) of the surface (main surface) CPt, where multiple pads PD are formed, and the chip mounting surface (top surface DPt) face each other. The die bond material DB is an adhesive used when bonding the semiconductor chip CP. In this embodiment, the die bond material DB is, for example, an epoxy-based thermosetting resin containing metal particles such as silver (Ag). However, solder can be exemplified as a modified example of the die bond material DB.

[0051] As shown in Figure 4, the planar shape of the semiconductor chip CP mounted on the die pad DP is a rectangle. Also, as shown in Figure 3, the semiconductor chip CP has a surface (main surface, top surface) CPt, a back surface (main surface, bottom surface) CPb located opposite the surface CPt, and side surfaces CPs located between the surface CPt and the back surface CPb.

[0052] As shown in Figures 3 and 4, multiple pads (bonding pads) PD are arranged on the surface CPt of the semiconductor chip CP. In the examples shown in Figures 3 and 4, the multiple pads PD are arranged along each edge of the surface CPt. Although not shown, multiple semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip CP (more specifically, the semiconductor element formation region provided on the upper surface of the substrate (semiconductor substrate) of the semiconductor chip CP). The multiple pads PD are electrically connected to these semiconductor elements via wiring (not shown) formed on a wiring layer located inside the semiconductor chip CP (more specifically, between the surface CPt and the semiconductor element formation region, not shown).

[0053] The semiconductor chip CP (more specifically, the substrate of the semiconductor chip CP) is made of, for example, silicon (Si). Furthermore, an insulating film is formed on the surface CPt, covering the substrate and wiring of the semiconductor chip CP. The surfaces of the multiple pads PD are exposed from this insulating film through openings formed in the insulating film. The pads PD are made of metal, and in this embodiment, they consist of, for example, aluminum (Al) or an alloy layer mainly composed of aluminum (Al).

[0054] As shown in Figure 4, multiple suspension leads TL are connected to the die pad DP. Each of the multiple suspension leads TL has one end connected to a corner of the die pad DP, which forms a rectangle in plan view. The other end of each of the multiple suspension leads TL extends toward the corner of the sealant MR. By extending the suspension leads TL toward the corner of the sealant MR, the arrangement of multiple leads LD arranged along each side (each main side) of the sealant MR can be done without obstructing it. In this case, the number of terminals (e.g., the number of leads LD) of the semiconductor device PKG1 can be increased. In addition, the suspension leads TL are half-etched from the bottom side. In this embodiment, the top, side, and bottom surfaces of the suspension leads TL are each sealed by the sealant MR. Therefore, as shown in Figure 2, the suspension leads TL (see Figure 4) are not exposed from the sealant MR on the bottom surface MRb of the sealant MR.

[0055] <Manufacturing method for semiconductor devices> Next, a method for manufacturing the semiconductor device shown in Figures 1 to 5 will be described. Figure 7 is a flowchart showing an example of the manufacturing process for the semiconductor device shown in Figures 1 to 5. The method for manufacturing the semiconductor device in this embodiment shown in Figure 7 includes a lead frame preparation step, a semiconductor chip mounting step, a wire bonding step, a encapsulation step, a half-dicing step, a metal film formation step, and a piece formation step.

[0056] <Lead frame preparation process> First, in the lead frame preparation process shown in Figure 7, the lead frame LF shown in Figures 8 and 9 is prepared. Figure 8 is a plan view of the lead frame prepared in the lead frame preparation process shown in Figure 7. Figure 9 is an enlarged bottom view of two of the multiple device forming sections shown in Figure 8. Figure 10 is an enlarged bottom view of section D in Figure 9. Figure 11 is an enlarged cross-sectional view along the EE line in Figure 10.

[0057] Figures 9 and 10 are plan views, but the thin-walled section LFhf is shown with hatching to clearly indicate the area where the plate thickness is reduced. In addition, in Figures 10 and 11, a dotted line is used to clearly indicate the boundary between section LDP1 and section LDP2. However, the dotted line shown in Figures 10 and 11 is a hypothetical line, and it is not necessary for the dotted line shown in Figures 10 and 11 to be visible in the lead frame LF prepared in this process.

[0058] As shown in Figure 8, the lead frame LF prepared in this process includes a plurality of device forming sections LFd connected to the frame section LFf. The lead frame LF also includes a dicing section LFc provided between adjacent device forming sections LFd.

[0059] The lead frame LF is made of, for example, copper (Cu) or a copper alloy. Each of the multiple device forming sections LFd is connected to the frame section LFf. The frame section LFf has the function of supporting each component formed within the device forming section LFd until the individualization process shown in Figure 7.

[0060] Each of the multiple device formation sections LFd corresponds to one semiconductor device package 1 shown in Figure 1. Each of the multiple device formation sections LFd has a die pad DP and multiple leads LD arranged spaced apart from the die pad DP. The lead frame LF is a so-called multi-cavity substrate in which multiple device formation sections LFd are arranged in a matrix. By using a lead frame LF equipped with multiple device formation sections LFd in this way, multiple semiconductor device packages 1 (see Figure 1) can be manufactured in a single batch, thereby improving manufacturing efficiency.

[0061] Furthermore, the dicing section LFc is the area that will be cut by the blade in the individualization process shown in Figure 7. Multiple dicing sections LFc include multiple dicing sections LFcX extending in the X direction and multiple dicing sections LFcY extending in the Y direction.

[0062] As shown in Figure 9, the dicing section LFc is formed to surround the device formation section LFd. Furthermore, tie bars LFtb are positioned within the dicing section LFc to surround the device formation section LFd. The tie bars LFtb are integrally formed with multiple lead LDs and the frame section (frame body) LFf shown in Figure 8.

[0063] Furthermore, when distinguishing between the two device formation sections LFd shown in Figure 9, they can be distinguished as device formation section LFd1 and device formation section LFd2. For example, the embodiment shown in Figure 9 can be expressed as follows: The lead frame LF has a device formation section LFd1 and a device formation section LFd2 which is located next to the device formation section LFd1 in the X direction. The lead frame LF also has a dicing section LFcY which is located between the device formation section LFd1 and the device formation section LFd2 and extends in the Y direction.

[0064] As shown in Figure 10, the device formation section LFd1 has a lead LD1. The device formation section LFd2 has a lead LD2. Each of the lead LD1 and lead LD2 includes a portion LDP1, which is removed from the lower side during the half-dicing process shown in Figure 7, and a portion LDP2, which is not removed during the hard-dicing process.

[0065] The remaining portion of the partial LDP1 that was not removed in the half-dicing process constitutes at least a part of the stepped portion LDe, as explained with reference to Figure 3. Partial LDP2, shown in Figure 10, includes the wire joint portion LDm. Partial LDP2 also includes the portion between partial LDP1 and the wire joint portion LDm.

[0066] As shown in Figure 10, the tie bar LFtb of the lead frame LF prepared in this process is connected to lead LD1 and lead LD2, respectively. The tie bar LFtb has a lead connection part TBC and a support part TBG. In the enlarged plane shown in Figure 10, the lead connection part TBC extends in the X direction from lead LD1 to lead LD2. The support part TBG extends in the Y direction, intersecting the X direction. One end of the lead connection part TBC is connected to lead LD1 (or lead LD2), and the other end is connected to the support part TBG.

[0067] Furthermore, a portion of the lead frame LF is pre-processed to reduce its thickness. As shown with hatching in Figure 9, the lead frame LF has a thin-walled portion (half-etched portion) LFhf that is thinner than the main body portion LDZ of the lead LD. In this embodiment, the thin-walled portion LFhf is formed by a half-etching process, that is, by etching the lead LD from the lower surface LDb side in the thickness direction up to a certain point.

[0068] The thin-walled section LFhf includes the tie bar LFtb and a portion of the wire joint LDm (the part other than the main body LDZ). Since the tie bar LFtb has been pre-etched, the structure shown in Figure 11 is obtained. That is, in the Z direction, the lower surface TBb of the tie bar LFtb and the lower surface LDb of the lead LD are at different positions from each other. Specifically, using the upper surfaces LDt of lead LD1 and LDt of lead LD2 as reference planes, the height difference between the lower surface TBb and the upper surface LDt of the tie bar LFtb is smaller than the height difference between the lower surface LDb and the upper surface LDt of lead LD1 and lead LD2, respectively. Note that the upper surface LDt of lead LD1 and the upper surface LDt of lead LD2 are at the same height from each other in the Z direction. Also, the lower surface LDb of lead LD1 and the lower surface LDb of lead LD2 are at the same height from each other in the Z direction.

[0069] As in this embodiment, when the tie bar LFtb is pre-etched, the amount of metal to be cut in the half-dicing process shown in Figure 7 can be reduced. The metal burr LDBL, as explained using Figure 5, extends in proportion to the amount of metal that is cut. Therefore, in this embodiment, since the amount of metal that is cut in the half-dicing process can be reduced, the length of the metal burr LDBL in the Y direction shown in Figure 5 can be shortened. As a result, it is possible to suppress short circuits between adjacent leads LD via the metal burr LDBL.

[0070] In half-etching, the untreated areas of the lead frame LF are covered with a mask, and an etching solution (or etching gas) is brought into contact with the treatment area of ​​the lead frame LF. This selectively removes a portion of the lead frame LF, forming a thin-walled section LFhf. Therefore, even when multiple thin-walled sections LFhf are to be formed, the etching process can be performed in a single operation.

[0071] Incidentally, if a half-etching process is performed in advance, a method can be considered in which the half-etching process forms the side LDs2 connected to the stepped portion LDe shown in Figure 3. In this case, the amount of metal cut during the half-dicing process shown in Figure 7 can be further reduced. However, from the following viewpoint, it is preferable that the side LDs2 be formed by the half-dicing process shown in Figure 7.

[0072] As already explained, checking for solder fillets is an effective method for visual inspection after mounting the semiconductor device PKG1, described using Figures 1 to 6, onto a mounting substrate (not shown). For easily visible solder fillets to be formed during visual inspection, it is important that the solder is wet and spread across the side LDs2 shown in Figure 3.

[0073] In the sealing process shown in Figure 6, the thin-walled portion LFhf (see Figure 9) of the lead frame LF is sealed with a sealant. In the case of the method in which the side LDs2 shown in Figure 3 are formed by half-etching, the side LDs2 are also sealed. In this case, it is necessary to remove a portion of the sealant that seals the side LDs2.

[0074] One possible method for removing a portion of the encapsulant is to irradiate it with a laser. However, from the viewpoint of improving manufacturing efficiency, it is preferable to perform cutting using a blade as a half-dicing process, as will be described later.

[0075] However, selective removal of only the sealant is difficult in cutting processes using a blade. Therefore, from the viewpoint of exposing the side LDs2 shown in Figure 3 from the sealant MR, it is preferable to form the side LDs2 shown in Figure 3 by cutting the portion LDP1 of the lead LD shown in Figure 11.

[0076] <Equipped with semiconductor chip> In the semiconductor chip mounting process shown in Figure 7, the semiconductor chip CP is mounted on the die pad DP via a die bond material DB, as shown in Figure 12. Figure 12 is an enlarged top view showing the state in which semiconductor chips are mounted on each of the multiple device formation sections shown in Figure 9. The semiconductor chip CP is mounted on the die pad DP of each of the multiple device formation sections LFd shown in Figure 12. In other words, in this process, the semiconductor chip CP1 is mounted on the device formation section LFd1, and the semiconductor chip CP is mounted on the device formation section LFd2.

[0077] In this process, as shown in Figure 3 which has already been explained, the semiconductor chip CP is mounted on the die pad DP with its back surface CPb and its top surface DPt facing each other.

[0078] In this process, for example, a semiconductor chip CP is mounted via a die bond material DB, which is an epoxy-based thermosetting resin. The die bond material DB is a fluid paste material before curing (thermal curing). When using a paste material as the die bond material DB in this way, first, the die bond material DB is applied to the die pad DP, and then the back surface CPb of the semiconductor chip CP is bonded to the top surface DPt of the die pad DP. After bonding, the die bond material DB is cured (for example, by heat treatment), and as shown in Figure 3, the semiconductor chip CP is fixed onto the die pad DP via the die bond material DB.

[0079] In this process, die bond material DB and semiconductor chip CP are placed on die pads DP provided in each of the multiple device formation sections LFd. Then, the semiconductor chip CP is mounted on each device formation section LFd.

[0080] In this embodiment, an embodiment in which a paste material made of thermosetting resin is used as the die bond material DB has been described, but various modifications can be applied. For example, solder may be used as the die bond material DB.

[0081] When solder is used as a variation of the die bond material DB, a paste material containing solder components (solder paste) is used as the paste material described above. When using solder paste, the die bond material DB is formed by performing a reflow process in which the die bond material DB is heated to a temperature above the melting point of solder and then cooled.

[0082] <Wire joining process> Next, in the wire bonding process shown in Figure 7, as shown in Figure 13, multiple pads (electrodes) PD and multiple leads LD of the semiconductor chip CP are electrically connected via multiple wires (conductive members) BW. Figure 13 is an enlarged top view showing the state in which the semiconductor chip and leads shown in Figure 12 are electrically connected via wires.

[0083] As shown in Figure 13, in this process, in each of the multiple device formation sections LFd, the semiconductor chip CP and the lead LD are electrically connected via a wire (conductive member) BW. For example, the lead LD1 of device formation section LFd1 is electrically connected to the pad PD1 of semiconductor chip CP1 via the wire (conductive member) BW1. The lead LD2 of device formation section LFd2 is electrically connected to the pad PD2 of semiconductor chip CP2 via the wire (conductive member) BW2. The method of wire bonding is not limited to the following, but an example is given below.

[0084] In this process, as shown in Figure 12, a lead frame LF, on which semiconductor chips CP are mounted on die pads DP of multiple device formation sections LFd, is placed on a heat stage (lead frame heating stand) (not shown).

[0085] Next, a portion of the wire BW (one end) is connected to the pad PD of the semiconductor chip CP, and the other portion of the wire BW (the other end) is connected to the wire junction LDm of the lead LD. For example, a plating film made of silver (Ag) or gold (Au) is formed on a portion of the lead LD (the upper surface LDt of the wire junction LDm), and the wire BW is joined to this plating film.

[0086] As explained using Figure 6, the wire joint LDm includes a main body LDZ and thin-walled sections LFhf provided on both sides of the main body LDZ. The thickness of the main body LDZ is greater than the thickness of the thin-walled sections LFhf. Therefore, considering stability on the heat stage, it is preferable that the entire joint of the wire BW shown in Figure 13 (the other parts mentioned above) is joined to the main body LDZ.

[0087] However, depending on the positional accuracy of the wire bonder used to join the wire BW, a portion of the wire BW may be joined to the thin-walled portion LFhf (see Figure 6). Even if a portion of the joining portion of the wire BW is joined to the thin-walled portion LFhf, if another portion is joined to the main body portion LDZ (see Figure 6), the wire BW and the wire joining portion LDm can be stably joined. In other words, in this embodiment, since thin-walled portions LFhf are provided on both sides of the main body portion LDZ, the reliability of the connection between the wire BW and the lead LD can be improved, and the width of the main body portion LDZ can be reduced.

[0088] <Sealing process> Next, in the encapsulation process shown in Figure 7, as shown in Figure 15, a encapsulation body MR is formed to encapsulate a portion of the die pad DP, a portion of each of the multiple leads LD, multiple wires BW, and the semiconductor chip CP. Figure 14 is a plan view showing the encapsulation body formed in the encapsulation process shown in Figure 7. Figure 15 is an enlarged cross-sectional view showing the state in which the lead frame is positioned within the cavity of the molding die, in an enlarged cross section along the FF line of Figure 14.

[0089] In this process, as shown in Figure 15, a encapsulation body MR is formed that encapsulates the lead LD1, lead LD2, tie bar LFtb, semiconductor chip CP1, semiconductor chip CP2, wire BW1, and wire BW2 together. Upon completion of this process, the lower surface LDb of lead LD1 and the lower surface LDb of lead LD2 are exposed from the encapsulation body MR.

[0090] In this process, the sealant MR shown in Figure 14 is formed, for example, by the transfer molding method described below. In the transfer molding method, for example, with the lead frame LF sandwiched between the molding die 50 shown in Figure 15, softened sealing resin is injected into the molding die 50 under pressure and then cured. The sealing resin consists of an insulating material.

[0091] The molding die 50 comprises an upper die (mold) 51 positioned on the lead frame LF and a lower die (mold) 52 positioned below the lead frame LF. The upper die 51 includes a clamping surface (not shown) that holds the lead frame LF and a cavity (recess) 53 formed inside the clamping surface. The lower die 52 includes a support surface (mold surface, pressing surface, surface) 52a positioned opposite the cavity 53 to support the lead frame LF. In this embodiment, since a QFN type package is manufactured, no cavity is formed on the support surface 52a of the lower die 52.

[0092] In the sealing process, sealing resin is injected into the cavity 53 under pressure to seal the semiconductor chip CP (see Figure 15) and the multiple wires BW (see Figure 15). In addition, a portion of the multiple leads LD (excluding the lower surface LDb) and a portion of the die pad DP (excluding the lower surface DPb) are also sealed with the sealing resin.

[0093] As shown in Figure 15, a tape material (resin film) TP is placed between the lead frame LF and the lower die 52. A pressing force is applied to the lower surface (back side, mounting side) of the lead frame LF from the support surface 52a of the lower die 52 via the tape material TP. Therefore, as shown in Figure 15, the lower surface LDb of the lead LD and the lower surface DPb of the die pad DP easily adhere to the tape material TP. In other words, in the sealing process of this embodiment, a sealing body MR is formed with the tape material in close contact with the lower surface DPb of the die pad DP and the lower surface LDb of each of the multiple lead LDs. By ensuring close contact with the tape material TP, it is possible to suppress the sealing resin from flowing around to the lower surface LDb of the lead LD and the lower surface DPb of the die pad DP. That is, the lower surface LDb of the lead LD and the lower surface DPb of the die pad DP can be exposed.

[0094] Next, the sealing resin supplied to the cavity 53 is thermocured to form the sealing body MR shown in Figure 14. More specifically, after the sealing body MR is molded in the cavity 53, it is heated until a portion of the thermosetting resin contained in the sealing body MR hardens (this is called pre-curing). Once this pre-curing makes it possible to remove the lead frame LF from the molding die, the lead frame LF is removed from the molding die. Then, it is transported to a heating furnace for further heat treatment (curebake). This hardens the remaining thermosetting resin, and the sealing body MR is obtained.

[0095] In this embodiment, a sealant MR is formed to seal multiple device forming sections LFd together. Focusing on the portion shown in Figure 15, the sealing process includes the following steps: The sealing process includes a step of adhering a single tape material TP to the device forming sections LFd1 and LFd2. The sealing process also includes a step of housing the device forming sections LFd1 and LFd2 in a single cavity 53. Furthermore, the sealing process includes a step of supplying resin into the cavity 53 to seal both the device forming sections LFd1 and LFd2 together.

[0096] The timing for adhering the tape material TP to the lead frame LF may vary as follows. For example, if an adhesive layer is provided on one side of the tape material TP, the tape material TP may be attached in advance before placing the lead frame LF into the cavity 53. Alternatively, the tape material TP may be placed in advance on the support surface 52a of the lower mold 52, and the lead frame LF may be placed on top of it. In this case, the lead frame LF and the tape material TP are pressed together by the supply pressure of the sealing resin.

[0097] A semiconductor package in which a sealant MR is formed to cover multiple device formation sections LFd arranged in a matrix, as in this embodiment, is called a MAP (Multi Array Package) type semiconductor device. The sealing method for sealing multiple device formation sections LFd together is called the block molding method. In a MAP type semiconductor device, the spacing between each of the multiple device formation sections LFd can be reduced, so the effective area of ​​a single lead frame LF increases. In other words, the number of products that can be obtained from a single lead frame LF increases. In this way, the manufacturing process can be made more efficient by increasing the effective area of ​​a single lead frame LF. In particular, when dozens of products are obtained from a single lead frame LF, the effect of increased manufacturing efficiency due to the larger effective area is significant.

[0098] In this process, as shown in Figure 15, the sealing resin wraps around and adheres to areas that are not in close contact with the molding die 50 or the tape material TP. Also, as described above, a thin-walled portion LFhf is pre-formed on the lead frame LF. The sealing resin wraps around the thin-walled portion LFhf and seals it. For this reason, the lower surface TBb of the tie bar LFtb, as explained using Figure 11, is also sealed in this process.

[0099] In this embodiment, it is necessary to expose the lower surface LDb2 of the stepped portion LDe shown in Figure 3 from the sealant MR. For this reason, a half-dicing process shown in Figure 7 is performed as a step to remove a part of the sealant MR (the part that covers the thin-walled portion LFhf shown in Figure 15).

[0100] <Half-dicing process> In the half-dicing process shown in Figure 7, the portion of the sealant MR shown in Figure 15 that covers the tie bar LFtb is removed by cutting. In this process, in addition to the sealant MR, a portion of the lead LD1 (a portion of partial LDP1) and a portion of the lead LD2 (a portion of partial LDP1) are removed. Also in this process, a portion of the tie bar LFtb shown in Figure 11 (the lower layer including the entire lower surface TBb) is removed. Figure 16 is an enlarged bottom view showing the state after the half-dicing process shown in Figure 7 has been completed and the sealant covering the tie bar has been removed. Figure 17 is an enlarged cross-sectional view showing the state in the middle of cutting with a blade along the GG line in Figure 16.

[0101] In this process, cutting is performed using a blade (rotating blade) BL1, as shown in Figure 17. This process can also be called the first cutting process. The resin embedded on the lower surface TBb (see Figure 17) of the tie bar LFtb is removed by cutting. The blade BL1 is an annular (ring-shaped) or disc-shaped cutting jig, with multiple abrasive grains fixed to the cutting portion located on the periphery of the circle. By pressing the cutting portion of the blade BL1, to which the multiple abrasive grains are fixed, against the workpiece, the workpiece can be cut and removed.

[0102] Furthermore, this process forms the lower surface LDb2 of the stepped portion LDe of the lead LD, as explained using Figure 3, and the side surface LDs2 connected to the lower surface LDb2. In other words, the side surface LDs2 is formed when a part of the lead LD (a part of the lower surface side of portion LD1) is cut by the blade BL1. In Figure 16, the outline of the remaining part of the lead LD that was not cut in this process is shown by a dotted line.

[0103] As shown in Figure 17, the width WBL1 of the blade BL1 used in this process, that is, the cutting width in this half-dicing process, is greater than the width WTB of the tie bar LFtb. This allows for the formation of side LDs2 on each of the leads LD connected to both sides of the tie bar LFtb. In other words, in this process, a groove is formed along the dicing portion LFc by cutting with the blade BL1, thereby forming a stepped portion LDe (see Figure 3) on each of the multiple leads LD.

[0104] In this process, the tie bar LFtb is not separated. By connecting the lead LD to the tie bar LFtb, a metal film can be easily formed using the electroplating method in the metal film formation process described later.

[0105] In this process, the blade BL1 shown in Figure 17 is rotated and moved along the dicing portion LFc (see Figure 16) of the lead frame LF. As a result, stepped portions LDe (see Figure 3) are formed on the periphery of the lead LD along the dicing portion LFc, as shown in Figure 16.

[0106] The length in the Z direction of the side LDs2 (see Figure 17) formed in this process, i.e., the machining depth, is, for example, less than half the thickness of the portion LD2 of the lead LD.

[0107] Furthermore, in blade dicing using a rotating blade BL1, a metal burr LDBL (see Figure 16) is formed that extends in the direction of rotation of the blade BL1. The length of the metal burr LDBL (the length in the Y direction in the example shown in Figure 16) is proportional to the amount of metal being cut.

[0108] Therefore, in the Y direction, the length of the metal burr LDBL located on the extension of the lead LD portion LDP1 is longer than the length of the metal burr LDBL located on the extension of the thin-walled portion LFhf. This is because the amount of metal cut from the thin-walled portion LFhf in this process is less than that from the portion LDP1.

[0109] As will be explained in more detail later, in this embodiment, we focus on the difference in the length of the metal burr LDBL depending on its position, and by utilizing this, we prevent adjacent lead LDs from short-circuiting through the metal burr LDBL.

[0110] <Metal film formation process> Next, in the metal film formation process shown in Figure 7, after the half-dicing process, a metal film SD (see Figure 3) is formed on the portion of the lead frame LF shown in Figure 16 that is exposed from the sealant MR (exposed surface). Figure 18 is a schematic diagram illustrating an example of the metal film formation process shown in Figure 7.

[0111] In this process, for example, as shown in Figure 18, the lead frame LF is immersed in a plating solution 61. The plating solution 61 is, for example, a solder solution. An anode rod 62 is immersed in the plating solution 61. In the electrolytic plating method, the anode rod 62 is used as the anode, and the metal part of the lead frame LF is used as the cathode. For this reason, as illustrated in Figure 18, the lead frame LF is connected to the negative electrode of the power supply 63, and the anode rod 62 is connected to the positive electrode of the power supply 63. When current is applied in this state, a reduction reaction occurs on the cathode side, and a metal film SD (see Figure 22) is formed on the surface of the metal part of the lead frame LF that is exposed from the sealant MR.

[0112] In the electroplating method, a metal film SD is uniformly formed on the parts that come into contact with the plating solution 61 and constitute the current path. Therefore, in this process, in addition to the lower surface DPb of the die pad DP shown in Figure 9, the lower surface LDb of the lead LD shown in Figure 3, the side surface LDs2, and the lower surface LDb2, a metal film SD (see Figure 3) is also formed on the lower surface of the tie bar LFtb.

[0113] Furthermore, the metal burr LDBL shown in Figure 16 is connected to the lead LD or tie bar LFtb. Therefore, as already explained in Figure 5, a metal film SD is also formed on the metal burr LDBL.

[0114] <Singulation process> Next, in the piece-forming process shown in Figure 7, the blade BL2 shown in Figure 20 is run along the dicing section LFc shown in Figure 19, thereby dividing and piece-forming each of the multiple device forming sections LFd. Figure 19 is an enlarged bottom view showing the state after the completion of the piece-forming process shown in Figure 7, where two adjacent device forming sections have been separated. Figure 20 is an enlarged cross-sectional view showing the piece-forming process shown in Figure 7.

[0115] Focusing on the two device forming sections LFd shown in Figure 19, this process can be described as follows: In this process, the tie bar LFtb and the sealant MR (i.e., a part of the sealant MR) located between the two device forming sections LFd are removed, separating device forming section LFd1 and device forming section LFd2 from each other. In other words, the remaining portion of the tie bar LFtb that was not removed in the half-dicing process is removed. The width WBL2 of the blade BL2 (see Figure 20) used in this process is smaller than the width WBL1 of the blade BL1 explained using Figure 17.

[0116] The blade BL2 shown in Figure 20 is an annular (ring-shaped) or disc-shaped cutting jig, in which multiple abrasive grains are fixed to the cutting portion located on the periphery of the circle. By pressing the cutting portion of the blade BL2, to which the multiple abrasive grains are fixed, against the workpiece, the workpiece can be cut and removed.

[0117] The width of blade BL2, WBL2, or in other words, the cutting width of the dicing portion LFc in the individualization process, is greater than or equal to the width of the support portion TBG of the tie bar LFtb shown in Figure 16. Therefore, once this process is complete, the support portion TBG is removed, and each of the multiple leads LD is separated from one another.

[0118] Here, we will explain the metal burrs that occur when cutting using blade BL2. In blade dicing using the rotating blade BL2, metal burrs are formed that extend in the direction of rotation of blade BL2. In this process, all of the lead frame LF and the sealant MR present in the dicing section LFc are cut. Therefore, even if metal burrs are formed in the direction of rotation of blade BL2, the metal burrs are removed along with the other components.

[0119] However, as shown in Figure 19, metal burrs (LDBL) remain near the portion LDP1 of the lead LD that remains after cutting by blade BL2. Near the boundary between the dicing portion LFc and the device formation portion LFd, the metal burrs (LDBL) and the metal film SD formed on the metal burrs (LDBL) may come into contact with blade BL2 (see Figure 20). In this case, the rotational force of blade BL2 may stretch the metal burrs (LDBL) in the Y direction.

[0120] If the metal burr LDBL is stretched in the Y direction, there is a concern that it may come into contact with the adjacent lead LD. Therefore, from the viewpoint of suppressing short circuits between adjacent lead LDs via the metal burr LDBL, it is necessary to shorten the metal burr LDBL that is stretched in the Y direction by this process.

[0121] In this embodiment, during the dicing process, the tie bar LFtb is cut by inserting the blade BL2 shown in Figure 20 between the remaining portion of the LDP1 of lead LD1 and the remaining portion of the LDP1 of lead LD2. The width WBL2 of the blade BL2, in other words, the cutting width of the dicing portion LFc in the dicing process, is less than or equal to the width WTB of the tie bar LFtb including the lead connection portion TBC (see Figure 20).

[0122] As already explained with reference to Figure 16, the length of the metal burr LDBL (length in the Y direction in the example shown in Figure 16) is proportional to the amount of metal being cut. Therefore, in the Y direction, the length of the metal burr LDBL located on the extension of the lead LD portion LDP1 is longer than the length of the metal burr LDBL located on the extension of the thin-walled portion LFhf. In other words, the length of the metal burr LDBL is shorter near the boundary between the dicing portion LFc and the device formation portion LFd.

[0123] Even in this embodiment, the metal burr LDBL may be stretched in the Y direction near the boundary between the dicing section LFc and the device forming section LFd due to the rotational force of the blade BL2 (see Figure 20). However, since the length of the stretched portion of the metal burr LDBL is short, it is possible to prevent the metal burr LDBL from reaching the adjacent lead LD.

[0124] From the viewpoint of preventing the metal burr LDBL from being stretched to an excessive length, the following is preferable. In the example shown in Figure 20, the width WBL2 of blade BL2 is smaller than the width WTB. In this case, during the piece formation process, blade BL2 does not come into contact with the remaining portion of each part LDP1 of lead LD1 and lead LD2. In other words, contact between blade BL2 (Figure 20) and the relatively long portion of the metal burr LDBL shown in Figure 16 is avoided. This makes it possible to shorten the length of the metal burr LDBL remaining on the device formation part LFd after the completion of the piece formation process (see Figure 19).

[0125] The structure shown in Figure 19 can be described as follows: At the completion of the individualization process, a portion of the lead connection part TBC of the tie bar LFtb remains connected to the remaining portion LDP1 of lead LD1 or lead LD2. In this state, during the individualization process, the blade BL2 shown in Figure 20 does not come into contact with the remaining portion LDP1.

[0126] Through the above steps, the semiconductor device PKG1, as explained using Figures 1 to 6, is obtained. Subsequently, after performing tests and inspections such as electrical tests and visual inspections as necessary, those determined to be good products are transported to the next process, such as the semiconductor device packaging process.

[0127] <Example 1> Next, a modification of the above-described embodiment will be explained. Figure 21 is an enlarged bottom view showing a modification of Figure 10. In the case of the lead frame LF2 according to the modification shown in Figure 21, the planar shape of the lead LD differs from that of the lead frame LF shown in Figure 10.

[0128] In this modified example, in the lead frame preparation step shown in Figure 7, the boundary between lead LD1 and the lead connection portion TBC of the tie bar LFtb forms an arc shape in plan view. Similarly, the boundary between lead LD2 and the lead connection portion TBC of the tie bar LFtb forms an arc shape in plan view.

[0129] Furthermore, in this modified example, in the half-dicing process described with reference to Figure 7, at least a portion of the arc-shaped part is removed.

[0130] As described above, in order to shorten the length of the metal burr LDBL shown in Figure 16, it is preferable to reduce the amount of metal that is cut during the half-dicing process shown in Figure 7.

[0131] In this modified example, as can be seen by comparing Figure 10 and Figure 21, the volume of the portion LDP1 that is machined during the half-dicing process is smaller for the lead frame LF2 shown in Figure 21 than for the lead frame LF shown in Figure 10. In other words, according to this modified example, the arc shape of the tip of the tie bar LFtb side of the lead LD makes it possible to reduce the amount of metal that is machined during the half-dicing process.

[0132] From the viewpoint of reducing the amount of metal that is cut, it is preferable that the portion LDP1 that is cut in the half-dicing process is included in a portion that has an overall arc shape.

[0133] In other words, as shown in the enlarged view in Figure 21, it is preferable that the aforementioned arc-shaped portion is partially included in part LDP1 and partially included in part LDP2.

[0134] To put it another way, it is preferable that the arc-shaped portion described above straddles the boundary between portion LDP1 and portion LDP2.

[0135] However, although not shown in the figures, a further modification of this modification is that the entire arc-shaped portion described above may be included in the partial LDP1. In this case, compared to this modification, the amount of metal cut during the half-dicing process is greater. Even in this modification, since the arc-shaped portion is included in the partial LDP1, the amount of metal cut during the half-dicing process can be reduced compared to the lead frame LF shown in Figure 10.

[0136] As shown in Figure 21, in the modified case where the arc-shaped portion straddles the boundary between the LDP1 and LDP2 portions, the resulting semiconductor device differs from the semiconductor device PKG1 described using Figures 1 to 6 in the following respects. Figure 22 is an enlarged bottom view showing the leads of a semiconductor device manufactured using the lead frame shown in Figure 21.

[0137] In this modified example, the portion of the arc-shaped area shown in Figure 21 that is included in the LDP1 portion is machined during the half-dicing process. On the other hand, the portion included in the LDP2 portion is not machined during the half-dicing process. Therefore, as shown in Figure 22, the structure around the stepped portion LDe of the lead LD of the semiconductor device PKG2 is as follows.

[0138] Each of the above multiple lead LDs includes a main body LDZ and a stepped portion LDe. The main body LDZ has a side LDs3 facing the die pad DP (see Figure 3) and a side LDs2 located opposite to side LDs3. Side LDs2 includes a flat portion FLP extending in the Y direction, which is the arrangement direction of the multiple lead LDs, and a curved portion BNP connected to the flat portion FLP and forming an arc shape in plan view.

[0139] Although not shown in Figure 22, the metal film SD shown in Figure 3 is formed on the side LDs2.

[0140] Regarding the semiconductor device PKG2 shown in Figure 22, the technical concept can be extracted and expressed as follows: That is, the semiconductor device PKG2 is Die pad and, A plurality of leads are provided, comprising a first upper surface and a first lower surface located opposite the first upper surface, and spaced apart from the die pad, The semiconductor chip mounted on the die pad mentioned above, Multiple conductive members electrically connect the above semiconductor chip and the above multiple leads, A encapsulant that seals a portion of the die pad, a portion of each of the multiple leads, the multiple conductive members, and the semiconductor chip, having a second upper surface and a second lower surface located opposite the second upper surface, such that the first lower surface of each of the multiple leads is exposed from the second lower surface. Includes, Each of the above leads is: A main body having the above-mentioned first upper surface and the above-mentioned first lower surface, A stepped portion is positioned further from the die pad than the main body and is thinner than the main body, Includes, The above multiple leads are arranged in the first direction, The stepped portion comprises the first upper surface and a third lower surface located opposite the first upper surface. The main body described above is The first side facing the die pad, The second side is located opposite to the first side described above, It has, The second aspect mentioned above is, A planar portion extending in the first direction described above, A curved surface portion that is connected to the above-mentioned planar portion and forms an arc shape in plan view, It includes.

[0141] <Modification 2> Next, other modifications relating to the shape of the lead frame will be described. Figure 23 is an enlarged bottom view showing another modification of Figure 10. The lead frame LF3 shown in Figure 23 differs from the lead frame LF shown in Figure 10 in the following respects.

[0142] In other words, the width WTBC of the lead connection portion TBC of the tie bar LFtb of lead frame LF3 is smaller than the width WLDP2 of the respective portions LDP2 of lead LD1 and lead LD2.

[0143] As already explained, the metal burr LDBL (see Figure 16) formed by cutting during the half-dicing process is proportional to the amount of metal cut. In this modified example, the width WTBC of the lead connection portion TBC is smaller compared to the lead frame LF shown in Figure 10. In other words, in this modified example, focusing on the lead connection portion TBC, the amount of metal cut during the half-dicing process is less than in the embodiment shown in Figure 10. Therefore, in this modified example, the length of the metal burr extending from the lead connection portion TBC is shorter compared to the example shown in Figure 16.

[0144] Therefore, in this modified example, the length of the metal burr can be further shortened compared to using the lead frame LF shown in Figure 10.

[0145] <Other variations> In addition to the modifications described above, the above-described technology can be applied to various other modifications. For example, in the above embodiments and modifications, a QFN type semiconductor device was described as an example of a semiconductor device, in which multiple leads are arranged on each of the four sides of the semiconductor device. However, the arrangement method of the multiple leads is not limited to the QFN type. For example, it can be applied to a DFN type semiconductor device in which multiple leads LD are arranged only on two sides of the four sides of the semiconductor device that are opposite each other.

[0146] Furthermore, in the above-described embodiment, it was explained that in the half-dicing process, not only a portion of the lead LD2 (a portion of the partial LDP1) but also a portion of the tie bar LFtb is removed. As a variation of the above embodiment, the tie bar LFtb may not be removed in the half-dicing process. However, if a portion of the tie bar LFtb is not removed in the half-dicing process, the sealant MR covering the lower surface TBb of the tie bar LFtb will also not be removed. On the other hand, it is conceivable that the position of the blade BL2 used in the subsequent individualization process may be shifted from its original position toward one of the two adjacent device forming portions LFd. In this case, the sealant MR covering the lower surface TBb of the tie bar LFtb (especially the lead connection portion TBC) will not be removed even in the individualization process. As a result, this unremoved sealant MR may later become foreign matter and fall off or scatter. Considering this point, it is preferable that in the half-dicing process, a portion of the tie bar LFtb is removed in addition to a portion of the lead LD2, as in the above-described embodiment. This allows the sealing material MR covering the lower surface TBb of the tie bar LFtb to also be removed during the half-dicing process.

[0147] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0148] 50 Molding molds 51 Upper mold (die) 52 Lower mold (mold) 52a Support surface (mold surface, pressing surface, surface) 53 Cavity (recessed area) 61 Plating solution 62 Anode rod 63 Power supply BL1, BL2 blades (dicing blades, rotating blades) BNP curved part BW, BW1, BW2 wires (conductive components) CP, CP1, CP2 semiconductor chips CPb back surface (main surface, bottom surface) CPs side CPt surface (principal surface, top surface) DB Diebonding material (adhesive) DP die pad (chip mounting area, tab) DPb,LDb,LDb2,LDb3,MRb,TBb Bottom surface DPs, LDs1, LDs2, LDs3, MRs (side view) DPt, LDt, MRt top surface FLP flat part LD, LD1, LD2 Lead (Terminal, External Terminal) LDBL metal burrs LDe Step section LDm wire joint LDP1,LDP2 part LDZ main body LF, LF2, LF3 Lead Frames LFc, LFcX, LFcY Dicing section LFd, LFd1, LFd2 device formation section LFf frame section (frame part, frame body) LFhf thin-walled section (half-etched section) LFtb Tie Bar MR sealing body (resin body) PD, PD1, PD2 pads (electrodes, bonding pads) PKG1, PKG2 Semiconductor Equipment SD metal film TBC lead connection TBG support part TL Suspension Lead TP tape material (resin film) WBL1,WBL2,WLDb,WLDb2,WLDP2,WLDt,WTB,WTBC Width

Claims

1. (a) A step of preparing a lead frame comprising: a first lead provided in a first device forming section; a second lead provided in a second device forming section located next to the first device forming section; and tie bars provided in a dicing section between the first device forming section and the second device forming section, and connected to the first lead and the second lead, respectively. (b) After step (a), a step of mounting a first semiconductor chip in the first device formation section and a second semiconductor chip in the second device formation section, (c) After step (b), the first lead and the first semiconductor chip are electrically connected to each other via a first conductive member, and the second lead and the second semiconductor chip are electrically connected to each other via a second conductive member. (d) After step (c), a step of forming a seal that encapsulates the first lead, the second lead, the tie bar, the first semiconductor chip, the second semiconductor chip, the first conductive member, and the second conductive member together, such that the lower surfaces of the first lead and the second lead are exposed. (e) After step (d), a step of removing a portion of the first lead and the second lead using a first blade having a first width greater than the width of the tie bar, (f) After step (e), a step of forming a metal film on the exposed surface of the lead frame that is exposed from the seal by a plating method, (g) After step (f), a second blade having a second width smaller than the first width is used to remove the tie bar and the sealant, thereby separating the first device forming section and the second device forming section from each other. Includes, The tie bar of the lead frame prepared in step (a) above is In a plan view, a lead connection portion extends in a first direction from the first lead to the second lead, A support portion extending in a second direction intersecting the first direction in a plan view, It has, In step (a) above, with the upper surfaces of the first lead and the second lead as reference planes, the height difference between the lower surface of the tie bar and the reference plane is smaller than the height difference between the lower surfaces of the first lead and the second lead and the reference plane. Each of the first lead and the second lead is, In step (e) above, a first portion is partially removed by the first blade, The second portion that is not removed in step (e) above, Includes, A method for manufacturing a semiconductor device, wherein in step (g), the tie bar is cut by inserting the second blade between the remaining portion of the first lead and the remaining portion of the first lead.

2. In claim 1, A method for manufacturing a semiconductor device, wherein in step (g), the second blade does not contact the first lead and the remaining portion of the first portion of the second lead.

3. In claim 1, A method for manufacturing a semiconductor device, wherein, upon completion of step (g), a portion of the lead connection portion of the tie bar is connected to at least the remaining portion of the first lead or the first portion of the second lead.

4. In claim 1, A method for manufacturing a semiconductor device, wherein, in step (a) above, the boundary between the first lead and the lead connection portion of the tie bar, and the boundary between the second lead and the lead connection portion of the tie bar, each form an arc shape in a plan view.

5. In claim 4, A method for manufacturing a semiconductor device, wherein in step (e), a portion of the arc-shaped part is removed.

6. In claim 4, A method for manufacturing a semiconductor device, wherein the arc-shaped portion straddles the boundary between the first portion and the second portion.

7. In claim 1, A method for manufacturing a semiconductor device, wherein in step (a), the thickness of the tie bar is half or less of the thickness of the first lead and the second lead, respectively.

8. In claim 1, Each of the first blades is a rotating blade, In step (e), a metal burr extending in the rotational direction of the first blade is formed from the first portion of the first lead and the first portion of the second lead. A method for manufacturing a semiconductor device, wherein in step (f), the metal film is also formed on the metal burr.

9. In claim 1, A method for manufacturing a semiconductor device, wherein the width of the lead connection portion of the tie bar of the lead frame prepared in step (a) is smaller than the width of the second portion of the first lead and the second lead, respectively.

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