Copper plasma etching method, and display devices and electronic devices manufactured thereby

Abstract

By improving the etching processability of copper wiring, we can realize high-resolution display devices. [Solution] A display device according to one embodiment includes a substrate, an insulating layer disposed on the substrate, at least one transistor disposed on the insulating layer, at least one signal wiring disposed on the insulating layer and electrically connected to the at least one transistor, and a light-emitting element connected to the at least one transistor, wherein the signal wiring contains copper, and the surface of the insulating layer contains chlorine.

Description

TECHNICAL FIELD

[0001] The present invention relates to a copper plasma etching method, and a display device and an electronic apparatus manufactured thereby. BACKGROUND ART

[0002] With the development of the information-oriented society, demands for display devices for displaying images are becoming increasingly diversified. For example, display devices are applied to various electronic apparatuses such as smartphones, digital cameras, notebook computers, navigation systems, and smart televisions.

[0003] The display device may be a flat panel display device such as a Liquid Crystal Display Device, a Field Emission Display Device, a Light Emitting Display Device, and the like. The light emitting display device includes an organic light emitting display device including an organic light emitting element, an inorganic light emitting display device including an inorganic light emitting element such as an inorganic semiconductor, and a micro light emitting display device including a micro light emitting element.

[0004] The display device may include a plurality of wirings through which various signals are transmitted. These wirings may be formed of various metal materials, and in particular, copper wirings are advantageous as wirings because they have a property of low resistance. However, copper has low etching processability, so it is difficult to apply it to display devices. PRIOR ART DOCUMENTS PATENT DOCUMENTS

[0005] PATENT DOCUMENT 1 Korean Patent Publication No. 1761943 SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0006] The problem that this invention aims to solve is to provide a copper plasma etching method that improves the etching processability of copper wiring and enables the realization of high-resolution display devices, as well as a display device and electronic device manufactured thereby.

[0007] The problems addressed by the present invention are not limited to those described above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A display device according to one embodiment for solving the above problem includes a substrate, an insulating layer disposed on the substrate, at least one transistor disposed on the insulating layer, at least one signal wiring disposed on the insulating layer and electrically connected to the at least one transistor, and a light-emitting element connected to the at least one transistor, wherein the signal wiring contains copper, and the surface of the insulating layer may contain chlorine.

[0009] The surface of the insulating layer may further contain copper.

[0010] The chlorine content may be greater than the copper content.

[0011] The ratio of the line width to the spacing of at least one of the signal wirings can be 1.1 / 1.5 to 1.1 / 1.1.

[0012] The at least one signal line may be at least one of a scan line, a data line, an initialization voltage line, a sensing line, a first voltage line, and a second voltage line that are electrically connected to the at least one transistor.

[0013] Furthermore, a copper plasma etching method according to one embodiment may include the steps of: placing a substrate on which a metal layer containing copper is formed in a chamber; supplying a first gas containing chlorine into the chamber; and plasma etching the metal layer.

[0014] The first chlorine-containing gas may include any one or more selected from the group consisting of Cl2, CCl4, BCl3, SiCl2, HCl, PCl3, CH2Cl2F, CHClF2, CCl2F2 and ICl.

[0015] The first gas may not contain H2.

[0016] The first gas may contain HCl.

[0017] After the first etching step, the method may further include a step of discharging the first gas, and a second etching step of supplying a second hydrogen-containing gas into the chamber to perform plasma etching on the metal layer.

[0018] The second hydrogen-containing gas may contain H2.

[0019] In the substrate, a photoresist pattern may be formed as an etching mask on the metal layer.

[0020] The first etching step and the second etching step constitute one cycle, and the cycle may be performed multiple times.

[0021] The temperature of the substrate surface may be 80 degrees or lower.

[0022] The following reactions may occur in the plasma etching.

[0023] Cu(s)+1 / 2Cl2(g)=CuCl(s) CuCl(s)+1 / 2Cl2(g)=CuCl2(s) Cu(s)+Cl2(g)=CuCl2(g) 3Cu(s)+3 / 2Cl2(g)=Cu3Cl3(g) 3CuCl2(s)+3H(g)=Cu3Cl3(g)+3HCl(g) CuCl2(s)+3H(g)=CuH(g)+2HCl(g) CuCl(s)+2H(g)=CuH(g)+HCl(g) 3CuCl2(s)+3 / 2H2(g)=Cu3Cl3(g)+3HCl(g) Here, (s) is the solid state and (g) is the gaseous state.

[0024] Furthermore, an electronic device according to one embodiment includes a display device for displaying images, a memory storing data information necessary for the operation of the display device, a processor for executing applications stored in the memory, and a power supply module for supplying power to the display device, the memory, and the processor, wherein the display device includes a substrate, an insulating layer disposed on the substrate, at least one transistor disposed on the insulating layer, at least one signal wiring disposed on the insulating layer and electrically connected to the at least one transistor, and a light-emitting element connected to the at least one transistor, wherein the signal wiring contains copper, and the surface of the insulating layer may contain chlorine.

[0025] The display device may have a resolution of 300 ppi to 1700 ppi.

[0026] The surface of the insulating layer may further contain copper.

[0027] The chlorine content may be greater than the copper content.

[0028] The ratio of the line width to the spacing of at least one of the signal wirings can be 1.1 / 1.5 to 1.1 / 1.1.

[0029] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0030] One embodiment of the copper plasma etching method can prevent the re-deposition of reaction products on the substrate or the inner wall of the chamber, thereby improving productivity. Furthermore, because the copper plasma etching process is performed at low temperatures, a photoresist pattern can be used as the etching mask. In addition, by reducing the skew of copper wiring, reliability can be improved, enabling the realization of high-resolution display devices and electronic devices.

[0031] The effects of the embodiments are not limited to those exemplified above, and a wider variety of effects are included herein. [Brief explanation of the drawing]

[0032] [Figure 1] This is a block diagram of an electronic device according to one embodiment. [Figure 2] This is a schematic diagram of an electronic device in various embodiments. [Figure 3] This is a schematic plan view of a display device according to one embodiment. [Figure 4] This is an equivalent circuit diagram of one subpixel according to one embodiment. [Figure 5] This is a schematic cross-sectional view showing one pixel of a display device according to one embodiment. [Figure 6] This is a schematic diagram of an etching apparatus for copper plasma etching. [Figure 7] This is a flowchart of a copper plasma etching method according to one embodiment. [Figure 8] This figure shows the steps of a copper plasma etching method according to one embodiment. [Figure 9] This figure shows the steps of a copper plasma etching method according to one embodiment. [Figure 10] This figure shows the steps of a copper plasma etching method according to one embodiment. [Figure 11] This figure shows the steps of a copper plasma etching method according to one embodiment. [Figure 12] This graph shows the Gibbs free energies of reaction products as they react to temperature. [Figure 13] This is a flowchart of a copper plasma etching method according to another embodiment. [Figure 14] This figure shows the steps of a copper plasma etching method according to one embodiment. [Figure 15] This figure shows the steps of a copper plasma etching method according to one embodiment. [Figure 16] This is a flowchart of a copper plasma etching method according to another embodiment. [Figure 17] This is an inspection image of the copper wiring edge after development, as shown in Experimental Example 1. [Figure 18] This is an inspection image of the central part of the copper wiring after development, as shown in Experimental Example 1. [Figure 19] This is an inspection image of the copper wiring edge after etching, as shown in Experimental Example 1. [Figure 20] This is an inspection image of the central part of the copper wiring after etching, as shown in Experimental Example 1. [Figure 21] This is an inspection image of the copper wiring edge after cleaning, as shown in Experimental Example 1. [Figure 22] This is an inspection image of the central part of the copper wiring after cleaning, as shown in Experimental Example 1. [Figure 23] This is an inspection image of the copper wiring after development, as shown in Experimental Example 2. [Figure 24] This is an inspection image of the copper wiring after etching, as shown in Experimental Example 2. [Figure 25] This is an inspection image of the copper wiring after cleaning, as shown in Experimental Example 2. [Figure 26] This image shows the insulating layer and copper wiring manufactured using Experimental Example 3. [Figure 27] This table shows the results of the XPS analysis of the insulating layer in Experimental Example 3. [Modes for carrying out the invention]

[0033] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the embodiments described below in detail, along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and can be realized in a variety of different forms, and these embodiments are provided merely to complete the disclosure of the present invention and to fully inform those who are ordinary skill in the art to which the invention pertains, of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0034] When elements or layers are referred to as “On” other elements or layers, this includes all cases where other layers or elements are interposed immediately above or between them. Similarly, when elements are referred to as “Below,” “Left,” and “Right,” this includes all cases where they are directly adjacent to or interposed with other elements, or where other layers or materials are interposed between them. Throughout this specification, the same reference numerals refer to the same component.

[0035] While terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component mentioned below may, of course, be the second component within the technical concept of the present invention.

[0036] The embodiments will be described below with reference to the attached drawings.

[0037] The display device according to the embodiment can be applied to various electronic devices. An electronic device according to one embodiment includes the above-described display device and may further include modules or devices having other additional functions in addition to the display device.

[0038] Figure 1 is a block diagram of an electronic device according to one embodiment. Referring to Figure 1, the electronic device 1 according to one embodiment may include a display module 11, a processor 12, a memory 13, and a power supply module 14.

[0039] The processor 12 may include at least one of the following: a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), or a controller.

[0040] Memory 13 stores data information necessary for the operation of the processor 12 and the display module 11. When the processor 12 executes an application stored in memory 13, video data signals and / or input control signals are transmitted to the display module 11, which processes the provided signals and can output video information via the display screen.

[0041] The power module 14 may include a power supply module such as a power adapter or a battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power necessary for the operation of the electronic device 1.

[0042] At least one of the components of the electronic device 1 described above may be included in the display device according to the embodiment described above. Furthermore, some of the individual modules that are functionally contained within a single module may be included in the display device, while other parts may be provided separately from the display device. For example, the display device includes a display module 11, while the processor 12, memory 13, and power supply module 14 may be provided in the form of other devices within the electronic device 1 rather than in the display device.

[0043] Figure 2 is a schematic diagram of an electronic device according to various embodiments.

[0044] Referring to Figure 2, various electronic devices to which the display device according to the embodiment is applied may include not only electronic devices for displaying images such as smartphones 1_1a, tablet PCs 1_1b, laptops 1_1c, televisions 1_1d, and desktop monitors 1_1e, but also wearable electronic devices including display modules such as smart glasses 1_2a, head-mounted displays 1_2b, and smartwatches 1_2c, and vehicle electronic devices 1_3 including display modules such as CID (Center Information Display) and rearview mirror displays located on the instrument panel, center fascia, and dashboard of an automobile.

[0045] Figure 3 is a schematic plan view of a display device according to one embodiment.

[0046] In this specification, "upper," "top," and "upper surface" refer to the upward direction relative to the display device 10, i.e., one direction of the third direction DR3, while "lower," "bottom," and "lower surface" refer to the other direction of the third direction DR3. Furthermore, "left," "right," "up," and "down" refer to the directions when the display device 10 is viewed from above. For example, "left" refers to one direction of the first direction DR1, "right" refers to the other direction of the first direction DR1, "up" refers to one direction of the second direction DR2, and "down" refers to the other direction of the second direction DR2.

[0047] Referring to Figure 3, the display device 10 can display videos or still images. The display device 10 refers to all electronic devices that provide a display screen. For example, the display device 10 may include televisions, laptops, monitors, billboards, the Internet of Things, mobile phones, smartphones, tablet PCs (Personal Computers), electronic clocks, smartwatches, watch phones, head-mounted displays, mobile communication terminals, electronic organizers, e-books, PMPs (Portable Multimedia Players), navigation systems, game consoles, digital cameras, camcorders, and more.

[0048] The display device 10 may include a display panel that provides a display screen. Examples of display panels include inorganic light-emitting diode display panels, organic light-emitting display panels, quantum dot light-emitting display panels, plasma display panels, and field emission display panels. Below, an example of a display panel using an inorganic light-emitting diode display panel is given, but it is not limited to this, and can be applied to other display panels as long as the same technical concept is applicable.

[0049] The shape of the display device 10 can be changed in various ways. For example, the display device 10 may have shapes such as a horizontal rectangle, a vertical rectangle, a square, a quadrilateral with rounded corners (vertices), other polygons, or a circle. The shape of the display area DPA of the display device 10 is also similar to the overall shape of the display device 10. Figure 3 shows an example of a horizontal rectangular display device 10 and its display area DPA.

[0050] The display device 10 may include a display area (DPA) and a non-display area (NDA). The display area (DPA) is the area where the screen can be displayed, and the non-display area (NDA) is the area where the screen cannot be displayed. The display area (DPA) may also be called the active area, and the non-display area (NDA) may also be called the inactive area. The display area (DPA) may generally occupy the center of the display device 10.

[0051] A display area (DPA) may contain multiple pixels (PX). These pixels (PX) may be arranged in a matrix direction. The shape of each pixel (PX) may be rectangular or square in a planar view, but is not limited to these; it may also be a rhombus with each side tilted in one direction. Each pixel (PX) may be arranged alternately in a stripe or pentile pattern. Furthermore, each pixel (PX) may contain one or more light-emitting elements (ED) that emit light in a specific wavelength band to display a specific color.

[0052] Non-display areas (NDAs) may be arranged around the display area (DPA). The non-display areas (NDAs) may enclose the display area (DPA) entirely or partially. The display area (DPA) may be rectangular in shape, and the non-display areas (NDAs) may be arranged adjacent to all four sides of the display area (DPA). The non-display areas (NDAs) may constitute the bezel of the display device 10. Wiring or circuit drive units included in the display device 10 may be placed in each non-display area (NDA), or external devices may be mounted therein.

[0053] Each pixel PX or sub-pixel of the display device 10 includes a pixel driving circuit. The aforementioned wiring can apply a driving signal to each pixel driving circuit as it passes through each pixel PX or its vicinity. The pixel driving circuit may include transistors and capacitors. The number of transistors and capacitors in each pixel driving circuit can be varied. According to one embodiment, each pixel PX of the display device 10 may have a 3T1C structure in which the pixel driving circuit includes three transistors and one capacitor. The pixel driving circuit will be described below using the 3T1C structure as an example, but is not limited to this, and various other modified forms of pixel PX structures such as 2T1C, 7T1C, and 6T1C structures can also be applied.

[0054] Figure 4 is an equivalent circuit diagram of one subpixel according to one embodiment.

[0055] Referring to Figure 4, in one embodiment, each pixel PX of the display device 10 may include, in addition to the light-emitting element EL, three transistors TR1, TR2, TR3 and one storage capacitor Cst.

[0056] The light-emitting element EL can emit light in response to a current supplied through the first transistor TR1. The light-emitting element EL may include a first electrode, a second electrode, and at least one light-emitting element disposed between them. The light-emitting element can emit light in a specific wavelength band in response to an electrical signal transmitted from the first electrode and the second electrode.

[0057] One end of the light-emitting element EL is connected to the source electrode of the first transistor TR1, and the other end may be connected to the second voltage wiring VSL, which is supplied with a lower potential voltage (hereinafter referred to as the second power supply voltage) lower than the high potential voltage (hereinafter referred to as the first power supply voltage) of the first voltage wiring VDL. The other end of the light-emitting element EL may also be connected to the source electrode of the second transistor TR2. In the example in Figure 4, a storage capacitor Cst is placed between the other end (first electrode) of the light-emitting element EL, the source electrode of the second transistor TR2, and the gate electrode of the first transistor TR1.

[0058] The first transistor TR1 can regulate the current flowing from the first voltage wiring VDL, to which the first power supply voltage is supplied, to the light-emitting element EL, depending on the voltage difference between the gate electrode and the source electrode. For example, the first transistor TR1 may be a drive transistor for driving the light-emitting element EL. The gate electrode of the first transistor TR1 may be connected to the source electrode of the second transistor TR2, the source electrode of the light-emitting element EL may be connected to the first electrode of the light-emitting element EL, and the drain electrode may be connected to the first voltage wiring VDL to which the first power supply voltage is applied.

[0059] The second transistor TR2 is turned on by the scan signal of the scan line SCL, connecting the data line DTL to the gate electrode of the first transistor TR1. The gate electrode of the second transistor TR2 may be connected to the scan line SCL, the source electrode to the gate electrode of the first transistor TR1, and the drain electrode to the data line DTL.

[0060] The third transistor TR3 is turned on by the sensing signal on the sensing line SSL, causing the initialization voltage wiring VIL to connect to one end of the light-emitting element EL. The gate electrode of the third transistor TR3 is connected to the sensing line SSL, the drain electrode is connected to the initialization voltage wiring VIL, and the source electrode may be connected to one end of the light-emitting element EL or to the source electrode of the first transistor TR1.

[0061] In one embodiment, the source and drain electrodes of each transistor TR1, TR2, and TR3 are not limited to the configuration described above, and may be reversed. Furthermore, each of the transistors TR1, TR2, and TR3 may be formed as a thin-film transistor. Also, although Figure 4 mainly describes the case where each transistor TR1, TR2, and TR3 is formed as an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), it is not limited to this. That is, each transistor TR1, TR2, and TR3 may be formed as a P-type MOSFET, or some may be formed as N-type MOSFETs and others as P-type MOSFETs.

[0062] The storage capacitor Cst is formed between the gate electrode and source electrode of the first transistor TR1. The storage capacitor Cst charges with the differential voltage between the gate voltage and source voltage of the first transistor TR1.

[0063] The following describes in detail the structure of one pixel PX of the display device 10 according to one embodiment, with further reference to other drawings.

[0064] Figure 5 is a schematic cross-sectional view showing one pixel of a display device according to one embodiment. Figure 5 will be used to specifically explain the structure of the display substrate 100 described above.

[0065] Referring to Figure 5, the display substrate 100 of the display device 10 according to one embodiment may include a substrate 110. The substrate 110 may be a base substrate or base member and is made of a transparent insulating material. For example, the substrate 110 may include glass or a polymer material. If the substrate 110 includes glass, the substrate 110 may be a rigid substrate, and if the substrate 110 includes a polymer material, the substrate 110 may be a flexible substrate that can be bent, folded, rolled, etc. In this embodiment, the case in which the substrate 110 is a rigid substrate containing glass will be described as an example. However, it is not limited thereto, and the substrate 110 may be a flexible substrate containing polyimide (PI).

[0066] A buffer layer 115 may be placed on the substrate 110. The buffer layer 115 consists of an inorganic film that can prevent the intrusion of air or moisture. The buffer layer 115 may contain silicon compounds, metal oxides, etc. For example, the buffer layer 115 may contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These can be used individually or in combination with each other. The buffer layer 115 may be a single film or a multilayer film consisting of laminated films of different materials.

[0067] A transistor TFT may be placed on the buffer layer 115. The transistor TFT may include a semiconductor layer 120, a gate electrode 130, a source electrode 140, and a drain electrode 145. The transistor TFT may constitute the pixel circuit for each of multiple pixels. For example, the transistor TFT may be a driving transistor or a switching transistor for the pixel circuit. The drawing shows an example in which one transistor TFT is placed in pixel PX of the display device 10, but it is not limited to this, and the display device 10 may include a larger number of transistors.

[0068] The semiconductor layer 120 may be placed on the buffer layer 115. The semiconductor layer 120 may be placed so as to partially overlap with the gate electrode 130 of the first conductive layer, which will be described later.

[0069] The semiconductor layer 120 may include polycrystalline silicon, single-crystal silicon, or an oxide semiconductor. In other embodiments, the semiconductor layer 120 may also include polycrystalline silicon. The oxide semiconductor may be an oxide semiconductor containing indium (In). For example, the oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0070] A gate insulating layer 125 may be disposed on the semiconductor layer 120. The gate insulating layer 125 may be disposed on a substrate 110 containing the semiconductor layer 120. The gate insulating layer 125 can serve as the gate insulating film of a transistor TFT. The gate insulating layer 125 may contain silicon compounds, metal oxides, etc. For example, the gate insulating layer 125 may contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These may be used alone or in combination with each other. The gate insulating layer 125 may be a single film or a multilayer film consisting of laminated films of different materials.

[0071] The gate electrode 130 may be placed on the gate insulating layer 125. The gate electrode 130 may be placed so as to overlap the channel region of the semiconductor layer 120 with a third direction DR3 which is the thickness direction. A scan line SCL may be placed on the gate insulating layer 125, spaced apart from the gate electrode 130. The scan line SCL may be electrically connected to the gate electrode 130.

[0072] An interlayer insulating layer 135 may be placed on the gate electrode 130 and the scan line SCL. The interlayer insulating layer 135 may be placed on the gate electrode 130, the scan line SCL, and the gate insulating layer 125. The interlayer insulating layer 135 can function as an insulating film between the gate electrode 130, the scan line SCL, and any other layers placed thereon. The interlayer insulating layer 135 may also be positioned to cover the gate electrode 130 and the scan line SCL, thereby protecting them.

[0073] The interlayer insulating layer 135 may contain silicon compounds, metal oxides, etc. For example, the interlayer insulating layer 135 may contain silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These can be used individually or in combination with each other. The interlayer insulating layer 135 may be a single film or a multilayer film consisting of laminated films of different materials.

[0074] The source electrode 140 and drain electrode 145 may be placed on the interlayer insulating layer 135. The source electrode 140 may be connected to the semiconductor layer 120 via a first contact hole CH1 that penetrates the interlayer insulating layer 135 and the gate insulating layer 125. The drain electrode 145 may be connected to the semiconductor layer 120 via a second contact hole CH2 that penetrates the interlayer insulating layer 135 and the gate insulating layer 125.

[0075] A connecting electrode 147 may be positioned between the source electrode 140 and the drain electrode 145. The connecting electrode 147 may serve to connect the circuit connected to the transistor TFT to the gate electrode 130. The connecting electrode 147 may be connected to the gate electrode 130 via a third contact hole CH3 that penetrates the interlayer insulating layer 135. For example, the connecting electrode 147 may be electrically connected to the scan line SCL. A data line DTL may be positioned on the interlayer insulating layer 135, spaced apart from the source electrode 140 and the drain electrode 145. The data line DTL may be electrically connected to either the source electrode 140 or the drain electrode 145.

[0076] The gate electrode 120, scan line SCL, source electrode 140, drain electrode 145, data line DTL, and connecting electrode 147 may contain one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The source electrode 140, drain electrode 145, data line DTL, and connecting electrode 147 may be single films or multilayer films. In this embodiment, an example in which such signal wiring contains Cu as the metal is described below as one aspect. However, while reactants may be formed when etching signal wiring containing metal, the spirit of the present invention is to provide a technique that can remove such reactants by etching, and the metal of the signal wiring is not limited to Cu unless it deviates from the spirit of the present invention.

[0077] The surface of the gate insulating layer 125 or interlayer insulating layer 135 described above may contain copper and chlorine. Here, the surface refers to the surface around at least one of the signal lines, including the gate electrode 130, scan line SCL, source electrode 140, drain electrode 145, or data line DTL. As will be described later, at least one of the signal lines, including the gate electrode 130, scan line SCL, source electrode 140, drain electrode 145, or data line DTL, contains copper and may be formed by a copper plasma etching process. In this case, at least one of the insulating layers on which the signal lines are formed, such as the gate insulating layer 125 or interlayer insulating layer 135, may have copper and chlorine remaining on its surface due to the copper plasma etching process. That is, when the copper plasma etching process described later is used, copper and chlorine may be detected on the surface of at least one of the gate insulating layer 125 or interlayer insulating layer 135. In one embodiment, at least one of the gate insulating layer 125 or interlayer insulating layer 135 may have a chlorine content greater than the copper content on its surface.

[0078] In one embodiment, if the spacing between at least one signal trace from the gate electrode 130, scan line SCL, source electrode 140, drain electrode 145, or data line DTL is S and the line width is L, then the ratio of the line width L to the spacing S of at least one signal trace (L / S) can be 1.1 / 1.5 to 1.1 / 1.1. For example, the ratio of the line width to the signal trace spacing (L / S) can be 1.1 / 1.5, 1.1 / 1.1, or 0.8 / 1.0. For example, the line width of the signal traces is in the range of 0.8 to 1.1, and the spacing of the signal traces is in the range of 1.0 to 1.5. Furthermore, when the ratio of the line width to the signal trace spacing is 1.1 / 1.5, a resolution of approximately 1700 ppi can be achieved, and when the ratio of the line width to the signal trace spacing is 1.1 / 1.1 or 0.8 / 1.0, a resolution of approximately 1500 ppi can be achieved. For example, by using the copper plasma etching method described later, a high resolution of approximately 1500 ppi to 1700 ppi can be achieved. Therefore, a display device 10 according to one embodiment can achieve a resolution of approximately 300 ppi to 1700 ppi.

[0079] In one embodiment, the above-described signal wiring may include not only the gate electrode 130, scan line SCL, source electrode 140, drain electrode 145, and data line DTL, but also the initialization voltage wiring VIL, sensing line SSL, first voltage wiring VDL, and second voltage wiring VSL shown in Figure 4, and may include all other signal wiring that can be formed of copper.

[0080] On the other hand, via layers 150 can be placed on the source electrode 140, drain electrode 145, data line DTL, and connecting electrode 147. The via layers 150 can flatten the step at the bottom and improve the film deposition properties of the first electrode 160 formed on top.

[0081] The via layer 150 may contain inorganic insulating materials or organic insulating materials such as acrylic resin (polyacrylates resin), epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenyleneethers resin, polyphenylenesulfides resin, or benzocyclobutene (BCB). The via layer 150 may be a single film or a multilayer film consisting of laminated films of different materials.

[0082] A light-emitting element EL may be placed on the via layer 150. The light-emitting element EL may include a first electrode 160, a light-emitting layer 165, and a second electrode 170.

[0083] The first electrode 160 may be placed on the via layer 150. The first electrode 160 may be arranged in a pattern shape on each pixel PX (also called sub-pixel SPX). The first electrode 160 may be the anode electrode of the light-emitting element EL. The first electrode 160 may be connected to the drain electrode 145 of the transistor TFT via a fourth contact hole CH4 that penetrates the via layer 150.

[0084] The first electrode 160 may contain a transparent conductive material. For example, the first electrode 160 may contain materials such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or ITZO (Indium Tin-Zinc Oxide). In some embodiments, the first electrode 160 may have a structure in which one or more layers of a transparent conductive material and a highly reflective metal layer are laminated, or these can be formed as a single layer. For example, the first electrode 160 may have a laminated structure such as ITO / silver (Ag) / ITO / , ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0085] A bank layer 155 may be placed on the first electrode 160. The bank layer 155 may include an opening OP that partially exposes the first electrode 160. The bank layer 155 is made of an organic or inorganic insulating material. For example, the bank layer 155 may contain at least one of the following: a photoresist, a polyimide resin, an acrylic resin, a silicon compound, or a polyacrylic resin.

[0086] The light-emitting layer 165 may be placed on the first electrode 160. The light-emitting layer 165 may further include at least one of the following: a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer. The light-emitting layer 165 may emit red, blue, and green light for each subpixel SPX, or it may emit white light. When the light-emitting layer 165 emits white light, red, blue, and green light can be realized via a wavelength conversion member, respectively.

[0087] A second electrode 170 may be placed on the light-emitting layer 165 and the bank layer 155. The second electrode 170 may be placed over the entire display area of ​​the substrate 110. The second electrode 170 may be a common electrode placed across multiple subpixels. The second electrode 170 may be the cathode electrode of the light-emitting element EL.

[0088] Furthermore, the gate electrode 130, scan line SCL, source electrode 140, drain electrode 145, connecting electrode 147, and data line DTL mentioned above may be included in the signal wiring as a metal layer (or conductive layer). These signal wirings are arranged throughout the display device 10 and play a role in transmitting various signals. The signal wiring may have low resistance characteristics so that signals are transmitted substantially equally to all pixels. Copper (Cu) is a typical metallic material that has low resistance characteristics.

[0089] The following describes a plasma etching method for signal wiring containing copper, based on the embodiments described below. While the material included in the signal wiring is not limited to copper, the following explanation will use copper as a representative example. Furthermore, the copper-containing signal wiring described below may also contain other metallic materials.

[0090] Figure 6 is a schematic diagram of an etching apparatus for copper plasma etching.

[0091] Referring to Figure 6, a copper plasma etching method according to one embodiment can be performed using an etching apparatus 200. The etching apparatus 200 may include a chamber CB, a susceptor SU, a microwave generator MWP, a magnetic field generator PSM, and a high-frequency power supply RFP. The etching apparatus 200 may also include a gas supply unit GSP, a gas exhaust unit GXP, and a cooling unit COL.

[0092] The etching apparatus 200 may be an electron cyclotron resonance (ECR) plasma etching apparatus capable of simultaneously using electric and magnetic fields to obtain a high-density plasma with a high plasma electron temperature. A magnetic field is formed inside the chamber CB by the magnetic field generation unit PSM, and microwaves generated by the microwave generation unit MWP can be input into the chamber CB. When the rotation frequency of electrons due to the magnetic field matches the microwave frequency, an electron cyclotron resonance phenomenon occurs. When gas is supplied to the ECR region (a region where an electromagnetic field exists that can accelerate electrons until the gas is ionized), the gas is ionized and a plasma is formed. Electrons in the plasma are accelerated by the resonance phenomenon as they pass through the ECR region, gaining a large amount of energy. These electrons have reduced diffusion loss due to the magnetic field, promoting gas ionization, and a high-density plasma with a high plasma electron temperature can be generated.

[0093] Chamber CB may provide a processing space in which the etching process is carried out. Chamber CH may maintain a vacuum state during the etching process. For example, Chamber CH may maintain a vacuum state during the etching process. -4 ~10 -2 Torr pressure can be provided. Plasma-induced etching gas can be formed within the processing space of chamber CH. Chamber CH may contain a ceramic material resistant to plasma.

[0094] The target substrate SB may correspond to a substrate on which the wiring and / or electrodes of the display device 10 described above are formed. The target substrate SB may include an insulating layer and at least one metal layer. For example, the target substrate SB provided to the etching apparatus 200 to form the data line DTL shown in Figure 5 may correspond to the multiple insulating layers 115, 125, 135 of a transistor laminated on the substrate 110 in Figure 5. Also, the metal layer of the target substrate SB to be etched may correspond to a copper layer deposited on the insulating layer for patterning as a data line DTL. However, it is not limited to this, and electrodes such as the gate electrode (130 in Figure 5) of the display device 10 or wiring such as a scan line SCL may be formed.

[0095] The susceptor SU may be positioned within the processing space provided by the chamber CH. The susceptor SU may be positioned so that the target substrate SB is located below the microwave generator MWP. The susceptor SU can support and transport the target substrate SB. The susceptor SU may support the target substrate SB so that the metal layer (copper layer in this example) of the target substrate SB to be etched faces the microwave generator MWP.

[0096] The magnetic field generating unit PSM can form a magnetic field within the processing space of the chamber CH above the target substrate SB. The magnetic field generating unit PSM can be positioned to surround a portion of the upper region of the chamber CH to form a magnetic field within the processing space of the chamber CH.

[0097] The microwave generator (MWP) may be positioned on the chamber CH. For example, the microwave generator (MWP) may be positioned facing the target substrate (SB), and the magnetic field generator (PSM) may be positioned between the microwave generator (MWP) and the target substrate (SB). The microwave generator (MWP) may provide microwaves within the region where the magnetic field is formed.

[0098] The high-frequency power supply (RFP) may be located outside the chamber (CH). The RFP may be connected to the susceptor (SU) to apply high-frequency RF to the susceptor (SU). The output frequency of the RFP may be in the range of several hundred kHz to several tens of MHz. Performing plasma etching together with the high frequency of the RFP may be advantageous for anisotropic etching due to the addition of the ionic reaction of reactive ion etching (RIE).

[0099] The gas supply unit GSP may be located above the chamber CH. The gas supply unit GSP may be located between the microwave generator MWP and the magnetic field generator PSM and may supply etching gas. In one embodiment, the gas supply unit GSP may supply a first etching gas and a second etching gas.

[0100] The gas exhaust section GXP may be located below the chamber CH, but is not limited to this, and may also be located above the chamber CH. The gas exhaust section GXP may include a vacuum pump. The gas exhaust section GXP can operate the vacuum pump to maintain a vacuum inside the chamber CB and exhaust etching gases when the etching reaction is stopped.

[0101] The cooling unit COL may be located below the chamber CH. The cooling unit COL may be connected to the susceptor SU to cool the susceptor SU. The cooling unit COL can cool the susceptor SU to a temperature of several tens of degrees below zero, and maintain the surface temperature of the target substrate SB below 80 degrees. Furthermore, it is sufficient that each component of the etching apparatus 200 can perform its function, and the arrangement of each component of the etching apparatus 200, such as the chamber CB, susceptor SU, microwave generator MWP, magnetic field generator PSM, high-frequency power supply RFP, gas supply GSP, gas exhaust GXP, and cooling unit COL, is not limited to the above arrangement.

[0102] The steps of a copper plasma etching method according to one embodiment will be described below with reference to the drawings.

[0103] Figure 7 is a flowchart of a copper plasma etching method according to one embodiment. The copper plasma etching method according to one embodiment can be performed in the plasma etching chamber described above.

[0104] Referring to Figure 7, a copper plasma etching method according to one embodiment may include a step of placing the target substrate (S100), a first etching step S200 of supplying a first gas to plasma etch the metal layer, a first gas discharge step (S300), and a second etching step (S400) of supplying a second gas to plasma etch the metal layer.

[0105] The step of placing the target substrate (S100) involves placing the target substrate inside the chamber. The target substrate may include a metal layer to be etched. In this embodiment, the metal layer may include copper. The metal layer may be formed by depositing it onto the target substrate to form the signal wiring of the display device described above. The target substrate may be placed on a susceptor of the chamber and then placed inside the chamber.

[0106] The first etching step S200 can first etch a metal layer formed on the target substrate. The first gas supplied in the first etching step S200 may contain chlorine. The first gas is for plasma etching of the metal layer and may contain, for example, one or more selected from the group consisting of Cl2, CCl4, BCl3, SiCl2, HCl, PCl3, CH2Cl2F, CHClF2, CCl2F2, and ICl. In the first etching step S200, the metal layer of the target substrate can be etched by plasma.

[0107] The first gas can be plasma-generated by the microwave and magnetic field generators described above. For example, chlorine in the first gas can be plasma-generated by the microwave and magnetic field generators and react with the copper in the metal layer in the form of ions or radicals. The first etching step S200 may be a step in which the copper and chlorine in the first gas react to form a reactant.

[0108] The first gas discharge step (S300) allows the first gas present in the chamber to be discharged to the outside of the chamber. In one embodiment, the first gas can be completely removed from the chamber in the first gas discharge step (S300). In other embodiments, in the first gas discharge step (S300), a portion of the first gas may be discharged from the chamber, with the remainder remaining inside the chamber. The first gas can be discharged via a pump provided at the chamber's outlet.

[0109] The second etching step (S400) may second-etch the metal layer formed on the target substrate. The second gas supplied in the second etching step (S400) may contain hydrogen. The second gas is for plasma etching the metal layer and may contain, for example, H2.

[0110] In the second etching step (S400), the metal layer of the target substrate can be etched by plasma. The second gas can be plasma-generated by a microwave generator and a magnetic field generator, which will be described later. For example, hydrogen in the second gas can be plasma-generated by the microwave generator and the magnetic field generator and can react with reactants formed in the first etching step S200 in the form of ions or radicals (for example, reactants formed by the reaction of copper and chlorine). When the reactants react with hydrogen, a reaction gas is generated and the reactants can be removed, so that the metal layer can be etched.

[0111] The steps of a copper plasma etching method according to one embodiment will be described below with reference to the drawings.

[0112] Figures 8 to 11 show the steps of a copper plasma etching method according to one embodiment.

[0113] Referring to Figure 8 in conjunction with Figures 6 and 7, the step of placing the target substrate (S100) is performed. The target substrate SB may be placed on the susceptor SU in the chamber CB. The target substrate SB may have a copper-containing metal layer MEL laminated on it. The target substrate SB may also be positioned so that the metal layer MEL faces upwards. An etching mask MS may be formed on the metal layer MEL of the target substrate SB. The etching mask MS may be a photoresist pattern or a hard mask pattern.

[0114] Next, after the target substrate SB is placed on the susceptor SU, the first etching step S200 is performed in which the first gas is supplied to plasma etch the metal layer MEL.

[0115] Specifically, the chamber CB of the etching apparatus 200 is brought into a vacuum state. The inside of the chamber CB can be brought into a vacuum state via the vacuum pump of the gas exhaust section GXP, 10 -4 ~10 -2 Torr pressure can be formed.

[0116] Next, the microwave generator (MWP) supplies microwaves into the chamber (CB), and the magnetic field generator (PSM) forms a magnetic field within the chamber (CB). Simultaneously, the high-frequency power supply (RFP) applies high frequency to the susceptor (SU).

[0117] Subsequently, a first gas is supplied into the chamber CB. The first gas is for plasma etching the metal layer MEL and can be supplied into the chamber CB via the gas supply unit GSP. The first gas may contain chlorine. For example, the first gas may contain one or more selected from the group consisting of Cl2, CCl4, BCl3, SiCl2, HCl, PCl3, CH2Cl2F, CHClF2, CCl2F2, and ICl.

[0118] Within the chamber CB, a first gas is supplied, and a plasma of the first gas, for example, a first plasma gas, is formed by the microwaves from the microwave generator MWP and the magnetic field from the magnetic field generator PSM. Because the first gas contains chlorine, the first plasma gas PZG1 may contain chloride ions and chlorine radicals. The metal layer MEL of the target substrate SB, which is not covered by the etching mask MS, is etched by chloride ions and chlorine radicals.

[0119] In the first etching step S200, the following reactions may occur sequentially or independently.

[0120] Cu(s) + 1 / 2Cl2(g) = CuCl(s) CuCl(s) + 1 / 2Cl2(g) = CuCl2(s) Cu(s) + Cl2(g) = CuCl2(g) 3Cu(s) + 3 / 2Cl2(g) = Cu3Cl3(g) Here, (s) is the solid state and (g) is the gaseous state.

[0121] As shown in Figure 9, chloride ions and chlorine radicals in the first plasma gas PZG1 generated in the first etching step S200 can react with the metal layer to form the reaction product RGM. For example, chloride ions and chlorine radicals can react with the copper in the metal layer to form solid CuCl and CuCl2 of the reaction product RGM, and gaseous CuCl2 and Cu3Cl3. Here, the gaseous CuCl2 and Cu3Cl3 vaporize and are exhausted to the outside of the chamber CB, while the solid CuCl and CuCl2 are deposited on the surface of the target substrate SB or on the inner wall of the chamber CB. In particular, CuCl and CuCl2 have boiling points of approximately 324°C and 280°C at 1 mTorr, respectively, making removal at low temperatures difficult. On the other hand, Cu3Cl3 has a boiling point of approximately 139°C at 1 mTorr, making removal easy even at low temperatures.

[0122] Figure 12 is a graph showing the Gibbs free energy of reaction products with respect to temperature. In Figure 12, the Gibbs free energy is calculated using -△G° / RT and shown on the vertical axis, while the temperature T is shown on the horizontal axis. △G° is the standard Gibbs free energy, R is the base constant, and T is the absolute temperature.

[0123] Referring to Figure 12, CuCl and CuCl2 exhibit a Gibbs free energy of -△G° / RT of less than approximately 20 at temperatures ranging from 50°C to 150°C, while CuH and Cu3Cl3 exhibit a Gibbs free energy of -△G° / RT of approximately 60 or more. This indicates that CuH and Cu3Cl3 vaporize more easily at lower temperatures than CuCl and CuCl2.

[0124] In the second etching step (S200), described later, copper plasma etching can be facilitated by generating Cu3Cl3, which is in a gaseous state at low temperatures, and CuH, which can be vaporized at room temperature, from the solid CuCl and CuCl2 generated in the first etching step S200.

[0125] Referring again to Figure 7, after the first etching step S200, a first gas discharge step (S300) is performed to discharge the first gas.

[0126] The first gas discharge stage (S300) can be performed by stopping the supply of the first gas. Specifically, the pressure in the chamber CB is maintained by the operation of the vacuum pump in the gas exhaust section GXP. When the supply of the first gas is stopped, the first gas, first plasma gas, and reaction products present in the chamber CB can be discharged to the gas exhaust section GXP via the vacuum pump.

[0127] In the first gas discharge stage (S300), at least a portion of the first gas may be discharged. For example, all of the first gas present in the chamber CB may be removed. In another example, at least a portion of the first gas may remain in the chamber CB. The first gas discharge stage (S300) may be performed for several seconds to several tens of seconds.

[0128] Next, a second etching step (S400) is performed in which a second gas is supplied to plasma etch the metal layer MEL.

[0129] Specifically, a second gas is supplied into the chamber CB. The second gas is for removing the reaction product RGM generated in the first etching step S200 and can be supplied into the chamber CB via the gas supply unit GSP. The second gas may contain hydrogen. For example, the second gas may contain H2.

[0130] Within the chamber CB, a second gas is supplied, and a plasma of the second gas, for example, a second plasma gas, is formed by the microwaves from the microwave generator MWP and the magnetic field from the magnetic field generator PSM. Because the second gas contains hydrogen, the second plasma gas PZG2 may contain hydrogen ions and hydrogen radicals. The reaction product RGM formed on the target substrate SB is etched by the hydrogen ions and hydrogen radicals.

[0131] In the second etching step (S400), the following reactions may occur sequentially or independently.

[0132] 3CuCl2(s)+3H(g)=Cu3Cl3(g)+3HCl(g) CuCl2(s) + 3H(g) = CuH(g) + 2HCl(g) CuCl(s) + 2H(g) = CuH(g) + HCl(g) 3CuCl2(s)+3 / 2H2(g)=Cu3Cl3(g)+3HCl(g) Here, (s) is the solid state and (g) is the gaseous state.

[0133] As shown in Figures 10 and 11, hydrogen ions and hydrogen radicals in the second plasma gas PZG2 generated in the second etching step (420) can react with the reaction product RGM to remove it. For example, hydrogen ions and hydrogen radicals can react with the reaction product RGM to produce the reaction products, which are gaseous HCl, CuH, and Cu3Cl3. HCl, CuH, and Cu3Cl3 can vaporize in a gaseous state even at low temperatures below about 150 degrees Celsius and be exhausted to the outside of chamber CB.

[0134] Furthermore, the temperature inside the chamber CB may rise due to the heat generated during the etching process and the energy of the plasma itself. In this case, a problem may arise in which some of the reaction products RGM, such as CuCl and CuCl2, vaporize and are re-deposited inside the chamber CB. To prevent the re-depositing of reaction products, one alternative solution is to cool the temperature of the target substrate SB.

[0135] In one embodiment, the target substrate SB may be cooled to a low temperature of approximately 150 degrees Celsius or lower to remove the above-mentioned reaction products.

[0136] As shown in Figure 6, the cooling unit COL provided in the etching apparatus 200 can cool the target substrate SB via the susceptor SU. The cooling unit COL can cool the temperature of the susceptor SU to 10 degrees or less, and can also cool it to 0 degrees or less, or to -20 degrees or less. The surface temperature of the target substrate SB may be 80 degrees or less.

[0137] In one embodiment, the surface temperature of the target substrate SB can be maintained at 80 degrees Celsius or lower during the copper plasma etching method. This prevents solid CuCl and CuCl2 from vaporizing and being re-deposited onto the surface of the target substrate SB or the inner wall of the chamber CB. Furthermore, since Cu3Cl3 has a boiling point of approximately 139 degrees Celsius at 1 mTorr, it can be easily removed even at low temperatures. This eliminates the need for heat or additional energy to remove Cu3Cl3, thereby improving productivity.

[0138] In one embodiment, since Cu3Cl3 has a boiling point of approximately 139 degrees Celsius at 1 mTorr, it can be easily removed even at low temperatures, thus enabling the copper plasma etching method to be performed at low temperatures. When conventional copper plasma etching methods are performed at high temperatures, a plasma source that emits high density and high electron energy is required to remove reaction products. In this case, if a photoresist pattern is used as an etching mask for the copper layer (or metal layer), the photoresist pattern is damaged by the plasma source, making it difficult to use as an etching mask. However, in this embodiment, since the copper plasma etching method can be performed at low temperatures, there is an advantage in that a photoresist pattern can be used as an etching mask.

[0139] In one embodiment, the first etching step S200 and the second etching step (S400) constitute a single cycle, and the cycle can be performed multiple times. For example, the first etching step and the second etching step can be performed alternately. More specifically, the first etching step can be performed by supplying the first etching gas, discharging the first etching gas, and then the second etching step can be performed by supplying the second etching gas. Next, the second etching gas can be discharged, the first etching step can be performed again by supplying the first etching gas, discharging the first etching gas, and then the second etching step can be performed by supplying the second etching gas.

[0140] By performing the first and second etching stages in multiple cycles, it is possible to prevent the copper metal layer from remaining unetched and improve the reliability of the etching process.

[0141] The following describes other copper plasma etching methods according to other embodiments with reference to other drawings.

[0142] Figure 13 is a flowchart of a copper plasma etching method according to another embodiment. Figures 14 and 15 show the steps of a copper plasma etching method according to one embodiment.

[0143] Referring to Figure 13, one embodiment of the copper plasma etching method may include the steps of placing the target substrate (S500), supplying the first gas and the second gas (S510), and plasma etching the metal layer (S520). One embodiment differs from the embodiments in Figures 7 to 12 described above in that the first gas and the second gas are supplied simultaneously to plasma etch the metal layer. In the following, redundant explanations of the same configuration as the embodiments described above will be omitted, and the differences will be explained.

[0144] Referring to Figure 14 in conjunction with Figure 13, the step of placing the target substrate (S500) is performed. The target substrate SB may be placed on the susceptor SU in the chamber CB. The target substrate SB may have a copper-containing metal layer MEL laminated on it, and an etching mask MS may be formed on the metal layer MEL. The etching mask MS may be a photoresist pattern or a hard mask pattern.

[0145] Next, the step of supplying the first gas and the second gas (S510) is performed.

[0146] Specifically, in the chamber CB of the etching apparatus 200, a vacuum and 10 -4 ~10 -2 Torr pressure is formed. Next, microwaves are supplied into chamber CB, forming a magnetic field within chamber CB. Simultaneously, a high frequency is applied to the susceptor SU by the high-frequency power supply unit RFP.

[0147] Subsequently, a first gas and a second gas are supplied into the chamber CB. The first and second gases are for plasma etching the metal layer MEL and can be supplied into the chamber CB via a gas supply unit GSP. The first gas may contain chlorine, for example, one or more selected from the group consisting of Cl2, CCl4, BCl3, SiCl2, HCl, PCl3, CH2Cl2F, CHClF2, CCl2F2, and ICl. The second gas may contain hydrogen, for example, H2.

[0148] Next, the metal layer MEL is etched. In the chamber CB, a first gas and a second gas are supplied, and the microwaves from the microwave generator MWP and the magnetic field from the magnetic field generator PSM generate a first plasma gas and a second plasma gas. For example, if the first gas contains chlorine, the first plasma gas PZG1 may contain chloride ions and chlorine radicals, and the second plasma gas PZG2 may contain hydrogen ions and hydrogen radicals. The metal layer MEL of the target substrate SB, which is not covered by the etching mask MS, is etched by chloride ions, hydrogen ions, chlorine radicals, and hydrogen radicals.

[0149] Specifically, the following reactions may occur sequentially or independently.

[0150] Cu(s) + 1 / 2Cl2(g) = CuCl(s) CuCl(s) + 1 / 2Cl2(g) = CuCl2(s) Cu(s) + Cl2(g) = CuCl2(g) 3Cu(s) + 3 / 2Cl2(g) = Cu3Cl3(g) 3CuCl2(s)+3H(g)=Cu3Cl3(g)+3HCl(g) CuCl2(s) + 3H(g) = CuH(g) + 2HCl(g) CuCl(s) + 2H(g) = CuH(g) + HCl(g) 3CuCl2(s)+3 / 2H2(g)=Cu3Cl3(g)+3HCl(g) Here, (s) is the solid state and (g) is the gaseous state.

[0151] In the embodiments shown in Figures 7 to 12 above, the above-described reactions occurred sequentially by separating the first etching step and the second etching step. However, in this embodiment, by supplying the first and second etching gases simultaneously, the above-described reactions can occur almost simultaneously.

[0152] As shown in Figures 14 and 15, chloride ions and chlorine radicals in the first plasma gas PZG1 react with the metal layer MEL to form the reaction product RGM, and the reaction product RGM is etched and removed by hydrogen ions and hydrogen radicals in the second plasma gas PZG2. For example, the reaction product RGM generated by the first plasma gas PZG1 can be formed and removed by the second plasma gas PZG2 almost simultaneously. The reaction in which the reaction product RGM is formed by the first plasma gas PZG1 and the reaction in which the reaction product RGM is removed by the second plasma gas PZG2 are the same as those in the embodiments of Figures 7 to 12 described above, so redundant explanations are omitted.

[0153] In one embodiment, by simultaneously supplying a first gas and a second gas for copper plasma etching and plasma etching the copper metal layer, the etching time of the copper metal layer can be shortened and productivity can be improved.

[0154] Figure 16 is a flowchart of a copper plasma etching method according to another embodiment.

[0155] Referring to Figure 16, one embodiment of the copper plasma etching method may include the steps of placing the target substrate (S600), supplying gas (S610), and plasma etching the metal layer (S560). One embodiment differs from the embodiments in Figures 13 to 15 described above in that a single gas is supplied to plasma etch the metal layer. In the following, redundant explanations of the same configuration as the embodiments described above will be omitted, and the differences will be explained.

[0156] Referring to Figure 16, the steps of placing the target substrate (S600) and supplying gas (S610) are performed. The gas is for plasma etching the metal layer MEL and can be supplied into the chamber CB via the gas supply unit GSP. The first gas may contain chlorine, for example, HCl.

[0157] Next, the metal layer MEL is etched (S620). A plasma gas is generated in the chamber CB by microwaves and a magnetic field. For example, if the gas contains chlorine, the first plasma gas may contain chloride ions and chlorine radicals, and if the gas contains hydrogen, it may contain hydrogen ions and hydrogen radicals. The metal layer MEL of the target substrate SB, which is not covered by the etching mask MS, is etched by chloride ions, hydrogen ions, chlorine radicals, and hydrogen radicals.

[0158] In one embodiment, HCl may be supplied as the etching gas. In this case, the first etching gas does not need to contain H2. In one embodiment, the same reactions as those in the embodiments of Figures 13 to 15 described above may occur almost simultaneously. For example, chloride ions and chlorine radicals in the first plasma gas react with the metal layer to form reaction products, and these reaction products can be etched and removed by hydrogen ions and hydrogen radicals in the second plasma gas. In other words, HCl, which is the etching gas, can become chloride ions and chlorine radicals, hydrogen ions and hydrogen radicals, when plasma-activated. The above-described reactions occur with chloride ions and chlorine radicals as the first plasma gas, and the above-described reactions occur with hydrogen ions and hydrogen radicals as the second plasma gas. As a result, reactions similar to those described above occur.

[0159] As described above, by supplying a single gas of HCl for copper plasma etching and plasma etching the copper metal layer, the etching process can be simplified, the etching time of the copper metal layer can be shortened, and productivity can be improved.

[0160] The following are experimental examples of the copper plasma etching method according to the embodiments described above. However, the present invention is not limited to the experimental examples below.

[0161] <Experimental Example 1> A copper plasma etching method was implemented to form copper wiring using HCl and H2 gas. Specifically, a copper metal layer was laminated on a glass substrate, a silicon oxide (SiOx) layer was laminated on the copper metal layer as a hard mask, and a photoresist pattern was formed on the silicon oxide layer. In this process, plasma etching was performed using electron cyclotron resonance, and the etching process was 10 -2 The Torr pressure test was performed for approximately 120 seconds, maintaining the substrate surface temperature below 80 degrees Celsius.

[0162] Figure 17 shows the ADI image of the copper wiring edge after development according to Experimental Example 1. Figure 18 shows the ADI image of the copper wiring center after development according to Experimental Example 1. Figure 19 shows the AEI image of the copper wiring edge after etching according to Experimental Example 1. Figure 20 shows the AEI image of the copper wiring center after etching according to Experimental Example 1. Figure 21 shows the ACI image of the copper wiring edge after cleaning according to Experimental Example 1. Figure 22 shows the ACI image of the copper wiring center after cleaning according to Experimental Example 1.

[0163] Referring to Figures 17 and 18, a copper metal layer (MEL), a hard mask layer (MSL), and a photoresist pattern (PRP) were formed on a glass substrate (SB). The line width of the photoresist pattern (PRP) at the edges of the formed copper wiring was approximately 2.26 μm, and the line width of the photoresist pattern (PRP) in the central part was approximately 2.19 μm.

[0164] Referring to Figures 19 and 20, a hard mask MSK was formed by etching the hard mask layer using a photoresist pattern PRP as a mask. The line width of the hard mask MSK at the edges of the formed copper wiring was approximately 1.92 μm, and the line width of the hard mask MSK in the central part was approximately 1.86 μm.

[0165] Referring to Figures 21 and 22, a hard mask MSK was used as a mask to etch the metal layer and form copper wiring CML. The line width of the edge portion of the copper wiring CML was approximately 1.98 μm, and the line width of the central portion of the copper wiring CML was approximately 1.84 μm.

[0166] Experimental Example 1 showed that the skew value of the copper wiring (the difference between the line width inspected after etching and the line width inspected after cleaning) was approximately -0.06 μm at the edges and approximately 0.02 μm in the center. In other words, at the edges, the line width of the copper wiring CML was 1.98 μm compared to the line width of the hard mask of 1.92 μm, resulting in a line width difference of 1.92 - 1.98 = -0.06 μm. In the center, the line width of the copper wiring CML was 1.84 μm compared to the line width of the hard mask of 1.86 μm, resulting in a line width difference of 1.86 - 1.84 = 0.02 μm. For example, the skew value of the copper wiring was formed within the range of -0.06 μm to 0.02 μm, confirming that the skew value was close to 0.

[0167] By using the copper plasma etching method according to the above embodiment, the ratio of line width L to the spacing S of copper wiring (L / S) can be set to 1.1 / 1.5 to 1.1 / 1.1. For example, the ratio of line width to the spacing of copper wiring (L / S) can be set to 1.1 / 1.5, 1.1 / 1.1, or 0.8 / 1.0. For example, the line width of the copper wiring is in the range of 0.8 to 1.1, and the spacing of the copper wiring is in the range of 1.0 to 1.5. Furthermore, when the ratio of line width to the spacing of copper wiring is 1.1 / 1.5, a resolution of approximately 1700 ppi can be achieved, and when the ratio of line width to the spacing of signal wiring is 1.1 / 1.1 or 0.8 / 1.0, a resolution of approximately 1500 ppi can be achieved. Therefore, by using the above copper plasma etching method, a high resolution of approximately 1500 ppi to 1700 ppi can be achieved. Therefore, a display device according to one embodiment can achieve a resolution of approximately 300 ppi to 1700 ppi. In other words, in copper plasma etching according to Experimental Example 1 using the method of the above embodiment, the line width of the copper wiring deviates very little from the line width of the hard mask. Therefore, the line width of the copper wiring can be precisely adjusted to the desired line width. Because the line width of the copper wiring can be precisely adjusted in this way, the spacing between adjacent copper wirings can also be precisely adjusted. This means that even if the desired line width and spacing of the copper wiring are small, copper wiring can be formed with high accuracy. Therefore, as mentioned above, high resolution can be achieved.

[0168] <Experimental Example 2> Under the same process conditions as in Experimental Example 1, the copper metal layer was etched using only a photoresist pattern instead of a hard mask. Specifically, a copper metal layer was laminated on a glass substrate, and a photoresist pattern was formed on the copper metal layer.

[0169] Figure 23 shows the inspection (ADI) image of the copper wiring after development according to Experimental Example 2. Figure 24 shows the inspection (AEI) image of the copper wiring after etching according to Experimental Example 2. Figure 25 shows the inspection (ACI) image of the copper wiring after cleaning according to Experimental Example 2.

[0170] Referring to Figure 23, a copper metal layer (MEL) and a photoresist pattern (PRP) were formed on a glass substrate (SB). At this time, the thickness of the photoresist pattern (PRP) was approximately 3.0 μm.

[0171] Referring to Figure 24, copper plasma etching was performed using a photoresist pattern PRP as a mask to form copper wiring CML. At this time, the residual thickness of the photoresist pattern PRP was approximately 2.3 μm.

[0172] Referring to Figure 25, the photoresist pattern PRP was removed. The image shows that the photoresist pattern was completely removed without any residue. In other words, referring to Figure 25, the photoresist pattern PRP that was present on the copper wiring CML in Figure 24 has disappeared.

[0173] This confirmed that copper plasma etching can be performed using only the photoresist pattern, without the need for a hard mask.

[0174] <Experimental Example 3> An insulating layer (INS) was formed on a glass substrate by laminating silicon oxide (SiOx), and a copper metal layer was then laminated on top of the INS and etched to form copper wiring (CML). The etching method varied between plasma etching and wet etching as described in the above embodiment, and the mask configuration also varied, using a photoresist pattern and a hard mask. Furthermore, the presence or absence of a mask stripping process was also varied. XPS analysis (X-ray Photoelectron Spectroscopy) was performed on the surface of the insulating layer (INS) where the copper wiring CML was not present, for each condition.

[0175] Figure 26 is an image showing the insulating layer and copper wiring manufactured according to Experimental Example 3. Figure 26 shows a plan view in which the insulating layer is formed as the lower layer and the copper wiring is formed on top of the insulating layer. Figure 27 is a table showing the XPS analysis results of the insulating layer according to Experimental Example 3. The terms in Figure 27 are as follows: In the Mask column, PR Mask is the photoresist pattern, Hard Mask is the hard mask, the number in the # column is the sample number, in the Strip column, ○ indicates that the mask stripping process was performed, × indicates that the mask stripping process was not performed, and the Point column indicates the observed area, showing whether it is the edge or the center. In Atomic%, the results of the XPS analysis of each atom are shown. For example, in C1s, the Atomic% of carbon is shown, calculated from the energy level of the photoelectrons corresponding to the carbon 1S orbital. Ratio is the proportion. N / D means not detected.

[0176] Referring to Figure 26, it was confirmed that copper wiring CML was formed on the insulating layer INS in Experimental Example 3.

[0177] Referring to Figure 27, no chlorine (Cl) or copper (Cu) was detected on the surface of the insulating layer after wet etching of copper wiring using a hard mask.

[0178] In contrast, during the copper plasma etching process using a photoresist pattern, chlorine and copper were detected on the surface of the insulating layer regardless of whether a stripping process was performed. In particular, when the stripping process was not performed, the amount of chlorine and copper detected was higher than when the stripping process was performed. Furthermore, when the stripping process was performed, the chlorine content was detected in a higher amount than the copper content.

[0179] These results confirmed the detection of copper and chlorine on the insulating layer surface after the copper plasma etching process. Specifically, the atomic ratio of chlorine on the insulating layer surface was approximately 0.29 at% to 1.87 at%, and the atomic ratio of copper was approximately 0.27 at% to 2.40 at%.

[0180] In one embodiment, the copper plasma etching process described above can be monitored in various ways. For example, the copper plasma etching process can be monitored by detecting the moment of completion of the etching process using OES (Optical Emission Spectroscopy), RGA (Remain Gas Analyzer), QMS (Quadraple Mass Spectrometer), etc., and by analyzing the amount of etching by-products and vaporized substances.

[0181] The above describes examples in which copper is included as a metallic material with low resistance properties in various signal wiring. It then explains copper plasma etching when copper is included in the signal wiring. However, even when metallic materials other than copper are included in the signal wiring, etching with a similar concept to the copper plasma etching described above can be used, taking into account the properties of the other metallic material.

[0182] Although embodiments of the present invention have been described above with reference to the attached drawings, any person with ordinary skill in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without altering its technical idea or essential features. Therefore, the above embodiments are illustrative in all respects and should not be interpreted as limiting. [Explanation of symbols]

[0183] 1 Electronic equipment 10 Display device 110 circuit boards EL light-emitting element 200 Etching equipment CB Chamber

Claims

1. circuit board and An insulating layer disposed on the substrate, At least one transistor disposed on the insulating layer, Displaced on the insulating layer and electrically connected to at least one signal wiring to the at least one transistor, Includes a light-emitting element connected to at least one transistor, The aforementioned signal wiring includes copper, The surface of the insulating layer contains chlorine, and the device is a display device.

2. The display device according to claim 1, wherein the surface of the insulating layer further contains copper.

3. The display device according to claim 2, wherein the chlorine content is greater than the copper content.

4. The display device according to claim 1, wherein the ratio of the line width to the spacing of at least one signal wiring is 1.1 / 1.5 to 1.1 / 1.

1.

5. The display device according to claim 1, wherein the at least one signal line is at least one of a scan line, a data line, an initialization voltage line, a sensing line, a first voltage line, and a second voltage line electrically connected to the at least one transistor.

6. The steps include placing a substrate in which a metal layer containing copper has been formed inside the chamber, The steps include supplying a first gas containing chlorine into the chamber, A copper plasma etching method comprising a first etching step of plasma etching the metal layer.

7. The first chlorine-containing gas is Cl ２ , CCl ４ , BCl ３ , SiCl ２ , HCl, PCl ３ , CH ２ Cl ２ F, CHClF ２ , CCl ２ F ２ and ICl, comprising at least one selected from the group consisting of, the copper plasma etching method according to claim 6.

8. The first gas is H ２ The copper plasma etching method according to claim 6, which does not include the following.

9. The copper plasma etching method according to claim 6, wherein the first gas comprises HCl.

10. After the first etching step, The step of discharging the first gas, The copper plasma etching method according to claim 6, further comprising a second etching step of supplying a second gas containing hydrogen into the chamber to plasma etch the metal layer.

11. The second gas containing hydrogen is H ２ The copper plasma etching method according to claim 10, including the method described in claim 10.

12. The copper plasma etching method according to claim 10, wherein the substrate has a photoresist pattern formed on the metal layer as an etching mask.

13. The copper plasma etching method according to claim 10, wherein the first etching step and the second etching step constitute a cycle, and the cycle is performed multiple times.

14. The copper plasma etching method according to claim 6, wherein the surface temperature of the substrate is 80 degrees or less.

15. The aforementioned plasma etching process results in the following reaction: Copper (s) + 1 / 2Cr ２ (g)=CuCl(s) CuCl(s)+1 / 2Cl ２ (g)=CuCl ２ (s) Copper (s) + Cl ２ (')=CuMCu, ２ (') 31 / (s)+3 / 2- ２ (')=Cu ３ Cl ３ (') 3CuCl ２ (s)+3H(g)=Cu ３ Cl ３ (g)+3HCl(g) CuCl ２ (s)+3H(g)=CuH(g)+2HCl(g) CuCl (s) + 2H (g) = CuH (g) + HCl (g) 33uCl ２ (1)+3022 ２ (g=Cu ３ 3l ３ (g+323,g) The copper plasma etching method according to claim 6, wherein (s) is in a solid state and (g) is in a gaseous state.

16. A display device that displays images, A memory in which data information necessary for the operation of the display device is stored, A processor that executes the application stored in the aforementioned memory, Includes a power supply module that supplies power to the display device, the memory, and the processor, The aforementioned display device is circuit board and An insulating layer disposed on the substrate, At least one transistor disposed on the insulating layer, Displaced on the insulating layer and electrically connected to at least one signal wiring to the at least one transistor, Includes a light-emitting element connected to at least one transistor, The aforementioned signal wiring includes copper, The surface of the insulating layer contains chlorine, in an electronic device.

17. The electronic device according to claim 16, wherein the display device has a resolution of 300 ppi to 1700 ppi.

18. The electronic device according to claim 16, wherein the surface of the insulating layer further contains copper.

19. The electronic device according to claim 18, wherein the chlorine content is greater than the copper content.

20. The electronic device according to claim 16, wherein the ratio of the line width to the spacing of at least one signal wiring is 1.1 / 1.5 to 1.1 / 1.1.

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