Printed circuit boards and package boards including the same

Abstract

The present invention provides printed circuit boards and package substrates that can stably realize fine patterns and improve reliability by suppressing copper migration and other issues. [Solution] This disclosure relates to a printed circuit board and a package substrate including the same, which includes a first insulating layer, a first conductor pattern disposed on the first insulating layer, a first insulating film that covers at least a portion of the upper surface of the first insulating layer and at least a portion of the upper surface and side surface of the first conductor pattern, and extends between the upper surface of the first insulating layer and the lower surface of the first conductor pattern, and a second insulating layer disposed on the first insulating film, wherein the thickness of the portion of the first insulating film that covers the upper surface of the first insulating layer is C, and the thickness of the portion of the first insulating film that extends between the upper surface of the first insulating layer and the lower surface of the first conductor pattern is E, and C > E.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a printed circuit board and a package substrate including the same.

BACKGROUND ART

[0002] Recently, photosensitive insulating materials have been used as materials for insulating layers in order to form fine patterns. However, when fine patterns are realized using a photosensitive insulating material, reliability risks such as copper migration may occur.

SUMMARY OF INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0003] One of various objectives of the present disclosure is to provide a printed circuit board and a package substrate that can stably realize fine patterns.

[0004] Another one of various objectives of the present disclosure is to provide a printed circuit board and a package substrate that can suppress copper migration and the like to improve reliability.

MEANS FOR SOLVING PROBLEMS

[0005] One of various solutions provided through the present disclosure is to enclose the top surface, side surfaces and bottom surface of a conductor pattern with an insulating film that satisfies a specific thickness relationship.

[0006] For example, a printed circuit board according to an example includes a first insulating layer, a first conductor pattern disposed on the first insulating layer, a first insulating film that covers at least a portion of the top surface of the first insulating layer and at least a portion of each of the top surface and side surfaces of the first conductor pattern and extends between the top surface of the first insulating layer and the bottom surface of the first conductor pattern, and a second insulating layer disposed on the first insulating film, wherein when the thickness of the portion of the first insulating film that covers the top surface of the first insulating layer is defined as C, and the thickness of the portion of the first insulating film that extends between the top surface of the first insulating layer and the bottom surface of the first conductor pattern is defined as E, C>E can be satisfied.

[0007] For example, one example of a package substrate includes a circuit board and an interconnect member disposed inside the circuit board, and the interconnect member may include the printed circuit board described above. [Effects of the Invention]

[0008] As one of the various effects of this disclosure, it is possible to provide printed circuit boards and package substrates that can stably realize fine patterns.

[0009] Another effect of the various effects of this disclosure is that it is possible to provide printed circuit boards and package boards that can improve reliability by suppressing copper migration and the like. [Brief explanation of the drawing]

[0010] [Figure 1] This is a block diagram illustrating an example of an electronic equipment system. [Figure 2] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 3] Figure 2 is a schematic enlarged cross-sectional view of the R1 region of the printed circuit board. [Figure 4] Figure 2 is a schematic, enlarged cross-sectional view of the R2 region of the printed circuit board. [Figure 5a] Figure 2 is a schematic cross-sectional view showing a manufacturing example of the R1 region of a printed circuit board. [Figure 5b] Figure 2 is a schematic cross-sectional view showing a manufacturing example of the R1 region of a printed circuit board. [Figure 5c] Figure 2 is a schematic cross-sectional view showing a manufacturing example of the R1 region of a printed circuit board. [Figure 5d] Figure 2 is a schematic cross-sectional view showing a manufacturing example of the R1 region of a printed circuit board. [Figure 5e] Figure 2 is a schematic cross-sectional view showing a manufacturing example of the R1 region of a printed circuit board. [Figure 5f] FIG. 2 is a process cross-sectional view schematically showing an example of manufacturing the R1 region of the printed circuit board. [Figure 5g] FIG. 2 is a process cross-sectional view schematically showing an example of manufacturing the R1 region of the printed circuit board. [Figure 5h] FIG. 2 is a process cross-sectional view schematically showing an example of manufacturing the R1 region of the printed circuit board. [Figure 6a] FIG. 2 is a process cross-sectional view schematically showing an example of manufacturing the R2 region of the printed circuit board. [Figure 6b] FIG. 2 is a process cross-sectional view schematically showing an example of manufacturing the R2 region of the printed circuit board. [Figure 6c] FIG. 2 is a process cross-sectional view schematically showing an example of manufacturing the R2 region of the printed circuit board. [Figure 6d] FIG. 2 is a process cross-sectional view schematically showing an example of manufacturing the R2 region of the printed circuit board. [Figure 6e] FIG. 2 is a process cross-sectional view schematically showing an example of manufacturing the R2 region of the printed circuit board. [Figure 6f] FIG. 2 is a process cross-sectional view schematically showing an example of manufacturing the R2 region of the printed circuit board. [Figure 6g] FIG. 2 is a process cross-sectional view schematically showing an example of manufacturing the R2 region of the printed circuit board. [Figure 6h] FIG. 2 is a process cross-sectional view schematically showing an example of manufacturing the R2 region of the printed circuit board. [Figure 7] FIG. 2 is a cross-sectional view schematically showing an example of a package substrate and a semiconductor package including the same. [Figure 8] FIG. 2 is a cross-sectional view schematically showing another example of a package substrate and a semiconductor package including the same. [Modes for Carrying Out the Invention]

[0011] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shapes, sizes, and the like of elements in the drawings may be displayed in an enlarged or reduced scale (or highlighted or simplified display) for clearer explanation.

[0012] Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0013] Referring to the drawings, an electronic device 1000 accommodates a main board 1010. Chip-related components 1020, network-related components 1030, other components 1040 and the like may be physically and / or electrically connected to the main board 1010, respectively. These can be combined with other electronic components described later to form various signal lines 1090.

[0014] The chip-related components 1020 may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). However, the present invention is not limited thereto, and other types of chip-related electronic components may also be included. In addition, these chip-related components 1020 may be combined with one another. The chip-related components 1020 may be in a package form.

[0015] The network-related component 1030 may include, but is not limited to, any other wireless and wired protocols designated as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (Long Term Evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth®, 3G, 4G, 5G, and later. Furthermore, the network-related component 1030 can be combined with the chip-related component 1020.

[0016] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCCs (multi-layer ceramic condensers), etc. However, they are not limited to these, and may also include passive elements in chip component form used for a variety of other applications. Furthermore, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0017] Depending on the type of electronic device 1000, the electronic device 1000 may further include other electronic components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, a battery 1080, etc. However, it may also include, but is not limited to, audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. In addition, depending on the type of electronic device 1000, other electronic components used for various purposes may be included.

[0018] Electronic device 1000 can be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smartwatch, automobile, artificial intelligence (AL), server, etc. However, it is not limited to these, and can also be any other electronic device that processes data.

[0019] Figure 2 is a schematic cross-sectional view showing an example of a printed circuit board, Figure 3 is a schematic enlarged cross-sectional view of the R1 region of the printed circuit board in Figure 2, and Figure 4 is a schematic enlarged cross-sectional view of the R2 region of the printed circuit board in Figure 2.

[0020] Referring to the drawings, an example of a printed circuit board 100 may include a first insulating layer 111, a first conductor pattern 121 disposed on the first insulating layer 111, a first insulating film 131 that covers at least a portion of the upper surface of the first insulating layer 111 and at least a portion of the upper surface and side surfaces of the first conductor pattern 121, and extends between the upper surface of the first insulating layer 111 and the lower surface of the first conductor pattern 121, and a second insulating layer 112 disposed on the first insulating film 131. In this example, the printed circuit board 100 can satisfy C > E, where C is the thickness of the first insulating film 131 in the portion that covers the upper surface of the first insulating layer 111, for example, the thickness of the first insulating film 131 in the portion where the first conductor pattern 121 etc. is not disposed, and E is the thickness of the portion of the first insulating film 131 that extends between the upper surface of the first insulating layer and the lower surface of the first conductor pattern 121. Furthermore, when D is the thickness of the portion of the first insulating film 131 that covers the upper surface of the first conductor pattern 121, the condition D+E>C can be satisfied.

[0021] On the other hand, ABF (Ajinomoto Build-up Film) (registered trademark) has considerable surface roughness, and therefore, when printed circuit boards are manufactured using it, it can be difficult to achieve fine patterns with an L (Line) / S (Space) of 2 μm / 2 μm. Therefore, in order to achieve fine patterns with an L / S of 2 μm / 2 μm, an insulating material with good and uniform surface roughness may be required, and for example, PID (Photo Imageable Dielectric) can be used. However, PID materials may be more vulnerable to copper migration compared to ABF materials.

[0022] On the other hand, in the printed circuit board 100 according to one example, the top, side, and bottom surfaces of the first conductor pattern 121 can all be surrounded by the first insulating film 131, and therefore copper migration can be prevented. Therefore, even when PID material is used instead of ABF as the material for the first and second insulating layers 111 and 112, and the first conductor pattern 121 is realized as a fine pattern, reliability issues can be improved. For example, the first conductor pattern 121 may be a plurality of first conductor patterns 121, in which case the line width of each of the plurality of first conductor patterns 121 may be 1 μm to 3 μm, and the spacing between the plurality of first conductor patterns 121 may be 1 μm to 3 μm.

[0023] Furthermore, in the printed circuit board 100 according to one example, the thickness of the first insulating film 131 can vary depending on its position. For example, as described above, the thickness C of the portion of the first insulating film 131 that covers the upper surface of the first insulating layer 111 may be greater than the thickness E of the portion of the first insulating film 131 that extends between the upper surface of the first insulating layer and the lower surface of the first conductor pattern 121. Also, the sum of the thickness D of the portion of the first insulating film 131 that covers the upper surface of the first conductor pattern 121 and the aforementioned thickness E may be greater than the aforementioned thickness C. In this case, the first conductor pattern 121 can be realized more precisely as a fine pattern. In addition, the first conductor pattern 121 can be more easily surrounded by the first insulating film 131, and therefore reliability can be improved more effectively.

[0024] For example, the first insulating film 131 may include a first-first insulating film 131-1 positioned on the upper surface of the first insulating layer 111 and extending between the upper surface of the first insulating layer 111 and the lower surface of the first conductor pattern 121, and a first-second insulating film 131-2 positioned on the upper surface of the first-first insulating film 131-1 and covering at least a portion of the upper and side surfaces of the first conductor pattern 121 along the shape of the first conductor pattern 121. Thus, the first insulating film 131 including the first-first and first-second insulating films 131-1 and 131-2 can satisfy the thickness relationship described above and more easily enclose the first conductor pattern 121. On the other hand, the first-first and first-second insulating films 131-1 and 131-2 may contain the same inorganic insulating material and therefore can be integrated with each other without boundaries. However, boundaries may be separated from each other if necessary.

[0025] In this case, if we let A be the thickness of the portion of the first insulating film 131-1 that is placed on the upper surface of the first insulating layer 111, for example, the thickness of the first insulating film 131-1 in the portion where the first conductor pattern 121 is not placed, and B be the thickness of the portion of the first insulating film 131-1 that extends between the upper surface of the first insulating layer 111 and the lower surface of the first conductor pattern 121, then B > A can be satisfied. For example, in order to realize the first conductor pattern 121 as a fine pattern, dry etching can be required in the seed etching process, and in this process, a portion of the first insulating film 131-1 in the portion where the first conductor pattern 121 is not placed can be removed. Therefore, the first insulating film 131-1 can satisfy the above-mentioned thickness relationship. Therefore, the first insulating film 131 including this can more easily satisfy the above-mentioned thickness relationship.

[0026] Referring to the drawings, an example of a printed circuit board 100 may further include a second conductor pattern 122 disposed on a second insulating layer 112, a second insulating film 132 covering at least a portion of the upper surface of the second insulating layer 112 and at least a portion of the upper and side surfaces of the second conductor pattern 122, and extending between the upper surface of the second insulating layer 112 and the lower surface of the second conductor pattern 122, and a third insulating layer 113 disposed on the second insulating film 132. For example, an example of a printed circuit board 100 may have a multilayer printed circuit board structure.

[0027] Furthermore, the above-described content for the first conductor pattern 121 can be applied substantially similarly to the second conductor pattern 122. For example, the second conductor pattern 122 may consist of multiple second conductor patterns 122, in which case the line width of each of the multiple second conductor patterns 122 may be 1 μm to 3 μm, and the spacing between the multiple second conductor patterns 122 may be 1 μm to 3 μm. Also, the above-described content for the first insulating film 131 can be applied substantially similarly to the second insulating film 132. For example, the second insulating film 132 may include a second-first insulating film 132-1 disposed on the upper surface of the second insulating layer 112 and extending between the upper surface of the second insulating layer 112 and the lower surface of the second conductor pattern 122, and a second-second insulating film 132-2 disposed on the upper surface of the second-first insulating film 132-1 and covering at least a portion of the upper and side surfaces of the second conductor pattern 122 in accordance with its shape. In this case, the relationship between the first-first insulating film 131-1 and the first insulating film 131, as described above, with respect to thicknesses A, B, C, D, and E, can be applied substantially similarly to the second-first insulating film 132-1 and the second insulating film 132.

[0028] Referring to the drawings, the printed circuit board 100 according to one example may further include a first pad pattern 123 disposed on a first insulating layer 111, a second pad pattern 124 disposed on a second insulating layer 112, and a via pattern 141 disposed between the first and second pad patterns 123 and 124, connecting the first and second pad patterns 123 and 124 to each other. For example, the printed circuit board 100 according to one example may have a structure that allows for vertical electrical connection.

[0029] On the other hand, the first insulating film 131 can further cover at least a portion of the upper and side surfaces of the first pad pattern 123, extend further between the upper surface of the first insulating layer 111 and the lower surface of the first pad pattern 123, further cover at least a portion of the side surface of the via pattern 141, and be in contact with at least a portion of the side surface of the via pattern 141. Furthermore, the second insulating film 132 can further cover at least a portion of the upper and side surfaces of the second pad pattern 124, extend further between the upper surface of the second insulating layer 112 and the lower surface of the second pad pattern 124, further cover at least another portion of the side surface of the via pattern 141, and be in contact with at least another portion of the side surface of the via pattern 141. In addition, the first and second insulating films 131 and 132 may be connected to each other. This makes it easier to realize the via pattern 141 with fine vias, and to more easily realize the reliability improvement effect described above.

[0030] In this case, if we let F be the thickness of the second insulating film 132 in the portion covering the upper surface of the second insulating layer 112, for example, the thickness of the second insulating film 132 in the portion where the second pad pattern 124 is not arranged, G be the thickness of the second insulating film 132 in the portion covering the upper surface of the second pad pattern 124, and H be the thickness of the portion extending between the upper surface of the second insulating layer 112 and the lower surface of the second pad pattern 124, then F > H and G + H > F can be satisfied. In this case, the reliability improvement effect described above can be achieved more easily.

[0031] Furthermore, when the thickness of the second insulating film 132 in the portion that covers and contacts the side surface of the via pattern 141 is J, the condition H > J can be satisfied. For example, in order for the via pattern 141 to contact the first pad pattern 123, it may be necessary to remove at least a portion of the second insulating film 132 deposited on the bottom surface of the via hole vh in which the via pattern 141 is formed. For example, an ion beam trimming process can be used. In this process, a portion of the second insulating film 132 deposited on the wall surface of the via hole vh can also be removed, and therefore the second insulating film 132 can satisfy the thickness relationship described above. For example, when such a thickness relationship is satisfied, electrical conduction can be made easier. Also, reliability can be improved.

[0032] Furthermore, if K is the thickness of the first portion of the first pad pattern 123 connected to the via pattern 141, for example, the central portion, and L is the thickness of the second portion of the first pad pattern 141 surrounding at least a part of the first portion, for example, the peripheral portion, then L > K can be satisfied. For example, if at least a part of the second insulating film 132 deposited on the bottom surface of the via hole vh is removed as described above, at least a part of the first pad pattern 141 exposed through the via hole vh can be removed. Therefore, the thickness of the corresponding first portion, for example, the central portion, can be reduced, and the above-described thickness relationship can be satisfied. For example, if such a thickness relationship is satisfied, electrical conduction can be made easier. Also, reliability can be improved.

[0033] On the other hand, the first to third insulating layers 111, 112, and 113 can each contain one or more photosensitive organic insulating materials, such as polyimide resins, phenolic resins, and polybenzoxazole resins. In this case, it can be easier to realize the first and second conductor patterns 121 and 122 as fine patterns. Furthermore, the first and second insulating films 131 and 132, for example, the first-first and first-second insulating films 131-1 and 131-2 and the second-first and second-second insulating films 132-1 and 132-2, can each be formed as thin film coating layers using CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition), and thus each can contain one or more inorganic insulating materials, such as Al2O3, SiO2, Si3N4, TiO2, TiON, and AlON. In this case, the first and second conductor patterns 121, 122, the first and second pad patterns 123, 124, and the via pattern 141 can be more easily passivated.

[0034] On the other hand, the first conductor pattern 121 and the first pad pattern 123 may each include a first seed metal layer sm1 and a first pattern metal layer pm1 disposed on the first seed metal layer sm1. Furthermore, the second conductor pattern 122, the second pad pattern 124, and the via pattern 141 may each include a second seed metal layer sm2 and a second pattern metal layer pm2 disposed on the second seed metal layer sm2. The first and second seed metal layers sm1 and sm2 may each include a first layer sm1-1 and sm2-1 containing titanium and a second layer sm1-2 and sm2-2 containing copper disposed on the first layers sm1-1 and sm2-1. For example, the first and second seed metal layers sm1 and sm2 may each be formed by a sputtering process and may include, but are not limited to, sputtered titanium and sputtered copper. The first and second pattern metal layers pm1 and pm2 may each include a third layer pm1 and pm2 containing copper. For example, the first and second pattern metal layers pm1 and pm2 can be formed by an electroplating process, and may, but are not limited to, electroplated copper. The third layers pm1 and pm2 may be thicker than the first and second layers sm1-1, sm2-1, sm1-2, and sm2-2, respectively.

[0035] In the following section, the components of an example printed circuit board 100 will be described in more detail with reference to the drawings.

[0036] The first to third insulating layers 111, 112, and 113 can each contain an insulating material. The insulating material can include an organic insulating material. The organic insulating material can include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, glass fabric) together with the resin. Preferably, the insulating material can include a photosensitive organic insulating material, and the photosensitive organic insulating material can include one or more of polyimide resins, phenolic resins, and polybenzoxazole resins. In this case, the patterning method can be simpler than that of conventional silicon interposers and silicon bridges, and it may be more advantageous in terms of cost. In addition, the first and second conductor patterns 121, 122 and the via pattern 141 can be easily formed with fine patterns and fine vias. Therefore, a fine circuit board can be provided, and such a fine circuit board can be easily applied as an interconnect bridge or 2.1D RDL layer in AI package substrates or server package substrates, etc.

[0037] The first and second conductor patterns 121, 122, the first and second pad patterns 123, 124, and the via pattern 141 may each contain a metallic material. The metallic material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The first and second conductor patterns 121, 122 may each contain a signal line pattern. The first and second pad patterns 123, 124 may each contain a signal pad pattern. Power patterns and / or ground patterns may be further arranged as needed, and these patterns may each have line, pad, and / or plane forms. The via pattern 141 may contain a signal via pattern. Power via patterns and / or ground via patterns may be further arranged as needed. The via pattern 141 can be integrated with the second pad pattern 124 without a boundary. The via pattern 141 may have a tapered shape in cross-section, with the width at the upper end being wider than the width at the lower end. The first conductor pattern 121 and the first pad pattern 123 may each include a first seed metal layer sm1 and a first pattern metal layer pm1, respectively, and the second conductor pattern 122, the second pad pattern 124, and the via pattern 141 may each include a second seed metal layer sm2 and a second pattern metal layer pm2. The first and second seed metal layers sm1 and sm2 may each include a first layer sm1-1 and sm2-1 containing titanium and a second layer sm1-2 and sm2-2 containing copper, respectively. The first and second pattern metal layers pm1 and pm2 may each include a third layer pm1 and pm2 containing copper. In this case, it may be more advantageous to form the fine patterns and fine vias described above.

[0038] The first and second insulating films 131 and 132 can each contain an inorganic insulating material. For example, the first and second insulating films 131 and 132, more specifically the first-first and first-second insulating films 131-1 and 131-2 and the second-first and second-second insulating films 132-1 and 132-2, can each contain one or more of Al2O3, SiO2, SiON, Si3N4, TiO2, TiON, and AlON. In this case, the first and second conductor patterns 121 and 122, the first and second pad patterns 123 and 124, and the via pattern 141 can be more easily passivated. Therefore, moisture penetration can be easily prevented even in high-temperature and high-humidity environments such as uHAST (unbiased Highly Accelerated Stress Test) and bHAST (biased Highly Accelerated Stress Test). Therefore, stable electrical performance can be maintained without migration of fine patterns. Therefore, it can be easily applied to various models of packaged fine circuit boards where reliability is required.

[0039] On the other hand, conductor patterns, pad patterns, via patterns, insulating films, and insulating layers can be further formed on the third insulating layer 113 as needed, and the above-described content can be applied substantially similarly to each of the further formed conductor patterns, pad patterns, via patterns, insulating films, and insulating layers. In addition, a base layer 110 can be placed below the first insulating layer 111. The base layer 110 may be a substrate of various materials such as an organic insulating layer, an inorganic insulating layer, a ceramic layer, or a glass layer. The base layer 110 may be omitted.

[0040] Figures 5a to 5h are schematic cross-sectional process views showing an example of the manufacturing process for the R1 region of the printed circuit board shown in Figure 2.

[0041] Referring to Figure 5a, the base layer 110 can be prepared. The base layer 110 can be a substrate of various materials, as described above.

[0042] Referring to Figure 5b, a first insulating layer 111 can be formed on the base layer 110. The first insulating layer 111 can be formed by applying and curing a PID material on the base layer 110, or by laminating and curing a film containing a PID material on the base layer 110.

[0043] Referring to Figure 5c, the first insulating film 131-1 can be formed on the first insulating layer 111. The first insulating film 131-1 can be formed by depositing an inorganic insulating material using an ALD or CVD process.

[0044] Referring to Figure 5d, a first seed metal layer sm1 can be formed on the first-first insulating film 131-1. For example, a first layer sm1-1 containing titanium and a second layer sm1-2 containing copper can be sequentially formed on the first-first insulating film 131-1 using a sputtering process.

[0045] Referring to Figure 5e, a first pattern metal layer pm1 can be formed on a first seed metal layer sm1. The first pattern metal layer pm1 can be formed by forming a photoresist for plating on the first seed metal layer sm1, creating openings in the photoresist for plating in a photolithography process, filling the openings with electroplating, and then removing the photoresist for plating. For example, a third layer pm1 containing copper can be formed.

[0046] Referring to Figure 5f, the first seed metal layer sm1 in the area where the first pattern metal layer pm1 is not formed can be removed using dry etching or the like. This allows the first conductor pattern 121 to be formed. On the other hand, during the dry etching process, a portion of the first-first insulating film 131-1 in the area where the first pattern metal layer pm1 is not formed can be removed, making the thickness of the first-first insulating film 131-1 in that area relatively thinner.

[0047] Referring to Figure 5g, a first-second insulating film 131-2 can be formed on the first-first insulating film 131-1 to cover the first conductor pattern 121. This allows the first insulating film 131 to be formed which passivates the first conductor pattern 121. The first-second insulating film 131-2 can be formed by depositing an inorganic insulating material using an ALD or CVD process.

[0048] Referring to Figure 5h, a second insulating layer 112 can be formed on the first insulating film 131. The second insulating layer 112 can be formed by coating and curing a PID material on the first insulating film 131, or by laminating and curing a film containing a PID material on the first insulating film 131.

[0049] Through a series of processes, the R1 region of an example printed circuit board can be manufactured, and the other contents may be substantially the same as described above.

[0050] Figures 6a to 6h are schematic cross-sectional process views showing an example of the manufacturing process for the R2 region of the printed circuit board shown in Figure 2.

[0051] Referring to Figure 6a, the base layer 110 can be prepared. Then, the first insulating layer 111, the 1-1 insulating film 131-1, the first pad pattern 123, the 1-2 insulating film 131-2, and the second insulating layer 112 can be sequentially formed on the base layer 110. The specific details regarding this may be substantially the same as those described in Figures 5a to 5h. After this, via holes vh can be formed in the second insulating layer 112, exposing a portion of the 1-2 insulating film 131-2 that covers the upper surface of the first pad pattern 123. The via holes vh can be formed using a photolithography process.

[0052] Referring to Figure 6b, the second-first insulating film 132-1 can be formed on the second insulating layer 112 and inside the via hole vh. The second-first insulating film 132-1 can be formed by depositing an inorganic insulating material using an ALD or CVD process. The second-first insulating film 132-1 can come into contact with the first-second insulating film 131-2 at the bottom surface of the via hole vh.

[0053] Referring to Figure 6c, the second-first insulating film 132-1 and the first-second insulating film 131-2 located at the bottom of the via hole vh can be removed. For example, a via photoresist can be formed on the second-first insulating film 132-1, an opening can be formed in the via photoresist to expose the via hole vh in a photolithography process, and the second-first insulating film 131-1 and the first-second insulating film 131-2 located at the bottom of the via hole vh can be removed by dry etching, for example, a trim process utilizing an ion beam. In this process, a portion of the second-first insulating film 132-1 located on the wall surface of the via hole vh can be removed, and thus the thickness in that portion can be reduced. Furthermore, a portion of the exposed first pad pattern 123 can be removed, and thus the thickness in that portion can be reduced. After the trim process, the via photoresist can be removed.

[0054] Referring to Figure 6d, a second seed metal layer sm2 can be formed on the second-first insulating film 132-1, the wall surface of the via hole vh, and the first pad pattern 123 exposed through the via hole vh. For example, a first layer sm2-1 containing titanium and a second layer sm2-2 containing copper can be sequentially formed on the second-first insulating film 132-1, the wall surface of the via hole vh, and the first pad pattern 123 exposed through the via hole vh using a sputtering process.

[0055] Referring to Figure 6e, a second pattern metal layer pm2 can be formed on the second seed metal layer sm2. The second pattern metal layer pm2 can be formed by forming a photoresist for plating on the second seed metal layer sm2, creating openings in the photoresist for plating in a photolithography process, filling the openings with electroplating, and then removing the photoresist for plating. For example, a third layer pm2 containing copper can be formed.

[0056] Referring to Figure 6f, the second seed metal layer sm2 in the area where the second pattern metal layer pm2 is not formed can be removed using dry etching or the like. This allows the second pad pattern 124 to be formed. This also allows the second conductor pattern 122 to be formed. On the other hand, during the dry etching process, a portion of the second-first insulating film 132-1 in the area where the second pattern metal layer pm2 is not formed can be removed, making the thickness of the second-first insulating film 132-1 in that area relatively thinner.

[0057] Referring to Figure 6g, a second-second insulating film 132-2 can be formed on the second-first insulating film 132-1 to cover the second pad pattern 124. The second-second insulating film 132-2 can also cover the second conductor pattern 122. This allows for the formation of a second insulating film 132 that passivates the second conductor pattern 122 and the second pad pattern 124. The second-second insulating film 132-2 can be formed by depositing an inorganic insulating material using an ALD or CVD process.

[0058] Referring to Figure 6h, a third insulating layer 113 can be formed on the second insulating film 132. The third insulating layer 113 can be formed by coating and curing a PID material on the second insulating film 132, or by laminating and curing a film containing a PID material on the second insulating film 132.

[0059] Through a series of processes, an example of the R2 region of a printed circuit board can be manufactured, and the other details may be substantially the same as those described above.

[0060] Figure 7 is a schematic cross-sectional view showing an example of a package substrate and a semiconductor package containing it.

[0061] Referring to the drawings, an example package substrate 200 may include a circuit board 210 and an interconnect member 220 disposed inside the circuit board 210. An example semiconductor package 500 may include a package substrate 200 and first and second semiconductor chips 410 and 420 mounted on the package substrate 200. The circuit board 210 may be a standard multilayer printed circuit board, and its specific structure is not particularly limited. The interconnect member 220 may be a bridge substrate 220 including fine patterns that interconnect the first and second semiconductor chips 410 and 420. The bridge substrate 220 may be embedded inside the circuit board 210. The bridge substrate 220 may include the printed circuit board 100 described above. The first and second semiconductor chips 410 and 420 may be a memory chip, an application processor chip, and / or a logic chip, respectively. The first and second semiconductor chips 410 and 420 may be the same type of chip or different types of chips.

[0062] Figure 8 is a schematic cross-sectional view showing another example of a package substrate and a semiconductor package containing it.

[0063] Referring to the drawings, the package substrate 300 according to another example may include a circuit board 310 and an interconnect member 320 disposed inside the circuit board 310. The semiconductor package 600 according to another example may include the package substrate 300 and first and second semiconductor chips 410, 420 mounted on the package substrate 300. The circuit board 310 may be a standard multilayer printed circuit board, and its specific structure is not particularly limited. The interconnect member 320 may be located on the outermost part of the circuit board 310 and may be a fine circuit layer 320 containing fine patterns that interconnect the first and second semiconductor chips 410, 420. The fine circuit layer 320 may be a 2.1D RDL layer. The fine circuit layer 320 may include the printed circuit board 100 according to the example described above. The first and second semiconductor chips 410, 420 may be a memory chip, an application processor chip, and / or a logic chip, respectively. The first and second semiconductor chips 410 and 420 may be of the same type or of different types.

[0064] In this disclosure, the expression "cover" may include not only covering the entire object but also covering at least a part of it, and may include not only direct covering but also indirect covering. Similarly, the expression "fill" may include not only completely filling the object but also filling at least a part of it, and may include roughly filling it. Furthermore, the expression "enclose" may include not only completely enclosing the object but also partially enclosing and roughly enclosing it. In addition, "expose" may include not only completely exposing the object but also partially exposing it, and may mean exposing the object that embeds the object in question.

[0065] In this disclosure, "on a cross-section" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. "On a plane" can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0066] In this disclosure, terms such as "lower side," "bottom," and "bottom surface" are used for convenience to mean the downward direction relative to the cross-section of the drawing, while terms such as "upper side," "top," and "top surface" are used to mean the opposite direction. However, this is a definition of direction for explanatory purposes only, and the scope of rights in the claims is not particularly limited by such descriptions of direction, and the concepts of up / down can be changed at any time.

[0067] In this disclosure, the term "connected" includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" includes both physically connected and unconnected cases. The terms "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of those components. In some cases, without departing from the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0068] In this disclosure, thickness, width, line width, spacing, etc., can be measured using a scanning microscope or optical microscope based on a cross-section obtained by polishing or cutting the printed circuit board. The cut cross-section can be vertical or horizontal, and the respective values ​​can be measured based on the required cut cross-section. For example, the width of the upper and / or lower ends of a via can be measured on a cross-section cut along the central axis of the via. In this case, if the values ​​are not constant, the values ​​can be determined by taking the average of the values ​​measured at any five points.

[0069] The expression "example" as used in this disclosure does not mean that each embodiment is identical to another, but is provided to highlight and illustrate the unique features of each embodiment that are distinct from one another. However, the examples presented above do not preclude their implementation in combination with features of other examples. For example, even if a matter described in one example is not described in another example, it can be understood as a description related to the other example unless there is a description in the other example that contradicts or inconsistes with that matter.

[0070] The terms used in this disclosure are for illustrative purposes only and are not intended to limit the disclosure. Where otherwise, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0071] 1000 electronic equipment 1010 Mainboard 1020 Chip-related components 1030 Network-related components 1040 Other parts 1050 Camera 1060 Antenna 1070 Display 1080 Battery 1090 signal line 100 Printed Circuit Boards 110 Base Layer 111, 112, 113 Insulating layer 121, 122 Conductor Patterns 123, 124 Pad Pattern 131-1, 131-2, 131, 132-1, 132-2, 132 insulating film 141 via patterns sm1, sm2 seed metal layer sm1-1, sm2-1 1st layer sm1-2, sm2-2 2nd layer pm1, pm2 pattern metal layer (or third layer) vh beer hall 500, 600 semiconductor packages 410, 420 semiconductor chips 200, 300 package substrates 210, 310 Circuit boards 220 Bridge board (or interconnect component) 320 Fine circuit layer (or interconnect component)

Claims

1. The first insulating layer and A first conductor pattern disposed on the first insulating layer, A first insulating film extends between the upper surface of the first insulating layer and the lower surface of the first conductor pattern, covering at least a portion of the upper surface and at least a portion of the upper surface and side surface of the first conductor pattern. The invention includes a second insulating layer disposed on the first insulating film, A printed circuit board that satisfies C > E, where C is the thickness of the portion of the first insulating film that covers the upper surface of the first insulating layer, and E is the thickness of the portion of the first insulating film that extends between the upper surface of the first insulating layer and the lower surface of the first conductor pattern.

2. The printed circuit board according to claim 1, wherein D satisfies D + E > C, where D is the thickness of the portion of the first insulating film that covers the upper surface of the first conductor pattern.

3. The printed circuit board according to claim 1, wherein the first insulating film includes a first-first insulating film disposed on the upper surface of the first insulating layer and extending between the upper surface of the first insulating layer and the lower surface of the first conductor pattern, and a first-second insulating film disposed on the upper surface of the first-first insulating film and covering at least a portion of the upper and side surfaces of the first conductor pattern in accordance with the shape of the first conductor pattern.

4. The printed circuit board according to claim 3, wherein when A is the thickness of the portion of the 1-1 insulating film disposed on the upper surface of the first insulating layer, and B is the thickness of the portion of the 1-1 insulating film extending between the upper surface of the first insulating layer and the lower surface of the first conductor pattern, B > A.

5. The printed circuit board according to claim 3, wherein the first-1 and first-2 insulating films each contain the same inorganic insulating material.

6. The first and second insulating layers each contain a photosensitive organic insulating material. The printed circuit board according to claim 1, wherein the first insulating film includes an inorganic insulating material.

7. The aforementioned photosensitive organic insulating material comprises one or more of the following: polyimide resin, phenolic resin, and polybenzoxazole resin. The aforementioned inorganic insulating material is Al ２ O ３ SiO ２ , SiON, Si ３ N ４ , TiO ２ The printed circuit board according to claim 6, comprising one or more of TiON and AlON.

8. The first conductor pattern is a plurality of first conductor patterns, The line width of each of the aforementioned plurality of first conductor patterns is 1 μm to 3 μm. The printed circuit board according to claim 1, wherein the spacing between the plurality of first conductor patterns is 1 μm to 3 μm.

9. A second conductor pattern arranged on the second insulating layer, A second insulating film extends between the upper surface of the second insulating layer and the lower surface of the second conductor pattern, covering at least a portion of the upper surface and at least a portion of the upper surface and side surface of the second conductor pattern. The printed circuit board according to claim 1, further comprising a third insulating layer disposed on the second insulating film.

10. The printed circuit board according to claim 9, wherein the second insulating film comprises a second-first insulating film disposed on the upper surface of the second insulating layer and extending between the upper surface of the second insulating layer and the lower surface of the second conductor pattern, and a second-second insulating film disposed on the upper surface of the second-first insulating film and covering at least a portion of the upper and side surfaces of the second conductor pattern in accordance with the shape of the second conductor pattern.

11. A first pad pattern disposed on the first insulating layer, A second pad pattern disposed on the second insulating layer, The present invention further includes via patterns positioned between the first and second pad patterns and connecting the first and second pad patterns to each other, The first insulating film further covers at least a portion of the upper surface and side surface of the first pad pattern, extends further between the upper surface of the first insulating layer and the lower surface of the first pad pattern, and further covers at least a portion of the side surface of the via pattern. The second insulating film further covers at least a portion of the upper surface and side surface of the second pad pattern, extends further between the upper surface of the second insulating layer and the lower surface of the second pad pattern, and further covers at least another portion of the side surface of the via pattern. The printed circuit board according to claim 9, wherein the first and second insulating films are connected to each other.

12. The printed circuit board according to claim 11, wherein the thickness of the portion of the second insulating film covering the upper surface of the second insulating layer is F, the thickness of the portion of the second insulating film covering the upper surface of the second pad pattern is G, and the thickness of the portion of the second insulating film extending between the upper surface of the second insulating layer and the lower surface of the second pad pattern is H, such that G + H > F.

13. The printed circuit board according to claim 12, wherein H > J is satisfied when J is the thickness of the portion of the second insulating film that covers the side surface of the via pattern.

14. The printed circuit board according to claim 12, wherein the thickness of the first portion of the first pad pattern connected to the via pattern is K, and the thickness of the second portion surrounding at least a part of the first portion of the first pad pattern is L, such that L > K.

15. The first conductor pattern and the first pad pattern each include a first seed metal layer and a first pattern metal layer disposed on the first seed metal layer, The second conductor pattern, the second pad pattern, and the via pattern each include a second seed metal layer and a second pattern metal layer disposed on the second seed metal layer, The first and second seed metal layers each include a first layer containing titanium and a second layer disposed on the first layer and containing copper. The first and second patterned metal layers each include a third layer containing copper. The printed circuit board according to claim 11, wherein the third layer is thicker than each of the first and second layers.

16. Circuit board and The circuit board includes an interconnect member disposed inside the circuit board, The interconnect member is a package substrate including a printed circuit board according to any one of claims 1 to 15.

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