Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device with reduced contact resistance. [Solution] The semiconductor device 1 includes a plurality of word line (WL) structures 300, each extending along a first direction X and spaced apart from each other along a second direction Y; a plurality of active regions 100, each extending in a diagonal direction that forms an acute angle with the first direction X, overlapping with the WL structures 300, and spaced apart from each other along the first direction X; a plurality of bit line (BL) pad regions 430, each overlapping with one end of the active region 100 and in contact with one side of the WL structure 300; a plurality of (SN) pad regions 530, each overlapping with the other end of the active region 100 and in contact with the other side of the WL structure 300; a plurality of first pad insulating regions 710, each in contact with the BL pad region 430 and in contact with one side of the WL structure 300, and having a first height H1; and a plurality of second pad insulating regions 720, each in contact with the SN pad region 530 and in contact with the other side of the WL structure 300, and having a second height H2 that is higher than the first height.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a plurality of active regions.

Background Art

[0002] Among semiconductor devices, a semiconductor device having a memory function is a device that can be used to store information, and may include an array including individual memory cells each containing a transistor. An example of the semiconductor device having a memory function is a dynamic random access memory (DRAM). The DRAM may include bit lines and word lines that can intersect each other in a perpendicular direction, the bit lines and the word lines may extend across the array including the memory cells to intersect each other, and the bit lines and the word lines can be utilized to access the individual memory cells.

[0003] Depending on how individual memory cells are designed and arranged, memory performance, cell stability and reliability, power efficiency, process ease, cost, and the like may vary, and continuous research is being conducted on the design of cell arrays of memory devices and methods of manufacturing the same.

Summary of Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention can provide a semiconductor device in which the contact resistance of bit line contacts and storage node contacts is reduced. The embodiments of the present invention can provide a semiconductor device with reduced bridging phenomenon and improved reliability even when word lines are misaligned during the manufacturing process. In addition, the embodiments of the present invention can simplify the manufacturing process of the semiconductor device in which the contact resistance of bit line contacts and storage node contacts is reduced, and achieve cost reduction.

Means for Solving the Problems

[0005] A semiconductor device according to one embodiment of the present invention may include a plurality of word line structures, each extending along a first direction and spaced apart from each other along a second direction; a plurality of active regions, each extending in a diagonal direction that forms an acute angle with the first direction, overlapping with the word line structures, and spaced apart from each other along the first direction; a plurality of bit line pad regions, each overlapping one end of the active region and in contact with one side of the word line structure; a plurality of storage node pad regions, each overlapping the other end of the active region and in contact with the other side of the word line structure; a plurality of first pad insulating regions, each in contact with the bit line pad regions and in contact with one side of the word line structure, and having a first height; and a plurality of second pad insulating regions, each in contact with the storage node pad regions and in contact with the other side of the word line structure, and having a second height greater than the first height.

[0006] Each of the plurality of bit line pad regions of the semiconductor device according to one embodiment of the present invention has a third height from the upper surface of the active region, and each of the plurality of storage node pad regions has a fourth height from the upper surface of the active region, and the third height and the fourth height may each be the same as the second height.

[0007] The lower surface of the bit line pad area and the lower surface of the storage node pad area of ​​the semiconductor device according to one embodiment of the present invention may be lower than the lower surface of the first pad insulation area.

[0008] The lower surface of the bit line pad area and the lower surface of the storage node pad area of ​​the semiconductor device according to one embodiment of the present invention can be located on the same plane as the lower surface of the second pad insulating area.

[0009] The semiconductor device according to one embodiment of the present invention may further include a plurality of bit line contact regions, each in contact with the upper surface of the bit line pad region, and a plurality of storage node contact regions, each in contact with the upper surface of the storage node pad region.

[0010] The semiconductor device according to one embodiment of the present invention may further include a plurality of bit line electrode layers, each disposed on the bit line contact region and overlapping the bit line pad region, and extending in the second direction, and a plurality of bit line spacers, each in contact with both sides of the bit line electrode layer and extending in the second direction.

[0011] The second direction of the semiconductor device according to one embodiment of the present invention is perpendicular to the first direction, and the second direction can form an acute angle with the diagonal direction.

[0012] The angle between the first direction and the diagonal direction of the semiconductor device according to one embodiment of the present invention may be between 30 degrees and 60 degrees.

[0013] The plurality of active regions of the semiconductor device according to one embodiment of the present invention may be further arranged spaced apart from each other along the second direction, and the plurality of active regions may be further arranged spaced apart from each other along the diagonal direction.

[0014] Each of the plurality of bit line pad regions of the semiconductor device according to one embodiment of the present invention may be arranged spaced apart from each other along the second direction, and each of the plurality of storage node pad regions may be arranged spaced apart from each other along the second direction.

[0015] Each of the plurality of first pad insulating regions of the semiconductor device according to one embodiment of the present invention may be in contact with the side surface of the bit line pad region facing the first direction, each of the plurality of first pad insulating regions may be in contact with the side surface of the storage node pad region facing the opposite direction to the first direction, each of the plurality of second pad insulating regions may be in contact with the side surface of the bit line pad region facing the opposite direction to the first direction, and each of the plurality of second pad insulating regions may be in contact with the side surface of the storage node pad region facing the first direction.

[0016] The plurality of first pad insulating regions of the semiconductor device according to one embodiment of the present invention may be spaced apart along the second direction, and the plurality of second pad insulating regions may be spaced apart along the second direction.

[0017] The semiconductor device according to one embodiment of the present invention further includes a cell isolation region surrounding the plurality of active regions, and each of the plurality of first pad insulating regions can be in contact with the upper surface of the cell isolation region.

[0018] Each of the plurality of bit line pad regions and the plurality of storage node pad regions of the semiconductor device according to one embodiment of the present invention may include polysilicon.

[0019] A method for manufacturing a semiconductor device according to one embodiment of the present invention may include the steps of: forming a plurality of active regions, each repeatedly spaced apart along a first direction and a second direction, extending diagonally with respect to the first direction, and surrounded by cell isolation regions; forming a first insulating layer on the plurality of active regions and the cell isolation regions; forming a plurality of open trenches, each etching a portion of two adjacent active regions and a portion of the first insulating layer; forming a pad layer that covers a plurality of first pad insulating regions and the plurality of open trenches remaining after the first insulating layer has been etched; removing a portion of the pad layer formed in the center of the open trenches; and forming a second pad insulating region in the center of the open trenches.

[0020] The manufacturing method for the semiconductor device according to one embodiment of the present invention may further include the step of forming a plurality of wordline structures that overlap the plurality of active regions, extend in the first direction, and are repeatedly spaced apart along the second direction.

[0021] The step of forming the plurality of wordline structures in the manufacturing method of the semiconductor device according to one embodiment of the present invention includes the operation of forming wordline trenches, each of which cuts through a plurality of pad layers extending in the second direction and spaced apart from each other along the first direction to form a plurality of bitline pad regions and a plurality of storage node pad regions, each of which cuts through a plurality of first pad insulating regions and a plurality of second pad insulating regions extending in the second direction and can recess into the interior of a plurality of active regions.

[0022] In the manufacturing method of the semiconductor device according to one embodiment of the present invention, the plurality of bit line pad regions may overlap one end of each of the plurality of active regions, and the plurality of storage node pad regions may overlap the other end of each of the plurality of active regions.

[0023] In the method of manufacturing the semiconductor device according to an embodiment of the present invention, the step of forming the plurality of word line structures may further include an operation of forming a word line electrode layer to which an operation signal of the word line structure is applied, an operation of forming a word line insulating layer formed along an inner wall of the word line trench and surrounding a lower surface and a side surface of the word line electrode layer, and an operation of forming a word line capping layer in contact with an upper surface of the word line electrode layer.

[0024] The method of manufacturing the semiconductor device according to an embodiment of the present invention may further include a step of forming a plurality of bit line contact regions each disposed on the bit line pad region, extending along the second direction, and spaced apart from each other in the first direction, a step of forming a plurality of bit line electrode layers each disposed on the bit line contact region, extending along the second direction, and spaced apart from each other in the first direction, a step of forming a plurality of bit line spacers each in contact with both sides of the bit line electrode layer and extending along the second direction, and a step of forming a plurality of storage node contact regions each disposed on the storage node pad region. [Effects of the Invention]

[0025] The semiconductor device according to the embodiment of the present invention can secure resistance by reducing the process burden of the bit line contact and the storage node contact region and securing a contact area. In addition, in the semiconductor device according to the embodiment of the present invention, the contact resistance can be reduced by disposing the pad region between the bit line contact and the active region and disposing the pad region between the storage node contact and the active region. The method for manufacturing a semiconductor device according to the embodiment of the present invention can reduce the manufacturing cost and simplify the process steps. [Brief Description of the Drawings]

[0026] [Figure 1]This is a circuit diagram exemplarily modeling a unit cell of a semiconductor device according to an embodiment of the present invention. [Figure 2] This is a first plan view exemplarily showing a part of a semiconductor device according to an embodiment of the present invention. [Figure 3] This is a second plan view exemplarily showing a part of a semiconductor device according to an embodiment of the present invention. [Figure 4] This is a cross-sectional view exemplarily showing a section cut along line A-A' of FIG. 2 and FIG. 3. [Figure 5] This is a cross-sectional view exemplarily showing a section cut along line B-B' of FIG. 2 and FIG. 3. [Figure 6] This is a cross-sectional view exemplarily showing a section cut along line C-C' of FIG. 2 and FIG. 3. [Figure 7] This is a cross-sectional view exemplarily showing a section cut along line D-D' of FIG. 2 and FIG. 3. [Figure 8] This is a cross-sectional view exemplarily showing a section cut along line E-E' of FIG. 2 and FIG. 3. [Figure 9] This is a flowchart for exemplarily explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10a] This is a plan view exemplarily showing the result obtained by performing step S10 in FIG. 9. [Figure 10b] This is a cross-sectional view exemplarily showing a section cut along line A-A' of FIG. 10a. [Figure 10c] This is a cross-sectional view exemplarily showing a section cut along line B-B' of FIG. 10a. [Figure 10d] This is a cross-sectional view exemplarily showing a section cut along line C-C' of FIG. 10a. [Figure 10e] This is a cross-sectional view exemplarily showing a section cut along line D-D' of FIG. 10a. [Figure 10f] This is a cross-sectional view exemplarily showing a section cut along line E-E' of FIG. 10a. [Figure 11a] This is a plan view exemplarily showing the result obtained by performing step S20 in FIG. 9. [Figure 11b]This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 11a. [Figure 11c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 11a. [Figure 11d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 11a. [Figure 11e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 11a. [Figure 11f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 11a. [Figure 12a] This is a plan view illustrating the results of performing step S30 in Figure 9. [Figure 12b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 12a. [Figure 12c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 12a. [Figure 12d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 12a. [Figure 12e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 12a. [Figure 12f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 12a. [Figure 13a] This is a plan view illustrating the results of performing step S40 in Figure 9. [Figure 13b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 13a. [Figure 13c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 13a. [Figure 13d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 13a. [Figure 13e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 13a. [Figure 13f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 13a. [Figure 14a] This is a plan view illustrating the results of performing step S50 in Figure 9. [Figure 14b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 14a. [Figure 14c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 14a. [Figure 14d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 14a. [Figure 14e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 14a. [Figure 14f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 14a. [Figure 15a] This is a plan view illustrating the results of performing step S60 in Figure 9. [Figure 15b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 15a. [Figure 15c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 15a. [Figure 15d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 15a. [Figure 15e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 15a. [Figure 15f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 15a. [Figure 16a] This is a plan view illustrating the results of performing step S70 in Figure 9. [Figure 16b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 16a. [Figure 16c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 16a. [Figure 16d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 16a. [Figure 16e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 16a. [Figure 16f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 16a. [Figure 17a] This is a plan view illustrating the results of performing step S80 in Figure 9. [Figure 17b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 17a. [Figure 17c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 17a. [Figure 17d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 17a. [Figure 17e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 17a. [Figure 17f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 17a. [Figure 18a] This is a plan view illustrating the results of performing step S90 in Figure 9. [Figure 18b] This is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 18a. [Figure 18c] This is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 18a. [Figure 18d] This is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 18a. [Figure 18e] This is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 18a. [Figure 18f] This is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 18a. [Figure 19] Figure 3 is a plan view illustrating a portion of a semiconductor device when the word line structure or bit line structure shown in Figure 3 is misaligned. [Modes for carrying out the invention]

[0027] Hereinafter, some embodiments of the present invention will be described in detail with reference to illustrative drawings. It should be noted that when assigning reference numerals to components in each drawing, efforts have been made to ensure that the same component has the same reference numeral whenever possible, even if it is shown in different drawings. Furthermore, when describing embodiments of the present invention, if it is determined that a specific description of a related known configuration or function would hinder understanding of the embodiments of the present invention, such detailed description will be omitted.

[0028] In describing the components of embodiments of the present invention, terms such as "first," "second," etc., may be used. These terms are used to distinguish the component from other components, and unless otherwise explicitly stated, they do not limit the nature, order, or sequence of the component. Furthermore, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as those generally understood by a person of ordinary skill in the art to which the present invention pertains. Terms defined in commonly used dictionaries may be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0029] Figure 1 is a circuit diagram illustrating the unit cell UC of a semiconductor device according to one embodiment of the present invention.

[0030] Referring to Figure 1, a unit cell UC of a semiconductor device according to one embodiment of the present invention may include a transistor TX and a capacitor CAP. The unit cell UC may also be a unit for storing data within the semiconductor device. A semiconductor device according to one embodiment of the present invention can function as a data storage device that can be included in various electronic devices such as computers. According to one embodiment of the present invention, the semiconductor device may be a volatile memory device (e.g., DRAM (Dynamic Random Access Memory)) or a non-volatile memory device (e.g., NAND memory).

[0031] Transistor TX may be a switching element between bit line BL and capacitor CAP. Transistor TX may, for example, be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Transistor TX can be operated by an electric field generated by a voltage applied to its gate. When transistor TX is turned on, it can electrically connect bit line BL and capacitor CAP. When transistor TX is turned off, it can prevent the electrical connection between bit line BL and capacitor CAP.

[0032] The word line WL can control the on / off state of transistor TX. For example, if the word line signal applied to word line WL is high level, transistor TX can be turned on. Conversely, if the word line signal applied to word line WL is low level, transistor TX can be turned off.

[0033] The bit line BL may be a wiring structure that transfers data. The bit line BL can transfer charge to the capacitor CAP when the transistor TX is in the ON state. If the bit line signal applied to the bit line BL is at a high level and the transistor TX is in the ON state, the data "1" can be stored in the capacitor CAP. If the bit line signal applied to the bit line BL is at a low level and the transistor TX is in the ON state, the data "0" can be stored in the capacitor CAP.

[0034] The capacitor CAP may be a memory element for storing data. The capacitor CAP may have one of the following capacitor structures: a MIM (Metal-Insulator-Metal) capacitor, a MOM (Metal-Oxide-Metal) capacitor, or a MOS (Metal-Oxide-Semiconductor) capacitor, but the scope of the present invention is not limited thereto. When the capacitor CAP stores a charge above a predetermined level, the unit cell UC may be storing the data "1". When the capacitor CAP stores a charge below a predetermined level, the unit cell UC may be storing the data "0".

[0035] In the step of writing data "1" to unit cell UC, a high-level bit line signal can be applied to bit line BL and a high-level word line signal can be applied to word line WL. When transistor TX is turned on by the high-level word line signal, bit line BL becomes the drain terminal and capacitor CAP becomes the source terminal. The potential level of capacitor CAP rises due to the high-level bit line signal, and data "1" can be recorded to unit cell UC.

[0036] In the step of recording the data "0" in the unit cell UC, a low-level bit line signal can be applied to the bit line BL, and a high-level word line signal can be applied to the word line WL. When the transistor TX is turned on, the bit line BL becomes the source terminal and the capacitor CAP becomes the drain terminal. The potential level of the capacitor CAP decreases due to the low-level bit line signal, and the data "0" can be recorded in the unit cell UC.

[0037] In the step of reading data from a unit cell UC, the bit line signal may have a reference level located between the high level and the low level, and the word line signal may have a high level. When the data "1" is recorded (stored) in the unit cell UC, when the transistor TX is turned on, the potential level of the capacitor CAP is high, so the level of the bit line signal may rise above the reference level. When the data "0" is recorded in the unit cell UC, when the transistor TX is turned on, the potential level of the capacitor CAP is low, so the level of the bit line signal may fall below the reference level. The semiconductor device can determine whether the level of the bit line signal has risen or fallen above the reference level and read the data from the unit cell UC.

[0038] Figure 2 is a first plan view illustrating a part of a semiconductor device 1 according to one embodiment of the present invention.

[0039] Figure 3 is a second plan view illustrating a part of a semiconductor device 1 according to one embodiment of the present invention.

[0040] Referring to Figures 1, 2, and 3, the first and second plan views are plan views illustrating the positional relationship between multiple active regions 100 and surrounding structures. For example, the first plan view may be a plan view illustrating the positional relationship between multiple active regions 100, multiple wordline structures 300, and surrounding structures arranged on a predetermined semiconductor layer. The second plan view may be a plan view illustrating the positional relationship between multiple active regions 100 and surrounding structures arranged below a predetermined semiconductor layer.

[0041] The semiconductor device 1 may include a plurality of active regions 100, a cell isolation region 200, a plurality of word line structures 300, a plurality of bit line electrode layers 410, a plurality of bit line spacers 420, a plurality of bit line pad regions 430, a plurality of storage node pad regions 530, a plurality of storage node contact regions 540, a plurality of first pad insulating regions 710, and a plurality of second pad insulating regions 720.

[0042] Each of the multiple active regions 100 may contain a semiconductor material (e.g., silicon (Si), silicon carbide (SIC), etc.). Each of the multiple active regions 100 may be surrounded by a cell isolation region 200. The multiple active regions 100 may be arranged in a matrix structure, for example. The multiple active regions 100 may be arranged in an m × n matrix structure (where m is an integer greater than or equal to 2, and n is an integer greater than or equal to 2). Each of the multiple active regions 100 may extend in a diagonal direction DG. The diagonal direction DG may be diagonal to a first direction X. The diagonal direction DG may form an acute angle with the first direction X. Parts of the multiple active regions 100 may be spaced apart from each other along the first direction X and arranged repeatedly. Parts of the multiple active regions 100 may be spaced apart from each other along a second direction Y and arranged repeatedly. Parts of the multiple active regions 100 may be spaced apart from each other along a diagonal direction DG and arranged repeatedly. The diagonal direction DG can form an acute angle with the first direction X. The acute angle formed by the first direction X and the diagonal direction DG may be between 30 and 60 degrees. Each of the multiple active regions 100 can overlap with the wordline structure 300. Although each of the multiple active regions 100 is illustrated in a parallelogram-like shape, the scope of the present invention is not limited to such a shape. For example, embodiments in which each of the four corner regions of the active region 100 has a rounded shape are also possible. Each of the multiple active regions 100 may include a region in which the channel of the transistor TX of the unit cell UC is formed. Each of the multiple active regions 100 can be surrounded by a cell isolation region 200. One end of each of the multiple active regions 100 can overlap with the bitline electrode layer 410. The aforementioned end of each of the multiple active regions 100 can overlap with the bitline pad region 430. The other end of each of the multiple active regions 100 can overlap with the storage node contact region 540. The other end of each of the multiple active regions 100 can overlap with the storage node pad region 530.

[0043] The cell isolation region 200 may include an insulating material. For example, the cell isolation region 200 may include at least one of silicon oxide or SOI (Silicon-On-Insulator). The cell isolation region 200 may surround each of the multiple active regions 100. The cell isolation region 200 can provide electrical insulation between the multiple active regions 100 that are separated from each other.

[0044] Each of the multiple wordline structures 300 can extend along a first direction X. The multiple wordline structures 300 can be spaced apart from each other along a second direction Y. Each of the multiple wordline structures 300 can include a predetermined electrode layer to which a wordline signal is applied. When the wordline signal is at a high level in the electrode layer within the wordline structure 300, a predetermined channel can be formed within the active region 100 that overlaps with the wordline structure 300. Each of the multiple wordline structures 300 can overlap with each of the multiple active regions 100 that are spaced apart from each other along the first direction X. Each of the multiple wordline structures 300 can pass through the center of each of the multiple active regions 100 that are spaced apart from each other along the first direction X, but this may vary depending on process limits and variables. If misalignment occurs in the masking pattern for forming the wordline structures 300, there is room for each wordline structure 300 to be formed so as to be biased to one side of the center of each active region 100. In this case, the occurrence of bridges may lead to a problem of reduced reliability of the semiconductor device 1. However, in the case of the semiconductor device 1 according to the embodiment of the present invention, the aforementioned problem of reduced reliability can be resolved, and more detailed information will be explained with reference to Figure 19. The closer the center of each word line structure 300 is to the center of the active region 100 and the further it extends in the first direction X, the more the reliability of the semiconductor device 1 can be improved. The internal structure of the word line structure 300 will be explained with reference to Figure 4 and subsequent figures.

[0045] Each of the multiple bitline electrode layers 410 may include a conductive material. For example, each of the multiple bitline electrode layers 410 may include a metallic material such as aluminum, copper, or tungsten. Each of the multiple bitline electrode layers 410 may extend along a second direction Y. Each of the multiple bitline electrode layers 410 may be spaced apart from each other along a first direction X. The first direction X and the second direction Y may be perpendicular to each other. Each of the multiple bitline electrode layers 410 may be an electrode layer to which a bitline signal is applied. Each of the multiple bitline electrode layers 410 may overlap with a plurality of bitline pad regions 430 spaced apart from each other along the second direction Y. Each of the multiple bitline electrode layers 410 may intersect with a plurality of wordline structures 300. Both sides of each of the multiple bitline electrode layers 410 may be in contact with the bitline spacer 420. Each of the multiple bitline electrode layers 410 may overlap with one end of each active region 100.

[0046] Each of the multiple bit line spacers 420 may include an insulating material. For example, each of the multiple bit line spacers 420 may include an insulating material such as silicon oxide or silicon nitride. Each of the multiple bit line spacers 420 may extend along a second direction Y. Each of the multiple bit line spacers 420 may be spaced apart from each other along a first direction X. The multiple bit line spacers 420 can prevent electrical interaction between the spaced bit line electrode layers 410. The multiple bit line spacers 420 may form a pair, and a pair of bit line spacers 420 may be in contact with both sides of the bit line electrode layer 410.

[0047] Each of the multiple bit line pad regions 430 may include a conductive material. For example, each of the multiple bit line pad regions 430 may include poly-silicon. As an example, the poly-silicon may also include certain impurities to improve conductivity. Each of the multiple bit line pad regions 430 may be configured to efficiently transmit the bit line signal applied to the bit line electrode layer 410 to the active region 100. Each of the multiple bit line pad regions 430 may be positioned between two adjacent word line structures 300. As an example, each of the multiple bit line pad regions 430 may be in contact with two opposing sides of two adjacent word line structures 300. The bit line pad region 430 may overlap one end of the active region 100. In any active region 100, the bit line pad region 430 may be in contact with one side of the word line structure 300 that overlaps with the active region 100. The bit line pad region 430 can also be in contact with the active region 100 and the word line structure 300 that overlaps with the active region 100 and is separated from it in the opposite direction to the second direction Y. Some of the multiple bit line pad regions 430 can be arranged separated from each other along the first direction X. Other parts of the multiple bit line pad regions 430 can be arranged separated from each other along the second direction Y.

[0048] Each of the multiple storage node pad areas 530 may include a conductive material. For example, each of the multiple storage node pad areas 430 may include polysilicon. The polysilicon may also include certain impurities to improve conductivity. The storage node pad areas 530 may include the same material as the bit line pad areas 430. Each of the multiple storage node pad areas 530 may be positioned between two adjacent word line structures 300. As an example, each of the multiple storage node pad areas 530 may be in contact with two opposing sides of two adjacent word line structures 300. The storage node pad area 530 may overlap with the other end of the active area 100 that is opposite to the aforementioned end. In any active area 100, the storage node pad area 530 may be in contact with one side of a word line structure 300 that overlaps with the active area 100. The storage node pad area 530 may also be in contact with a word line structure 300 that overlaps with the active area 100 and is separated from the active area 100 in a second direction Y. Some of the multiple storage node pad areas 530 can be arranged spaced apart from each other in a first direction X. Other parts of the multiple storage node pad areas 530 can be arranged spaced apart from each other in a second direction Y.

[0049] Each of the multiple storage node contact areas 540 may include a conductive material. For example, each of the multiple storage node contact areas 540 may include at least one of polysilicon, aluminum, copper, and titanium. In the case of polysilicon, it may include a predetermined impurity to improve conductivity. Each of the storage node contact areas 540 may be positioned between two adjacent bit lines. The storage node contact 540 may overlap with the other end of the active area 100. A portion of the storage node contact 540 may overlap with a word line structure 300 that overlaps with the active area 100. Each of the multiple storage node contact areas 540 may be positioned spaced apart from each other in a first direction X. Each of the multiple storage node contact areas 540 may be positioned spaced apart from each other in a second direction Y.

[0050] Figure 4 is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figures 2 and 3.

[0051] Referring to Figures 2, 3, and 4, the first cross section CS1 may include a substrate region 10, an active region 100, a cell isolation region 200, a word line structure 300, a bit line structure 400, a storage node pad region 530, a storage node contact region 540, and a second pad isolation region 720.

[0052] The substrate region 10 may be a semiconductor region located below the active region 100. The substrate region 10 may contain a semiconductor material. For example, the substrate region 10 may contain at least one of silicon, silicon germanium, or a combination thereof.

[0053] The active region 100 can be positioned at a predetermined distance from the surface (top surface in the drawing) of the semiconductor layer SL. The active region 100 can be in contact with the side and bottom surfaces of the wordline structure 300. For example, the active region 100 can enclose the side and bottom surfaces of the wordline insulating layer 340.

[0054] When a channel is formed within the active region 100, the charge carrier can move from the bit line electrode layer 410 through the bit line contact region 440, the bit line pad region 430, the active region 100, the storage node pad region 530, and the storage node contact region 540 to a capacitor (not shown) connected to the storage node contact region 540 (CAP in Figure 1) (it is also possible to move in the opposite direction, from the capacitor to the bit line electrode layer 410). Both sides of the active region 100 can come into contact with the cell isolation region 200.

[0055] The cell isolation region 200 can be in contact with the side surface of the active region 100. The upper surface of the cell isolation region 200 can be in contact with the second pad isolation region 720. In embodiments in which the bit line pad region 430 or the storage node pad region 530 is formed to be thicker horizontally than shown in Figures 3 and 4, the upper surface of the cell isolation region 200 can also be in contact with the bit line pad region 430 or the storage node pad region 530.

[0056] The wordline structure 300 may include a first wordline electrode layer 310, a second wordline electrode layer 320, a wordline capping layer 330, and a wordline insulating layer 340. The wordline structure 300 may extend (or recess) into the semiconductor layer SL at a predetermined depth along a third direction Z from the same plane as the upper surface of the bitline pad region 530. The wordline structure 300 is preferably formed in the central region of the active region 100, but this may vary depending on process limits, variables, and defects. In this description, the surface of the semiconductor layer SL can be defined as the position on the same plane as the surface in contact with the lower surface of the first pad insulating region 710 and the cell isolation region 200 in Figure 6, which will be described later.

[0057] The first wordline electrode layer 310 may include a conductive material. For example, the first wordline electrode layer 310 may include tungsten, aluminum, copper, tungsten nitride, tungsten silicide, cobalt silicide, titanium silicide, tantalum nitride, or a combination thereof. The first wordline electrode layer 310 may be placed beneath the second wordline electrode layer 320. The sides and bottom of the first wordline electrode layer 310 may be surrounded by the wordline insulating layer 340.

[0058] The second wordline electrode layer 320 may include a conductive material. For example, the second wordline electrode layer 320 may include tungsten, aluminum, copper, tungsten nitride, tungsten silicide, cobalt silicide, titanium silicide, tantalum nitride, or a combination thereof. The second wordline electrode layer 320 may also be an area in which a predetermined impurity (e.g., phosphorus, germanium, etc.) is implanted. The second wordline electrode layer 320 may be placed on the first wordline electrode layer 310. The second wordline electrode layer 320 may be placed below the wordline capping layer 330. Both sides of the second wordline electrode layer 320 may be in contact with the wordline insulating layer 340.

[0059] Although not shown in the drawings, a predetermined antioxidant layer can be placed between the first and second wordline electrode layers 310 and 320. The predetermined antioxidant layer can capture impurities (e.g., oxygen) contained within the first and second wordline electrode layers 310 and 320.

[0060] The first and second word line electrode layers 310 and 320 can have a word line signal applied to them. When the word line signal is at a high level, a channel can be formed in the active region 100 through which charge moves around the word line structure 300. When the word line signal is at a low level, the channel may not be formed. When the channel is formed, the bit line electrode layer 410 and the storage node contact 540 can be electrically connected as described above. For example, in the operation of recording data "1", when a high-level bit line signal is applied to the bit line electrode layer 410 and the first and second word line electrode layers 310 and 320, charge can move to the storage node contact 540 according to the bit line signal of the bit line electrode layer 410, via the bit line contact region 440, the bit line pad region 430, the channel, and the storage node pad region 530. Since the storage node contact 540 can be electrically connected to a predetermined capacitor structure (not shown), the charge can be stored in the capacitor structure via the storage node contact 540. The capacitor structure can be modeled on a circuit diagram as shown in capacitor CAP in Figure 1.

[0061] The word line capping layer 330 may include an insulating material. For example, the word line capping layer 330 may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. The word line capping layer 330 may be placed on the second word line electrode layer 320. The word line capping layer 330 may be a region filled with insulating material between the surface of the semiconductor layer SL and the upper surface of the second word line electrode layer 320. The word line capping layer 330 can electrically isolate the first and second word line electrode layers 310, 320 from the bit line structure 400. The word line capping layer 330 can electrically isolate the first and second word line electrode layers 310, 320 from the storage node contact 540. Although the drawing shows that the depth of the word line capping layer 330 from the surface of the semiconductor layer SL is shallower than the depth of the bit line pad area 430 or the depth of the storage node pad area 530, according to other embodiments, the depth of the word line capping layer 330 may be formed to be deeper than the depth of both the bit line pad area 430 and the storage node pad area 530.

[0062] The wordline insulating layer 340 may include an insulating material. For example, the wordline insulating layer 340 may include silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. The wordline insulating layer 340 may be formed along the sides and bottom surface of the wordline structure 300. The wordline insulating layer 340 can physically isolate the first and second wordline electrode layers 310, 320 from the active region 100. The wordline insulating layer 340 can electrically isolate the first and second wordline electrode layers 310, 320 from the storage node pad region 530.

[0063] The bit line structure 400 may include a bit line electrode layer 410, a bit line spacer 420, a bit line pad region 430, a bit line contact region 440, and a bit line capping layer 450.

[0064] The bit line electrode layer 410 may include a conductive material. For example, the bit line electrode layer 410 may include tungsten, aluminum, copper, tungsten nitride, tungsten silicide, cobalt silicide, titanium silicide, tantalum nitride, or a combination thereof. The bit line electrode layer 410 may be positioned away from the surface of the semiconductor layer SL. The bit line electrode layer 410 may be positioned away from the bit line pad region 430. When viewed from a third direction Z, the bit line electrode layer 410 may overlap with the bit line pad region 430. The bit line electrode layer 410 may overlap with the word line structure 300. Each of the two sides of the bit line electrode layer 410 may be in contact with the bit line spacer 420. The bit line electrode layer 410 may be positioned below the bit line capping layer 450.

[0065] The bit line spacer 420 may include an insulating material. For example, the bit line spacer 420 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The bit line spacer 420 can contact both sides of the bit line electrode layer 410, respectively. The bit line spacer 420 can contact both sides of the bit line contact area 440. The bit line spacer 420 can contact both sides of the bit line capping layer 450. The bit line spacer 420 can electrically isolate the bit line electrode layer 410 from the storage node contact area 540. The bit line spacer 420 can electrically isolate the bit line contact area 440 from the storage node contact area 540.

[0066] The bit line pad region 430 may include a conductive material. For example, the bit line pad region 430 may include polysilicon. The polysilicon may include predetermined impurities. The bit line pad region 430 may be formed to have a predetermined height from below the surface of the semiconductor layer SL to above the surface of the semiconductor layer SL. The lower surface of the bit line pad region 430 may be located below the surface of the semiconductor layer SL, and the upper surface of the bit line pad region 430 may be located above the surface of the semiconductor layer SL. The lower surface of the bit line pad region 430 may be in contact with the active region 100. One side of the bit line pad region 430 may be in contact with the word line structure 300. The other side of the bit line pad region 430 may be in contact with the second pad insulating region 720.

[0067] Without the bit line pad region 430, if the word line structure 300 is formed misaligned from the center of the active region 100 toward the bit line contact region 440 (based on Figure 4, where the word line structure 300 is formed biased to the left), the contact area between the bit line contact region 440 and the active region 100 may decrease, potentially leading to increased contact resistance, decreased current capacity, and performance degradation due to temperature rise. However, when the bit line pad region 430 is formed, the upper surface of the bit line pad region 430 can ensure contact area with the bit line contact region 440, and the lower surface of the bit line pad region 430 can ensure contact area with the active region 100, resulting in reduced contact resistance, increased current capacity, reduced temperature rise, and improved performance of the semiconductor device 1.

[0068] The bit line contact region 440 may include a conductive material. For example, the bit line contact region 440 may include at least one of polysilicon, copper, aluminum, titanium, titanium nitride, or a combination thereof. The bit line contact region 440 may use the same material as the bit line electrode layer 410, or it may use different materials. If different materials are used, for example, it may be more advantageous to select a highly conductive metallic material for the bit line electrode layer 410, while it may be more advantageous to select a material for the bit line contact region 440 that is advantageous in reducing the contact resistance between the bit line electrode layer 410 and the bit line pad region 430. The bit line contact region 440 may be in contact with the underside of the bit line electrode layer 410. Each of the two sides of the bit line contact region 440 may be in contact with the bit line spacer 420. The underside of the bit line contact region 440 may be in contact with the bit line pad region 430. The bit line contact region 440 may be placed on the surface of the semiconductor layer SL.

[0069] The bit line capping layer 450 may include an insulating material. For example, the bit line capping layer 450 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The bit line capping layer 450 may be in contact with the upper surface of the bit line electrode layer 410. The bit line capping layer 450 may be in contact with the bit line spacer 420. Together with the bit line spacer 420, the bit line capping layer 450 can prevent electrical interaction between the bit line electrode layer 410 and the bit line contact region 420, which are positioned around the bit line structure 400.

[0070] The storage node pad region 530 may include a conductive material. For example, the storage node pad region 530 may include polysilicon. The polysilicon may include predetermined impurities. The storage node pad region 530 may be formed to have a predetermined height from below the surface of the semiconductor layer SL to above the surface of the semiconductor layer SL. The lower surface of the storage node pad region 530 may be located below the surface of the semiconductor layer SL, and the upper surface of the storage node pad region 530 may be located above the surface of the semiconductor layer SL. The lower surface of the storage node pad region 530 may be in contact with the active region 100. One side of the storage node pad region 530 may be in contact with the second pad insulating region 720. The other side of the storage node pad region 530 may be in contact with the wordline structure 300.

[0071] Without the storage node pad area 530, if the word line structure 300 is misaligned from the center of the active area 100 toward the storage node contact area 540 (based on Figure 4, where the word line structure 300 is formed biased to the right), the contact area between the storage node contact area 540 and the active area 100 may decrease, potentially leading to increased connection resistance, decreased current capacity, and performance degradation due to temperature rise. However, when the storage node pad area 530 is formed, the upper surface of the storage node pad area 530 can ensure contact area with the storage node contact area 540, and the lower surface of the storage node pad area 530 can ensure contact area with the active area 100, resulting in reduced contact resistance, increased current capacity, reduced temperature rise, and improved performance of the semiconductor device 1.

[0072] The storage node contact area 540 may include a conductive material. For example, the storage node contact area 540 may include at least one of polysilicon, copper, aluminum, titanium, titanium nitride, or a combination thereof. The lower surface of the storage node contact area 540 may be in contact with the storage node pad area 530. One side of the storage node contact area 540 may be in contact with the bit line spacer 420.

[0073] In the following explanations of Figures 5 to 18f, explanations that overlap with those explained in Figures 1 to 4 will be omitted as much as possible.

[0074] Figure 5 is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figures 2 and 3.

[0075] Referring to Figures 2, 3, 4, and 5, the second cross section CS2 may include a substrate region 10, an active region 100, a cell isolation region 200, a first word line electrode layer 310, a second word line electrode layer 320, a word line capping layer 330, a word line insulating layer 340, a bit line electrode layer 410, a bit line spacer 420, a bit line contact region 440, a bit line capping layer 450, and a contact insulating region 600.

[0076] The first wordline electrode layer 310 can extend along the first direction X. The first wordline electrode layer 310 can be placed on the wordline insulating layer 340. The second wordline electrode layer 320 can extend along the first direction X. The second wordline electrode layer 320 can be placed on the first wordline electrode layer 310. The wordline capping layer 330 can extend along the first direction X. The wordline capping layer 330 can be placed on the second wordline electrode layer 320. The wordline insulating layer 340 can extend along the first direction X. The lower surface of the wordline insulating layer 340 can be in contact with the cell isolation region 200 and the active region 100.

[0077] In Figure 5, the lower surface of the wordline insulating layer 340 is shown to be formed horizontally. However, depending on the process, the etching rates of the active region 100 and the cell isolation region 200 may differ, and the lower surface of the wordline insulating layer 340 may be formed lower above the cell isolation region 200 than above the active region 100 (i.e., the wordline insulating layer 340 may be formed at a deeper location above the cell isolation region 200 than above the active region 100). Hereinafter, this disclosure will exemplify embodiments in which the lower surface of the wordline insulating layer 340 is formed horizontally.

[0078] Multiple bit line electrode layers 410 can be arranged spaced apart from each other along a first direction X. Both sides of each of the multiple bit line electrode layers 410 can be in contact with a bit line spacer 420. A contact insulating layer 600 can be placed between bit line spacers 420 arranged on one side of different bit line electrode layers 410.

[0079] The contact insulating layer 600 may include an insulating material. For example, the contact insulating layer 600 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. A more detailed description of the contact insulating layer 600 will be provided later with reference to Figure 8.

[0080] Figure 6 is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figures 2 and 3.

[0081] Referring to Figures 2, 3, 4, and 6, the third cross-section CS3 may include a substrate region 10, an active region 100, a cell separation structure 200, a bit line electrode layer 410, a bit line spacer 420, a bit line pad region 430, a bit line contact region 440, a bit line capping layer 450, a storage node pad region 530, a storage node contact region 540, a first pad insulation region 710, and a second pad insulation region 720.

[0082] The lower surface of the bit line pad area 430 can be in contact with the active area 100 and the cell isolation area 200. A portion of one side of the bit line pad area 430 (right side, as per Figure 6) can be in contact with the cell isolation area 200. Another portion of the aforementioned side of the bit line pad area 430 can be in contact with the first pad insulation area 710. A portion of the other side of the bit line pad area 430 (left side, as per Figure 6) can be in contact with the second pad insulation area 720. The upper surface of the bit line pad area 430 can be in contact with the bit line contact area 440.

[0083] The storage node pad area 530 can be in contact with the upper surface of the active area 100. A portion of one side of the storage node pad area 530 (left side, reference to Figure 6) can be in contact with the cell isolation area 200. Another portion of the aforementioned side of the storage node pad area 530 can be in contact with the first pad isolation area 710. The other side of the storage node pad area 530 (right side, reference to Figure 6) can be in contact with the second pad isolation area 720.

[0084] Each of the multiple bit line pad areas 430 and storage node pad areas 530 can be arranged alternately with respect to each other along a first direction X. The height of the bit line pad areas 430 may be the same as the height of the storage node pad areas 530, but the scope of the present invention is not limited thereto. For example, the height of the bit line pad areas 430 may be greater than or the same as the height of the storage node pad areas 530. The lower surface of the bit line pad area 430 may be lower than the lower surface of the first pad isolation area 710. The lower surface of the storage node pad area 530 may be lower than the lower surface of the first pad isolation area 710. The lower surface of the bit line pad area 430 may be located on the same plane as the lower surface of the second pad isolation area 720. The lower surface of the storage node pad area 530 may be located on the same plane as the lower surface of the second pad isolation area 720.

[0085] Each of the two sides of the storage node contact area 540 can contact the bit line spacer 420. The bottom surface of the storage node contact area 540 can contact the storage node pad area 530. Depending on the embodiment, a portion of the bottom surface of the storage node contact area 540 can contact the first pad isolation area 710 and / or the second pad isolation area 720.

[0086] Each of the multiple bit line contact areas 430 can contact the upper surface of the bit line pad area 430. On the other hand, each of the multiple storage node contact areas 540 can contact the upper surface of the storage node pad area 530.

[0087] The first pad insulating region 710 may include an insulating material. For example, the first pad insulating region 710 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The first pad insulating region 710 can be positioned between adjacent bit line pad regions 430 and storage node pad regions 530. The first pad insulating region 710 may be in contact with one side of the bit line pad region 430. The first pad insulating region 710 may be in contact with the side of the bit line pad region 430 facing the first direction X (right side, top of Figure 6). The first pad insulating region 710 may be in contact with one side of the storage node pad region 530. The first pad insulating region 710 may be in contact with the side of the storage node pad region 530 facing the opposite direction of the first direction X (left side, top of Figure 6). The first pad insulating region 710 may be formed to a first height from the top surface of the cell isolation region 200 (top surface of the semiconductor layer SL). The upper surface of the first pad insulating area 710 can, for example, be placed on the same plane as the upper surface of the bit line pad area 430.

[0088] The second pad insulating region 720 may include an insulating material. The second pad insulating region 720 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. For example, the second pad insulating region 720 may include the same material as the first pad insulating region 710. The second pad insulating region 720 may be positioned between adjacent bit line pad regions 430 and storage node pad regions 530. The second pad insulating region 720 may be in contact with the other side of the bit line pad region 430. The second pad insulating region 720 may be in contact with the side of the bit line pad region 430 facing the opposite direction from the first direction X. The second pad insulating region 720 may be in contact with the other side of the storage node pad region 530. The second pad insulating region 720 may be in contact with the side of the storage node pad region 530 facing the first direction X. The second pad insulating region 720 may be formed only to a second height. The upper surface of the second pad insulating region 720 can, for example, be placed on the same plane as the upper surface of the bit line pad region 430. The lower surface of the second pad insulating region 720 can be positioned lower than the upper surface of the semiconductor layer SL.

[0089] Figure 7 is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figures 2 and 3.

[0090] Referring to Figures 2, 3, 4, and 7, the fourth cross section CS4 may include a substrate region 10, an active region 100, a cell separation structure 200, a bit line pad region 430, a first word line electrode layer 310, a second word line electrode layer 320, a word line capping layer 330, a word line insulating layer 340, a bit line electrode layer 410, a bit line contact region 440, and a bit line capping layer 450.

[0091] The bitline electrode layer 410 can extend along the second direction Y. The bitline contact region 440 can extend along the second direction Y. The bitline capping layer 450 can extend along the second direction Y.

[0092] A portion of the lower surface of the wordline structure 300 can be in contact with the active region 100. Another portion of the lower surface of the wordline structure 300 can be in contact with the cell separation region 200. A portion of one side of the wordline structure 300 (e.g., the bottom) can be in contact with the active region 100. Another portion of one side of the wordline structure 300 (e.g., the top) can be in contact with the bitline pad region 430. A portion of the other side of the wordline structure 300 (e.g., the bottom) can be in contact with the cell separation region 200. The top of the other side of the wordline structure 300 (e.g., the top) can be in contact with the bitline pad region 430.

[0093] Each of the multiple bitline pad areas 430 can be placed between adjacent wordline structures 300.

[0094] Figure 8 is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figures 2 and 3.

[0095] Referring to Figures 2, 3, 4, and 8, the fifth section CS5 may include a substrate region 10, an active region 100, a cell isolation structure 200, a wordline structure 300, a storage node pad region 530, a storage node contact region 540, and a contact isolation region 600.

[0096] Both sides of each of the multiple storage node contact areas 540 can be in contact with the contact isolation area 600. Both sides of each of the multiple contact isolation areas 600 can be in contact with the storage node contact area 540. The multiple storage node contact areas 540 and the multiple contact isolation areas 600 can be arranged alternately and repeatedly along the second direction Y.

[0097] The active region 100 can be in contact with a portion of the lower surface and a portion of one side (top left side, Figure 8) of the wordline structure 300 (e.g., the bottom). The cell separation region 200 can be in contact with another portion of the lower surface and a portion of another side (top right side, Figure 8) of the wordline structure 300 (e.g., the bottom).

[0098] The storage node pad area 530 can be in contact with a part of one side (e.g., the top) of the wordline structure 300. The storage node pad area 530 can be in contact with a part of the other side (e.g., the top) of the wordline structure 300.

[0099] Figure 9 is a flowchart illustrating an exemplary method for manufacturing a semiconductor device 1 according to one embodiment of the present invention.

[0100] Figures 10a to 18f are plan views or cross-sectional views illustrating the manufacturing method of the semiconductor device 1 according to Figure 9.

[0101] Figure 10a is a plan view illustrating the results of performing step S10 in Figure 9.

[0102] Referring to Figures 2, 3, 9, and 10a to 10f, the method for manufacturing the semiconductor device 1 (hereinafter referred to as "this manufacturing method") may include the step (S10) of forming a plurality of active regions 100 and cell isolation regions 200 surrounding the plurality of active regions 100.

[0103] Referring to Figure 10a, some of the multiple active regions 100 can be formed repeatedly, spaced apart from each other along the first direction X. Other parts of the multiple active regions 100 can be formed repeatedly, spaced apart from each other along the second direction Y. Other parts of the multiple active regions 100 can be formed repeatedly, spaced apart from each other along the diagonal direction DG. Each of the multiple active regions 100 can be formed in a form that extends along the diagonal direction DG. The angle between the diagonal direction DG and the first direction X may be between 30 degrees and 60 degrees.

[0104] Next, a cell isolation region 200 can be formed in which the remaining empty spaces other than the multiple active regions 100 are gap-filled with an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.).

[0105] Figure 10b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 10a.

[0106] Referring to Figures 10a and 10b, a predetermined trench can be formed from the upper surface of a semiconductor layer SL containing a semiconductor material (e.g., silicon, silicon germanium, etc.). The region remaining after the trench is formed may be an active region 100 or a substrate region 10. In this description, the active region 100 can be defined as a region having the same depth as the predetermined trench. In this example, the substrate region 10 is in contact with the lower surface of the active region 100 and can be defined as the remaining region other than the active region 100 after the formation of the predetermined trench.

[0107] After the predetermined trench is formed, a cell isolation region 200 can be formed by gap-filling the inside of the trench with an insulating material.

[0108] Figure 10c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 10a.

[0109] Figure 10d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 10a.

[0110] Referring to Figures 10a, 10c, and 10d, multiple active regions 100 can be repeatedly formed along the first direction X by the operation of forming the predetermined trench. Cell separation regions 200 can be formed between the multiple active regions 100.

[0111] Figure 10e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 10a.

[0112] Figure 10f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 10a.

[0113] Referring to Figures 10a, 10e, and 10f, multiple active regions 100 can be repeatedly formed along the second direction Y by the operation of forming the predetermined trench. Cell separation regions 200 can be formed between the multiple active regions 100.

[0114] The following explanation of Figures 11a to 11f will focus on the differences between them and Figures 10a to 10f.

[0115] Figure 11a is a plan view illustrating the results of performing step S20 in Figure 9.

[0116] Referring to Figures 2, 3, 9, and 11a to 11f, the manufacturing method may include a step (S20) of depositing a first pad insulating layer HM1 onto a plurality of active regions 100 and cell isolation regions 200.

[0117] Referring to Figures 10a and 11a, a first pad insulating layer HM1 can be deposited overlapping each of the multiple active regions 100 and cell isolation regions 200. The first pad insulating layer HM1 may contain the same material as the first pad insulating region 710 described in the description relating to Figure 3.

[0118] Figure 11b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 11a.

[0119] Referring to Figures 10a, 11a, and 11b, the first pad insulating layer HM1 can be deposited on the upper surface of the semiconductor layer SL. The first pad insulating layer HM1 can be placed on the upper surface of the semiconductor layer SL to a predetermined thickness.

[0120] Figure 11c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 11a.

[0121] Figure 11d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 11a.

[0122] Referring to Figures 10a, 11a, 11c, and 11d, the first pad insulating layer HM1 can be deposited extending along the first direction X on the upper surface of the semiconductor layer SL.

[0123] Figure 11e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 11a.

[0124] Figure 11f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 11a.

[0125] Referring to Figures 10a, 11a, 11e, and 11f, the first pad insulating layer HM1 can be deposited extending along the second direction Y on the upper surface of the semiconductor layer SL.

[0126] Below, we will explain Figures 12a to 12f, focusing on the differences between them and Figures 11a to 11f.

[0127] Figure 12a is a plan view illustrating the results of performing step S30 in Figure 9.

[0128] Referring to Figures 2, 3, 9, and 12a to 12f, the manufacturing method may include the step (S30) of forming open trenches OT by etching a portion of each of the multiple active regions 100 and a portion of the first pad insulating layer HM1.

[0129] Referring to Figures 11a and 12a, the open trench OT can be formed to overlap with portions of each of two active regions 100 that are adjacent to each other in the first direction X. In Figure 12a, the portion of the active region 100 that overlaps with the left portion of each of the multiple open trench OTs may be the portion that overlaps with the storage node contact region 540 and the storage node pad region 530 in Figure 2.

[0130] In Figure 12a, the portion of the active region 100 that overlaps with the right-hand portion of each of the multiple open trenches OT may also be the portion that overlaps with the bit line electrode layer 410 in Figure 2 and the bit line pad region 430 in Figure 3.

[0131] Figure 12b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 12a.

[0132] Referring to Figures 11a, 12a, and 12b, some of the multiple open trenches OT may be trenches in which one end of the active region 100 (left side in Figure 12b) is etched to a predetermined depth. The open trenches OT may also be trenches in which a portion of the cell isolation region 200 adjacent to one end of the active region 100 is etched to the predetermined depth. The portion of the etched cell isolation region 200 and the portion of the first pad insulating layer HM1 placed on the etched portion of the active region 100 are both etched and removed.

[0133] Some of the open trenches OT may be trenches in which the other end of the active region 100 (upper right side of Figure 12b) is etched to the predetermined depth. The open trenches OT may also be trenches in which another portion of the cell isolation region 200 adjacent to the other end of the active region is etched to the predetermined depth. The other portion of the etched cell isolation region 200 and the portion of the first pad insulating layer HM1 placed on the etched portion of the active region 100 are both etched and removed.

[0134] Figure 12c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 12a.

[0135] Figure 12d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 12a.

[0136] Referring to Figures 11a, 12a, 12c, and 12d, each of the multiple open trenches OT can recess from the surface of the first pad insulating layer HM1 into the interior of the semiconductor layer SL. Each of the multiple open trenches OT can be formed to overlap a portion of each of two adjacent active regions 100. Each of the multiple open trenches OT can be separated along a first direction X and repeatedly formed.

[0137] Since the open trench OT is formed over a portion of each of two active regions 100 adjacent to each other in the first direction X, the width of the open trench OT in the first direction X can be formed relatively wide, and considering the minimum pitch for which etching is possible, the process burden of the open trench OT can be reduced.

[0138] Figure 12e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 12a.

[0139] Figure 12f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 12a.

[0140] Referring to Figures 11a, 12a, 12e, and 12f, the open trench OT can extend along the second direction Y.

[0141] Below, we will explain Figures 13a to 13f, focusing on the differences between them and Figures 12a to 12f.

[0142] Figure 13a is a plan view illustrating the results of performing step S40 in Figure 9.

[0143] Referring to Figures 2, 3, 9, and 13a to 13f, the manufacturing method may include the step (S40) of forming a pad layer PAD that covers a first pad insulating layer HM1 and an open trench OT.

[0144] Referring to Figures 12a and 13a, a pad layer PAD can be placed inside the open trench OT. The pad layer PAD may contain the same material (e.g., polysilicon) as the bit line pad area 430 and storage node pad area 530 in Figure 3.

[0145] Figure 13b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 13a.

[0146] Referring to Figures 12a, 13a, and 13b, the pad layer PAD can cover the top and both sides of the first pad insulating layer HM1. The pad layer PAD can be formed along the inner wall of the open trench OT. The pad layer PAD can be formed at a predetermined height from the bottom surface of the open trench OT when viewed from a third direction Z.

[0147] Figure 13c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 13a.

[0148] Figure 13d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 13a.

[0149] Referring to Figures 12a, 13a, 13c, and 13d, the pad layer PAD can be formed to cover the lower and side surfaces of the open trench OT and the upper and side surfaces of the first pad insulating layer HM1 along the first direction X.

[0150] Figure 13e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 13a.

[0151] Figure 13f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 13a.

[0152] Referring to Figures 12a, 13a, 13e, and 13f, the pad layer PAD can extend along the second direction Y.

[0153] Below, we will explain Figures 14a to 14f, focusing on the differences between them and Figures 13a to 13f.

[0154] Figure 14a is a plan view illustrating the results of performing step S50 in Figure 9.

[0155] Referring to Figures 2, 3, 9, and 14a to 14f, the manufacturing method may include a step (S50) of removing the portion of the pad layer PAD formed in the center of the open trench OT, thereby physically separating the pad layer PAD in contact with one side of the open trench OT from the pad layer PAD in contact with the other side of the open trench OT.

[0156] Referring to Figures 13a and 14a, when a pad layer PAD is connected between two separated active regions 100, the two active regions 100, which should be electrically separated from each other, become electrically connected, so the portion of the pad layer PAD formed in the center of the open trench OT needs to be removed. A gap region G can be formed by removing a portion of the pad layer PAD between two adjacent active regions 100 in the first direction X. In Figure 14a, the gap region G is shown to be in contact with the ends of the separated active regions 100 in the first direction X, but the scope of the present invention is not limited thereto, and the width of the gap region G in the first direction X can be formed to be narrower (i.e., the width of the remaining pad layer PAD in the first direction X may be wider). For convenience of explanation, this disclosure describes an embodiment in which the gap region G is formed to be in contact with the ends of two adjacent active regions 100 in the first direction X. The gap region G can extend in the second direction Y.

[0157] Figure 14b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 14a.

[0158] Referring to Figures 13a, 14a, and 14b, the pad layer PAD remaining after the etching process of the pad layer PAD in step S50 can be located above both ends of the active region 100, respectively. The pad layer PAD can be in contact with the side surface of the first pad insulating layer HM1.

[0159] Figure 14c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 14a.

[0160] Figure 14d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 14a.

[0161] Referring to Figures 13a, 14a, 14c, and 14d, the gap regions G can be spaced apart and repeated along a first direction X. The gap regions G can be located in the center of the open trench OT. In the two adjacent active regions 100 in Figure 14c, the pad layer PAD touching the right end of the left active region 100 and the pad layer PAD touching the left end of the right active region 100 can be physically separated from each other. In step S50, the etching process of the pad layers PAD can be performed to such an extent that all of the pad layers PAD located in the center of the open trench OT can be removed.

[0162] Figure 14e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 14a.

[0163] Figure 14f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 14a.

[0164] Figure 14e may be substantially identical to the cross-section of Figure 13e. Figure 14f may be substantially identical to the cross-section of Figure 13f.

[0165] Below, we will explain Figures 15a to 15f, focusing on the differences between them and Figures 14a to 14f.

[0166] Figure 15a is a plan view illustrating the results of performing step S60 in Figure 9.

[0167] Referring to Figures 2, 3, 9, and 15a to 15f, the manufacturing method may include the step (S60) of forming a second pad insulating layer HM2 that gap-fills the gap region G, which is the central part of the open trench OT.

[0168] Referring to Figures 14a and 15a, a second pad insulating layer HM2 can be formed to gap-fill the gap region (G in Figure 14a) with an insulating material. The second pad insulating layer HM2 can extend along the second direction Y. Multiple second pad insulating layers HM2 can be arranged repeatedly and spaced apart along the first direction X.

[0169] Figure 15b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 15a.

[0170] Referring to Figures 14a, 15a, and 15b, a second pad insulating layer HM2 can be formed on the side surface of the pad layer PAD. After forming the second pad layer HM2, a planarization process may be performed. The first pad insulating layer HM1 may have a first height H1. The first pad insulating layer HM1 may be placed on the upper surface of the semiconductor layer SL. The lower surface of the first pad insulating layer HM1 may be in the same plane as the upper surface of the semiconductor layer SL. The second pad insulating layer HM2 may have a second height H2. The second height H2 may be greater than the first height H1. The lower surface of the second pad insulating layer HM2 may be in the same plane as the lower surface of the open trench OT. The upper surface of the first pad insulating layer HM1 and the upper surface of the second pad insulating layer HM2 may be in the same plane. The upper surface of the pad layer PAD may also be in the same plane as the upper surfaces of the first pad insulating layer HM1 and the second pad insulating layer HM2, respectively.

[0171] Figure 15c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 15a.

[0172] Figure 15d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 15a.

[0173] Referring to Figures 14a, 15a, 15c, and 15d, the second pad insulating layer HM2 can be placed in the space between two pad layers PAD located spaced apart from each other in a first direction X within each open trench OT. Multiple second pad insulating layers HM2 can be formed repeatedly, spaced apart from each other along the first direction X. The second pad insulating layer HM2 can be formed on the cell isolation region 200.

[0174] Figure 15e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 15a.

[0175] Figure 15f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 15a.

[0176] Figure 15e may be substantially identical to the cross-section of Figure 14e. Figure 15f may be substantially identical to the cross-section of Figure 14f.

[0177] Below, we will explain Figures 16a to 16f, focusing on the differences between them and Figures 15a to 15f.

[0178] Figure 16a is a plan view illustrating the results of performing step S70 in Figure 9.

[0179] Referring to Figures 2, 3, 9, and 16a to 16f, this manufacturing method may include a step (S70) of forming a plurality of wordline structures 300.

[0180] Referring to Figures 9, 10a, and 16a, the wordline structure 300 can be formed to extend along a first direction X. The wordline structure 300 can be formed through a pad layer PAD. The wordline structure 300 can cut through a portion of the pad layer PAD. In this description, the portion of the pad layer PAD remaining after cutting can be defined as the bitline pad layer 430, and the other portion of the pad layer PAD remaining after cutting can be defined as the storage node pad layer 530. The wordline structure 300 can be formed through a first pad insulating layer HM1 and a second pad insulating layer HM2. The wordline structure 300 can cut through a portion of the first pad insulating layer HM1 and a second pad insulating layer HM2. The portion of the first pad insulating layer HM1 remaining after cutting can be defined as the first pad insulating region 710. The portion of the second pad insulating layer HM2 remaining after cutting can be defined as the second pad insulating region 720.

[0181] Multiple first pad isolation regions 710 can be spaced apart and repeated along the second direction Y. Each of the multiple first pad isolation regions 710 can be positioned between adjacent word line structures 300 in the second direction Y. One side of the multiple first pad isolation regions 710 (the left side in Figure 16a) can be in contact with the bit line pad region 430. The other side of the multiple first pad isolation regions 710 (the right side in Figure 16a) can be in contact with the storage node pad region 530.

[0182] Multiple second pad isolation regions 720 can be spaced apart and repeated along the second direction Y. Each of the multiple second pad isolation regions 720 can be positioned between adjacent word line structures 300 in the second direction Y. One side of the multiple second pad isolation regions 720 (the left side in Figure 16a) can be in contact with the storage node pad region 530. The other side of the multiple second pad isolation regions 720 (the right side in Figure 16a) can be in contact with the bit line pad region 430.

[0183] Multiple bit line pad regions 430 can overlap one end of the active region 100. Multiple bit line pad regions 430 can be spaced apart and repeated along the second direction Y. Multiple bit line pad regions 430 can be placed between word line structures 300 adjacent to each other in the second direction Y. One side of the multiple bit line pad regions 430 (the left side in Figure 16a) can be in contact with the second pad insulating region 720. The other side of the multiple bit line pad regions 430 (the right side in Figure 16a) can be in contact with the first pad insulating region 710.

[0184] Multiple storage node pad areas 530 can overlap the other end of the active area 100. Multiple storage node pad areas 530 can be spaced apart and repeated along the second direction Y. Multiple storage node pad areas 530 can be placed between word line structures 300 adjacent to each other in the second direction Y. One side of a plurality of storage node pad areas 530 (the left side in Figure 16a) can be in contact with the first pad isolation area 710. The other side of a plurality of storage node pad areas 530 (the right side in Figure 16a) can be in contact with the second pad isolation area 720.

[0185] Figure 16b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 16a.

[0186] Figure 16c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 16a.

[0187] Referring to Figures 15a, 16a, 16b, and 16c, a word line trench WT can be formed extending along a third direction Z from the plane on which the upper surface of the bit line pad region 430 and the upper surface of the storage node pad region 530 are located. The word line trench WT may have a greater recess depth in the third direction Z from the upper surface of the semiconductor layer SL than the open trench OT shown in Figure 12b and other figures. After the word line trench WT is formed, a word line insulating layer 340 can be formed in contact with the lower and side surfaces of the word line trench WT and extending along a first direction X. Next, a first word line electrode layer 310 can be formed on the word line insulating layer 340 and extending along the first direction X. Next, a second word line electrode layer 320 can be formed on the first word line electrode layer 310 and extending along the first direction X.

[0188] As illustrated in Figures 16b and 16c, an embodiment is illustrated in which the upper surface of the semiconductor layer SL is located higher than the upper surface of the first word line electrode layer 310 and lower than the upper surface of the second word line electrode layer 320; however, the scope of the present invention is not limited thereto. For example, the upper surface of the second word line electrode layer 320 can also be located lower than the upper surface of the semiconductor layer SL.

[0189] Figure 16d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 16a.

[0190] Referring to Figures 15a, 15d, 16a, and 16d, Figure 16d may have substantially the same cross-section as Figure 15d. The first pad isolation region 710 can be positioned on the upper surface of the semiconductor layer SL so as to be in contact with the cell isolation region 200. The bit line pad region 430 can be positioned so as to be in contact with one side of the first pad isolation region 710 (the left side in Figure 16d). The storage node pad region 530 can be positioned so as to be in contact with the other side of the first pad isolation region 710 (the right side in Figure 16d). The second pad isolation region 720 can be positioned so as to be in contact with one side of the bit line pad region 430 (the left side in Figure 16d). The second pad isolation region 720 can be positioned so as to be in contact with one side of the storage node pad region 530 (the right side in Figure 16d).

[0191] The first pad isolation region 710 may have a first height H1. The second pad isolation region 720, the bit line pad region 430, and the storage node pad region 530 may have a second height H2.

[0192] Figure 16e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 16a.

[0193] Referring to Figures 15a, 16a, and 16e, multiple wordline structures 300 can be arranged repeatedly, spaced apart from one another along the second direction Y. One side of the wordline structure 300 can be in contact with the bitline pad region 430, which is in contact with the active region 100, and the lower surface of the wordline structure 300 is in contact with the side surface.

[0194] Figure 16f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 16a.

[0195] Referring to Figures 15a, 16a, and 16f, multiple wordline structures 300 can be arranged repeatedly, spaced apart from each other along the second direction Y. One side of the wordline structure 300 can be in contact with the storage node pad area 530, which is in contact with the active area 100, which is in contact with the bottom surface and side surface of the wordline structure 300.

[0196] Referring to Figures 12a and 16a, if open trenches OT are formed in the areas where the bit line pad region 430 is formed and the storage node pad region 530 is formed, the width of the formable trench becomes narrower, and considering the minimum machinable pitch, it may be necessary to perform the etching process several times, which can lead to increased costs and process steps. However, as shown in Figure 12a, if the pad trench (OT) is formed over a portion of each of two adjacent active regions 100 to simultaneously form the pad layer PAD, there is no risk of hitting the limits of the process technology, and the etching process can be performed only once, thus reducing manufacturing costs. Furthermore, even if the pad layer PAD is formed to extend along the second direction Y, the bit line pad region 430 between adjacent active regions 100 is electrically and physically isolated from each other while forming the word line structure 300, and the storage node pad region 530 between adjacent active regions 100 is also electrically and physically isolated from each other, simplifying the manufacturing process.

[0197] Below, we will explain Figures 17a to 17f, focusing on the differences between them and Figures 16a to 16f.

[0198] Figure 17a is a plan view illustrating the results of performing step S80 in Figure 9.

[0199] Referring to Figures 2, 3, 9, and 17a to 17f, the manufacturing method may include the step (S80) of forming a plurality of bit line electrode layers 410, a plurality of bit line spacers 420, a plurality of bit line contact regions 440, and a plurality of bit line capping layers 430.

[0200] Figure 17b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 17a.

[0201] Referring to Figures 9, 10a, 17a, and 17b, a bit line contact region 440 can be formed in contact with the upper surface of the bit line pad region 430. Next, a bit line electrode layer 410 can be formed on the bit line contact region 440. The bit line electrode layer 410 can be formed to extend in the second direction Y. Next, a bit line capping layer 450 can be formed on the bit line electrode layer 410. Bit line spacers 420 can be formed in contact with both sides of the bit line electrode layer 410, the bit line contact region 440, and the bit line contact capping layer 450, respectively.

[0202] Figure 17c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 17a.

[0203] Referring to Figures 9, 10a, 17a, and 17c, multiple bit line contact regions 440 can be formed spaced apart from each other in the first direction X. Multiple bit line electrode layers 410 can be formed spaced apart from each other in the first direction X. Multiple bit line capping layers 450 can be formed spaced apart from each other in the first direction X. Multiple bit line spacers 420 can be adjacent to the bit line electrode layers 410 on each side in the first direction X and the opposite side in the first direction X.

[0204] Figure 17d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 17a.

[0205] Referring to Figures 9, 10a, 17a, and 17d, a portion of the bit line spacer 420 can be placed on the first pad isolation area 710. Another portion of the bit line spacer 420 can be placed on the second pad isolation area 720.

[0206] Figure 17e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 17a.

[0207] Referring to Figures 9, 10a, 17a, and 17e, the bit line contact region 440, the bit line electrode layer 410, the bit line capping layer 450, and the bit line spacer 420 can each be formed to extend along the second direction Y.

[0208] Figure 17f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 17a.

[0209] Figure 17f may be substantially identical to Figure 16f.

[0210] Below, we will explain Figures 18a to 18f, focusing on the differences between them and Figures 17a to 17f.

[0211] Figure 18a is a plan view illustrating the results of performing step S90 in Figure 9.

[0212] Referring to Figures 2, 3, 9, and 18a-18f, this manufacturing method may include the step (S90) of forming a plurality of storage node contact areas 540.

[0213] Figure 18b is an illustrative cross-sectional view showing a plane cut along the line A-A' in Figure 18a.

[0214] Referring to Figures 9, 10a, 18a, and 18b, each of the multiple storage node contact areas 540 can be formed so as to overlap a portion of the active area 100. One end of the active area 100 can be formed so as to overlap the bit line pad area 430. The other end of the active area 100 can be formed so as to overlap the storage node contact area 540. The storage node contact 540 can be in contact with the upper surface of the storage node pad area 530. The storage node contact 540 can be in contact with the upper surface of the second pad isolation area 720.

[0215] Figure 18c is an illustrative cross-sectional view showing a plane cut along the line B-B' in Figure 18a.

[0216] Referring to Figure 18c, multiple contact isolation regions 600 can be positioned between bit line spacers 420. For example, a contact isolation region 600 can be in contact with a bit line spacer 420 in a first direction X. A contact isolation region 600 can be in contact with a bit line spacer 420 in the opposite direction to the first direction X.

[0217] Figure 18d is an illustrative cross-sectional view showing a plane cut along the line C-C' in Figure 18a.

[0218] Referring to Figure 18d, multiple storage node contact areas 540 can be positioned between bit line spacers 420. For example, a storage node contact area 540 can be in contact with a bit line spacer 420 in a first direction X. A storage node contact area 540 can be in contact with a bit line spacer 420 in the opposite direction to the first direction X.

[0219] Referring to Figures 10d, 15b, and 18d, the deeper the depth to which the cell isolation region 200 is formed, the more difficult the process of forming the cell isolation region 200 may be. By forming the first pad insulation region 710 and the second pad insulation region 720 to a position higher than the surface of the semiconductor layer SL, a first height H1 can be separated between the upper surfaces of the first pad insulation region 710 and the second pad insulation region 720 and the surface of the semiconductor layer SL.

[0220] Embodiments of the present invention that include a first pad insulation region 710 and a second pad insulation region 720 can achieve the effect of forming the cell isolation region 200 at the same depth, even if the cell isolation region 200 is formed to be shallower than the first height H1, compared to embodiments that do not include the first pad insulation region 710 and the second pad insulation region 720. As a result, embodiments of the present invention can provide a semiconductor device 1 with reduced manufacturing burden because the cell isolation region 200 does not need to be formed relatively shallowly.

[0221] Figure 18e is an illustrative cross-sectional view showing a plane cut along the line D-D' in Figure 18a.

[0222] Figure 18e may be substantially identical to Figure 17e.

[0223] Figure 18f is an illustrative cross-sectional view showing a plane cut along the line E-E' in Figure 18a.

[0224] Referring to Figure 18f, multiple storage node contact areas 540 and multiple contact insulation layers 600 can be formed alternately and repeatedly along the second direction Y. Both sides of each of the multiple storage node contact areas 540 can be in contact with the contact insulation layer 600. Both sides of each of the multiple contact insulation layers 600 can be in contact with the storage node contact area 540. As an example, a storage node contact area 540 can be in contact with the contact insulation layer 600 in the second direction Y. A storage node contact area 540 can be in contact with the contact insulation layer 600 in the opposite direction of the second direction Y. Also, a contact insulation layer 600 can be in contact with a storage node contact area 540 in the second direction Y. A contact insulation layer 600 can be in contact with a storage node contact area 540 in the opposite direction of the second direction Y.

[0225] Figure 19 is a plan view illustrating a portion of a semiconductor device when the word line structure 300 or bit line structure 400 in Figure 3 is misaligned.

[0226] In embodiments where the first pad insulation region 710 and the second pad insulation region 720 are absent, the lower surfaces of the bit line contact region 440 and the storage node contact region 540 and the upper surface of the semiconductor layer SL can be located on the same plane. In this case, if the word line structure 300 or the bit line structure 400 is formed with misalignment, a bridging phenomenon may occur between the storage node contact 540 corresponding to the active region 100-2 and the portion of the active region 100-1 where the bit line contact 430 of the active region 100-1 is formed. This can cause electrical interactions between different unit cells UC, potentially reducing the area in the active region 100 where the bit line contact 440 or storage node contact 540 can be formed, and potentially degrading the reliability of the semiconductor device 1.

[0227] The active regions 100-1 and 100-2 shown in Figure 19 may represent adjacent active regions 100 in Figures 2 and 3. For example, active region 100-2 may represent any active region 100 among multiple active regions 100. Active region 100-1 may represent an active region 100 adjacent to active region 100-2. Active region 100-1 may also be an active region 100 separated from active region 100-2 in the second direction Y.

[0228] However, in the embodiment of the present invention, the upper surface of the semiconductor layer SL is located in a plane separated by a first height H1, which is the height of the first pad insulating region 710, from the lower surface of the bit line contact region 440 and the storage node contact 540. This prevents the bridging phenomenon, in which electrical interaction occurs between adjacent unit cells UC, even if the word line structure 300 or the bit line structure 400 is formed with misalignment.

[0229] Referring to Figures 18a to 18f and Figure 19, the dotted lines in Figure 19 may represent the positions of the precisely aligned word line structures 300 and bit line electrode layers 410. The first miss bit line electrode layer 410-L may represent a bit line electrode layer formed off-center to the left (opposite direction to the first direction X). The second miss bit line electrode layer 410-R may represent a bit line electrode layer formed off-center to the right (first direction X). The first miss word line structure 300-U may represent a word line structure formed off-center to the upper side (second direction Y) in the drawing. The second miss word line structure 300-D may represent a word line structure formed off-center to the lower side (opposite direction to the second direction Y) in the drawing.

[0230] When the word line structure 300 is biased in the second direction Y, if the region located at one end of the first misword line structure 300-U and overlapping with the bit line pad region 430 is defined as the first region 100a, then the distance W1 from the third direction Z to the storage node contact region 540a of the adjacent active region 100 in the opposite direction of the second direction Y becomes close. However, the first pad isolation region 710 not only separates the bit line pad region 430 and the storage node contact region 540a horizontally, but also vertically (see Figure 18d), thereby preventing electrical interaction between the storage node contact region 540a and the first region 100a.

[0231] If the word line structure 300 is biased in the opposite direction to the second direction Y, and the region located at one end of the second misword line structure 300-D and overlapping with the storage node pad region 530 is defined as the second region 100B, then the distance W2 of the second region 100B becomes close to that of the bit line pad region 430B of the active region 100 adjacent to the second direction Y when viewed from the third direction Z. However, the first pad isolation region 710 allows the bit line pad region 430B and the storage node contact region 540 to be separated not only horizontally but also vertically (see Figure 18d), thereby preventing electrical interaction between the second region 101B and the bit line pad region 430B.

[0232] If the bit line electrode layer 410 is biased in the first direction X, and the region located at one end of the first mis-bit line electrode layer 410-L and overlapping with the storage node pad region 530 is defined as the third region 100C, then the distance W3 of the third region 100C becomes close to that of the bit line pad region 430C of the active region 100 adjacent to the second direction Y when viewed from the third direction Z. However, the first pad insulating region 710 allows the bit line pad region 430C and the storage node contact region 540 to be separated not only horizontally but also vertically (see Figure 18d), thereby preventing electrical interaction between the third region 100C and the bit line pad region 430C.

[0233] If the bit line electrode layer 410 is biased in the opposite direction to the first direction X, and the region located at one end of the second mis-bit line electrode layer 410-R and overlapping with the bit line pad region 430 is defined as the fourth region 100D, then the distance W4 of the fourth region 100D becomes close to the storage node contact region 540D of the active region 100, which is adjacent in the opposite direction to the second direction Y, when viewed from the third direction Z. However, the first pad insulating region 710 allows the bit line pad region 430 and the storage node contact region 540D to be separated not only horizontally but also vertically (see Figure 18d), thereby preventing electrical interaction between the fourth region 100D and the storage node contact region 540D.

[0234] Furthermore, according to embodiments of the present invention, even if the open trench OT is formed with some bias in the first direction X or the opposite direction of the first direction X in step S30 of Figure 9, the first pad insulating region 710 prevents electrical interaction between the adjacent bit line pad regions 430 and the storage node contact region 540, thereby providing a semiconductor device 1 with improved reliability.

[0235] The above description is merely illustrative of the technical idea of ​​the present invention, and various modifications and variations are possible for those with ordinary skill in the art to which the present invention pertains, without departing from the essential characteristics of the present invention. The embodiments disclosed herein are for illustrative purposes only, not to limit the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by the embodiments. The scope of protection of the present invention should be interpreted as defined by the claimed claims, and all technical ideas within an equivalent scope should be interpreted as being included within the scope of the rights of the present invention. [Explanation of symbols]

[0236] 100 active area 200-cell isolation area 300 Wordline Structures 310 First Word Line Electrode Layer 320 Second Wordline Electrode Layer 330 Wordline Capping Layer 340 Wordline Insulation Layer 400-bit line structure 410 bit line electrode layer 420 bit line spacer 430-bit line pad area 440-bit line contact area 450-bit line capping layer 530 Storage Node Pad Area 540 Storage Node Contact Area 600 Contact Insulation Area 710 First pad insulation area 720 Second pad insulation area HM Mask Layer OT Open Trench PAD pad layer, SL semiconductor layer WL Wardline BL Bitline TX transistor CAP Capacitor UC unit cell X 1st direction Y Second direction Z 3rd direction DG diagonal direction

Claims

1. Each of these consists of multiple wordline structures that extend along a first direction and separate from each other along a second direction, Each of these comprises multiple active regions that extend in an oblique direction forming an acute angle with the first direction, overlap with the wordline structure, and are separated from each other along the first direction, Each of these overlaps with one end of the active region and is in contact with one side of the word line structure, Each of these overlaps with the other end of the active region and is in contact with the other side of the wordline structure, and Each of these contacts the bit line pad area and one side of the word line structure, and comprises a plurality of first pad insulating areas having a first height, A semiconductor device comprising a plurality of second pad insulating regions, each of which is in contact with the storage node pad region and in contact with the other side of the word line structure and has a second height greater than the first height.

2. Each of the plurality of bit line pad regions has a third height from the upper surface of the active region, Each of the plurality of storage node pad regions has a fourth height from the upper surface of the active region, The semiconductor device according to claim 1, wherein the third height and the fourth height are each the same as the second height.

3. The semiconductor device according to claim 2, wherein the lower surface of the bit line pad area and the lower surface of the storage node pad area are lower than the lower surface of the first pad insulation area.

4. The semiconductor device according to claim 2, wherein the lower surface of the bit line pad region and the lower surface of the storage node pad region are located on the same plane as the lower surface of the second pad insulating region.

5. Each of these comprises a plurality of bit line contact areas that are in contact with the upper surface of the bit line pad area, The semiconductor device according to claim 1, further comprising a plurality of storage node contact areas, each in contact with the upper surface of the storage node pad area.

6. Each of the bit line electrode layers is positioned on the bit line contact region, overlaps with the bit line pad region, and extends in the second direction, The semiconductor device according to claim 5, further comprising a plurality of bit line spacers, each in contact with both sides of the bit line electrode layer and extending in the second direction.

7. The semiconductor device according to claim 1, wherein the second direction is perpendicular to the first direction, and the second direction forms an acute angle with the diagonal direction.

8. The semiconductor device according to claim 1, wherein the angle between the first direction and the diagonal direction is between 30 degrees and 60 degrees.

9. The semiconductor device according to claim 1, wherein the plurality of active regions are further arranged spaced apart from each other along the second direction, and the plurality of active regions are further arranged spaced apart from each other along the diagonal direction.

10. Each of the plurality of bit line pad regions is arranged to be spaced apart from each other along the second direction, The semiconductor device according to claim 9, wherein each of the plurality of storage node pad areas is arranged to be spaced apart from one another along the second direction.

11. Each of the plurality of first pad isolation regions is in contact with the side surface of the bit line pad region facing the first direction, and each of the plurality of first pad isolation regions is in contact with the side surface of the storage node pad region facing the opposite direction to the first direction. The semiconductor device according to claim 10, wherein each of the plurality of second pad insulating regions is in contact with the side surface of the bit line pad region facing the opposite direction to the first direction, and each of the plurality of second pad insulating regions is in contact with the side surface of the storage node pad region facing the first direction.

12. The semiconductor device according to claim 11, wherein the plurality of first pad insulating regions are spaced apart along the second direction, and the plurality of second pad insulating regions are spaced apart along the second direction.

13. It further includes a cell isolation region surrounding the plurality of active regions, The semiconductor device according to claim 1, wherein each of the plurality of first pad insulating regions is in contact with the upper surface of the cell isolation region.

14. The semiconductor device according to claim 1, wherein each of the plurality of bit line pad regions and the plurality of storage node pad regions includes polysilicon.

15. The steps include: each being arranged repeatedly at a distance from each other along a first direction and a second direction, extending diagonally with respect to the first direction, and forming a plurality of active regions surrounded by cell separation regions; The steps include forming a first insulating layer on the plurality of active regions and the cell isolation regions, The steps include forming a plurality of open trenches, each etching a portion of two adjacent active regions and a portion of the first insulating layer, The steps include forming a pad layer that covers a plurality of first pad insulating regions remaining after etching the first insulating layer and the plurality of open trenches, The step of removing the portion of the pad layer that is formed in the center of the open trench, A method for manufacturing a semiconductor device, comprising the step of forming a second pad insulating region in the central part of the open trench.

16. The method for manufacturing a semiconductor device according to claim 15, further comprising the step of forming a plurality of word line structures that overlap with the plurality of active regions, extend in the first direction, and are repeatedly spaced apart along the second direction.

17. The step of forming the plurality of wordline structures includes the operation of forming a wordline trench, The method for manufacturing a semiconductor device according to claim 16, wherein each word line trench cuts through a plurality of pad layers extending in the second direction and spaced apart from each other along the first direction to form a plurality of bit line pad regions and a plurality of storage node pad regions, and each cuts through a plurality of first pad insulating regions and a plurality of second pad insulating regions extending in the second direction and recesses into the interior of a plurality of active regions.

18. The plurality of bit line pad regions overlap one end of each of the plurality of active regions, The method for manufacturing a semiconductor device according to claim 17, wherein the plurality of storage node pad regions overlap the other end of each of the plurality of active regions.

19. The step of forming the plurality of word line structures is: The operation of forming a word line electrode layer to which the operation signal of the word line structure is applied, The operation of forming a word line insulating layer along the inner wall of the word line trench and surrounding the lower surface and side surface of the word line electrode layer, The method for manufacturing a semiconductor device according to claim 17, further comprising the operation of forming a word line capping layer in contact with the upper surface of the word line electrode layer.

20. The steps include: each of these is positioned on the bit line pad area, extending along the second direction and separating from each other in the first direction to form a plurality of bit line contact areas; The steps include forming a plurality of bit line electrode layers, each positioned on the bit line contact region, extending along the second direction and spaced apart from each other in the first direction, The steps include forming a plurality of bit line spacers, each in contact with both sides of the bit line electrode layer and extending along the second direction, A method for manufacturing a semiconductor device according to claim 18, further comprising the step of forming a plurality of storage node contact areas, each of which is arranged on the storage node pad area.

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