PWM signal generator, power supply, and PWM signal generation method

Abstract

Precisely controls the output voltage of a switching power supply. [Solution] The precision control pulse width modulation signal generator includes a basic pulse width modulation signal generator 512 configured to generate a basic pulse width modulation signal from the clock signal of FPGA 510, a slew rate controller 520 configured to correct the edges of the basic pulse width modulation signal, and a comparator 530 having a first input terminal that receives the output of the slew rate controller 520 and a second input terminal that receives a comparison threshold, and configured to output a precision control pulse width modulation signal based on a comparison of the first input signal and the second input signal. The precision control pulse width modulation signal may be used by a switching power supply to precisely control its output voltage.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a signal generation system, and more particularly to a system for generating a pulse width modulated signal having characteristics specified by a user.

BACKGROUND ART

[0002] Modern power supply modules allow users to control the voltage level of the output signal. For direct current (DC) power supplies, the final output signal is typically a signal having a constant DC output voltage. It is important that the output voltage is stable, that is, the output voltage remains relatively constant over time and is maintained within a small tolerance range. It is also important that users can accurately control the output voltage level of the power supply to meet desired applications.

[0003] Power supplies use various types of circuits depending on their design to generate output voltage signals. Discrete linear regulated power supplies can be used to generate signals that meet both the above output tolerance and fine control requirements. However, especially when used in large-scale power supplies, discrete linear regulated power supplies may be too large to physically fit within design constraints. When a small physical size is important, switching power supplies are often used. In general, in a switching power supply such as a buck converter, a Pulse-Width-Modulated (PWM) signal is used to control a semiconductor switch such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) switch. MOSFET switches are very small. When the duty cycle of the PWM signal that controls the MOSFET is low, the MOSFET switch is off for a longer time than it is on, and as a result, the output voltage of the voltage generation circuit is relatively low. Conversely, when the duty cycle of the PWM signal is high, the output of the voltage generation circuit is correspondingly high.

[0004] When using FPGAs (Field-Programmable Gate Arrays) in circuit design, the operational constraints of the FPGA fabric can limit the choice of circuit design. For example, a phase-locked loop (PLL) that generates a clock signal higher than the FPGA's native frequency can be implemented on the FPGA. However, due to the limitations of the FPGA fabric, a PWM signal generator may not be able to use these PLLs to control the PWM signal generator with high precision at these high frequencies.

[0005] Using a standard PWM signal generator with an FPGA presents challenges in precisely controlling the PWM duty cycle. As mentioned above, one of the key elements in power supply design is the ability for the user to finely control the final output voltage of the power supply by adjusting the duty cycle of the PWM signal. As described above, changing the duty cycle of the PWM signal causes the switching power supply to increase or decrease the final output voltage of the power supply. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2025-110505 [Patent Document 2] Japanese Patent Publication No. 2009-225574 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] As mentioned above, FPGA fabrics typically have a maximum clock rate at which they can operate without errors. For example, the maximum main or master clock frequency of an FPGA that does not experience propagation delay issues may be around 100 MHz, which corresponds to a clock cycle of 10 nanoseconds (ns). If the desired frequency of the PWM signal generated by the FPGA is around 1 MHz, this corresponds to a clock cycle of 1000 nanoseconds. Again, note that, as mentioned above, precise control of the desired output voltage is important. Using the above clock cycle as an example, if the FPGA fabric limits the minimum change in the PWM to 10 nanoseconds, then generating a PWM by modulating a 1000 nanosecond clock cycle allows for a minimum variation of 1% in the PWM, which is a relatively large value. The limitation of clock signal resolution due to the FPGA's maximum clock speed directly limits the user's ability to precisely control the duty cycle of the PWM implemented using the FPGA. Furthermore, the inability to finely control the PWM duty cycle limits the user's precise control when specifying the final output voltage from the power supply. [Means for solving the problem]

[0008] Embodiments of the disclosed technology include integrating the control of a field-programmable gate array (FPGA) with a digital-to-analog converter (DAC) to generate a pulse-width modulation (PWM) signal with a resolution of less than 1 nanosecond at a frequency of 1 MHz. Other examples include a precisely tunable PWM signal generator based on a clock generator that allows for precision control of less than 1%.

[0009] This disclosure includes generating a precisely tunable PWM control signal. The PWM signal may be used to control a MOSFET in a synchronous switching power supply (e.g., a buck converter). In embodiments, the duty cycle of the PWM signal is directly correlated with the output of the buck converter. Therefore, if the PWM control signal has high resolution, the output of the buck converter can be controlled more precisely.

[0010] In some embodiments, the FPGA generates a master clock at 100 MHz or 125 MHz. Faster clock signals may face propagation delay issues due to the FPGA fabric. For example, even if the FPGA generates a 100 MHz clock, if the clock signal fluctuation is limited to a minimum of 10 nanoseconds, the overall resolution of the clock signal generated by the FPGA is limited to a clock fluctuation of 1% of the clock signal.

[0011] To obtain higher resolution, this disclosure includes modifying the PWM signal that can be generated by the FPGA and using additional circuitry to generate a finely controllable PWM signal. The FPGA generates the PWM signal from a master clock, as detailed below. [Brief explanation of the drawing]

[0012] [Figure 1] Figure 1 is a functional block diagram of a precisely controllable pulse-width modulation (PWM) signal generator according to an embodiment of the present disclosure. [Figure 2] Figure 2 is a graph showing the output voltages of each part of the PWM signal generator in Figure 1, based on an embodiment of the present disclosure. [Figure 3A] Figure 3A shows an example of the components of the down-through rate controller for the PWM signal generator of Figure 1, based on an embodiment of the present disclosure. [Figure 3B] Figure 3B is another example of the components of the down-through rate controller for the PWM signal generator of Figure 1, based on an embodiment of the present disclosure. [Figure 3C] Figure 3C is yet another example of the components of the down-through rate controller for the PWM signal generator of Figure 1, based on an embodiment of the present disclosure. [Figure 4] Figure 4 is a block diagram of an example embodiment of a comparator used as a component of the duty cycle controller of the PWM signal generator in Figure 1. [Figure 5]Figure 5 is a block diagram of an example voltage generator that includes some or all of the components of the PWM signal generator of Figure 1 according to an embodiment of the present disclosure. [Figure 6] Figure 6 is a flowchart illustrating an example of a process used to generate a precisely controllable PWM signal according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0013] Referring to Figure 1, a precisely controllable PWM generator 100 is illustrated, which includes a preliminary PWM signal generator 10, a slew rate controller 20, and a duty cycle controller 30. As will be explained in more detail below, the preliminary PWM signal generator 10 receives a master clock signal, such as a 100 MHz clock signal generated by the FPGA, and outputs a PWM signal with a predetermined duty cycle that is adjustable to 1% accuracy. Other inputs to the PWM signal generator 10 include the desired PWM frequency and the preliminary (or gross) duty cycle. The PWM signal output from the PWM signal generator 10 may be generated from a master clock signal, such as the FPGA master clock, based on the overall structure. In one embodiment, the PWM signal generator 10 generates a 25 MHz PWM signal from a 100 MHz master clock signal. The output of the PWM signal generator 10 is called a PWM signal with a selectable preliminary duty cycle, but the preliminary duty cycle is limited by the master clock signal.

[0014] The slew-rate controller 20 includes a circuit or circuit function that controls one of the edges of the PWM signal output from the PWM signal generator 10. This function of the slew-rate controller 20 can be controlled through the control lines shown in Figure 1. Referring to Figure 2, the original master clock signal is shown as 210. In this embodiment, the frequency of the master clock signal 210 is 100 MHz and may be generated by the FPGA. In another embodiment, the master clock signal may be generated by another clock signal source. Whatever it may be generated, the master clock signal 210 may be an example of a clock signal provided to the PWM signal generator 10 in Figure 1.

[0015] The PWM signal generator 10 uses the master clock signal 210 to generate a PWM signal 220 with a desired frequency. In the illustrated embodiment, the frequency of the PWM signal 220 is 25 MHz and the duty cycle is 50%. Compared to the master clock signal 210, the PWM signal 220 remains high for two cycles of the master clock signal 210, and then transitions to low for two more cycles of the master clock signal.

[0016] Referring to Figure 1, the slew-rate controller 20 uses various circuits to modify the PWM signal 220. As will be described below, ultimately, by modifying the PWM signal 220, the ability to adjust the desired PWM duty cycle more precisely than can be achieved by the PWM signal generator 10 is obtained. This is because the PWM signal generator 10 is limited to an accuracy of 1%. Returning to Figure 2, an example output of the slew-rate controller 20 (Figure 1) is shown as the slew-down PWM signal 230. Comparing the slew-down PWM signal 230 to the PWM signal 220 in Figure 2, the difference between these signals is based on the difference in the falling edges of the two PWM signals. The original PWM signal 220 has a falling edge 222 that falls instantly or very quickly between the high and low values ​​of the PWM signal 220. Referring to the thru-down PWM signal 230, the falling edge 232 takes much longer to transition from the high value to the low value of the thru-down PWM signal 230. This falling rate of the PWM signal 230 is called the thru-rate, which is the rate of change in the output value of a signal like the thru-down PWM signal 230 relative to the time it takes for the value to completely change from high to low. The portion 222 of the falling edge of the PWM signal 220 has a very fast, i.e., instantaneous thru-rate, while the portion 232 of the falling edge of the thru-down PWM signal 230 has a much lower thru-rate. Generally, although not mandatory, the thru-rate of the falling edge 232 is controlled by the thru-rate controller 20 (Figure 1) so that the high-to-low transition is completed before the next rising edge of the PWM signal 220.

[0017] In some embodiments, different circuits may be used within the slew rate controller 20 (Figure 1) to control the slew rate of the falling edge 232 of the through-down PWM signal 230. Referring to Figure 3A, the slew rate controller 50 may be an example of the slew rate controller 20 in Figure 1. The slew rate controller 50 includes a diode 52, which may be a Schottky diode, and is coupled to a capacitor 54 and a current sink or current generator 56. When turned on, the current generator 56 provides a path between the capacitor 54 coupled to the output of the slew rate controller 50 and the ground reference point.

[0018] The input to the slew-rate controller 50 is the output of the PWM signal generator 10 (Figure 1), an example of which is shown as the PWM signal 220 in Figure 2. The slew-rate controller 50 makes the falling edge 232 of the PWM signal 230 have a slower or lower slew rate than the falling edge 222 of the PWM signal 220. More specifically, when the PWM signal 220 is in the HIGH state, the capacitor 54 is charged with the energy supplied by the high-state signal. The PWM signal 220 would then, in some cases, fall to the LOW state immediately, as shown in Figure 2, but the slew-rate controller 50 delays or slows down the transition time between the high and low states, thereby increasing the slew time and decreasing the slew rate of the falling edge 232. In practice, when the input of the PWM signal 220 to the slew-rate controller 50 transitions from high to low, the current generator 56 provides a path to ground reference. The operation of the current generator 56 controls how quickly the energy stored in the capacitor 54 is discharged relative to ground. The diode 52 is a unidirectional element that prevents the energy stored in the capacitor 54 from being discharged in the reverse direction through the diode. Instead, the capacitor 54 is discharged at a controllable rate via the current generator 56, and when fully discharged, the falling edge 232 of the slew-down PWM signal 230 reaches a low state. This controlled discharge of the capacitor 54 is shown in Figure 2 by the decrease in the slew rate (falling edge) 232 of the slew-down PWM signal 230.

[0019] Referring again to FIG. 3A, the size of the capacitor 54, the level to which the capacitor 54 is charged, and the discharge rate of the current generator 56 control the slew rate of the falling edge 232 of the slew-down PWM signal 230. For example, when the speed at which the current generator 56 sinks current from the capacitor 54 to the ground reference is increased, the speed at which the falling edge 232 drops from the high state to the low state increases, while when the speed at which the current generator 56 sinks current to the ground reference is decreased, the falling edge 232 drops more slowly. As such, the embodiments of the present disclosure can control the slew rate of the PWM signal in real time by controlling the operation of the current generator 56.

[0020] In addition to controlling the slew rate using a current generator 56 as seen in the slew rate controller 50 in Figure 3A, other slew rate control methods may be used. For example, Figure 3B shows a slew rate controller 60, in which case the current generator 56 in Figure 3A is replaced with a single resistor 66. The other circuit components of the slew rate controller 60 are unchanged from those of the slew rate controller 50, and for the sake of brevity, these functions will not be described again. In the slew rate controller 60 of Figure 3B, when the PWM signal 220 drops from a high state to a low state, energy is discharged from the capacitor 54 through the resistor 66 to ground reference. One difference between the slew rate controller 60 of Figure 3B and the slew rate controller 50 of Figure 3A is that the resistor 66 is static, and the rate at which the capacitor 54 discharges to ground reference depends on the resistive-capacitive network (RC circuit) of the resistor 66 and the capacitor 54. Although not shown in the diagram, when a capacitor like capacitor 54 is discharged through a fixed RC circuit, it follows a nonlinear path. In this case, immediately after the PWM signal 220 transitions from high to low, its energy is discharged more quickly, and capacitor 54 discharges more rapidly compared to after it has been further discharged. Therefore, compared to the slew-down PWM signal 230 in Figure 3A, when using a slew-rate controller 60 with a fixed RC circuit, the falling edge 232 of the slew-down PWM signal 230 becomes curved or inverted J-shaped, compared to the relatively linear shape of the falling edge 232 when using the slew-rate controller 50 (Figure 3A).

[0021] Figure 3C illustrates yet another slew-rate controller 70, which is similar to the slew-rate controller 60 in Figure 3B, but differs in that the slew-rate controller 70 has a controllable resistor 76. In this embodiment, the resistance value of the controllable resistor 76 may be changed or altered during the down-slew interval in which the PWM signal 220 transitions from high to low. This controllable resistor allows the system to change the parameters of the RC circuit formed by the resistor 76 and the capacitor 54, thereby controlling the speed of the falling edge portion 232 of the slew-down PWM signal 230, and thereby modifying the shape of the discharge curve compared to the output of the slew-rate controller 60. Similar to controlling the current generator 56 in the slew-rate controller 50 in Figure 3A, the resistor 76 in the slew-rate controller 70 in Figure 3C is controllable in real time.

[0022] In the illustrated embodiments of this disclosure, the modification of the falling edge of the PWM signal 220 is described, but it is also possible to modify the rising edge of the PWM signal 220 to control the entire output of the new, precisely controlled PWM signal. In another embodiment, it is also possible to modify both the rising and falling edges of the PWM signal 220.

[0023] Referring again to Figure 1, the output of the down-through rate controller 20 is passed to the duty cycle controller 30 to generate a final PWM signal with controllable duty cycles. In some embodiments, the duty cycle controller 30 includes a comparator, such as the comparator 90 shown in Figure 4. The comparator 90 has a non-inverting input terminal 92 and an inverting input terminal 94. In the illustrated embodiment, the non-inverting input terminal 92 is coupled to the output of the through rate controller 20 (Figure 1), while the inverting input terminal 94 receives a threshold used by the comparator 90. By changing the threshold of the comparator 90, the output of the comparator controls the duty cycle of the new PWM signal. This will be explained with reference to Figure 2. This threshold may be an example of a duty cycle control signal supplied to the duty cycle controller 30, as shown in Figure 1.

[0024] Figure 2 shows the new PWM signal 240, which in some embodiments represents the output of the comparator 90 in Figure 4.

[0025] Referring to Figure 4, by comparing the new PWM signal 240 with the PWM signal 220, we can see that the new PWM signal 240 has a larger duty cycle than the original PWM signal 220. Furthermore, the falling edge 242 of the new PWM signal 240 coincides with the crossover point 236 of the through-down PWM signal 230, indicating where the portion of the falling edge 232 of the through-down PWM signal 230 passes the variable comparator threshold 234. Thus, by adjusting the level of the variable comparator threshold 234, we control where the falling edge of the new PWM signal 240 is positioned in time. This means that the edge position of the new PWM signal 240 can be controlled in steps smaller than the minimum period of the master clock signal 210. By controlling the time at which the falling edge of the new PWM signal 240 occurs, we adjust the duty cycle of the new PWM signal 240. In other words, the duty cycle of the new PWM signal 240 is adjusted by controlling the threshold of comparator 90 in Figure 4. More specifically, in the illustrated embodiment, increasing the threshold of the comparator 90 decreases the duty cycle of the new PWM signal 240, while decreasing the threshold of the comparator 90 increases the duty cycle. It should also be noted that in this embodiment, the rising edge of the new PWM signal 240 always coincides with the rising edge of the original PWM signal 220. The threshold supplied to the inverting input terminal 94 of the comparator 90 may be an example of a duty cycle control signal supplied to the duty cycle controller 30, as shown in Figure 1.

[0026] Thus, the duty cycle of the new PWM signal 240 can be specified by controlling the slew rate of the falling edge portion 232 of the slew-down PWM signal 230. The duty cycle of the new PWM signal 240 can also be specified by controlling the threshold value (Figure 4) of the comparator 90 in the duty cycle controller 30 (Figure 1). As will be described below, in some embodiments, the duty cycle of the new PWM 240 can be changed by controlling only one of these values, while in other embodiments, these control elements or both may be used. Often, changing the slew rate of the slew-down PWM signal 230 will change the duty cycle of the new PWM signal 240 more relatively than changing the threshold value of the comparator 90. However, as described above, one or both of these control mechanisms may be used to generate a new PWM signal 240 with a desired final duty cycle.

[0027] Figure 5 is a block diagram of a voltage generator 500 that includes some or all of the PWM signal generator of Figure 1 according to an embodiment of the present disclosure. In the illustrated embodiment, FPGA 510 generates a master clock signal, which PWM signal generator 512 uses to generate a base PWM signal. In the illustrated embodiment, PWM signal generator 512 is shown to be integrated into FPGA 510 itself, but in other embodiments, PWM signal generator 512 may be external to FPGA. PWM signal generator 512 may also be an embodiment of PWM signal generator 10 in Figure 1. As described above, PWM signal generator 512 generates a PWM signal based on a master clock signal, such as the master clock signal of FPGA 510. However, as described above, note again that PWM signal generator 512 can only control the duty cycle of the PWM signal in relatively large steps based on the master clock frequency. In the above example, PWM signal generator 512 can only control the output PWM signal with a resolution of 1%. By using the additional components described herein, embodiments of the disclosure can achieve a much higher precision in the final PWM signal than simply manipulating the master clock signal.

[0028] The PWM signal from the PWM signal generator 512 is then sent to the slew rate controller 520. This may be an embodiment of the slew rate controller 20 in Figure 1. As described above, the slew rate controller 20 may control one or both of the rising and falling edges of the PWM signal, but in the illustrated embodiment, the slew rate controller 520 controls the falling edge of the PWM signal and is therefore called a down slew rate controller. The PWM signal with a slewed falling edge output by the slew rate controller 520 is then fed to the duty cycle controller 530. This may be an embodiment of the duty cycle controller 30 in Figure 1. In some embodiments, the duty cycle controller 530 may include a comparator such as the comparator 90 in Figure 4, or other circuits may provide the duty cycle control function instead. As will be explained in detail below, the outputs from the digital-to-analog converters (DACs) 505 and DAC 507 may provide feedback control to the down-through rate controller 520 and the duty cycle controller 530 during operation.

[0029] The output of the duty cycle controller 530 is a precisely controllable final PWM signal having a specified duty cycle, according to embodiments of the present disclosure. This new final PWM signal, such as the new PWM signal 240 in Figure 2, is supplied to the switching power supply 550. This may also be a buck converter that generates the final output voltage. As described above, the switching power supply generates a controllable final output voltage, which is determined by the duty cycle of the PWM signal driving the MOSFETs in the switching power supply 550. Thus, by adjusting the duty cycle of the PWM signal driving the switching power supply 550, the final output voltage of the switching power supply 550, i.e., the final output voltage of the voltage generator 500, can be controlled with great precision.

[0030] In some embodiments, the final output voltage from the switching power supply 550 is coupled to the output voltage monitor 560, which generates a signal based on the difference between the desired output voltage from the voltage generator 500 and the actual output voltage. In some embodiments, this is called an error signal and may be fed back to an error controller 516 in the FPGA 510. In some embodiments, the analog error signal is converted to a digital signal by an analog-to-digital converter (ADC) 565 and returned to the error controller 516 in the FPGA 510. In the illustrated embodiments, the function of the error controller 516 is illustrated as being implemented by the FPGA 510, but in other embodiments, the error controller may exist separately from the FPGA. By providing feedback from the output voltage monitor 560, the digital error signal from the ADC 565 forms a measurement feedback circuit, which allows the error controller 516 to correct the operation of other components of the voltage generator 500 to produce a highly accurate final output voltage.

[0031] The error controller 516 generates a slew control signal that actively controls the slew rate controller 520, controlling the shape of the corrected PWM signal output from the slew rate controller. In the illustrated embodiment, the error controller 516 generates a digital slew rate control signal, which is converted to an analog slew rate control signal by the DAC 507. The analog slew rate control signal is then sent to the slew rate controller 520 to actively control the slew rate, as described with reference to Figures 3A and 3C. As described above, the slew rate control signal may also control the discharge rate of the current generator 56 (Figure 3A) or change the controllable resistor 76 (Figure 3B). In other examples of the slew rate controller 520, the slew rate control signal may control other characteristics of the slew rate controller 520.

[0032] Furthermore, the error controller 516 may use the error signal from the output voltage monitor 560 as a data signal source to control the DAC 505 to adjust the controllable threshold applied to the duty cycle controller 530, as described above. As described with reference to the DAC 507, the output from the error controller 516 may be a digital signal representing a threshold, which may then be converted to an analog threshold signal by the DAC 505 and applied to the duty cycle controller 530 (which in some embodiments is a comparator). In some embodiments, the reference voltage output of the DAC 505 increases or decreases the threshold voltage applied to the comparator in linear steps, while in other embodiments, the reference voltage output of the DAC 505 may utilize a logarithmic increase or decrease to control the threshold voltage. According to embodiments of this disclosure, this novel approach to controlling either or both the down-through rate controller 520 and the duty cycle controller 530 improves the accuracy of generating the PWM signal.

[0033] In some embodiments, more or fewer of the components independently illustrated in Figure 5 may be physically integrated into the FPGA 510 itself. For example, either or both of the down-through rate controller 520 and the duty cycle controller 530 may be integrated into the FPGA 510. In other embodiments, the DAC 505 and DAC 507 may also be part of the FPGA 510, depending on the implementation details. Similarly, although the PWM signal generator 512 is illustrated as being implemented within the FPGA 510, it may exist independently or separately from the FPGA 510.

[0034] Furthermore, in the illustrated implementation, the FPGA 510 may receive one or more user inputs 503, which may specify the desired output of the voltage generator 500. This user input may be controlled by a menu on the voltage generator 500 itself, or it may be specified in another way, such as by inputting it on a controlling computer.

[0035] Figure 6 is a flowchart illustrating an example of a process in flow 600 used to generate a controllable PWM signal according to an embodiment of the present disclosure. Flow 600 begins with receiving a clock signal in process 602. As described above, the clock signal may be a master clock generated by the FPGA or may be generated using other circuits.

[0036] In step 604, a base PWM signal is generated from the master clock signal. This function may be performed, for example, by the PWM signal generator 512 shown in Figure 5. Next, in step 606, the slew rate of the generated PWM signal is controlled. For example, either the falling edge or rising edge, or both, of the PWM signal are modified by the slew correction function described above. In the above description, the falling edge of the rescaled clock signal is controlled by the slew rate controller 20, which can take various forms as shown in Figures 3A, 3B, and 3C, but other embodiments are possible without departing from the spirit of the invention. Controlling the slew rate of the falling edge of the PWM signal increases the transition time between the high and low states of the PWM signal. The slew rate can be controlled in the various ways described above, which results in skies of various shapes and durations.

[0037] In step 608, a comparison threshold (setpoint) used in the following steps is generated. In some embodiments, this threshold may start from a set initial value, and its value may be changed during the operation of flow 600, as will be explained in detail below.

[0038] Next, in step 610, the duty cycle controller generates a new PWM signal from the slew-corrected PWM signal as described above. In one embodiment, as described above, a comparator compares the level of the instantaneous corrected PWM signal to a threshold set in step 608, and the output of the comparator becomes the new PWM signal with the duty cycle corrected.

[0039] Finally, in step 612, a new PWM signal from a duty cycle controller, such as the comparator 90 in Figure 4, is applied to a switching power supply, such as a buck converter. The output of the switching power supply becomes the output voltage desired and set by the user.

[0040] The feedback signal may be generated in step 614 based either on the new PWM signal output by the duty cycle controller in step 610, or on the final output voltage signal from the switching power supply in step 612. In either form, the feedback signal generated in step 614 is based on a comparison of the desired signal with the actual instantaneous signal. Flow 600 then uses this feedback signal to control the circuits and systems in the power supply circuit, as described above. This feedback signal may also be used to control the original PWM signal created in step 604. For example, in the embodiment described, the clock signal in step 602 is scaled down to a clock signal of 25% of the original clock rate. However, the feedback signal in step 614 can be used to scale the scaled clock rate to another value. Also, although the PWM signal 220 has a 50% duty cycle as described above and illustrated in Figure 2, a different basic duty cycle may be selected for the basic PWM signal.

[0041] Alternatively, or in addition to the above, the feedback signal from step 614 can be used to control the slew rate of a slew rate controller, such as the slew rate controller 20 in Figure 1, which controls the slew rate of the PWM signal in step 606. The slew rate can be changed in various ways, such as increasing or decreasing the linear slew rate change rate of the falling edge of the PWM signal, or increasing or decreasing the nonlinear slew rate. Various methods of changing the slew rate are explained with reference to Figures 3A, 3B, and 3C above.

[0042] Furthermore, in addition to, or instead of, both of the above uses of the feedback signal, the feedback signal of step 614 may also be used in step 610 to modify the threshold set in step 608, which is used by the duty cycle controller to create the final modified PWM signal. The feedback from step 614 to steps 604, 606, and 608 is shown by dashed lines, indicating that, as described above, any or all of these feedback mechanisms may be used in any combination to modify the final PWM signal, and furthermore, to modify the final output voltage signal to a user-specified final output voltage signal. Although not typical, it is possible that the original duty cycle of the final PWM signal precisely matches the desired duty cycle, and therefore no adjustment based on the feedback signal of step 614 is necessary.

[0043] Embodiments of the disclosed technology can operate on a specially programmed general-purpose computer, including specially created hardware, firmware, digital signal processors, or processors that operate according to programmed instructions. The terms “controller” or “processor” in this application mean microprocessors, microcomputers, ASICs, and dedicated hardware controllers, etc. Embodiments of the disclosed technology can be implemented by one or more computers (including monitoring modules) or other devices, using computer-readable data such as program modules and computer-executable instructions. Generally, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor in a computer or other device, perform specific tasks or implement specific abstract data type expressions. Computer-executable instructions may be stored on computer-readable storage media such as hard disks, optical disks, removable storage media, solid-state memory, and RAM. As will be understood by those skilled in the art, the functions of the program modules may be combined or distributed as needed in various embodiments. Furthermore, these functions can be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits or field-programmable gate arrays (FPGAs). One or more aspects of the disclosed technology can be more effectively implemented using specific data structures, such data structures are considered to be within the scope of computer-executable instructions and computer-usable data described herein.

[0044] The disclosed embodiments may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored in one or more computer-readable media that can be read and executed by one or more processors. Such instructions may be referred to as computer program products. The computer-readable media described herein means any medium accessible by a computing device. For example, but not limited to, computer-readable media may include computer storage media and communication media.

[0045] Computer storage media means any medium that can be used to store computer-readable information. Examples of computer storage media include, but are not limited to, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory and other memory technologies, compact disc read-only memory (CD-ROM), DVD (Digital Video Disc) and other optical disc storage devices, magnetic cassettes, magnetic tapes, magnetic disk storage devices and other magnetic storage devices, and any other volatile or non-volatile removable or non-removable media implemented by any technology. Computer storage media exclude signals themselves and temporary forms of signal transmission.

[0046] A communication medium means any medium that can be used to transmit computer-readable information. Examples of communication mediums, though not limited to them, include coaxial cables, fiber optic cables, air, or any other medium suitable for transmitting electrical, optical, radio frequency (RF), infrared, sound, or other types of signals.

[0047] In addition, the description of this application refers to certain features. It should be understood that the disclosures herein include all possible combinations of these particular features. Where a particular feature is disclosed in relation to a particular aspect or example, that feature may, to the extent possible, also be used in relation to other aspects and examples.

[0048] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, as long as the circumstances do not rule out such possibilities. Examples

[0049] The following examples are provided that are useful for understanding the technology disclosed herein. These embodiments may include one or more of the examples described below, or any combination thereof.

[0050] Embodiment 1 is a precision-controlled pulse width modulation signal generator, which may include a basic pulse width modulation signal generator that generates a basic pulse width modulation signal from a clock signal, a slew rate controller configured to change the edges of the basic pulse width modulation signal, and a comparator having a first input terminal that receives the output signal of the slew rate controller and a second input terminal that receives a comparison threshold, and configured to output a precision-controlled pulse width modulation signal based on a comparison of the first input signal and the second input signal.

[0051] Example 2 is a signal generator based on Example 1, wherein the slew rate controller is actively controlled.

[0052] Example 3 is a signal generator based on Example 1 or Example 2, wherein the slew-rate controller includes a controllable current sink.

[0053] Example 4 is a signal generator based on any of Examples 1 to 3, wherein the slew-rate controller includes a resistive-capacitive network.

[0054] Example 5 is a signal generator based on any of Examples 1 to 4, wherein the resistance in the resistor-capacitance circuit is controllable.

[0055] Example 6 is a signal generator based on any of Examples 1 to 5, wherein the comparison threshold applied to the second input terminal is controllable.

[0056] Example 7 is a signal generator based on any of Examples 1 to 6, wherein the basic pulse width modulation signal generator is implemented using a field-programmable gate array.

[0057] Example 8 is a signal generator based on any of Examples 1 to 7, wherein the clock signal is the master clock signal of a field-programmable gate array.

[0058] Example 9 is a power supply, A basic pulse width modulation signal generation circuit configured to generate a basic pulse width modulation signal from a clock, A slew rate controller configured to modify the edges of the above basic pulse width modulated signal, A comparator having a first input terminal that receives the output signal of the slew rate controller and a second input terminal that receives a comparison threshold, and configured to output a second pulse width modulated signal based on a comparison of the first input signal and the second input signal. A pulse width modulation signal generator having, A switching power supply configured to be coupled to the output of the above comparator and generate the output voltage of the above power supply, It may also be equipped with [the following].

[0059] Example 10 is a power supply based on Example 9, wherein the switching power supply includes a switching transistor controlled by the second pulse width modulated signal output by the comparator.

[0060] Example 11 is a power supply based on Example 9 or Example 10, which may further include an error correction circuit configured to receive the output voltage of the power supply and generate an error signal indicating the difference between the output voltage of the power supply and a desired output voltage of the power supply.

[0061] Example 12 is a power supply based on any of Examples 9 to 11, wherein the error correction circuit is coupled to a controller within the power supply.

[0062] Example 13 is a power supply based on any of Examples 9 to 11, wherein the controller is configured to modify the operation of one or more of the slew rate controller and the comparison threshold.

[0063] Example 14 is a power supply based on any of Examples 9 to 11, wherein either or both of the basic pulse width modulation signal generation circuit and the controller are part of a field-programmable gate array.

[0064] Example 15 is a method for generating a precision pulse width modulation signal, which may include a process for generating a basic pulse width modulation signal, a process for generating a modified pulse width modulation signal by controlling the slew rate of the edges of the basic pulse width modulation signal, a process for comparing the modified pulse width modulation signal with a threshold, and a process for outputting the precision pulse width modulation signal based on the comparison between the modified pulse width modulation signal and the threshold.

[0065] Example 16 is a method based on Example 15, which may further include a process for generating a feedback signal that compares the modified pulse width modulated signal with a desired pulse width modulated signal.

[0066] Example 17 is a method based on Example 15 or Example 16, which may further include a process for correcting the slew rate of the edges of the basic pulse width modulated signal using a feedback signal.

[0067] Example 18 is a method based on any of Examples 15 to 17, which may further include a process for changing the threshold value based on a feedback signal.

[0068] Example 19 is a method based on any of Examples 15 to 18, which may further include a process of receiving a clock signal from a field-programmable gate array, wherein the process of generating the basic pulse width modulated signal includes a process of generating the basic pulse width modulated signal from the clock signal.

[0069] The aforementioned versions of the subject matter of this disclosure have many effects that have been described or will be apparent to those skilled in the art. Nevertheless, not all of these effects or features are required in all versions of the disclosed apparatus, system, or method.

[0070] In addition, the description of this application refers to certain features. It should be understood that the disclosures herein include all possible combinations of these particular features. Where a particular feature is disclosed in relation to a particular aspect or example, that feature may, to the extent possible, also be used in relation to other aspects and examples.

[0071] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, as long as the circumstances do not rule out such possibilities.

[0072] For the sake of explanation, specific embodiments of the present invention have been illustrated and described, but it should be understood that various modifications are possible without deviating from the gist and scope of the present invention. Therefore, the present invention should not be limited to anything other than the appended claims. [Explanation of Symbols]

[0073] 10 Basic PWM Signal Generator 20 Slew Rate Controller 30 Duty Cycle Controller 50 Thru-Rate Controller 52 Bypass 54 Capacitors 56 Current Generator 60 Thru-Rate Controller 66 resistors 70 Slew Rate Controller 76 controllable resistors 90 Comparator 92 Non-inverting input terminal 94 Inverting Input Terminal 100 Precisely controllable PWM signal generators Output voltage of a 200 PWM signal generator 210 Original Master Clock Signal 220 PWM signal 222 Falling Edge 230 PWM signal 232 Falling Edge 234 Variable comparator threshold 236 Crossing points 240 New PWM signal 242 Falling Edge 500 Voltage Generator 503 User Input 505 Digital-to-Analog Converter (DAC) 507 Digital-to-Analog Converter (DAC) 510 FPGA 512 PWM Signal Generator 516 Error Controller 520 Slew Rate Controller 530 Duty Cycle Controller 550 Switching Power Supply 560 Output Voltage Monitor 565 Analog-to-Digital Converter (ADC)

Claims

1. A pulse width modulation signal generator, A basic pulse width modulation signal generator configured to generate a basic pulse width modulation signal from a clock signal, A slew rate controller configured to modify the edges of the above basic pulse width modulated signal, A comparator having a first input terminal that receives the output signal of the slew rate controller and a second input terminal that receives a comparison threshold, and configured to output a precision control pulse width modulated signal based on a comparison of the first input signal and the second input signal. A PWM signal generator equipped with [a specific feature].

2. A PWM signal generator according to claim 1, wherein the comparator is configured to output the precision-controlled pulse width modulated signal that can control the edge position in steps smaller than the minimum duration of the clock signal.

3. A PWM signal generator according to claim 1, wherein the slew rate controller includes a controllable current sink or a resistive-capacitive circuit.

4. The above basic pulse width modulation signal generator is implemented using a field-programmable gate array. A PWM signal generator according to claim 1, wherein the above clock signal is the master clock signal of the above field-programmable gate array.

5. It is a power source, A basic pulse width modulation signal generation circuit configured to generate a basic pulse width modulation signal from a clock signal, A slew rate controller configured to modify the edges of the above basic pulse width modulated signal, A comparator having a first input terminal that receives the output signal of the slew rate controller and a second input terminal that receives a comparison threshold, and configured to output a second pulse width modulated signal based on a comparison of the first input signal and the second input signal. A pulse width modulation signal generator having, A switching power supply, which is coupled to the output of the above comparator and configured to generate the output voltage of the above power supply, A power supply equipped with [a specific feature].

6. The power supply according to claim 5, wherein the comparator is configured to output the second pulse-width modulated signal that can control the edge position in steps smaller than the minimum duration of the clock signal.

7. The system further comprises an error correction circuit configured to receive the output voltage of the above-mentioned power supply and generate an error signal indicating the difference between the above-mentioned output voltage of the power supply and the desired output voltage of the power supply, The error correction circuit is coupled to the controller in the power supply, The power supply according to claim 5, wherein the controller is configured to modify the operation of one or more of the slew rate controller and the comparison threshold.

8. Either or both of the above basic pulse width modulation signal generation circuit and the above controller are part of a field-programmable gate array. The power supply according to claim 7, wherein the above clock signal is the master clock signal of the above field-programmable gate array.

9. A method for generating a pulse-width modulated (PWM) signal, The process of generating a basic pulse width modulated signal, The process involves controlling the slew rate of the edges of the above basic pulse width modulated signal to generate a modified pulse width modulated signal, The above modified pulse width modulated signal is compared with a threshold, Based on the comparison of the above modified pulse width modulated signal and the above threshold, a process is performed to output a precise pulse width modulated signal. A PWM signal generation method comprising the following.

10. The system further includes a function to receive a clock signal from a field-programmable gate array. The process for generating the basic pulse width modulated signal includes the process for generating the basic pulse width modulated signal from the above clock signal. A PWM signal generation method according to claim 9, wherein the edge position of the basic pulse width modulated signal can be controlled in steps smaller than the minimum period of the clock signal.

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