Memory device

Abstract

To provide highly reliable storage devices. [Solution] A first conductor, a second conductor above the first conductor, and a third conductor above the second conductor. A conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, and a fifth The sixth conductor above the conductor, the seventh conductor, the first insulator, the second insulator, and the first semiconductor It has a second semiconductor and a third conductor and a fourth conductor which have an opening. From the inner side surface outwards, a first insulator, a first semiconductor, a second insulator, and a second semiconductor are provided in that order. In the region between the third conductor and the second insulator, a seventh conductive material is present between the first semiconductor and the second insulator. A body is provided, and the first semiconductor is electrically connected to the second conductor and the fifth conductor, and the second semiconductor The conductor is electrically connected to the first conductor and the sixth conductor.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The field of expertise is related to products, methods, or methods of manufacture. Or, one aspect of the present invention is , process, machine, manufacture, or composition of matter This concerns (—).

[0003] In this specification, a semiconductor device is defined as a device that can function by utilizing semiconductor properties. This refers to the whole. Therefore, it includes semiconductor elements such as transistors and diodes, or elements that include semiconductor elements. A circuit is a semiconductor device. It is also used in display devices, light-emitting devices, lighting devices, electro-optical devices, and memory devices. The following may include semiconductor elements and semiconductor circuits: Also, display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices Electronic devices and other equipment are sometimes also referred to as semiconductor devices. One aspect of the present invention is described in particular. This relates to a memory device and a method for manufacturing the same. [Background technology]

[0004] In recent years, with the increasing volume of data being handled, there has been a growing demand for semiconductor devices with larger storage capacities. It is being done. In order to increase the storage capacity per unit area, memory cells are stacked to form This is effective (see Patent Documents 1 and 2). Memory cells are stacked and provided. This allows the storage capacity per unit area to be increased in proportion to the number of stacked memory cells. Yes, it is possible. Patent documents 3 and 4 disclose memory devices using oxide semiconductors. therein. Patent Document 5 discloses a semiconductor memory using an oxide semiconductor as a charge storage layer .

[0005] Further, Non-Patent Document 1 discloses CAAC-IGZO as a crystalline oxide semiconductor therein. Further, Non-Patent Document 1 also discloses the growth mechanism of CAAC-IGZO and the like therein. [Prior Art Documents] [Patent Documents]

[0006] [Patent Document 1] U.S. Patent Publication No. 2011 / 0065270A1 [Patent Document 2] U.S. Patent No. 9634097B2 [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2018-207038 [Patent Document 4] Japanese Unexamined Patent Application Publication No. 2019-8862 [Patent Document 5] Japanese Unexamined Patent Application Publication No. 2018-157205 [Non-Patent Documents]

[0007] [Non-Patent Document 1] Noboru Kimizuka and Shunpei Yamazaki, "PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE SEMICONDUCTOR CAAC-IGZO" FUNDAMENTALS (USA), Wiley-SID Series in Display Technology, 2017, pp. 94-97 [Summary of the Invention] [Problems to be Solved by the Invention]

[0008] In Patent Documents 1 and 2, multiple memory elements (also called memory cells) are stacked. These are connected in series to form a three-dimensional memory cell array (memoryst). It forms a ring (also called a ring).

[0009] In Patent Document 1, a columnar semiconductor is in contact with an insulator having a charge storage layer. In Patent Document 2, a columnar semiconductor functions as a tunnel dielectric. It is in contact with an insulator. Both Patent Document 1 and Patent Document 2 describe the writing of information to a memory cell. The process is carried out by the extraction and injection of charge through an insulator. In this case, it is a semiconductor. A trap center may form at the interface where the material and the insulator come into contact. This can trap electrons and alter the threshold voltage of a transistor. Also, the charge Through extraction and injection, one of the insulator's interiors and the interface where the semiconductor and the insulator are in contact, Both deteriorate, and the charge held in the charge storage layer may leak out and disappear. This could negatively impact the reliability of the storage device.

[0010] Therefore, one embodiment of the present invention aims to provide a highly reliable storage device. Furthermore, one embodiment of the present invention aims to provide a storage device with a large storage capacity. Furthermore, one embodiment of the present invention aims to provide a storage device with a small footprint. Furthermore, one embodiment of the present invention aims to provide a memory device with low manufacturing costs. Furthermore, one embodiment of the present invention aims to provide a highly reliable semiconductor device. One embodiment of the present invention aims to provide a semiconductor device with low manufacturing costs. Furthermore, one embodiment of the present invention aims to provide a novel semiconductor device.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. The embodiment does not need to solve all of these problems. Other problems are addressed in the specification. This will become clear from the description in the drawings, claims, etc., and the specification, drawings, claims Based on these descriptions, it is possible to identify other issues besides those mentioned above. [Means for solving the problem]

[0012] One aspect of the present invention comprises a first conductor, a second conductor above the first conductor, and a third conductor above the second conductor. 3 conductors, a 4th conductor above the 3rd conductor, a 5th conductor above the 4th conductor, and a 5th conductor The body consists of a sixth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor, and It has two semiconductors, and at least the third conductor and the fourth conductor have an opening, and within the opening From the side surface outwards, a first insulator, a first semiconductor, a second insulator, and a second semiconductor are provided in that order. In the region between the third conductor and the second insulator, a seventh conductor is present between the first semiconductor and the second insulator. The first semiconductor is provided and is electrically connected to the second conductor and the fifth conductor, and the second semiconductor This is a memory device that is electrically connected to the first conductor and the sixth conductor.

[0013] In the above, inside the opening of the third conductor, the first insulator, the first semiconductor, and the seventh The conductor, the second insulator, and the second semiconductor are each arranged as concentric layers. preferable.

[0014] In the above, inside the opening of the fourth conductor, the first insulator, the first semiconductor, and the second It is preferable that the insulator and the second semiconductor are provided as concentric layers.

[0015] In the above, it is preferable that the first semiconductor is a first oxide semiconductor.

[0016] In the above, the first oxide semiconductor is indium, element M (where element M is aluminum, One or more selected from gallium, yttrium, tin, and titanium, and sub- It is preferable that it contains lead.

[0017] In the above, it is preferable that the second semiconductor is a second oxide semiconductor.

[0018] In the above, the first oxide semiconductor is indium, element M (where element M is aluminum, One or more selected from gallium, yttrium, tin, and titanium, and sub- It is preferable that it contains lead.

[0019] In the above, the openings are also provided in the second conductor and the fifth conductor, and the second conductor and the fifth A second insulator is provided between the two semiconductors, and a second insulator is provided between the fifth conductor and the second semiconductor. It is preferable that such a feature be provided.

[0020] Another aspect of the present invention involves forming a first conductor and forming a second conductor above the first conductor. Then, a first semiconductor is formed that is electrically connected to the second conductor, and the first semiconductor and the second conductor An opening is formed, and within the opening, an insulating layer covers the side surface of the first semiconductor and the side surface of the second conductor. The process includes a step of forming a rim and a second semiconductor that is electrically connected to a first conductor, and the first semiconductor An insulator is provided between the conductor and the second semiconductor, and an insulator is provided between the second conductor and the second semiconductor. This is a method for manufacturing a memory device.

[0021] In the above, it is preferable that the first semiconductor is a first oxide semiconductor.

[0022] In the above, the first oxide semiconductor is indium, element M (where element M is aluminum, One or more selected from gallium, yttrium, tin, and titanium, and sub- It is preferable that it contains lead.

[0023] In the above, it is preferable that the second semiconductor is a second oxide semiconductor.

[0024] In the above, the second oxide semiconductor is indium, element M (element M is aluminum, One or more selected from gallium, yttrium, tin, and titanium, and sub- It is preferable that it contains lead.

[0025] Another aspect of the present invention involves forming a first conductor and forming a second conductor above the first conductor. Furthermore, the width of the second conductor becomes shorter than the width of the first conductor. Processed in such a way, a third conductor is formed above the second conductor, and the third conductor, the second conductor, and The process involves forming an opening in the first conductor, forming an insulator within the opening, and forming a semiconductor within the opening. The first conductor and the semiconductor are provided with an insulator, and the second conductor and the semiconductor are provided with an insulator. This is a method for manufacturing a memory device.

[0026] In the above, the semiconductor is preferably an oxide semiconductor.

[0027] In the above, the oxide semiconductor is indium, element M (element M is aluminum, gallium) Contains one or more selected from ttrium, yttrium, tin, and titanium, and zinc. It is preferable to do so. [Effects of the Invention]

[0028] In fabricating a three-dimensional memory cell array in which multiple memory elements are stacked and connected in series, In this process, the total number of steps is the product of the number of memory elements to be stacked and the number of steps required to manufacture one memory element. This is preferable because it can be reduced. In other words, the manufacturing process of the memory cell array described above involves stacking memory cells. It is not proportional to the number of memory elements. For example, the manufacturing process of a memory cell array A having four layers of memory elements. When comparing the number of memory elements with the number of manufacturing steps for memory cell array B having 32 layers of memory elements, Despite the number of stacked cells being eight times greater, the number of manufacturing steps for memory cell array B is... The number of manufacturing steps for Luarray A can be significantly reduced to less than eight times the number of steps required for Luarray A.

[0029] One embodiment of the present invention can provide a highly reliable storage device. In one embodiment, a storage device with a large memory capacity can be provided. This makes it possible to provide a storage device with a small footprint. Furthermore, according to one embodiment of the present invention, It is possible to provide a memory device with low manufacturing costs. Furthermore, according to one embodiment of the present invention, reliability High-performance semiconductor devices can be provided. Furthermore, according to one embodiment of the present invention, manufacturing costs can be reduced. It is possible to provide a semiconductor device with low noise. Furthermore, according to one embodiment of the present invention, a novel semiconductor device can be provided. We can provide the device.

[0030] Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not need to have all of these effects. Other effects are described in the specification. This will become clear from the descriptions in the drawings and claims, and the specification, drawings, and claims will be clear from the description, drawings, and claims. It is possible to extract other effects from any of these descriptions. [Brief explanation of the drawing]

[0031] [Figure 1] Figures 1A and 1B are perspective views of the storage device. [Figure 2] Figure 2 is a cross-sectional view of the memory device. [Figure 3] Figure 3 is a cross-sectional view of a memory string. [Figure 4] Figure 4 is a circuit diagram of the memory string. [Figure 5] Figures 5A and 5B are cross-sectional views of the memory string. [Figure 6] Figure 6 is a cross-sectional view of the memory element. [Figure 7] Figures 7A and 7B are cross-sectional views of the memory string. [Figure 8] Figure 8 is a cross-sectional view of a memory string. [Figure 9] Figure 9A is a diagram illustrating the classification of crystal structures. Figure 9B is a diagram illustrating the XRD spectrum of the CAAC-IGZO film. Figure 9C is a diagram illustrating the micro-electron diffraction pattern of the CAAC-IGZO film. [Figure 10] Figures 10A to 10C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 11] Figures 11A to 11C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 12] Figures 12A to 12C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 13] Figures 13A to 13C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 14] Figures 14A to 14C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 15] Figures 15A to 15C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 16] Figures 16A to 16C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 17] Figures 17A to 17C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 18] Figures 18A to 18C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 19] Figures 19A to 19C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 20] Figures 20A to 20C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 21] Figures 21A to 21C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 22] Figures 22A to 22C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 23] Figures 23A to 23C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 24] Figures 24A to 24C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 25] Figures 25A to 25C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 26] Figures 26A to 26C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 27] Figures 27A to 27C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 28] Figures 28A to 28C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 29] Figures 29A to 29C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 30] Figures 30A to 30C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 31] Figures 31A to 31C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 32] Figure 32A is a schematic diagram of a multi-chamber type film deposition apparatus. Figure 32B is a cross-sectional view of the film deposition chamber. [Figure 33] Figures 33A to 33C illustrate an example of the configuration of an ALD device. [Figure 34] Figure 34 illustrates an example of a memory string circuit configuration. [Figure 35] Figure 35 illustrates an example of a memory string circuit configuration. [Figure 36] Figure 36 illustrates an example of a memory string circuit configuration. [Figure 37] Figure 37 illustrates an example of a memory string circuit configuration. [Figure 38] Figure 38 illustrates an example of a memory string circuit configuration. [Figure 39] Figure 39 is a timing chart illustrating an example of a memory string write operation. [Figure 40] Figures 40A and 40B are circuit diagrams illustrating an example of memory string writing operation. [Figure 41] Figures 41A and 41B are circuit diagrams illustrating an example of memory string writing operation. [Figure 42] Figure 42 is a timing chart illustrating an example of a memory string read operation. [Figure 43] Figures 43A and 43B are circuit diagrams illustrating an example of memory string read operation. [Figure 44] Figures 44A and 44B are circuit diagrams illustrating an example of memory string read operation. [Figure 45] Figure 45 is a circuit diagram illustrating an example of memory string read operation. [Figure 46] Figure 46 is a block diagram illustrating an example of a semiconductor device configuration. [Figure 47]Figures 47A to 47C are perspective views illustrating an example of a semiconductor device configuration. [Figure 48] Figure 48 is a cross-sectional view illustrating a semiconductor device according to one aspect of the present invention. [Figure 49] Figure 49 is a cross-sectional view illustrating a semiconductor device according to one aspect of the present invention. [Figure 50] Figure 50A is a perspective view illustrating an example of a computer configuration, and Figure 50B is a perspective view illustrating a monolithic IC. [Figure 51] Figures 51A and 51B illustrate the memory hierarchy of a computer and a monolithic IC, respectively. [Figure 52] Figure 52A is a schematic diagram of a semiconductor device. Figure 52B is a perspective view of the semiconductor device. [Figure 53] Figures 53A to 53E are diagrams illustrating an example of a storage device. [Figure 54] Figures 54A to 54G are diagrams illustrating an example of an electronic device. [Modes for carrying out the invention]

[0032] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further modifications are possible. Therefore, the present invention can be implemented in the following forms. The interpretation is not limited to the description of the state. Furthermore, the structure of the invention described below... Furthermore, the same reference numeral is used across different drawings for parts that are identical or have similar functions. We will use it and omit the repetition of its explanation.

[0033] Furthermore, the position, size, and scope of each component shown in the drawings, etc., are intended to facilitate understanding of the invention. Therefore, it may not represent the actual location, size, or range. For this reason, disclosure is required. The invention is not necessarily limited to the location, size, scope, etc. disclosed in the drawings, etc. For example. In the actual manufacturing process, the resist mask may be unintentionally damaged by processes such as etching. While there may be some reduction in value, this is sometimes not reflected in the diagram for the sake of clarity.

[0034] Furthermore, in order to make the explanations easier to understand, some components are omitted from the drawings and other diagrams. It may happen.

[0035] Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit.

[0036] Furthermore, in this specification, etc., "terminal" in an electrical circuit means an input or output of current, This refers to the part where pressure is input or output, or where signals are received or transmitted. In some cases, a portion of the wiring or electrodes may function as a terminal.

[0037] In this specification, the terms "above" and "below" refer to the relative positions of the constituent elements, specifically whether they are directly above or below. It is not limited to being below and in direct contact. For example, "electrode on insulating layer A" If the expression is "B", then it is not necessary for electrode B to be formed in direct contact with insulating layer A. Cases containing other components between marginal layer A and electrode B are not excluded.

[0038] Furthermore, the source and drain functions may differ when using transistors with different polarities, or when rotating In circuit operation, the direction of the current changes, and depending on the operating conditions, they can be swapped. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain may be used interchangeably. Let's assume that.

[0039] Furthermore, in this specification, "electrically connected" refers to both a direct connection and a "some kind of connection". This includes cases where it is connected via "something that has an electrical effect". Here, "something "A device having an electrical function" is one that enables the exchange of electrical signals between connected objects. If so, there are no particular restrictions. Therefore, even when it is expressed as "electrically connected", In real-world circuits, there may be no physical connections, only prolonged wiring. .

[0040] Furthermore, in this specification and elsewhere, "parallel" means, for example, two straight lines that are at an angle of -10° or more and 10° or less. This refers to a state where objects are positioned at the following angles. Therefore, it also includes cases where the angle is between -5° and 5°. Furthermore, "perpendicular" and "orthogonal" refer to, for example, two lines that are at an angle of 80° or more but less than or equal to 100°. This refers to a state where objects are arranged at an angle. Therefore, it includes cases where the angle is between 85° and 95°.

[0041] Furthermore, in this specification and other documents, regarding count values ​​and measured values, or count values ​​or measured values, Regarding things, methods, and events that can be converted into quantitative values, the terms "identical," "same," and "equal" are used. Or, when we say "uniform," unless otherwise specified, it means plus or minus 20%. This includes errors.

[0042] Furthermore, voltage is the potential difference between a certain potential and a reference potential (e.g., ground potential or source potential). This often indicates that voltage and electric potential are interchangeable. In this specification, unless otherwise specified, voltage and potential may be used interchangeably. It shall be considered as such.

[0043] Furthermore, even when the term "semiconductor" is used, if, for example, its conductivity is sufficiently low, it can be referred to as an "insulator." It possesses the following characteristics. Therefore, it is also possible to use it by replacing "semiconductor" with "insulator". In this case, the boundary between "semiconductors" and "insulators" is ambiguous, and a strict distinction between the two is difficult. Therefore, the terms "semiconductor" and "insulator" as used herein are interchangeable. It may be possible.

[0044] Furthermore, even when the term "semiconductor" is used, for example, if the conductivity is sufficiently high, it can be referred to as a "conductor." It possesses the following characteristics. Therefore, it is also possible to use it by replacing "semiconductor" with "conductor". In this case, the boundary between "semiconductors" and "conductors" is ambiguous, and a strict distinction between the two is difficult. Therefore, the terms "semiconductor" and "conductor" as used herein are interchangeable. It may be possible.

[0045] Furthermore, in this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. This is for visual inspection only and does not indicate any order or ranking, such as process order or layering order. Furthermore, even if an ordinal number is not attached to a term in this specification, the confusion of its constituent elements may occur. To avoid this, ordinal numbers may be added to the claims. Also, in this specification, etc. Even if a term is given an ordinal number in the patent claim, if a different ordinal number is used in the patent claim Ordinal numbers may be attached. Also, even if a term is used with an ordinal number in this specification, Ordinal numbers may be omitted in patent claims and other documents.

[0046] In this specification, the "on state" of a transistor refers to the source and This refers to a state where the drain can be considered electrically short-circuited (also called a "conductive state"). Furthermore, the "off state" of a transistor means that the source and drain of the transistor are electrically disconnected. This refers to a state in which a device can be considered to be conducting (also called a "non-conductive state").

[0047] Furthermore, in this specification, "on-current" refers to the current when the transistor is in the ON state and the source is connected to the transistor. It can also refer to the current flowing between the drains. Furthermore, "off-current" refers to the current flowing between the drains of a transistor. It can also refer to the current flowing between the source and drain when the circuit is in a faulty state.

[0048] Furthermore, in this specification, etc., the high power supply potential VDD (hereinafter simply referred to as "VDD", "H potential", etc.) (Also called "H") is the low power supply potential VSS (hereinafter simply referred to as "VSS", "L potential", etc.) It indicates a power supply potential that is higher than VDD (also called "L"). Also, VSS is a power supply potential that is higher than VDD. It also shows a low potential power supply potential. Furthermore, the ground potential (hereinafter simply referred to as "GND") The potential (also called the electric potential) can also be used as VDD or VSS. For example, VDD is grounded. In the case of potential, VSS is at a potential lower than the ground potential, and when VSS is at the ground potential, VDD is at a higher potential than the ground potential.

[0049] Furthermore, the transistors described herein, unless otherwise explicitly stated, are enhancement transistors. Let's assume it's a normally-off type n-channel field-effect transistor. Therefore, its equation is The voltage value (also called "Vth") shall be greater than 0V. Also, unless otherwise specified... Except in cases where, "supplying a high potential to the gate of a transistor" means "to supply a high potential to the gate of a transistor." It can be synonymous with "to turn on." Also, unless explicitly stated, "transition" "Supplying an inductive potential to the gate of a transistor" is synonymous with "turning the transistor off." There are cases where this is the case.

[0050] Furthermore, in this specification, etc., "gate" refers to part or all of the gate electrode and gate wiring. This refers to the gate wiring of at least one transistor and another transistor. This refers to wiring used to electrically connect poles or other wiring.

[0051] Furthermore, in this specification, etc., "source" refers to the source region, source electrode, and source wiring. This refers to part or all of something. The source region is the part of the semiconductor layer whose resistivity is below a certain value. It refers to a region. The source electrode refers to the conductive layer of the part connected to the source region. Source wiring refers to the source electrode of at least one transistor and another electrode or other wiring. This refers to the wiring used to electrically connect two things.

[0052] Furthermore, in this specification, etc., "drain" refers to the drain region, drain electrode, and drain This refers to part or all of the wiring. The drain region is a part of the semiconductor layer with constant resistivity. This refers to the region below a certain value. The drain electrode is the conductive layer of the part connected to the drain region. This refers to the drain wiring, which is the connection between the drain electrode of at least one transistor and another This refers to wiring used to electrically connect electrodes or other wiring.

[0053] Furthermore, in drawings and other diagrams, in order to make the potential of wiring and electrodes easier to understand, wiring and In cases where an "H" indicating an H potential or an "L" indicating an L potential is added adjacent to an electrode, etc. Yes. Also, the wires and electrodes where a potential change occurs are marked with the letters "H" or "L". This may be noted as follows. Also, if the transistor is in the off state, the transistor Sometimes, an "×" symbol is added in addition.

[0054] Furthermore, generally speaking, "capacitance" refers to a configuration in which two electrodes face each other with an insulator (dielectric) in between. In this specification, the term "capacitive element" includes the case of the "capacitance" described above. In other words, in this specification, a "capacitive element" refers to a device in which two electrodes face each other across an insulator. Those with a matching configuration, those with a configuration in which two wires face each other with an insulator in between, This includes cases where two wires are arranged with an insulator in between.

[0055] Furthermore, in this specification, when the same reference numeral is used for multiple elements, we will not specifically distinguish them. When necessary, use identifiers such as "_1", "_2", "[n]", "[m,n]" in the code. Sometimes a designation is added to indicate the type of conductor. For example, the second conductor WWL may be referred to as conductor WWL [2] is sometimes written as such.

[0056] (Embodiment 1) Figure 1A shows a semiconductor storage device 100 and a drive circuit 2000 according to one aspect of the present invention. A perspective view of the main unit 200 is shown. The storage device 100 is a storage device having a three-dimensional stacked structure. ru.

[0057] The drive circuit 2000 includes WSL driver 2001, WBL driver 2002, and RSL driver. Driver 2003, RBL Driver 2004, WWL Driver 2005, RWL Driver 200 6. It has SEL driver 2007, etc. Note that RBL driver 2004 is sensean It may also have the function of a p. Also, the RSL driver 2003 is connected to ground. It's fine if you do that.

[0058] The WSL driver 2001 connects to the storage device 100 via the wiring WSL_A. Driver 2002 connects to storage device 100 via wiring WBL_A. RSL driver Unit 2003 connects to the storage device 100 via wiring RSL_A. RBL driver 20 04 connects to the storage device 100 via wiring RBL_A. WWL driver 2005 , connected to the storage device 100 via either or both of the wiring WWL_A and wiring SG_A. The RWL driver 2006 connects to the storage device 100 via wiring RWL_A. The SEL driver 2007 connects to the storage device 100 via wiring SEL_A. Also, Wiring BG_A connects to the back gate of the storage device 100.

[0059] It is preferable that the storage device 100 is provided above the layer on which the drive circuit 2000 is provided. Furthermore, as shown in Figure 1B, the storage device 100 is provided so as to overlap with a part of the drive circuit. This is preferable because it reduces the occupied area of ​​the semiconductor device 200. When 00 and the drive circuit are superimposed, the entire drive circuit may be superimposed with the memory device 100, It may be superimposed on a part of the drive circuit. Also, the storage device 100 and the drive circuit have a specific number It may also be superimposed on the path. For example, the memory device 100 may be superimposed on the sense amplifier. An amplifier can be placed there.

[0060] A semiconductor device 200 according to one aspect of the present invention is a wiring W that functions as a source line for writing. It has SL_A and a wiring RSL_A that functions as a source line for reading. One of its features is, but it is not limited to, that wiring WSL_A and wiring RSL_A are mutual It may be connected to a drive circuit that functions as a source line driver.

[0061] A semiconductor device 200 according to one aspect of the present invention includes wiring W that functions as a bit line for writing. It has a wiring RBL_A that functions as a bit line for reading, and a wiring RBL_A that functions as a bit line for reading. One of its features is, but it is not limited to, that wiring WBL_A and wiring RBL_A are mutual It may be connected to a drive circuit that functions as a bit line driver.

[0062] Note that in Figure 1A and other images, arrows indicating the X, Y, and Z directions may be included. The X, Y, and Z directions are each orthogonal to each other. In this context, one of the X, Y, or Z directions is referred to as the "first direction" or "first direction." In some cases, the other one may be called the "second direction" or "second option." Furthermore, the remaining one is sometimes referred to as the "third direction" or "third direction." (See Specified In this case, the direction perpendicular to the upper surface of the base 121, which will be described later, is defined as the Z direction.

[0063] Figure 2 shows a cross-section in the XZ plane. Figure 2 shows the region A1-A indicated by the dashed line in Figure 1. 2. This is a cross-sectional view of the connection between the conductive SEL and the wiring. As mentioned above, the explanation is For the sake of clarity, some components may be omitted in Figures 1 and 2, etc. .

[0064] <Example of storage device configuration> A storage device 100 according to one aspect of the present invention has a memory cell array 110. The array 110 has multiple memory strings 120. The memory strings 120 are arranged in the Z direction. They extend in the direction and are arranged in a matrix on the XY plane.

[0065] Figure 3 shows an example of a cross-sectional configuration of a memory string 120 according to one aspect of the present invention, and Figure 4 shows the corresponding The circuit diagram is shown. The memory string 120 consists of multiple memory elements MC (also called "memory cells"). .) has a configuration in which five memory elements MC are connected in series. This shows the case where the memory string 120 has memory elements MC, but the number of memory elements MC is not limited to 5. It is not fixed. If n is the number of memory elements MC in the memory string 120, n can be any integer greater than or equal to 2.

[0066] Furthermore, the memory string 120 consists of multiple conductors WWL, multiple conductors RWL, and a conductive It has a body SG and a conductor SEL. Note that the conductor WWL is part of the wiring WWL_A. Conductor RWL functions as part of wiring RWL_A, and conductor SG is wiring The conductive SEL functions as part of SG_A, and the wiring SEL_A functions as part of the wiring SEL_A. Multiple conductors WWL and multiple conductors RWL are arranged in alternating layers with an insulator 123 in between. The conductor SG is located below multiple conductors WWL and multiple conductors RWL. It is provided. Below the conductive SG, a conductive WSL is provided, and below the conductive WSL Conductor RSL is provided there. Conductor SEL consists of multiple conductor WWL and multiple conductors It is located above the conductive RWL. Above the conductive SEL, the conductive WBL is provided. Furthermore, a conductive RBL is provided on top of the conductive WBL.

[0067] In Figures 3 and 4, five memory elements MC are shown as memory element MC[1] to memory element MC[5]. This indicates that... In that case, it is simply indicated as "memory element MC". Conductor WWL, conductor RWL, and insulator 12 The same applies to other components such as 3.

[0068] The memory string 120 has a transistor STr1 connected to the memory element MC[1], and It has a transistor STr2 connected to a memory element MC[5].

[0069] Conductors WWL, RWL, SG, and SEL are used in memory cell array 1 It extends in the X-axis direction beyond 10. Also, conductor WWL, conductor RWL, conductor SG, The conductive SELs are stacked in a stepped pattern on the outside of the memory cell array 110 (Figure 1). See Figure 2.) On the other hand, conductors WSL, RSL, WBL, and R The BL extends in the Y-axis direction beyond the memory cell array 110 (see Figures 1 and 3). .

[0070] Figure 5A shows a cross-section of the XY plane, including the region B1-B2 indicated by the dashed line in Figure 3, as viewed from the Z direction. As shown in Figure 3, the cross-section of the XY plane containing the region C1-C2, indicated by the dashed line, viewed from the Z direction. Figure 5B shows this. Figure 6 shows an enlarged view of the region 105 indicated by the dashed line in Figure 3. Figure 6 is described This corresponds to a cross-sectional view of a memory element MC.

[0071] The memory string 120 is a conductor that functions as part of the wiring RSL_A on the substrate 121. Having RSL, the device has wiring WSL_A as part of the circuit via insulator 118 on the conductive RSL. It has a conductive WSL. For the substrate 121, for example, an insulator may be used. Conductor WSL, insulator 123[1], conductor SG, insulator 123[2], conductor RW L[1], insulator 123[3], conductor WWL[1], insulator 123[4], conductor RW L[2], insulator 123[5], conductor WWL[2], insulator 123[6], conductor RW L[3], insulator 123[7], conductor WWL[3], insulator 123[8], conductor RW L[4], insulator 123[9], conductor WWL[4], insulator 123

[10] , conductor R WL[5], insulator 123

[11] , conductor WWL[5], insulator 123

[12] , and It has a conductive SEL (see Figure 3). In addition, an insulator 138 is placed on the conductive SEL. It has a conductive WBL that functions as part of the wiring WBL_A, and an insulator 1 on the conductive WBL. It has a conductive RBL that functions as part of wiring RBL_A via 86.

[0072] Furthermore, the memory string 120 consists of an insulator 118, a conductor WSL, an insulator 123[1], Conductor SG, insulator 123[2], conductor RWL[1], insulator 123[3], conductor W WL[1], insulator 123[4], conductor RWL[2], insulator 123[5], conductor W WL[2], insulator 123[6], conductor RWL[3], insulator 123[7], conductor W WL[3], insulator 123[8], conductor RWL[4], insulator 123[9], conductor W WL[4], insulator 123

[10] , conductor RWL[5], insulator 123

[11] , conductive Body WWL[5], insulator 123

[12] , conductor SEL, insulator 138, conductor WBL. It has an opening 141 formed by removing a portion of the insulator 186 and the conductor RBL, respectively.

[0073] The opening 141 extends in the Z direction and reaches the conductor WSL and the conductor RSL. In 141, the diameter of region 142 overlapping with the conductor RWL is equal to the diameter of region 1 overlapping with the conductor WWL. It is larger than the diameter of 43. Therefore, the side surface of the opening 141 has an uneven shape.

[0074] In addition, an insulator 124 and a semiconductor 125 are provided along the side surface of the opening 141. The semiconductor 125 has a region that overlaps with the side surface of the opening 141 via the insulator 124.

[0075] Furthermore, the memory string 120 has a conductor 130 that extends in the Z direction. 0 is located at or near the center of the opening 141. Also, the opening 1 of the conductor 130 An insulator 129, a semiconductor 127, and an insulator 126 are provided in the region overlapping with the side of 41. The semiconductor 127 has a region that overlaps with the side surface of the conductor 130 via the insulator 129. The insulator 126, via the insulator 129 and semiconductor 127, is on the side of the conductor 130. It has a region that overlaps with the surface. Also, at the bottom of the opening 141, the semiconductor 127 is a conductor R Having an area electrically connected to SL, the semiconductor 127 is conductive at the top of the opening 141. It has a region that is electrically connected to the body RBL. Also, at the bottom of the opening 141, semiconductor 1 25 has a region that is electrically connected to the conductor WSL, and above the opening 141, semiconductor Body 125 has a region that is electrically connected to the conductor WBL. Also, at the bottom of the opening 141 In this configuration, the conductor 130 overlaps with the conductor RSL via the insulator 129 and semiconductor 127. It has a region. Furthermore, in the region where the conductor RWL and the conductor 130 overlap, semiconductor 1 A conductor 128 is provided between 25 and the insulator 126.

[0076] Between the conductor WWL and the conductor 130, from the conductor WWL side, there is an insulator 124 and a semiconductor 1 25, insulator 126, semiconductor 127, and insulator 129 are provided in that order (see Figure 5A). Between the conductive RWL and the conductor 130, from the conductor RWL side, there is an insulator 124 and a semiconductor 12 5. Conductor 128, insulator 126, semiconductor 127, and insulator 129 are provided in that order. (See Figure 5B).

[0077] The memory element MC has transistors WTr and RTr (see Figure 6). The region where body WWL and conductor 130 overlap functions as a transistor WTr. Conductor WWL L acts as the gate electrode of transistor WTr, and conductor 130 is connected to transistor WTr It functions as the back gate electrode of the transistor WTr. Also, a part of semiconductor 125 is the transistor WTr It functions as a semiconductor layer in which a channel is formed. The semiconductor layer overlaps with the gate electrode (conductor WWL) via a portion of the insulator 124. In this embodiment, for example, a part of the conductive WWL functions as a gate electrode. However, the gate electrode and the conductor WWL are provided independently, and the two are electrically connected. You may do so.

[0078] The region where conductor 128, conductor RWL, and conductor 130 overlap is the transistor RTr. It functions as follows: The conductor RWL acts as the gate electrode of the transistor RTr. Also, The conductor 130 functions as the back gate electrode of the transistor RTr. A portion of it functions as a semiconductor layer where the channel of the transistor RTr is formed. The semiconductor layer in which the channel of staRTr is formed consists of an insulator 126, a conductor 128, and a semiconductor 1 25 and overlap with the gate electrode (conductor RWL) through a portion of the insulator 124 respectively. The semiconductor layer in which the channel of transistor RTr is formed is separated by a portion of the insulator 129. It overlaps with the back gate electrode (conductor 130).

[0079] One of the sources and drains of transistor STr1 is a semicircular interface with transistor WTr. It is electrically connected to conductor 125. The source and drain of transistor STr1 are It electrically connects to the conductor WSL. Also, the source and dray of transistor STr2. One end of the transistor RTr is electrically connected to semiconductor 127. The source and drain of STr2 are electrically connected to the conductor RBL. One of the sources and drains of transistor STr3 is a semicircular interface with transistor WTr. It is electrically connected to conductor 125. The source and drain of transistor STr3 are , electrically connected to the conductor WBL. Here, the conductor SEL is connected to the transistor STr2. It also functions as the gate of transistor STr3 (see Figures 3 and 4). A portion of semiconductor 127 serves as the semiconductor layer in which the channel of transistor STr2 is formed. In this way, a portion of the semiconductor 125 is part of the semiconductor layer in which the channel of transistor STr3 is formed. It functions in this way.

[0080] Let me explain back gates here. Gates and back gates are the components of the semiconductor layer. They are arranged to overlap through the flannel formation region. The back gate functions similarly to a gate. It is possible to change the transistor threshold by changing the potential of the back gate. The value voltage can be changed. Either the gate or the back gate is the "first gate". If one is called the "first gate" and the other is called the "second gate" or "second gate" There is.

[0081] The gate and back gate are formed from a conductive layer or a semiconductor layer with low resistivity, To prevent the electric field generated outside the transistor from acting on the semiconductor layer where the channel is formed. It has the function of (especially the electrostatic shielding function against static electricity). That is, it has the function of ( This prevents the electrical characteristics of a transistor from fluctuating due to the influence of an electric field.

[0082] Furthermore, by controlling the potential of the back gate, the threshold voltage of the transistor can be controlled. This is possible. The potential of the back gate may be the same as the gate potential, or it may be the ground potential (GND). It may be an electric potential or any other electric potential.

[0083] The semiconductor layer in which the channels of transistors WTr and RTr are formed is single-layered. Crystalline semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors, either individually or in combination. They can be used together. Examples of semiconductor materials include silicon and germanium. These can be used. Also, silicon germanium, silicon carbide, gallium arsenide Compound semiconductors such as oxide semiconductors and nitride semiconductors may also be used. Transistor STr 1. The same applies to transistors STr2 and STr3.

[0084] Furthermore, the semiconductor layers used in the transistor may be stacked. When stacking semiconductor layers, Semiconductors having different crystalline states may be used, or different semiconductor materials may be used. It's okay to be there.

[0085] Transistor WTr, Transistor RTr, Transistor STr1, Transistor STr 2. The semiconductor layer used in transistor STr3 is an oxide semiconductor having a metal oxide. It is preferable that it be a conductor. Transistors using metal oxides as semiconductor layers are amorphous Compared to transistors using silicon as the semiconductor layer, a higher field-effect mobility can be obtained. Furthermore, in transistors using polycrystalline silicon as the semiconductor layer, grain boundaries are formed in the semiconductor layer. There is a risk. At grain boundaries, carriers are trapped, leading to a decrease in the transistor's on-current and an electric field. This is highly likely to cause a decrease in effective mobility, etc. On the other hand, as will be explained in more detail later, oxide semiconductors In the body, a crystal structure in which no clear grain boundaries can be observed, or a crystal structure with very few grain boundaries, is observed. This makes it possible to create such structures. Using such oxide semiconductors in the semiconductor layer offers high efficiency. This enables the realization of transistors with good electrical characteristics, such as current and field-effect mobility. Therefore, it is suitable.

[0086] In this embodiment, the oxide semiconductor is In:Ga:Zn=1:3:4 [atomic ratio] or a composition in its vicinity, In:Ga:Zn=4:2:3 [atomic ratio] or a composition in its vicinity , In:Ga:Zn=1:1:1 [atomic ratio] or a composition close to that, or In:Ga An oxide with a composition of Zn = 1:1:0.5 [atomic ratio] or close to it is used.

[0087] Furthermore, in oxide semiconductors, especially crystalline oxide semiconductors such as CAAC-IGZO, Nanoclusters of several nanometers (e.g., 1-3 nm) in size, with the c-axis oriented perpendicular to the surface being formed. —It has a distinctive structure in which the elements are connected to each other. Therefore, even within the opening that extends in the Z direction, This makes it possible to form a crystal structure in which no clear grain boundaries can be identified.

[0088] In particular, the WTr transistor has a semiconductor layer in which the channel is formed that contains a type of metal oxide. It is preferable that it is a transistor using an oxide semiconductor (also called an "OS transistor"). It seems so. Oxide semiconductors have a band gap of 2 eV or more, so the off-current is extremely low. Here, the conductor 128 and either the source or drain of the transistor WTr are electrically connected. The nodes that are directly connected are designated as nodes ND. An OS transistor is used for the transistor WTr. This allows the charge written to node ND to be retained for a long period of time. (This constitutes the memory element MC.) When an OS transistor is used as the transistor, the memory element MC is called "OS memory". It can be done. Also, the memory string 120 including the memory element MC is also called "OS memory". It can be called "OS memory". Also, the storage device 100 can be called "OS memory".

[0089] OS memory can be written to for more than a year, or even more than 10 years, even if the power supply is cut off. It can retain the information it has collected. Therefore, OS memory can be considered non-volatile memory. It's also possible.

[0090] Furthermore, because the amount of charge written to OS memory does not change easily over a long period of time, OS memory is binary ( It can store not only 1-bit information, but also multi-bit information.

[0091] Furthermore, since OS memory uses a method of writing electric charge to nodes via transistors, conventional This eliminates the need for the high voltage required in flash memory, and also enables high-speed writing operations. Furthermore, the erase operation performed before data rewriting in flash memory is performed in OS memory. It is unnecessary. Also, charge injection and extraction to the floating gate or charge trapping layer. Since this does not occur, the OS memory can perform virtually unlimited data write and read operations. Yes, it is possible. OS memory degrades less and is more reliable compared to conventional flash memory. Sex can be obtained.

[0092] Furthermore, the OS memory is either magnetoresistive memory (MRAM) or resistive random-access memory (ReRAM). ) and so on do not involve structural changes at the atomic level. Therefore, OS memory is magnetoresistive It offers superior rewrite endurance compared to Moly and resistive random-access memory.

[0093] Furthermore, OS transistors exhibit almost no increase in off-current even in high-temperature environments. Specifically, The off-current hardly increases even at ambient temperatures between 20°C and 200°C. However, the on-current does not easily decrease. The storage device, including the OS memory, operates even in high-temperature environments. This provides stability and high reliability. Furthermore, OS transistors have an insulating gap between the source and drain. The edge breakdown voltage is high. By using OS transistors in the transistors that make up the semiconductor device, This enables the creation of semiconductor devices that operate stably and reliably even in high-temperature environments.

[0094] Semiconductor 127 is preferably an n-type semiconductor. Also, the conductive WWL of semiconductor 125. The region overlapping with this is preferably an i-type or substantially i-type semiconductor. In this case, the tra WTr is an enhancement-type (normally-off) transistor. RTr is a depletion-type (normally-on) transistor.

[0095] Furthermore, semiconductors 125 and 127 may have the same material or different materials. It is also possible to do so. For example, semiconductor 125 and semiconductor 127 are each oxide semiconductors. This is also acceptable. Furthermore, semiconductors 125 and 127 are semiconductors having silicon. Alternatively, semiconductor 125 may be an oxide semiconductor, and semiconductor 127 may be a silicon semiconductor. It may also be used as a body. Alternatively, semiconductor 125 may be a semiconductor having silicon, and semiconductor 127 may be an acid It may also be a monoxide semiconductor.

[0096] Note that Figure 5A corresponds to the XY plane at or near the center of the transistor WTr, and Figure 5 B corresponds to the XY plane at or near the center of transistor RTr. (See Figure 5A and) In Figure 5B, when the cross-sectional shape of the conductor 130 is circular, the insulator 129 is the conductor 13 It is provided as a concentric layer on the outside of 0, and the semiconductor 127 is concentric on the outside of the insulator 129 The insulator 126 is provided as a layer, and the insulator 126 is provided as a concentric layer on the outside of the semiconductor 127. The semiconductor 125 is provided as a concentric layer on the outside of the insulator 126, and the insulator 124 is semi It is provided as a concentric layer on the outside of the conductor 125. Also, the conductor 128 is an insulator. It is provided as a concentric layer between 126 and semiconductor 125.

[0097] Furthermore, the cross-sectional shape of the conductor 130 is not limited to a circle. As shown in Figure 7A, the cross-sectional shape of the conductor 130 is The cross-sectional shape may be rectangular. Also, as shown in Figure 7B, the cross-sectional shape of the conductor 130 is triangular. But that's fine.

[0098] Furthermore, as described above, at the bottom of the memory string 120, the semiconductor 125 is a conductive WSL. An example was shown in which semiconductor 127 is electrically connected to conductor RSL, but in this implementation The form is not limited to this.

[0099] As shown in Figure 8, two memory strings adjacent to each other in the Y-axis direction are electrically connected, and one This can be made into memory string 120A. In memory string 120A, Listing 120_1 and memory string 120_2 are connected to conductor 119 and conductor It is electrically connected by 122.

[0100] At the top of memory string 120_1, semiconductor 125 and conductor WSL are electrically connected. The semiconductor 127 and the conductor RSL are electrically connected. Also, the memory string 120_2 At the top, semiconductor 125 and conductor WBL are electrically connected, and semiconductor 127 and conductor RB L is electrically connected. Also, memory string 120_1 and memory string 1 In the lower part of 20_2, each semiconductor 125 is electrically connected via the conductor 119. Each semiconductor 127 is electrically connected via the conductor 122.

[0101] Memory string 120A is connected from the conductor WSL and conductor RSL side to the conductor WBL , and toward the conductor RBL side, memory elements MC[1] to MC

[10] are provided In addition, memory elements MC[5] and MC[6] are connected to the conductor 119, They are electrically connected via the conductor 122.

[0102] Furthermore, the memory string 120 can also be called a memory device, and the memory element MC can be called a memory device. can also be referred to as an apparatus.

[0103] [Constituent Materials of Semiconductor Device] Next, constituent materials that can be used for the memory device 100 will be described.

[0104] [Substrate] The memory device 100 is provided over a base 121. As a substrate that can be used as the base 121 , for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. As the insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), a resin substrate, or the like is given. Further, as the semiconductor substrate , for example, a semiconductor substrate formed using silicon or germanium as a material, or silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide is given. Furthermore, a semiconductor substrate having an insulator region inside the above-described semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate or the like is given. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like is given. Alternatively, a substrate including a metal nitride, a substrate including a metal oxide, or the like is given. Furthermore , a substrate in which a conductor or a semiconductor is provided over an insulator substrate, a substrate in which a conductor or an insulator is provided over a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided over a conductor substrate, or the like is given. Alternatively , a substrate in which an element is provided over any of these substrates may be used. As an element provided over the substrate , a capacitive element, a resistive element, a switch element, a light-emitting element, a memory element, or the like is given.

[0105] [Insulator] As the insulator, an oxide, nitride, oxynitride, nitride oxide, or metal oxide having insulating properties Examples include metal oxides and nitrides, and metal nitride oxides.

[0106] In this specification, "oxiditride" refers to a compound whose main component is oxygen rather than nitrogen. It refers to materials with a high oxygen content. For example, "silicon oxidnitride" is a material with a higher oxygen content than nitrogen. This refers to a material containing silicon, nitrogen, and oxygen. Furthermore, in this specification, "nitriding acid" is also used. A "nitride" refers to a material in which nitrogen has a higher nitrogen content than oxygen as its main component. For example, "nitriding acid" "Aluminium oxide" is a compound containing more nitrogen than oxygen, consisting of aluminum, nitrogen, and oxygen. This shows materials that include [the specified element].

[0107] For example, as transistors become smaller and more integrated, the gate insulator becomes thinner. Problems such as leakage current may occur in the insulator that functions as a gate insulator. By using igh-k material, the physical film thickness can be maintained while lowering the voltage during transistor operation. This becomes possible. On the other hand, the insulator that functions as an interlayer film uses a material with a low dielectric constant. Therefore, parasitic capacitance between wires can be reduced. Thus, depending on the function of the insulator... Then, you should select the materials.

[0108] Furthermore, insulators with high dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. Aluminium, an oxide containing aluminum and hafnium, an oxide containing aluminum and hafnium Oxidized nitrides, silicon and hafnium oxides, silicon and hafnium Examples include oxide nitrides having [a certain characteristic], or nitrides having silicon and hafnium.

[0109] Furthermore, insulators with low dielectric constants include silicon oxide, silicon oxide nitride, and silicon oxide nitride. Cone, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, carbon Silicon oxide with added elements and nitrogen, porous silicon oxide, or resins, etc. ru.

[0110] Furthermore, OS transistors have the function of suppressing the permeation of impurities such as hydrogen and oxygen. By surrounding it with an insulator, the electrical characteristics of the transistor can be stabilized. Examples of insulators that have the function of suppressing the permeation of impurities and oxygen include boron, Carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, aluminum Gon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, ha An insulator containing phenium or tantalum may be used in a single layer or in a multilayer configuration. It includes an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, such as a(V) oxide. Aluminum, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, Zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. Metal nitrides such as metal oxides, aluminum nitride, silicon nitride, and silicon nitride are used. It is possible to be there.

[0111] Furthermore, when an oxide semiconductor is used for semiconductor 125 and / or semiconductor 127, gate insulation An insulator that functions as a border is an insulator that has a region containing oxygen that is released by heating. Preferably, silicon oxide having a region containing oxygen that is desorbed by heating or This involves a structure in which silicon oxide nitride is in contact with semiconductor 125 and / or semiconductor 127. This allows for compensation of oxygen deficiencies in semiconductor 125 and / or semiconductor 127. .

[0112] [Conductor] Examples of the conductor include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, tita nium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesi um, zirconium, beryllium, indium, ruthenium, iridium, stronti um, a metal element selected from lanthanum and the like, or an alloy containing the above-mentioned metal elements as a component, or it is preferable to use an alloy or the like in which the above-mentioned metal elements are combined. For example, tantalum nitride , titanium nitride, tungsten, a nitride containing titanium and aluminum, tantalum and alumi num-containing nitride, ruthenium oxide, ruthenium nitride, strontium and ruthenium-containi ng oxide, an oxide containing lanthanum and nickel, or the like is preferably used. In addition, tanta lum nitride, titanium nitride, a nitride containing titanium and aluminum, tantalum and aluminum-containi ng nitride, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium , the oxide containing lanthanum and nickel is preferable because it is a conductive material that is less likely to be oxidized, or a material that maintains conductivity even when absorbing oxy gen. In addition, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, a silicide such as nickel silici de may be used.

[0113] In addition, a plurality of conductive layers formed of the above materials may be stacked and used. For example, a laminated structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined may be employed. In addition, a laminated structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. In addition, the above-described material containing a metal element, the conductive material containing oxygen, and nitrogen ​​​ A laminated structure may be formed by combining a conductive material containing with .

[0114] Furthermore, an oxide semiconductor, a type of metal oxide, is used in the channel formation region of the transistor. In this case, the conductor functioning as a gate electrode contains a material containing the aforementioned metal element, It is preferable to use a laminated structure that combines an oxygen-containing conductive material with [another material]. In this case, It is preferable to provide an oxygen-containing conductive material on the channel formation region side. By providing it on the channel-forming region side, oxygen released from the conductive material can be channeled into the channel-forming region It will become easier to supply to the region.

[0115] In particular, as a conductor that functions as a gate electrode, it is included in the oxide semiconductor in which the channel is formed. It is preferable to use a conductive material containing a metallic element and oxygen. Conductive materials containing metallic elements and nitrogen may be used. For example, titanium nitride, tantalum nitride. Conductive materials containing nitrogen, such as tungsten, may also be used. In addition, indium tin oxide and tungsten oxide may be used. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, and tungsten oxide. Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium zinc oxide Indium tin oxide with added silicon may also be used. Um gallium zinc oxide may also be used. By using such a material, the channel shape In some cases, hydrogen contained in the oxide semiconductor being formed can be captured. Alternatively, outward In some cases, it is possible to capture hydrogen that has entered from insulators and other materials.

[0116] [Oxide Semiconductors] As semiconductors 125 and 127, metal oxides (oxide semiconductors) that function as semiconductors. It is preferable to use a body. Below, the following applies to semiconductor 125 and semiconductor 127. Let's discuss oxide semiconductors.

[0117] The oxide semiconductor preferably contains at least indium or zinc. In particular, indium Preferably, it contains aluminum and zinc. In addition, aluminum and gallium It is preferable that it contains yttrium, tin, etc. Also, boron, titanium, iron, nitrile Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Ha One of the following materials is selected from tungsten, tantalum, magnesium, cobalt, etc. It may include multiple species.

[0118] Here, the oxide semiconductor is an In-M-Zn oxide having indium, element M, and zinc. Let's consider the case where it's a physical object. Note that element M is aluminum, gallium, yttrium, or tin. , one or more types selected from titanium, etc. Other elements M applicable The elements are boron, iron, nickel, germanium, zirconium, molybdenum, and lanthanum. N, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt Examples include [examples]. However, in some cases, it is acceptable to combine multiple of the aforementioned elements as element M. be.

[0119] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxi They are sometimes collectively referred to as (de) metal oxides (met It may also be called al oxynitride.

[0120] [Classification of crystal structures] First, we will explain the classification of crystal structures in oxide semiconductors using Figure 9A. 9A is an oxide semiconductor, typically IGZO (containing metal oxides such as In, Ga, and Zn). This is a diagram illustrating the classification of crystal structures of substances.

[0121] As shown in Figure 9A, oxide semiconductors can be broadly classified as "Amorphous". They are classified into "Crystalline" and "Crystal". It is done. Also, within "Amorphous," there are completely amorph It includes ous. Also, within "Crystalline" there is CAAC(c-axi s-aligned crystalline), nc(nanocrystalline) e) and CAC (cloud-aligned composite) are included (e xcluding single crystal and poly crystal ). Note that the classification of "Crystalline" includes single crystal, p Polycrystalline and completely amorphous crystals are excluded. Furthermore, within "Crystal," there are single crystals and poly crystals. It includes rystal.

[0122] The structures within the thick border shown in Figure 9A are "Amorphous" and "Crystal It is an intermediate state between "tal (crystal)" and a new boundary region (New crystall This structure belongs to the ine phase. In other words, this structure is energetically unstable. It is completely different from the definite "Amorphous" or "Crystal." This can be rephrased as structure.

[0123] The crystal structure of the film or substrate is determined by X-ray diffraction (XRD). It can be evaluated using the (on) spectrum. Here, "Crystalline" GIXD (Grazing-Incidence) of CAAC-IGZO film, which is classified as such. The XRD spectrum obtained by the XRD measurement is shown in Figure 9B. Note that the GIXD method is a thin-film method. It is also called the Seemann-Bohlin method. Hereafter, the results obtained by GIXD measurement shown in Figure 9B The obtained XRD spectrum will simply be referred to as the XRD spectrum. Note that the CAAC shown in Figure 9B - The composition of the IGZO film is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 9B is 500 nm.

[0124] As shown in Figure 9B, the XRD spectrum of the CAAC-IGZO film clearly shows crystallinity. A peak is detected. Specifically, in the XRD spectrum of the CAAC-IGZO film, 2 A peak indicating c-axis orientation is detected near θ=31°. Note that, as shown in Figure 9B, 2 The peaks near θ=31° are asymmetrical with respect to the angle at which the peak intensity was detected.

[0125] Furthermore, the crystal structure of the film or substrate is determined by nano-beam diffraction (NBED). Diffraction patterns observed by electron diffraction (extremely low-voltage electrons) This can be evaluated using the sub-ray diffraction pattern (also called the sub-ray diffraction pattern). Diffraction of CAAC-IGZO film The pattern is shown in Figure 9C. Figure 9C shows an NBED with an electron beam incident parallel to the substrate. This is the diffraction pattern that is observed. Note that the composition of the CAAC-IGZO film shown in Figure 9C is also shown. The ratio is approximately In:Ga:Zn=4:2:3 [atomic ratio]. Furthermore, by micro-electron diffraction... Electron diffraction is performed with a probe diameter of 1 nm.

[0126] As shown in Figure 9C, the diffraction pattern of the CAAC-IGZO film shows multiple c-axis orientations. Spots are observed.

[0127] [Structure of oxide semiconductors] Note that oxide semiconductors may be classified differently from those shown in Figure 9A when considering their crystal structure. For example, oxide semiconductors include single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. They can be divided into and . Non-single-crystal oxide semiconductors include, for example, the aforementioned CAAC-OS, and There is also nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors and pseudo-amorphous materials. Amorphous-like oxide semiconductor (a-like OS) This includes semiconductors, amorphous oxide semiconductors, and so on.

[0128] Next, we will discuss the details of the aforementioned CAAC-OS, nc-OS, and a-like OS. Give an explanation.

[0129] [CAAC-OS] CAAC-OS has multiple crystalline regions, and these multiple crystalline regions are arranged with their c-axis in a specific direction. It is an oxide semiconductor that is oriented in a particular direction. Note that the specific direction refers to the thickness direction of the CAAC-OS film. The direction normal to the surface on which the CAAC-OS film is formed, or the direction normal to the surface of the CAAC-OS film. Furthermore, a crystalline region is a region in which the atomic arrangement has periodicity. If considered as an arrangement, a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-O S has a region in the ab-plane direction where multiple crystalline regions are connected, and this region is strained. This can sometimes occur. Note that strain refers to the deformation of the lattice arrangement in a region where multiple crystal regions are connected. Areas where the orientation of the grid arrangement changes between aligned regions and aligned regions with a different grid arrangement. This refers to the fact that CAAC-OS is c-axis oriented and has a clear orientation in the ab-plane direction. It is an oxide semiconductor that does not exist.

[0130] Each of the above multiple crystalline regions is composed of one or more minute crystals (with a maximum diameter of 10n It is composed of crystals that are less than m in size. If the crystalline region is composed of one minute crystal, The maximum diameter of the crystalline region is less than 10 nm. Furthermore, the crystalline region is composed of numerous tiny crystals. If this is the case, the size of the crystalline region may be around several tens of nanometers.

[0131] Furthermore, in In-M-Zn oxide, CAAC-OS contains indium (In) and acid A layer containing an element (hereinafter referred to as the In layer), and a layer containing the element M, zinc (Zn), and oxygen (hereinafter referred to as the In layer). It tends to have a layered crystalline structure (also called a layered structure) in which (M,Zn) layers are stacked. Furthermore, indium and element M are mutually substitutable. Therefore, the (M,Zn) layer contains It may contain indium. Also, the In layer may contain element M. The In layer may also contain Zn. This layered structure can be seen, for example, in high-resolution TEM images. In this context, it is observed as a grid image.

[0132] When structural analysis of a CAAC-OS film is performed using, for example, an XRD instrument, the θ / 2θ skid is observed. Out-of-plane XRD measurements using a champ showed a peak indicating c-axis orientation at 2θ. It is detected at 31° or near that angle. Note that the position of the peak indicating c-axis orientation (value of 2θ) This may vary depending on the type and composition of the metal elements that make up CAAC-OS.

[0133] Furthermore, for example, in the electron diffraction pattern of a CAAC-OS film, multiple bright spots (spots) may be observed. ) is observed. Note that one spot and another spot are determined by the incident electron beam that has passed through the sample. Observations are made at point-symmetric positions with respect to the spot (also called a direct spot) as the center of symmetry. ru.

[0134] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is a hexagonal lattice. While this is the basic principle, the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, In the distortion described, there may be grid arrangements such as pentagons and heptagons. Note that CAAC- In OS, clear grain boundaries can be observed even near strain. It is not possible. In other words, the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This can be seen. This is because CAAC-OS has a dense arrangement of oxygen atoms in the ab-plane direction. Due to the absence of certain elements, or because the substitution of metal atoms changes the bond distance between atoms, This is thought to be because it allows for distortion to be tolerated.

[0135] Furthermore, a crystal structure in which clear grain boundaries can be observed is known as polycrystalline. It is called l). The grain boundaries become recombination centers, where carriers are trapped and the transistor is formed This is highly likely to cause a decrease in current, a decrease in field-effect mobility, etc. Therefore, a clear conclusion is reached. CAAC-OS, which lacks visible grain boundaries, has a crystal structure suitable for the semiconductor layer of transistors. It is one of the crystalline oxides. Note that CAAC-OS requires the presence of Zn. The configuration is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are In oxide It is preferable because it can suppress the generation of grain boundaries more effectively than other materials.

[0136] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less prone to a decrease in electron mobility caused by grain boundaries. Furthermore, the crystallinity of oxide semiconductors can decrease due to impurities or the formation of defects. Therefore, CAAC-OS is also an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Yes, that's correct. Therefore, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are highly heat-resistant and reliable. -OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors expands the degree of freedom in the manufacturing process. This becomes possible.

[0137] [nc-OS] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially between 1 nm and 3 nm). It has periodicity in the atomic arrangement in the region of less than nm. In other words, nc-OS is minute It has crystals. The size of these minute crystals is, for example, between 1 nm and 10 nm. In particular, because they are between 1 nm and 3 nm in size, these minute crystals are also called nanocrystals. In nc-OS, no regularity is observed in the crystal orientation between different nanocrystals. Therefore, across the entire film... No orientation is observed. Therefore, nc-OS is a-like depending on the analytical method. It can sometimes be indistinguishable from OS or amorphous oxide semiconductors. For example, with respect to an nc-OS film, When performing structural analysis using an XRD device, out-of-pla scans using θ / 2θ scans are performed. In ne XRD measurements, no peak indicating crystallinity is detected. Furthermore, compared to nc-OS films... Electron diffraction using electron beams with probe diameters larger than nanocrystals (e.g., 50 nm or larger). When electron diffraction (also called limited-field diffraction) is performed, a diffraction pattern resembling a halo pattern can be observed. It is measured. On the other hand, for the nc-OS film, the size is close to or smaller than that of the nanocrystals. Electron diffraction (nanobeam electron diffraction) using an electron beam with a lobe diameter (e.g., 1 nm to 30 nm) Also called sub-ray diffraction, when this is performed, multiple particles are found within a ring-shaped region centered on the direct spot. In some cases, electron diffraction patterns with multiple spots observed may be obtained.

[0138] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, it has a-like properties. OS has a higher hydrogen concentration in the membrane compared to nc-OS and CAAC-OS.

[0139] [Oxide semiconductor configuration] Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS is a material composition. Regarding.

[0140] [CAC-OS] CAC-OS refers to, for example, metal oxides in which the elements constituting the metal oxide are between 0.5 nm and 10 nm in size. Preferably, a composition of material that is unevenly distributed with a size of 1 nm to 3 nm or near that size. In addition, in the following, in a metal oxide, one or more metal elements are unevenly distributed, The region containing the metallic element is 0.5 nm to 10 nm, preferably 1 nm to 3 nm. The following state, where particles of similar or near-similar size are mixed, is also referred to as a mosaic or patchy appearance.

[0141] Furthermore, CAC-OS is a system where the material separates into a first region and a second region, resulting in a mosaic effect. This results in a cloud-like structure, where the first region is distributed within the membrane (hereinafter also referred to as a cloud-like structure). Therefore, CAC-OS is a mixture of the first region and the second region. It is a composite metal oxide having the following configuration.

[0142] Here, In for the metal elements constituting CAC-OS in In-Ga-Zn oxide The atomic ratios of Ga and Zn are expressed as [In], [Ga], and [Zn] respectively. To note, for example, in CAC-OS in In-Ga-Zn oxide, the first region is This is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Yes. Or, for example, in the first region, [In] is greater than [In] in the second region. This is a region where the [Ga] is large and smaller than the [Ga] in the second region. In the second region, [Ga] is greater than [Ga] in the first region, and [In This is a region smaller than [In] in the first region.

[0143] Specifically, the first region mentioned above is mainly composed of indium oxide, indium zinc oxide, etc. This is the region. Furthermore, the second region mentioned above includes gallium oxide, gallium zinc oxide, etc. This is the region in which is the principal component. In other words, the first region described above is called the region in which In is the principal component. It can be replaced. Furthermore, the second region mentioned above can be rephrased as the region with Ga as the main component. It is possible.

[0144] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0145] For example, in CAC-OS in In-Ga-Zn oxide, energy-dispersive X-ray spectroscopy is used. Law(EDX:Energy Dispersive X-ray spectrosco The EDX mapping obtained using py) shows the region with In as the main component (the first region) It has a structure in which a region mainly composed of ) and a region mainly composed of Ga (the second region) are unevenly distributed and mixed. This can be confirmed.

[0146] When CAC-OS is used in a transistor, the conductivity is due to the first region and the second region The insulating properties resulting from this work in a complementary manner to enable the switching function (On / The function to turn it off can be added to CAC-OS. In other words, CAC-OS is In part of the material, it has conductive properties, and in part of the material, it has insulating properties, and the whole material It has the function of a semiconductor. By separating the conductive function and the insulating function, dual This allows for maximizing the functionality of the transistor. Therefore, CAC-OS is used in transistors. As a result, high on-current (I on ), high field-effect mobility (μ), and good switching This enables the implementation of a specific action.

[0147] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention The oxide semiconductor may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, and CA C-OS, nc-OS, and CAAC-OS.

[0148] 〔Transistor Including Oxide Semiconductor〕 Next, the case where the above oxide semiconductor is used for a transistor will be described.

[0149] By using the above oxide semiconductor for a transistor, a transistor with high field-effect mobility can be achieved. In addition, a highly reliable transistor can be achieved.

[0150] An oxide semiconductor with a low carrier concentration is preferably used for a channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is preferably 1×10 18 c m -3 or less, more preferably lower than 1×10 17 cm -3 , still more preferably lower than 1×10 16 cm -3 , still more preferably lower than 1×10 13 cm -3 , still more preferably lower than 1×10 , still more preferably lower than 1×10 12 cm -3 . Note that in the case where the carrier concentration of the oxide semiconductor film is lowered, the impurity concentration in the oxide semiconductor film is reduced to lower the density of defect states. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as highly purified intrinsic or substantially highly purified intrinsic. The oxide semiconductor with a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Moreover, a highly purified intrinsic or substantially highly purified intrinsic state is sometimes referred to as i-type or substantially ​​​It is sometimes referred to as type i.

[0151] Furthermore, oxide semiconductor films that are high-purity intrinsic or substantially high-purity intrinsic have a low defect level density. Therefore, the trap level density may also be low.

[0152] Furthermore, the time required for charges trapped in the trap levels of oxide semiconductors to disappear is long. Furthermore, it can behave as if it were a fixed charge. Therefore, it can behave as if it were a fixed charge. Transistors in which a channel formation region is formed in an oxide semiconductor exhibit unstable electrical properties. There are cases where this is the case.

[0153] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the oxide semiconductor must be Reducing it is effective. Also, in order to reduce the impurity concentration in oxide semiconductors, It is also preferable to reduce the concentration of impurities in the contacting film. Examples of impurities include hydrogen, nitrogen, and aluminum. Examples include potash metals, alkaline earth metals, iron, nickel, and silicon.

[0154] 〔impurities〕 Here, we will explain the effects of various impurities in oxide semiconductors.

[0155] In oxide semiconductors, if silicon or carbon, which are among the Group 14 elements, are present, the oxide Defect levels are formed in semiconductors. Therefore, in the channel formation region of oxide semiconductors... The concentration of silicon and carbon, and the silicon near the interface with the channel formation region of the oxide semiconductor. or carbon concentration (Secondary Ion Mass Spectrometry (SIMS) The concentration obtained by spectrometry is 2 × 10 18 ate / c m 3 The following is preferably 2 × 10 17atoms / cm 3 The following applies:

[0156] Furthermore, if alkali metals or alkaline earth metals are present in the oxide semiconductor, defect levels are formed. And, it may generate carriers. Therefore, alkali metals or alkaline earth metals are included. Transistors using oxide semiconductors tend to exhibit normally-on characteristics. Therefore, alkali metals or alkali metals in the channel formation region of oxide semiconductors obtained by SIMS. The concentration of potassium earth metals is 1 × 10⁻⁶ 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0157] Furthermore, in oxide semiconductors, when nitrogen is present, electrons, which are carriers, are generated. The concentration increases, making it easier to convert to n-type. As a result, oxide semiconductors containing nitrogen become semiconductors. The transistor used tends to exhibit normally-on characteristics. Alternatively, in oxide semiconductors... If nitrogen is present, a trap level may be formed. As a result, the transistor Electrical properties may become unstable. For this reason, oxide semiconductors obtained by SIMS The nitrogen concentration in the channel formation region is 5 × 10 19 atoms / cm 3 Less than 5 ×10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 Below Below, more preferably 5 × 10 17 atoms / cm 3 Do the following:

[0158] Furthermore, the hydrogen contained in oxide semiconductors reacts with the oxygen bonded to the metal atoms to form water. This can sometimes form an oxygen vacancy. When hydrogen enters this oxygen vacancy, the electrons, which are carriers, In some cases, this can be generated. Also, some of the hydrogen combines with oxygen that is bonded to a metal atom, resulting in a It can generate electrons, which are rear electrons. Therefore, using an oxide semiconductor containing hydrogen... Transistors tend to exhibit normally-on characteristics. Therefore, the channel of oxide semiconductors It is preferable that the amount of hydrogen in the formation region is reduced as much as possible. Specifically, acid In the channel formation region of a ionized semiconductor, the hydrogen concentration obtained by SIMS is 1 × 10⁻⁶. 20 atoms / cm 3 Less than 5 × 10 19 atoms / cm 3 Less than, better Mashiku is 1 x 10 19 atoms / cm 3 Less than 5 × 10 18 Atom s / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0159] Using oxide semiconductors with sufficiently reduced impurities in the channel formation region of transistors. This allows for the provision of stable electrical characteristics.

[0160] [Other semiconductor materials] The semiconductor materials that can be used for semiconductors 125 and 127 are the oxide semiconductors described above. It is not limited to the body. Semiconductors 125 and 127 are semiconductors having a band gap. Body materials (semiconductor materials other than zero-gap semiconductors) may also be used. For example, silicon Semiconductors of any element, compound semiconductors such as gallium arsenide, and layered materials that function as semiconductors. Materials such as atomic layer materials, two-dimensional materials, etc., may also be used as semiconductor materials. In particular, It is preferable to use a layered material that functions as a semiconductor as a semiconductor material.

[0161] In this specification, the term "layered material" refers to a general term for a group of materials having a layered crystalline structure. The crystal structure consists of layers formed by covalent and ionic bonds, and van der Waals forces It is a layered structure in which layers are formed by bonds weaker than covalent or ionic bonds. The quality is high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions in this way and has high two-dimensional electrical conductivity in the channel formation region, It is possible to provide transistors with high current.

[0162] Layered materials include graphene, silicene, and chalcogenides. It is a compound containing chalcogens. Furthermore, chalcogens are a general term for elements belonging to Group 16. It contains oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of cogenides include transition metal chalcogenides and group 13 chalcogenides.

[0163] As semiconductors 125 and 127, for example, transition metal chalcoids that function as semiconductors. It is preferable to use a genide. Applicable transitions as semiconductor 125 and semiconductor 127 Specifically, examples of transfer metal chalcogenides include molybdenum sulfide (typically MoS2), and Molybdenum renide (typically MoSe2), molybdenum telluride (typically MoTe2) ), tungsten sulfide (typically WS2), tungsten selenide (typically WSe 2) Tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS 2) Hafnium selenide (typically HfSe2), zirconium sulfide (typically Z Examples include rS2 and zirconium selenide (typically ZrSe2).

[0164] <Example of a method for manufacturing a storage device> Next, an example of a method for manufacturing a storage device according to the present invention will be described with reference to Figures 10A to 31C. In Figures 10A to 31C, A is a top view seen from the Z direction, and B is A is a cross-section of the area shown by the dashed line A1-A2. Also, C is a cross-section of A3-A4. This is a cross-sectional view of the area indicated by the dashed line. Note that in this manufacturing method, there are two sections (also called "two stages"). This example shows how to fabricate two memory strings 120 having memory elements MC of ) but in this implementation The form is not limited to this. The memory string 120 has three or more memory elements MC. It is also possible that the memory string 120 has 32 or more rows, preferably 64 or more rows. Preferably, the memory element MC has 128 or more rows, and more preferably 256 or more rows. It is preferable.

[0165] First, a conductor 122 is formed on a substrate 121 having an insulating surface, and around the conductor 122, An insulator 132 is formed (see Figures 10A to 10C).

[0166] Specifically, a conductive film is formed, and the conductive film is processed using a lithography method to create a conductor 12 Form 2. Next, an insulating film is formed on the substrate 121 so as to cover the conductor 122. It is preferable to perform a planarization treatment on the insulating film. In this planarization treatment, the conductor 122 It is preferable to polish the insulating film until the surface is exposed. By the above method, the insulator 13 2 can be formed. However, the method of forming the conductor 122 and the insulator 132 is This is not limited to that. An insulator 132 is formed on the substrate 121, and the unnecessary portion of the insulator 132 is removed. By doing so, grooves and openings are formed, and the conductive material 122 is embedded in the grooves and openings. This is also acceptable. A method for forming such a conductor is the damascene method (single damascene method, dual damascene method). This method is sometimes referred to as the machine method. The structure shown in Figures 10A to 10C is obtained using the above method. It is possible.

[0167] The formation of conductors 122 and insulators 132 is done by sputtering, CVD, molecular beam epitaxy, etc. SIE (MBE: Molecular Beam Epitaxy), pulsed laser deposition (PLD: Pulsed Laser Deposition) method or ALD (Ato This can be done using methods such as the mic Layer Deposition (MIC) method.

[0168] Furthermore, the CVD method is a plasma CVD (PECVD) method that utilizes plasma. Processed CVD (CVD), thermal CVD (TCVD) which utilizes heat. Method D) can be classified into methods such as photoCVD (Photo-CVD), which utilizes light. Depending on the source gas, the process can be performed using metal CVD (MCVD) or organometallic CVD. It can be divided into MOCVD (Metal Organic CVD) methods.

[0169] Plasma CVD can produce high-quality films at relatively low temperatures. Thermal CVD, on the other hand, uses plasma This film deposition method does not use plasma, thus minimizing plasma damage to the workpiece. Yes, for example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) included in semiconductor devices. These can sometimes be charged up by receiving an electric charge from the plasma. In some cases, the accumulated electric charge can damage the wiring, electrodes, and components contained in semiconductor devices. Yes, it does. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage occurs. Therefore, the yield of semiconductor devices can be increased. In addition, with the thermal CVD method, film deposition is possible. Because no plasma damage occurs inside, a film with fewer defects can be obtained.

[0170] The ALD method includes thermal ALD, which carries out the reaction between the precursor and reactant using only thermal energy. Thermal ALD method, PEALD (P) using plasma-excited reactant Examples include the lasma-enhanced ALD method.

[0171] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer. This allows for the deposition of extremely thin films, films on structures with high aspect ratios, and pinholes. It enables film formation with fewer defects, excellent coverage, and low-temperature film formation, etc. This has the effect of enabling film deposition at lower temperatures by utilizing plasma in the PEALD method. This can be preferable in some cases.

[0172] CVD and ALD are film deposition methods in which particles emitted from a target or other source are deposited. In contrast, this is a film formation method in which a film is formed by a reaction on the surface of the object being treated. This film formation method is less affected by the shape of the workpiece and has good step-level coverage. The ALD method has excellent step coverage and excellent thickness uniformity, so the aspect ratio It is suitable for coating surfaces with high apertures. However, the ALD method has a relatively slow film deposition rate. Because the deposition rate is slow, it is not suitable for use in combination with other film deposition methods that have a high deposition rate, such as CVD. It can be preferable in some cases.

[0173] The CVD method allows for control over the composition of the resulting film by adjusting the flow rate ratio of the source gas. Example For example, in the CVD method, films of any composition can be formed by changing the flow rate ratio of the raw material gas. Furthermore, for example, in the CVD method, the flow rate ratio of the raw material gas is changed while the film is being deposited. This allows for the formation of films with continuously changing compositions. By changing the flow rate ratio of the raw material gases... When depositing films while simultaneously depositing them, the process of transporting and adjusting pressure is more time-consuming compared to depositing films using multiple deposition chambers. By eliminating the time required for processing, the time required for film deposition can be shortened. Therefore, the production time of semiconductor devices It can sometimes increase productivity.

[0174] Furthermore, the ALD method involves simultaneously introducing multiple precursors of different compositions, or different By controlling the number of cycles for each precursor, multiple precursors of different compositions can be used to create films of any desired composition. It can be used to form a thin film.

[0175] In lithography, the resist is first exposed through a photomask. Next, The exposed areas are removed or left intact using a developer to form a resist mask. By etching through the resist mask, a conductor, semiconductor, or insulator is obtained. These can be processed into desired shapes. For example, KrF excimer laser light, ArF excimer laser light Using kiserum laser light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the resist. Also, the substrate and the projection lens and An immersion technique may be used, in which a liquid (e.g., water) is filled between the elements and exposed. Alternatively, the aforementioned method may be used. Instead of light, electron beams or ion beams may be used. When using a photomask, a photomask is not required. Note that to remove the resist mask, Dry etching, wet etching, and dry etching processes such as shading. A process combining this with wet etching can be used. When using a process that combines processing and wet etching, dry etching process You may perform a wet etching process afterward, or a dry etching process after the wet etching process. Ching treatment may be performed.

[0176] Alternatively, a hard mask made of an insulator or conductor may be used instead of a resist mask. When using a hard mask, an insulating film or conductive film that will serve as the hard mask material is formed on the conductive film. Then, a resist mask is formed on top of it, and the hard mask material is etched to create the desired shape. A hard mask can be formed in a specific shape.

[0177] The above processing can be performed using either a dry etching method or a wet etching method. Etching is suitable for microfabrication.

[0178] As a dry etching apparatus, a capacitively coupled plasma (CCP) system with parallel plate electrodes is used. Using a capacitively coupled plasma etching apparatus This is possible. A capacitively coupled plasma etching apparatus having parallel plate electrodes is a parallel plate type Alternatively, a configuration in which a high-frequency power supply is applied to one of the electrodes may be used. Alternatively, a configuration in which multiple different high-frequency power supplies are applied to the electrodes may be used. Alternatively, a configuration in which a high-frequency power supply of the same frequency is applied to each of the parallel plate electrodes. A configuration in which high-frequency power supplies of different frequencies are applied may also be used. Alternatively, a system with a high-density plasma source may be used. A dry etching apparatus can be used. Dry etching with a high-density plasma source. The device, for example, uses inductively coupled plasma (ICP). Plasma etching equipment and the like can be used.

[0179] When a hard mask is used for etching a conductive film, the etching process is performed using a hard mask. You can either remove the resist mask used for formation before proceeding, or leave the resist mask in place. You can proceed as is. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the above conductive film. If the material for the mask does not affect subsequent processes, or can be used in subsequent processes, then it is not necessarily necessary to use a mask. There is no need to remove the code mask.

[0180] The conductive film that will become the conductor 122 is formed by sputtering, and the conductive film containing metal elements is created using the sputtering method. It is preferable to do so. Alternatively, it can be formed using the CVD method.

[0181] The surface of the insulator 132 is preferably planarized as needed. Chemical treatment can be performed using chemical mechanical polishing (CMP) or reflow methods.

[0182] An insulator 118 is formed on the conductor 122 and the insulator 132. The insulator 118 is an insulating material. A material that can be used for body 132 and a method that can be used for forming the insulator 132. It can be formed using this method.

[0183] Conductors 119 and 117 are formed on the insulator 118 (Figures 10A to 10C). See reference.) Conductor 119 and insulator 117 are conductor 122 and insulator respectively. A material that can be used in 132, and is used in the formation of the conductor 122 and the insulator 132. It can be formed using a method that allows for this.

[0184] Insulating film 123A, conductive film 134A, and conductive film are applied to the conductor 119 and the insulator 117. 136A is stacked alternately. In this embodiment, on the conductive 119 and the insulator 117 An insulating film 123A is formed, and a conductive film 134A is formed on the insulating film 123A. This example shows how to form an insulating film 123A on top and a conductive film 136A on top of the insulating film 123A. See Figures 10A to 10C. Conductive film 134A, conductive film 136A, and insulating film 123 CVD can be used to form A. Alternatively, sputtering may be used. .

[0185] As conductor 122, conductor 119, conductive film 134A, and conductive film 136A, impurities are Conductive materials such as added silicon or metals can be used. Conductor 1 36 selectively etches the conductor 119 and the conductor 134 in a subsequent process. Because it is necessary to perform a test, the conductive film 136A is made of conductor 122, conductor 119, and conductive It is preferable that the material is different from that of film 134A. On the other hand, conductor 122, conductor 119, The conductive film 134A may be made of the same material or different materials. Conductor 12 2. Conductor 119, conductive film 134A, or conductive film 136A to which impurities are added. When using silicon, amorphous silicon or polysilicon can be used. Furthermore, p-type and n-type impurities can be used as impurities added to silicon. Furthermore, as conductive materials containing silicon, titanium, cobalt, or nickel are also used. The rectide can be used as a conductor 122, a conductive film 134A, or a conductive film 136A. Also, metal materials can be used for the conductor 122, the conductive film 134A, or the conductive film 136A. In some cases, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum Den, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium Contains one or more metallic elements selected from conium, beryllium, indium, ruthenium, etc. Materials can be used.

[0186] Alternatively, one of the conductive films 134A and 136A may be used as a dummy layer. These are the conductor 122, the insulator 118, the conductor 119, the insulator 123, and the conductive film 134A. A material that can selectively etch the other of the conductive film 136A is preferred, for example, Silicon nitride or silicon nitride oxide can be used. In a subsequent process, a dummy layer is By removing the dummy layer and forming a conductor in the area where the dummy layer was removed, the conductor 134 and the conductive One of the bodies 136 can be formed.

[0187] Insulator 132, insulator 118, insulator 117, and insulating film 123A have insulating properties. Oxides, nitrides, oxide nitrides, oxides, metal oxides, metal oxide nitrides, metal nitrides Oxides can be used. Silicon oxide, silicon oxide nitride, silicon nitride oxide , nitride silicon, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide or resin, aluminum oxide Um, gallium oxide, hafnium oxide, zirconium oxide, aluminum and hafnium Oxides containing aluminum, oxidized nitrides containing aluminum and hafnium, silicon and Oxides containing hafnium, silicon and hafnium-containing oxides or nitrides Nitrides containing ammonium compounds and hafnium can be used.

[0188] In a subsequent process, the conductor 136 is combined with conductor 137, conductor 134, conductor 119, and insulator. Since it is necessary to selectively etch 138 and the insulator 123, The dielectric film 136A consists of conductive film 134A, conductive film 134A, insulator 138, and insulating film 123 It is preferable that the material is capable of selective etching of A. For example, conductive film 136A The conductive film 134A is made of a different material, and the insulator 138 and insulating film 123A are made of silicon oxide. It is preferable to use condensate or silicon oxide nitride.

[0189] Furthermore, in this embodiment, there are six layers of insulating film 123A, three layers of conductive film 134A, and conductive film An example of forming two layers of 136A is shown, but the number of layers is not limited to this. Depending on the performance of the placement, each can be formed. Here, the number of layers of conductive film 134A If m is an integer greater than or equal to 2, then the number of layers of insulating film 123A is 2 × m, and the number of conductive films 136A is 2 × m. The number of layers is m-1. For example, m is 33 or more, preferably 65 or more, more preferably The value can be 129 or more, and more preferably 257 or more.

[0190] A conductive film 137A is formed on the uppermost insulating film 123A, and an insulating film 13 8A is formed. Conductive film 137A is formed using the same method and materials as conductive film 134A. It can be formed. Also, insulating film 138A can be formed using the same method as insulating film 123A. It can be formed from various materials.

[0191] Next, insulating film 138A, conductive film 137A, insulating film 123A, conductive film 134A, and conductive The film 136A is processed to form a stepped insulator 138B, a conductor 137B, as shown in Figure 11B. Insulator 123B, conductor 134B, and conductor 136B are formed (Figures 11A to 11A) See 1C. ) Insulating film 138A, conductive film 137A, insulating film 123A, conductive film 134A, In processing the conductive film 136A, insulating film 138A, conductive film 137A, insulating film 123A Etching of conductive film 134A and conductive film 136A and mask slimming are performed alternately. By doing so, the stepped insulator 138B, conductor 137B, insulator 123B, and conductor 134 B and the conductor 136B can be formed.

[0192] Next, an insulator 150 is formed (see Figures 11A to 11C). The insulator 150 is CV It can be formed using method D. The insulator 150 can be formed using CMP or reflow. It is preferable that the surface is planarized.

[0193] Next, insulator 150, insulator 138B, conductor 137B, insulator 123B, conductor 134 B and the conductor 136B are processed to form grooves, and the insulator 138, conductor 137, and insulator 123, conductor 134, and conductor 136 are obtained. (See Figures 12A to 12C.)

[0194] Here, if a dummy layer is used for one of the conductive films 134A and 136A, the above addition The dummy layer is removed from the exposed side by the process, and a conductive material is formed in the area where the dummy layer was removed. This may be done. In this case, if a conductor is formed inside the groove, this conductor is removed. The removal of the dummy layer and the formation of the conductor may be carried out in a later step.

[0195] Next, an insulator 152 is formed to fill the groove portion (see Figures 12A to 12C). The insulator 152 can be formed using the CVD method or the ALD method. In particular, AL By using the D method, a film with uniform thickness can be formed even for grooves and openings with large aspect ratios. This is preferable because it can achieve this. Alternatively, the ALD method and the CVD method can be combined for insulation. Body 152 may be formed. The insulator 152 may be planarized using the CMP method or the reflow method. It is preferable that it has been treated.

[0196] Next, the conductor 184 and insulating material are placed on the insulator 138, insulator 150, and insulator 152. Forms body 185 (see Figures 13A to 13C). Conductor 184 and insulator 18 5 is a material that can be used for the conductor 122 and the insulator 132, respectively, and the conductor It can be formed using a method that can be used to form 122 and the insulator 132. Cut.

[0197] Next, an insulator 186 is formed on the conductor 184 and the insulator 185 (Figures 14A to 14A). See 14C. ) Insulator 186 is a material that can be used for insulator 132, and insulator 1 32 can be formed using a method that can be used for the formation of 32.

[0198] Next, a conductor 187 and an insulator 188 are formed on the insulator 186 (Figures 14A to 14A). See 14C.) Conductor 187 and insulator 188 are conductor 122 and insulator 188, respectively. A material that can be used for the insulator 132, and for the formation of the conductor 122 and the insulator 132. It can be formed using any applicable method.

[0199] Next, an insulator 189 is formed on the conductor 187 and the insulator 188 (Figures 14A to 14A). See 14C. ) Insulator 189 is a material that can be used for insulator 132, and insulator 1 32 can be formed using a method that can be used for the formation of 32.

[0200] Next, a mask is formed on the insulator 189, and the insulator 189, conductor 187, insulator 186, Conductor 184, insulator 138, conductor 137, insulator 123, conductor 134, and conductive Body 136 is processed using lithography to expose the conductive material 119 in the first opening It forms a mouth (see Figures 15A to 15C).

[0201] Here, if a dummy layer is used for one of the conductors 134 and 136, the above processing is performed The dummy layer is removed from the more exposed side, and a conductor is formed in the area where the dummy layer was removed. This is also acceptable. In this case, if a conductor is formed inside the first opening, this conductor is removed. do.

[0202] Next, isotropic etching is performed on the conductor 136 to enlarge the diameter of the opening of the conductor 136. (See Figures 16A to 16C.) This process results in the diameter of the opening of the conductor 136 being the same as that of the insulator. The diameters of the openings of 138, conductor 137, insulator 123, and conductor 134 are larger than the diameters of the openings of conductor 134. Furthermore, the conductor 136 is located above or below the insulator 138, conductor 137, and insulator It can be said that it has a recess on the side surface of 123 or the conductor 134. The process involves isotropic etching using dry etching with gas, radicals, plasma, etc. Isotropic etching can be performed using wet etching with a liquid. The liquid used in wet etching is sometimes called etchant. When performing isotropic etching using a gas containing at least one of chlorine, bromine, and fluorine, Isotropic etching can be performed using radicals, plasma, etc. It is preferable to carry out the procedure without removing the mask used for formation. The first opening obtained by the above process The mouth corresponds to the opening 141 shown in Figure 3.

[0203] Next, an insulating film 124A is formed on the insulator 189 and inside the first opening (Figure 17A). (See Figure 17C.) Although not shown, the insulating film 124A has a layered structure. This is also acceptable. The insulating film 124A can be formed using the CVD method or the ALD method. In particular, By using the ALD method, a uniform film thickness can be applied even to grooves and openings with large aspect ratios. This is preferable because it allows for the formation of [a specific type of plasma]. In particular, the PEALD method utilizes plasma. This allows for film deposition at lower temperatures, which is preferable in some cases. Alternatively, the ALD method and CV The insulating film 124A may be formed by combining method D. The insulating film 124A has a layered structure. In this case, each insulating film may be formed using the same deposition apparatus, or it may be formed using different deposition apparatuses. That's good too.

[0204] The insulating film 124A formed by the above method has good coverage and penetrates the recesses of the conductor 136. Insulator 123, conductor 13 4, and not only the sides of the conductor 136, but also a portion of the upper surface and a portion of the lower surface of the insulator 123. The insulating film 124A can be formed so as to be in contact with the part as well.

[0205] Next, the insulating film 124A formed at the bottom of the first opening is removed to obtain the insulator 124B. Anisotropic etching is preferred for removing the border film 124A. Since the insulating film 124A on 189 is also removed, the insulator 124B is only the side wall of the first opening. It is provided there (see Figures 18A to 18C). The insulating film 124A at the bottom of the first opening is removed. This exposes the conductor 119 again.

[0206] Next, in the XY plane shown in Figures 18A to 18C, conductor 184 and conductor 1 Remove the insulator 124B that overlaps with 87. To remove the insulator 124B, first remove the first opening A material 180 (also called a sacrificial layer) that can be easily removed in a later process is embedded in the part. Then, the material is removed by etching or the like to the desired depth inside the first opening (Figures 19A to 19A). See 19C.) Next, material 180 is used as a mask to remove the insulation exposed by the etching. Remove body 124B to obtain insulator 124 (see Figures 20A to 20C). Insulator 12 After removing 4B, remove material 180.

[0207] Next, a semiconductor film 125A and a conductive film 12 are placed on the insulator 189 and inside the first opening. Forms 8A (see Figures 21A to 21C). The semiconductor film 125A is inside the first opening. And it is provided so as to be in contact with at least the conductor 119, the insulator 124, and the conductor 184. It is preferable that this be done.

[0208] The semiconductor film 125A can be formed using CVD or ALD methods. In particular, ALD By using this method, a film of uniform thickness can be formed even on grooves and openings with large aspect ratios. This is preferable because it allows for the use of plasma. In particular, the PEALD method utilizes plasma. This allows for film deposition at lower temperatures, which is preferable in some cases. Alternatively, the ALD method and the CVD method can be used. The semiconductor film 125A may be formed by combining these. The semiconductor film 125A has a CAAC structure. It is preferable that the semiconductor film 125A is an oxide semiconductor having a CAAC structure. In the case of a semiconductor, the c-axis of the semiconductor film 125A is within the first opening, and the surface to be formed It is oriented in the direction normal to the insulator. At this time, the insulator 138 and the conductor 137 are connected via the insulator 124. , semiconductor film 125A located on the sides of insulator 123, conductor 134, and conductor 136 The c-axis is oriented toward axis 178 shown in Figures 21B and 21C from the surface to be formed. Furthermore, axis 178 can be called the central axis of the first opening. This allows the above to be located The c-axis of the semiconductor 125 is oriented toward axis 178 from the surface to be formed.

[0209] Here, when forming a metal oxide as the semiconductor film 125A using the ALD method, the index Using a precursor containing um, a precursor containing gallium, and a precursor containing zinc It is preferable to form an In-Ga-Zn oxide.

[0210] As precursors containing indium, triethylindium, tris(2,2,6,6- Tetramethyl-3,5-heptanedione) indium, cyclopentadienyl indione Indium(III) chloride and other materials can be used. Also, gallium-containing polycarbonates can be used. As a derivative, trimethylgallium, triethylgallium, tris(dimethylamide)gallium Gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl (3,5-heptanedionic acid) gallium, dimethylchlorogallium, diethylchlorogallium Gallium, gallium(III) chloride, etc. can be used. Also, zinc-containing precursors can be used. As a supplement, dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5 - Zinc heptanedione, zinc chloride, etc. can be used.

[0211] The conductive film 128A is conductive through at least the insulator 124 and the semiconductor film 125A. It is sufficient that it is formed to fill the recess of body 136, and not necessarily the entire interior of the first opening No filling is necessary. The conductive film 128A can be formed using the CVD method or the ALD method. It is possible. In particular, by using the ALD method, even grooves and openings with a large aspect ratio can be processed. It is preferable because it can form a uniform film. In particular, in the PEALD method, Using a different method may be preferable as it allows for film formation at lower temperatures. Alternatively, AL The conductive film 128A may be formed by combining the D method and the CVD method.

[0212] Next, the conductive film 128A is processed to form the conductor 128 (see Figures 22A to 22C). .) The conductive film 128A is processed using either isotropic etching or anisotropic etching. This is possible. In forming the conductive film 128A, as shown in Figures 21A to 21C, If the conductive film 128A fills the recess and the first opening is not completely filled, the conductive film 12 For processing 8A, isotropic etching is preferable. On the other hand, the recess and the first opening If the conductive film 128A is formed to fill the opening, anisotropic etching is used. Preferably, the conductive material 128 is formed inside the recess by the processing described above. It is possible.

[0213] Next, material 181 is formed inside the first opening (see Figures 22A to 22C). 181 is used in the processing of semiconductor films 125A, conductors 119, insulators 118, etc. It is used as a sacrificial layer to protect 125A. Material 181 is formed of an insulating material. While this is preferable, one aspect of this embodiment is not limited thereto. Material 181 is electrically conductive. Any material may be used. Material 181 is a material that can be used for insulating film 124A, and insulating film 1 It can be formed using a method that can be used to form 24A.

[0214] Next, using the conductor 128 as a mask, a portion of the semiconductor film 125A is made highly resistive, creating a high-resistance region. It is preferable to form a (Type I region). As a method for forming a high-resistance region, the semiconductor film 125 By irradiating A with microwaves, the hydrogen contained in the semiconductor film 125A can be removed. By irradiating with microwaves in an oxygen-containing atmosphere, oxygen is supplied to the semiconductor film 125A. Therefore, it is preferable. In this embodiment, under an atmosphere containing oxygen and argon, semi A portion of the conductive film 125A is irradiated with microwaves, and the semiconductor film 125 that is not covered by the conductor 128 The first region of A is made to have high resistance.

[0215] Heat treatment may be performed here. The heat treatment is performed in a nitrogen-containing atmosphere at 200°C or higher for 50°C. The heat treatment is carried out at a temperature of 0°C or lower, preferably between 300°C and 400°C. The atmosphere is not limited to the above, but includes an atmosphere containing at least one of nitrogen, oxygen, and argon. It is fine to do so. Also, the heat treatment may be carried out in a reduced pressure atmosphere or in an atmospheric pressure atmosphere. That's fine.

[0216] The heat treatment reduces the resistance of the second region of the semiconductor film 125A that is in contact with the conductor 128. A resistive region (N-type region) can be formed. The semiconductor film 125A and the conductor 128 are in contact. By performing a heat treatment in this state, the interface between the conductor 128 and the semiconductor film 125A becomes conductive. A metal compound layer is formed containing the metal elements present in body 128 and the components of the semiconductor film 125A. In some cases, the formation of the metal compound layer results in the region in contact with the conductor 128. This is preferable because it reduces the resistance of the semiconductor film 125A. Also, the semiconductor film 125A contains Oxygen may be absorbed by the conductor 128. The semiconductor film 125A and the conductor 128 are in contact. By performing a heat treatment in this state, the semiconductor film 125A becomes even less resistive. This may be done before microwave treatment. The second region, whose resistance has been reduced by the heat treatment, is conductive. Because it is covered by body 128, it is unaffected by microwaves and maintains low resistance even after microwave treatment. The value can be maintained.

[0217] The carrier concentration in the first region after the above microwave treatment and heat treatment is 1 × 10⁻⁶ 18 / cm 3 Less than 1 × 10 17 / cm 3 More preferably, 1 × 10 16 / cm 3 The following is preferable. Also, the carrier concentration in the second region is 1 × 10⁻⁶. 18 / cm 3 Preferably, 1 × 1019 / cm 3 More preferably, 1 × 10 20 / cm 3 It is preferable that the above conditions are met.

[0218] Furthermore, the process of performing the high-resistance treatment on the semiconductor film 125A is not limited to after the formation of the material 181. The high-resistance treatment may be performed before the formation of material 181. Also, the insulating film 126A described later... The high-resistance treatment may be performed before the formation of the insulating film 126A, or the high-resistance treatment may be performed after the formation of the insulating film 126A. That's fine.

[0219] Next, the material 181 and semiconductor film 125A and conductor 11 are formed at the bottom of the first opening. 9, and the insulator 118 are removed to obtain semiconductor 125B. Semiconductor film 125A, material 18 1. Anisotropic etching is preferred for removing the conductor 119 and the insulator 118. At this time, the semiconductor film 125A on the insulator 189 and the material 181 are also removed. Therefore, the semiconductor 125B is provided only on the side wall of the first opening (see Figures 23A to 23C). (Illuminate.) The first opening bottom, semiconductor film 125A, material 181, conductor 119, and insulating By removing body 118, the conductor 122 is exposed.

[0220] Next, in the XY plane shown in Figures 24A to 24C, material 18 overlaps with the conductor 187. 1. Remove semiconductor 125B. To remove semiconductor 125B, first remove the inside of the first opening. A material 182 (also called a sacrificial layer) that can be easily removed in a later process is then embedded in the structure. Remove the material from the inside of the first opening to a desired depth by etching or the like (Figures 24A to 24A). See 4C.) Next, using material 182 as a mask, the material 1 exposed by the etching is removed. Remove semiconductor 81 and semiconductor 125B to obtain semiconductor 125 (see Figures 24A to 24C). After removing semiconductor 125B, material 182 and material 181 are removed.

[0221] Next, an insulating film 126A is formed on the insulator 189 and inside the first opening (Figure 25A). (See Figure 25C.) Although not shown, the insulating film 126A has a layered structure. This is also acceptable. The insulating film 126A can be formed using the CVD method or the ALD method. In particular, By using the ALD method, a uniform film thickness can be applied even to grooves and openings with large aspect ratios. This is preferable because it allows for the formation of [a specific type of plasma]. In particular, the PEALD method utilizes plasma. This allows for film deposition at lower temperatures, which is preferable in some cases. Alternatively, the ALD method and CV The insulating film 126A may be formed by combining method D. The insulating film 126A has a layered structure. In this case, each insulating film may be formed using the same deposition apparatus, or it may be formed using different deposition apparatuses. That's good too.

[0222] Next, the insulating film 126A formed at the bottom of the first opening is removed to obtain the insulator 126B. Anisotropic etching is preferred for removing the border film 126A. Since the insulating film 126A on 189 is also removed, the insulator 126B is only the side wall of the first opening. It is provided there (see Figures 26A to 26C). The insulating film 126A at the bottom of the first opening is removed. This exposes the conductor 122 again.

[0223] Next, in the XY plane shown in Figures 27A to 27C, the insulator 1 overlaps with the conductor 187. Remove 26B. To remove insulator 126B, first, into the first opening, in a later step, A removable material 183 (also called a sacrificial layer) is formed to embed inside the first opening Remove the material to the desired depth by etching or other means (see Figures 27A to 27C). Next, Using material 183 as a mask, remove the insulator 126B exposed by the etching. Obtain insulator 126 (see Figures 27A to 27C). After removing insulator 126B, material 1 Remove 83.

[0224] Next, a semiconductor film 127A is formed inside the first opening so as to be in contact with the conductor 122 (Figure See Figures 28A to 28C. The semiconductor film 127A is formed using CVD or ALD. This is possible. In particular, by using the ALD method, grooves and openings with large aspect ratios can be treated. Even if this is done, it is preferable because it is possible to form a film with a uniform thickness. In particular, with the PEALD method Using plasma allows for film deposition at lower temperatures, which can be preferable in some cases. Alternatively, the semiconductor film 127A may be formed by combining the ALD method and the CVD method. Furthermore, it is preferable that the semiconductor film 127A be formed in contact with the conductor 187. The semiconductor film 127A is preferably an oxide semiconductor having a CAAC structure. If film 127A is an oxide semiconductor having a CAAC structure, the c-axis of semiconductor film 127A is , within the first opening, it is oriented in the direction normal to the surface to be formed. At this time, the side of the first opening The c-axis of the semiconductor film 127A located on the surface is the axis shown in Figures 28B and 28C from the surface to be formed. It is oriented toward 178. As a result, the c-axis of the semiconductor 127 located above is formed It is oriented from the surface toward axis 178.

[0225] Here, when forming a metal oxide as the semiconductor film 127A using the ALD method, the index Using a precursor containing um, a precursor containing gallium, and a precursor containing zinc It is preferable to form an In-Ga-Zn oxide.

[0226] As precursors containing indium, triethylindium, tris(2,2,6,6- Tetramethyl-3,5-heptanedione) indium, cyclopentadienyl indione Indium(III) chloride and other materials can be used. Also, gallium-containing polycarbonates can be used. As a derivative, trimethylgallium, triethylgallium, tris(dimethylamide)gallium Gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl (3,5-heptanedionic acid) gallium, dimethylchlorogallium, diethylchlorogallium Gallium, gallium(III) chloride, etc. can be used. Also, zinc-containing precursors can be used. As a supplement, dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5 - Zinc heptanedione, zinc chloride, etc. can be used.

[0227] Next, the semiconductor film 127A formed on the insulator 189 is removed. First, within the first opening, the inside of the semiconductor film 127A can be easily processed in a later step. Form the removable material 179 (also called the sacrificial layer) to embed it. Next, material 179 Using this as a mask, the semiconductor film 127A is removed to obtain semiconductor 127 (Figures 29A to 29A). See 9C.) To remove the semiconductor film 127A, etching or CMP methods can be used. Yes, it is possible. When removing semiconductor film 127A by etching, dry etching is used. Alternatively, wet etching may be used. After removing the semiconductor film 127A, material 179 Remove.

[0228] Next, an insulator 129 is formed on the insulator 189 and inside the semiconductor 127, and the insulator 1 A conductor 130 is formed inside 29 (see Figures 30A to 30C). Insulator 129 The conductor 130 can be formed using CVD or ALD methods. By using the ALD method, even grooves and openings with a large aspect ratio can be made with a uniform thickness. This method is preferable because it can form a film. Alternatively, the ALD method and the CVD method can be combined. It may be formed in this way. Furthermore, different film deposition methods and equipment may be used for each film to be formed. For example, the insulator 129 is a material that can be used for the insulating film 124A, and the insulating film 124 A method can be used to form A. In addition, the conductor 130 is conductive A material that can be used for film 128A, and which can be used for forming conductive film 128A. The law can be used.

[0229] Here, the semiconductor 127 is subjected to the same high-resistance treatment as that performed on the semiconductor film 125A. Alternatively, when the semiconductor 127 is subjected to a high-resistance treatment, the high-resistance treatment is performed on the conductor 13 It is preferable to perform this before the formation of 0 or before the formation of the insulator 129. By performing a resistance-increasing treatment on A, it is also possible to increase the resistance of the first region of semiconductor 125. In addition, the high-resistance treatment in the previous step may be omitted.

[0230] Next, heat treatment is performed. The heat treatment is carried out in a nitrogen-containing atmosphere at a temperature between 200°C and 500°C. Preferably, the process is carried out at a temperature of 300°C to 400°C. The atmosphere for the heat treatment is In addition to the above, the procedure can be carried out in an atmosphere containing at least one of nitrogen, oxygen, and argon. Furthermore, the heat treatment may be carried out under reduced pressure or under atmospheric pressure.

[0231] The conductor 130 forms a conductive film on the insulator 129 and on the inside of the insulator 129, and the conductive The film is obtained by removing it using methods such as CMP until the surface of the insulator 129 is exposed. This can be done (see Figures 30A to 30C). Note that the aforementioned heat treatment is for conductor type 130. It can be done after reaching adulthood.

[0232] Next, an insulator 156 is formed on the conductor 130 and the insulator 129 (Figures 31A to 31A). See 31C.) The insulator 156 is shaped using methods such as CVD, ALD, and sputtering. It is possible.

[0233] Next, insulator 156, insulator 129, insulator 189, insulator 188, insulator 186, insulator Body 185, insulator 138, insulator 150, and insulator 123 are subjected to lithography. Process the material to expose conductors 134, 136, 130, and 137. A second opening is formed in such a way. The second opening is formed by a stepped conductor 134, and These are formed on each of the conductive materials 136 (see Figures 31A to 31C). However, there is an opening that exposes the conductor 184 and the conductor 187, and the conductor 119, An opening that exposes the conductor 122 may be formed in the above process.

[0234] Next, a conductor 161 is electrically connected to the conductor 134 so as to be embedded in the second opening. Conductor 162 electrically connected to the electric body 136, Conductor 1 electrically connected to the conductor 130 63, and a conductor 164 that is electrically connected to the conductor 137 (Figures 31A to 31A) See 31C.) Conductors 161, 162, 163, and 164 are, It can be formed using the CVD method or the ALD method. In particular, by using the ALD method, Because it can form a film of uniform thickness even on grooves and openings with a large spectral ratio. , preferred. Alternatively, the above conductor may be formed by combining the ALD method and the CVD method. Furthermore, conductors 161, 162, 163, and 164 are made up of multiple layers. It may have a laminated structure consisting of conductor 161, conductor 162, conductor 163, The conductor 164 forms a conductive film on the insulator 156 and inside the second opening, and CMP It can be formed by removing unwanted conductive films using methods such as [method name]. However, the conductors 184, 187, 119, and 122 are electrically charged, respectively. A conductive material that connects to the target may be formed in the above process.

[0235] Next, conductor 171, which is electrically connected to conductor 161, and conductor 162, which are electrically connected to conductor 161. Conductor 172, Conductor 173 which is electrically connected to Conductor 163, and Conductor 164 which is electrically connected to A conductive element 174 is formed that is electrically connected (see Figures 31A to 31C). Conductor 171 Conductors 172, 173, and 174 form a conductive film on the insulator 156. This can be formed by processing using lithography. This processing is performed by dry etching. Wet etching can be used. Dry etching allows for fine processing. Suitable for industrial use.

[0236] Conductors 171, 161, and 134 are either conductor SG or conductor WWL. It can function as such. Conductors 172, 162, and 136 are conductive. It can function as a body RWL. Conductor 173, Conductor 163, and Conductor 13 0 can function as a conductive BG. Conductors 174, 164, and conductor The electric element 137 can function as a conductor SEL. Conductor 184 is a conductor WB. It can function as L. Conductor 187 can function as conductor RBL. This process results in a semiconductor 125 that functions as a channel formation region and a gate. A transistor STr1 having a conductor 134 that functions as a channel formation region A transistor STr having a semiconductor 127 and a conductor 137 that functions as a gate. 2. A semiconductor 125 that functions as a channel formation region and a conductor 13 that functions as a gate. A transistor STr3 having 7, a semiconductor 125 that functions as a channel formation region, A transistor WTr having a conductor 134 that functions as a gate, and channel formation A semiconductor 127 that functions as a region, a conductor 136 that functions as a gate, and a backgear The conductor 130 functions as a conductor, and the conductor 128 is between the semiconductor 127 and the conductor 136. It is possible to fabricate a transistor RTr having the following properties. Also, transistor STr1, Transistor STr2, transistor STr3, transistor WTr, and transistor R A memory device having transistors can be manufactured.

[0237] <Example of a film deposition apparatus configuration> Here, as an example of a device capable of forming films using the ALD method, the film deposition apparatus 4000 The configuration will be explained using Figures 32A and 32B. Figure 32A shows a multi-chamber type. Figure 32B is a schematic diagram of the film deposition apparatus 4000, and can be used in the film deposition apparatus 4000. This is a cross-sectional view of the ALD device.

[0238] The film deposition apparatus 4000 includes an loading / unloading room 4002, a loading / unloading room 4004, and a transport room 4006. , deposition chamber 4008, deposition chamber 4009, deposition chamber 4010, transport arm 4014, It has. Here, loading / unloading room 4002, loading / unloading room 4004, and film deposition rooms 4008 to 4 010 is independently connected to the transport chamber 4006. This allows the film deposition chamber 400 Continuous film deposition can be performed without exposure to air in values ​​8 to 4010, and impurities are present in the film. This prevents contamination. Furthermore, contamination at the substrate-film interface and the interfaces between each film is reduced. The residue is reduced, and a clean interface is obtained.

[0239] Furthermore, there are loading / unloading rooms 4002, 4004, transporting room 4006, and film deposition room 4008. To prevent moisture from adhering, etc., an inert gas (such as nitrogen gas) with a controlled dew point is used. It is preferable to fill it with ) and to maintain reduced pressure.

[0240] Furthermore, ALD equipment can be used in deposition chambers 4008 to 4010. It is also possible to use a film deposition apparatus other than the ALD apparatus in any of rooms 4008 to 4010. i. Examples of film deposition apparatus that can be used in film deposition chambers 4008 to 4010 include spa Tuttering equipment, Plasma CVD (PECVD: Plasma Enhanced CV) D) Equipment, thermal CVD (TCVD) equipment, optical CVD (Photo CVD) equipment, metal CVD (MCVD) equipment, organometallic CVD ( MOCVD: Metal Organic CVD) apparatus, and the like. In addition, the film formation chamber 40 Any one or more of 08 to 4010 may be provided with an apparatus having a function other than the film formation apparatus It does not matter even if it is. Examples of the apparatus include a heating apparatus (typically, a vacuum heating apparatus), a pla sma generation apparatus (typically, a microwave plasma generation apparatus), and the like.

[0241] For example, the film formation chamber 4008 is an ALD apparatus, the film formation chamber 4009 is a PECVD apparatus, and the film formation When the chamber 4010 is a metal CVD apparatus, a metal oxide can be formed in the film formation chamber 4008, an insulating film functioning as a gate insulating film in the film formation chamber 4009 , and a conductive film functioning as a gate electrode in the film formation chamber 4010 can be formed. At this time, the metal oxide, the insulating film thereon, and the conductive film thereon can be formed continuously without being exposed to the atmosphere.

[0242] In addition, although the film formation apparatus 4000 is configured to include the loading / unloading chamber 4002, the loading / unloading chamber 4004, and the film formation chambers 4008 to 4010, the present invention is not limited to this. The number of film formation chambers of the film formation apparatus 4000 may be four or more. In addition, the film formation apparatus 4000 may be a single-wafer type, or may be a batch type in which a plurality of substrates are subjected to film formation collectively.

[0243] <ALD Apparatus> Next, the configuration of the ALD apparatus that can be used for the film formation apparatus 4000 will be described with reference to FIG. 32B. The ALD apparatus includes a film formation chamber (chamber 4020), a source material supply unit 4021( source material supply units 4021a and 4021b), a source material supply unit 4031, and a high-speed valve 4022 that is an introduction amount controller (high-speed valves 4022a and 4022b), and a source material introduction port 40 ​​23 (raw material inlet 4023a and 4023b), raw material inlet 4033, and raw material outlet It has 4024 and an exhaust device 4025. A raw material inlet is installed inside the chamber 4020. 4023a, 4023b, and 4033 supply raw materials to the raw material supply unit 4021 via supply pipes and valves. a, 4021b, and 4031 are connected respectively, and the raw material discharge port 4024 is discharge It is connected to the exhaust system 4025 via outlet pipes, valves, and pressure regulators.

[0244] Furthermore, as shown in Figure 32B, the plasma generator 4028 is connected to the chamber 4020. This allows for film deposition using plasma ALD in addition to thermal ALD. The generator 4028 is an ICP type plastic generator that uses a coil 4029 connected to a high-frequency power supply. It is preferable to use a zuma generator. The high-frequency power supply should be between 10 kHz and 100 MHz. More preferably 1 MHz to 60 MHz, and more preferably 10 MHz to 60 MHz. It can output power with a specific frequency. For example, 13.56MHz, 60MHz It can output power with frequency. In the plasma ALD method, thin-film deposition lasers can be used even at low temperatures. Since it allows for film deposition without dropping the film, it is suitable for use in single-wafer film deposition systems with low deposition efficiency.

[0245] Inside the chamber is a substrate holder 4026, and a substrate 403 is placed on the substrate holder 4026. Place 0. The substrate holder 4026 has a mechanism to which a constant potential or high frequency is applied. It may be provided. Alternatively, the substrate holder 4026 may be floating. It may be grounded. Also, a heater 4027 is provided on the outer wall of the chamber. The temperature of the inside of the chamber 4020, the substrate holder 4026, and the surface of the substrate 4030 is controlled. It can be controlled. Heater 4027 raises the temperature of the substrate 4030 surface to 100°C or 500°C. It is preferable that the temperature can be controlled to be below ℃, preferably between 200℃ and 400℃, and heater 4 It is preferable that the temperature of the 027 itself be set to between 100°C and 500°C.

[0246] In the raw material supply sections 4021a, 4021b, and 4031, vaporizers and heating means are used. The raw material gas is formed from solid or liquid raw materials. Alternatively, the raw material supply unit 4021a, 4 021b and 4031 may be configured to supply a gaseous raw material gas.

[0247] Furthermore, Figure 32B shows two raw material supply units 4021 and one raw material supply unit 4031. Although an example is shown, this embodiment is not limited thereto. One raw material supply unit 4021, and There may be three or more of these. Also, there may be two or more raw material supply units 4031. Valves 4022a and 4022b can be precisely controlled in time, and the raw material supply unit 4021 Controls the supply of raw material gas from a and raw material gas supplied from raw material supply unit 4021b. It is structured in this way.

[0248] In the film deposition apparatus shown in Figure 32B, the substrate 4030 is loaded onto the substrate holder 4026, and the chamber - After sealing 4020, the heater 4027 heats the substrate 4030 to the desired temperature (for example) The temperature should be between 100°C and 500°C, preferably between 200°C and 400°C, and the raw material supply should be set accordingly. The supply of raw material gas from section 4021a, exhaust by exhaust device 4025, and raw material supply The supply of raw material gas from the supply unit 4031 and exhaust gas from the exhaust device 4025 are repeated. This is used to form a thin film on the substrate surface. Furthermore, in the formation of the thin film, the raw material supply unit 4 The raw material gas supplied from 021b may be supplied, and exhaust may be performed by the exhaust device 4025. The temperature of heater 4027 depends on the type of film to be formed, the source gas, the desired film quality, the substrate, and the settings thereon. The appropriate value should be determined according to the heat resistance of the film or element being applied. For example, heater 4027 The film may be deposited at a temperature of 200°C to 300°C, or at 300°C to 500°C. You can also set it to the bottom and deposit the film there.

[0249] By depositing a film while heating the substrate 4030 using the heater 4027, the substrate required in subsequent processes is formed. The heating treatment of plate 4030 can be omitted. That is, heater 4027 is provided. By using the chamber 4020 or the film deposition apparatus 4000, the shape of the film on the substrate 4030 can be determined. This can also serve as a heat treatment for the substrate 4030.

[0250] In the film deposition apparatus shown in Figure 32B, the raw material supply unit 4021 and the raw material supply unit 4031 are used By appropriately selecting raw materials (such as volatile organometallic compounds), metal oxides can be formed. This can be done. In-Ga-Zn acid, which contains indium, gallium, and zinc as metal oxides. When forming a compound, there are at least three raw material supply units 4021 and at least one raw material supply unit It is preferable to use a film deposition apparatus equipped with a feeding section 4031. First raw material supply section 4021 A precursor containing indium is supplied from the second raw material supply unit 4021, and gallium is supplied from the second raw material supply unit 4021. A precursor containing zinc is supplied, and a zinc-containing precursor is supplied from the third raw material supply unit 4021. It is preferable to use a precursor containing gallium and zinc for the formation of the metal oxide. If present, at least two raw material supply units 4021 should be provided. Precursors, gallium-containing precursors, and zinc-containing precursors, respectively The aforementioned precursor can be used.

[0251] In addition, a reactant is supplied from the raw material supply unit 4031. As a reactant, An oxidizing agent containing at least one of nitrogen, oxygen, and water can be used.

[0252] Furthermore, the raw materials used in the raw material supply units 4021a, 4021b, and 4031 (volatile organic gold By appropriately selecting compound species (such as genus compounds), hafnium, aluminum, tantalum, zirconium, aluminum, tartar, zirconium, aluminum The oxide (including complex oxides) contains one or more elements selected from conium, etc. An insulating layer can be formed. Specifically, it is composed of hafnium oxide. An insulating layer comprising aluminum oxide, an insulating layer comprising hafnium silicate A film is formed containing an insulating layer, or an insulating layer containing aluminum silicate. It is possible to use in the raw material supply units 4021a, 4021b, and 4031. By appropriately selecting raw materials (such as volatile organometallic compounds), a tungsten layer and titanium can be formed. Thin films such as metal layers and nitride layers such as titanium nitride layers can also be deposited.

[0253] For example, when forming a hafnium oxide layer using an ALD apparatus, a solvent and a hafnium precursor are used. Liquids containing compound (such as hafnium alkoxide or tetrakisdimethylamide hafnium) A first raw material gas obtained by vaporizing hafnium amide (such as TDMAHf), and an oxidizing agent Then, ozone (O3) and oxygen (O2) are used as second raw material gases. In this case, the raw material supply unit The first raw material gas supplied from 4021a is TDMAHf, and from the raw material supply unit 4031 The second raw material gas supplied will be ozone and oxygen. The chemical formula for humium is Hf[N(CH3)2]4. Other material liquids include tetrahedron. Examples include lacs(ethylmethylamide)hafnium. Additionally, water is used as a second raw material gas. You can use it.

[0254] When forming an aluminum oxide layer using an ALD apparatus, the solvent and aluminum precursor are used. A first raw material gas obtained by vaporizing a liquid containing a compound (TMA: trimethylaluminum, etc.) A second raw material gas containing ozone (O3) and oxygen (O2) as oxidizing agents is used. In this case, the first raw material gas supplied from the raw material supply unit 4021a is TMA, and the raw material supply unit 4 The second raw material gas supplied from 031 will be ozone and oxygen. The chemical formula for nium is Al(CH3)3. Other material liquids include Tris(dimethyl) Aluminum (Aluminum), Triisobutylaluminum, Aluminum Tris(2,2, Examples include 6,6-tetramethyl-3,5-heptanedione). Also, the second raw material is Water can be used as a substitute.

[0255] Figures 33A to 33C illustrate the differences in ALD apparatus that can be used in film deposition apparatus 4000. The following describes the configuration. Note that the same configuration as the ALD device shown in Figure 32B, and its mechanism Detailed explanations of Noh theater may be omitted in some cases.

[0256] Figure 33A is a schematic diagram showing one embodiment of a plasma ALD apparatus. Plasma ALD apparatus 410 In the case of 0, a plasma generation chamber 4111 is provided above the reaction chamber 4120. The reaction chamber 4120 can be called a chamber. Alternatively, reaction chamber 4120 and plastic The Zuma generation chamber 4111 can be collectively referred to as the chamber. The reaction chamber 4120 is the raw material The plasma generation chamber 4111 has an inlet 4123 and a raw material outlet 4124, and the raw material inlet It has 4133. In addition, the plasma generator 4128 generates high-frequency waves such as RF and micro Waves are applied to the gas introduced into the plasma generation chamber 4111, and within the plasma generation chamber 4111, Plasma 4131 can be generated. Plasma 4131 is generated using microwaves. In such cases, microwaves with a frequency of 2.45 GHz are typically used. Plasma generated using radio waves is called ECR (Electron Cyclotron R). It is sometimes called plasma (esonance). Also, the reaction chamber 4120 is connected to the substrate holder 4 It has 126, on which the substrate 4130 is placed. It is introduced from the raw material inlet 4123. The raw material gas is decomposed by heat from a heater installed in the reaction chamber 4120, and the substrate 4130 It accumulates on top. Also, the raw material gas introduced from the raw material inlet 4133 is used in the plasma generator. 4128 creates a plasma state. The source gas, now in a plasma state, is transferred to the substrate 4130. Before reaching the surface, it recombines with electrons and other molecules, becoming a radical state and reaching the substrate 4130. In this way, an ALD apparatus that performs film deposition using radicals is called a radical ALD (Ra It is sometimes called a (dical-enhanced ALD) device. Also known as plasma ALD. Apparatus 4100 shows a configuration in which the plasma generation chamber 4111 is located above the reaction chamber 4120. However, this embodiment is not limited thereto. Plasma generation chamber 4111 is connected to reaction chamber 412 It may be provided adjacent to the side of 0.

[0257] Figure 33B is a schematic diagram showing one embodiment of a plasma ALD apparatus. Plasma ALD apparatus 420 Unit 0 has a chamber 4220. Chamber 4220 contains an electrode 4213 and a raw material discharge chamber. It has an outlet 4224 and a substrate holder 4226, on which a substrate 4230 is placed. Electrode 4 213 is a raw material inlet 4223 and supplies the introduced raw material gas into the chamber 4220. It has a shower head 4214. Also, the electrode 4213 has a capacitor 4217. A power supply 4215 capable of applying high frequency is connected via this. The board holder 4226 is A mechanism for applying a constant potential or high frequency may be provided. Alternatively, the substrate may be... The rod 4226 may be floating or grounded. Electrode 4213, The substrate holder 4226 is an upper electrode for generating plasma 4231, and It functions as a lower electrode. The raw material gas introduced from the raw material inlet 4223 is in the chamber It is decomposed by the heat from the heater provided in 4220 and deposited on the substrate 4230. The raw material gas introduced from the raw material inlet 4223 is supplied to the electrode 4213 and the substrate holder 4 Between 226 and 226, it enters a plasma state. The raw material gas that has entered a plasma state becomes plasma 4231 The potential difference (also called the ion sheath) that arises between the substrate 4230 and the material is incident on the substrate 4230. do.

[0258] Figure 33C is a schematic diagram showing one embodiment of a plasma ALD apparatus different from that shown in Figure 33B. The Zuma ALD apparatus 4300 has a chamber 4320. Chamber 4320 is It has an electrode 4313, a raw material discharge port 4324, and a substrate holder 4326, on which a substrate 4330 is placed. The following are arranged. Electrode 4313 is connected to the raw material inlet 4323 and the introduced raw material gas into the chamber. - It has a shower head 4314 that supplies water into 4320. Also, the electrode 4313 has A power supply 4315, which can apply high frequency via capacitor 4317, is connected to the circuit board. The holder 4326 may be provided with a mechanism to which a constant potential or high frequency is applied. Alternatively, the substrate holder 4326 may be floating or grounded. The electrode 4313 and the substrate holder 4326 each generate plasma 4331. It functions as an upper electrode and a lower electrode for the plasma ALD apparatus 4300. A high frequency can be applied between 4313 and the substrate holder 4326 via the capacitor 4322. Plasma ALD apparatus 42 has a mesh 4319 to which the power supply 4321 is connected. It is different from 00. By providing mesh 4319, the plasma 4231 is separated from the substrate 4130. It can be separated. The raw material gas introduced from the raw material inlet 4323 is in the chamber 4320. It is decomposed by heat from a heater provided therein and deposited on the substrate 4330. Alternatively, raw material The raw material gas introduced from the inlet 4323 is supplied to the electrode 4313 and the substrate holder 4326. It enters a plasma state in between. The raw material gas, now in a plasma state, is electrically charged through mesh 4319. The load is removed, and the material reaches the substrate 4130 in an electrically neutral state, such as a radical. This allows for film deposition with suppressed damage from ion incidence and plasma.

[0259] By forming semiconductor 125 or semiconductor 127 using the ALD method, the normal of the film-deposited surface When it is possible to form a metal oxide with a CAAC structure in which the c-axis is oriented approximately parallel to the direction. There is.

[0260] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0261] (Embodiment 2) This embodiment describes the circuit configuration and operation of the memory string 120, which is a storage device. To clarify, Figure 34 shows an example of the circuit configuration of the memory string 120. Also, Figure 35 shows the memory element The equivalent circuit diagram of the MC is shown.

[0262] Furthermore, in order to make the potential of wiring, electrodes, or conductors easier to understand in drawings and other diagrams, "H" indicates an H potential, or "L" indicates an L potential, adjacent to wiring, electrodes, or conductors. The following may be added: Also, for wiring, electrodes, or conductors where a potential change occurs, “H " or "L" may be enclosed in letters. Also, the transistor is in the off state. In some cases, an "×" symbol may be superimposed on the transistor in question.

[0263] <Example of a memory string circuit configuration> Figure 34 shows an example of the circuit configuration of a memory string 120 equipped with five memory elements MC. The memory element MC has transistors WTr and RTr. In Figure 34, This indicates that the transistor WTr included in the memory element MC[1] is referred to as transistor WTr[1]. The transistor RTr included in the memory element MC[1] is shown as transistor RTr[1]. Therefore, the memory string 120 shown in Figure 34 is a transistor WTr[1] Transistors WTr[5] and transistors RTr[1] or transistors RT It has r[5]. Also, the memory string 120 shown in Figure 34 has a transistor STr It has transistors STr2 and STr3. Memory string 1 20 is a NAND flash memory device.

[0264] Furthermore, in equivalent circuit diagrams, etc., it should be explicitly stated that the transistor is an OS transistor. For this reason, the "OS" is sometimes added to the circuit symbol for a transistor. Similarly, A Si transistor (a transistor that uses silicon in the semiconductor layer where the channel is formed) In order to clearly indicate that it is a transistor, the letter "Si" is sometimes added to the circuit symbol for a transistor. In Figure 34, transistors WTr and RTr are OS transistors. This indicates that...

[0265] NAND type storage devices that include OS memory are called "OS NAND type" or "OS NAND It is also called a "type of memory device." Furthermore, it has a configuration in which multiple OS memories are stacked in the Z direction. S NAND type storage device is called "3D OS NAND type" or "3D OS NAND It is also called a "type of memory device."

[0266] Transistor WTr is a normally-off type transistor. Transistor RTr is a normally-off type transistor. - It is a Mari-on type transistor. Also, as described in the above embodiment, The stRTr includes a conductor 128 between the gate and the semiconductor layer. The conductor 128 is a transistor It can function as a floating gate for transistor RTr. For example, transistor RTr[ The conductor 128 contained in [1] is called conductor 128[1].

[0267] Furthermore, the conductor 128 and either the source or drain of the transistor WTr are electrically connected. The adjacent node is denoted as node ND. For example, conductor 128[1] and transistor WTr[ The node to which either the source or drain of [1] is electrically connected is called node ND[1].

[0268] One of the sources or drains of transistor RTr[1] is electrically connected to the conductor RSL. The other end is electrically connected to either the source or drain of transistor RTr[2]. The gate of transistor RTr[1] is electrically connected to the conductor RWL[1]. The back gate of transistor RTr[1] is electrically connected to the conductor BG. Either the source or drain of the zistor WTr[1] is electrically connected to the conductor 128[1]. The other end is electrically connected to the conductor 128[2]. The source of transistor STr1 is electrically connected to the conductor WWL[1]. Alternatively, one end of the drain is electrically connected to the conductor WSL, and the other end is connected to the conductor 128[1] Electrically connected, the gate is electrically connected to the conductor SG.

[0269] Here, as shown in Figure 35, the transistor RTr is connected to the capacitor Cs and the transistor Tr. It can be expressed by substituting the following: The gate of the transistor Tr is connected to the conductor RW via capacitance Cs. It is electrically connected to L.

[0270] Furthermore, either the source or the drain of transistor RTr[5] [4] is electrically connected to the other of the source or drain of transistor STr2 The source or drain of transistor RTr[5] is electrically connected. The backgate of transistor RTr[5] is electrically connected to the conductor RWL[5]. The wire is electrically connected to the conductor BG. The source or wire of transistor WTr[5] One end of the input is electrically connected to the conductor 128[5], and the other end is connected to the transistor STr3. It is electrically connected to either the drain or the gate of transistor WTr[5] It is electrically connected to the conductor WWL[5]. Also, the source of transistor STr2 or The other end of the drain is electrically connected to conductor RBL, and the gate is electrically connected to conductor SEL. It continues. Also, the source or drain of transistor STr3 is connected to the conductor WBL. Electrically connected, the gate is electrically connected to the conductor SEL.

[0271] If memory string 120 has n memory elements MC (where n is an integer greater than or equal to 1), then The i-th memory element MC (where i is an integer between 2 and n-1), excluding the nth and nth memory elements MC. In [i], either the source or the drain of transistor RTr[i] is Electrically connected to the other side of the source or drain of stRTr[i-1], the other side is a transistor It is electrically connected to either the source or drain of the transistor RTr[i+1]. The gate of transistor RTr[i] is electrically connected to the conductor RWL[i]. The back gate of RTr[i] is electrically connected to the conductor BG. Transistor WTr[ One of the sources or drains of [i] is electrically connected to the conductor 128[i], and the other is connected to the source or drain. It is electrically connected to conductor 128[i+1]. The gate of transistor WTr[i] is a conductor It is electrically connected to the electrostatic element WWL[i]. Note that the first and nth memory elements MC are The connection relationship with other elements and conductors is as follows: the memory element MC[1] and the memory element MC You can refer to the connection relationships described in [5].

[0272] Transistors STr1, STr2, and STr3 are, for example, It can be an OS transistor or a Si transistor. At least one of the transistors STr1, STr2, and STr3 One is an OS transistor, and the others may be Si transistors. When both transistor WTr and transistor RTr are formed with OS transistors, Transistor STr1, transistor STr2, and transistor STr3 are also OS Transistors It is preferable to form it with a t. By arranging the semiconductor materials used for the transistor, semiconductor This can increase the productivity of the equipment.

[0273] Furthermore, an OS transistor is used for the WTr transistor, and a Si transistor is used for the RTr transistor. A zista may be used. An OS transistor is used as the transistor WTr, and the transistor Equivalent circuit diagram of memory string 120 when using a Si transistor as RTr. This is shown in Figure 36.

[0274] When forming the transistor RTr with a Si transistor, the semiconductor 125 is, for example, polycrystalline. Silicon can be used. When forming a WTr transistor with an OS transistor, For example, CAAC-IGZO can be used for conductor 127. In this case, transistor STr 1. An OS transistor is used for transistor STr3, and S is used for transistor STr2. It is preferable to use an i-transistor.

[0275] Furthermore, as shown in Figure 37, depending on the purpose or application, the transistor WTr may be used A Si transistor may be used, and an OS transistor may be used as the transistor RTr. In this case, Si transistors are used for transistors STr1 and STr3. It is preferable to use an OS transistor for transistor STr2. Also, in Figure 38 As shown, depending on the purpose or application, transistors WTr and R Si transistors may be used for both Tr. Transistor WTr and transistor When using Si transistors for both RTr, transistor STr1, transistor It is preferable to use Si transistors for STr2 and transistor STr3 as well.

[0276] <Example of memory string operation> Next, we will explain an example of the operation of the memory string 120 shown in Figure 34.

[0277] [Writing operation] This section describes an example of operation when writing a high potential or low potential to a memory element MC. Figure 39 shows the writing process. This is a timing chart explaining the operation. Figures 40A to 41B show the write operation. This is a circuit diagram to explain the circuit.

[0278] Initially, an L potential is written to memory element MC[1] through memory element MC[5]. It shall be so. Also, conductors WWL[1] to WWL[5], conductors RWL[1] Conductors RWL[5], conductors SEL, conductors BG, conductors WBL, conductors RBL, Assume that an L potential is supplied to the electric element SG, conductor WSL, and conductor RSL. Oh, the conductive BG can control the threshold voltage of the transistor RTr. To ensure that the zista RTr becomes the desired normally-on type transistor, a conductive BG is supplied. The potential may be adjusted as appropriate. The conductor SEL is connected to transistor STr2 and transistor Although it is explained that the gate of the ZISTA STr3 is a common conductor, different conductors are used. You may do so.

[0279] [Period T1] During period T1, the conductor WWL[3] was kept at L potential, while the conductor WWL[1] and the conductor Body WWL[2], conductor WWL[4], conductor WWL[5], conductor SG, and conductor A high potential is supplied to the SEL (see Figure 40A). Also, the conductors WSL and WBL are supplied. Then, either the H potential or the L potential is supplied to each. The potential of the conductor WSL is supplied to node 1] through node ND[3], and node ND[4] and Node The potential of the conductor WBL is supplied to the ND[5].

[0280] [Period T2] During period T2, an L potential is supplied to the conductor WWL[2] and the conductor WWL[4]. See Figure 40B.) Then, transistors WTr[2] and WTr[4] The device is turned off, and the charge written to nodes ND[3] and ND[4] is retained. It will be done.

[0281] [Period T3] During period T3, the potential of the conductor WSL is supplied to nodes ND[1] and ND[2]. The potential of the conductor WBL is supplied to node ND[5]. (See Figure 40B.)

[0282] [Period T4] During period T4, an L potential is supplied to the conductor WWL[1] and the conductor WWL[5]. See Figure 41A.) Then, transistors WTr[1] and WTr[5] The device is turned off, and the charges written to nodes ND[2] and ND[5] are retained. It will be done.

[0283] [Period T5] During period T5, the potential of the conductor WSL is supplied to node ND[1]. (See Figure 41A) Light. ).

[0284] [Period T6] During period T6, an L potential is supplied to the conductor SG (see Figure 41B). Then, The zistor STr1 is turned off, and the charge written to node ND[1] is retained. In this case, an L potential may be supplied to the conductor SEL.

[0285] In this way, information can be written to the memory element MC.

[0286] Memory string 120 writes information to both conductive WSL and conductive WBL. This can be done from memory element MC[3] and memory element MC[4] Simultaneous writing is possible. Furthermore, memory element MC[3] and memory element MC[ After writing to [4], simultaneously write to memory element MC[2] and memory element MC[5] Writing can be performed. In this way, multiple memory elements within one memory string 120 Because it is possible to write to child memory controllers simultaneously, the information writing speed can be increased. This allows for a more reliable supply of charge corresponding to the information being written. ru.

[0287] Furthermore, when writing information to the i-th memory element MC, if i is close to n, the conductor WBL side By writing information from there, information is written to memory elements MC from the 1st to the i-1th. The operation can be omitted. Also, if i is close to 1, information is written from the conductive WSL side. By doing so, the write operation for the information of memory elements MC from the (i+1)th to the nth element is omitted. This is possible. In memory string 120, the time and power consumption associated with the write operation are reduced. It can be reduced.

[0288] In this embodiment, during the writing operation, an L potential is constantly supplied to the conductor WWL[3]. The device is then used to write to memory elements MC[1] through MC[3] from the conductive WSL side. Furthermore, writing to memory elements MC[4] and MC[5] is performed from the conductor WBL side. Although an example has been shown, the present invention is not limited thereto. Any conductor WWL[i] can be used as a boundary for memory elements. Writing to MC[1] or memory element MC[i] is performed from the conductive WSL side, and memory element M Writing to C[i+1] or memory element MC[n] may be performed from the conductor WBL side. Furthermore, writing to memory elements MC[1] through MC[n] is performed from the conductive WSL side. Alternatively, writing to memory element MC[1] to memory element MC[n] may be done via the conductor WBL. You can go from the side.

[0289] [Read operation] An example of the read operation of the memory string 120 in the above circuit configuration will be explained. Initially, Conductor WWL[1] to Conductor WWL[5], Conductor RWL[1] to Conductor RWL[5] Conductor SG, Conductor SEL, Conductor BG, Conductor WSL, Conductor RSL, Conductor WB Assume that L and the conductor RBL are supplied with an L potential. Figure 42 shows the readout operation. This is a timing chart for explanation. Figures 43A to 45 are for explaining the read operation. This is the circuit diagram.

[0290] In this embodiment, the operation of sequentially reading memory elements MC[1] to MC[5] is performed. I will explain.

[0291] [Period T7] During period T7, the conductors RWL[2] to RWL[5], conductor SEL, and A high potential is supplied to the conductor RSL (see Figure 43A). Then, the transistor RTr[2 Transistor RTr[5] turns ON. Also, transistor STr2 turns ON. In this state, the semiconductor 127 of the transistor RTr and the conductor RBL become electrically connected.

[0292] At this time, if a high potential is maintained at node ND[1] of memory element MC[1], then conductivity Even if the potential supplied to the body RWL[1] is an L potential, the transistor RTr[1] is O This results in a state where the conductor RSL and the conductor RBL are connected to the transistor RTr[1] or The transistor RTr[5] becomes conductive, and the H potential supplied to the conductor RSL It can be detected on the conductor RBL side. That is, the node ND[ of memory element MC[1] It is possible to detect that the potential held in [1] is the H potential. Note that the conductor RBL is It is preferable to functionally connect to the RBL driver 2004, which is equipped with a amplifier, etc. (See Figures 1A and 1B.)

[0293] On the other hand, when an L potential is maintained at node ND[1] of memory element MC[1], conductor R Since the potential supplied to WL[1] is L potential, transistor RTr[1] is in the OFF state. This is the state in which the conductor RSL and conductor RBL do not conduct electricity, and therefore, the supply to conductor RSL The H potential cannot be detected on the conductor RBL side. Therefore, the conductor RBL side In this case, it is confirmed that an L potential is maintained at node ND[1] of memory element MC[1]. It can be released.

[0294] [Period T8] Next, during period T8, a high potential is supplied to the conductor RWL[1] and to the conductor RWL[2] An L potential is supplied (see Figure 43B). At this time, node ND[2] of memory element MC[2] is supplied. If an H potential is maintained in [ ], then the potential supplied to the conductor RWL[2] is an L potential. However, transistor RTr[2] remains in the ON state. Therefore, conductor RSL and conductor R BL becomes conductive via transistors RTr[1] through RTr[5]. Therefore, the H potential supplied to the conductor RSL can be detected on the conductor RBL side. The potential held at node ND[2] of memory element MC[2] is a high potential. It can be detected.

[0295] On the other hand, when an L potential is maintained at node ND[2] of memory element MC[2], conductor R Since the potential supplied to WL[2] is L potential, transistor RTr[2] is in the OFF state. This is the state in which the conductor RSL and conductor RBL do not conduct electricity, and therefore, the supply to conductor RSL The H potential cannot be detected on the conductor RBL side. Therefore, the conductor RBL side In this case, it is confirmed that an L potential is maintained at node ND[2] of memory element MC[2]. It can be released.

[0296] [Period T9] Next, during period T9, an H potential is supplied to the conductor RWL[2], and to the conductor RWL[3] An L potential is supplied (see Figure 44A). At this time, node ND[3] of memory element MC[3] If an H potential is maintained in [3], then the potential supplied to the conductor RWL[3] is an L potential. However, transistor RTr[3] remains in the ON state. Therefore, conductor RSL and conductor R BL becomes conductive via transistors RTr[1] through RTr[5]. Therefore, the H potential supplied to the conductor RSL can be detected on the conductor RBL side. The potential held at node ND[3] of memory element MC[3] is the H potential. It can be detected.

[0297] On the other hand, when an L potential is maintained at node ND[3] of memory element MC[3], conductor R Since the potential supplied to WL[3] is L potential, transistor RTr[3] is in the OFF state. This is the state in which the conductor RSL and conductor RBL do not conduct electricity, and therefore, the supply to conductor RSL The H potential cannot be detected on the conductor RBL side. Therefore, the conductor RBL side In this case, it is confirmed that an L potential is maintained at node ND[3] of memory element MC[3]. It can be released.

[0298] [Period T10] Next, during period T10, an H potential is supplied to the conductor RWL[3], and the conductor RWL[4] An L potential is supplied to (see Figure 44B). At this time, the node ND[ of memory element MC[4] If an H potential is maintained in [4], then the potential supplied to the conductor RWL[4] is an L potential. Even so, transistor RTr[4] remains in the ON state. Therefore, conductor RSL and conductor The RBL is in a conductive state via transistors RTr[1] through RTr[5] Therefore, the H potential supplied to the conductor RSL can be detected on the conductor RBL side. Furthermore, the potential held at node ND[4] of memory element MC[4] is a high potential. It can be detected.

[0299] On the other hand, when an L potential is maintained at node ND[4] of memory element MC[4], conductor R Since the potential supplied to WL[4] is an L potential, transistor RTr[4] is in an OFF state. This is the state in which the conductor RSL and conductor RBL do not conduct electricity, and therefore, the supply to conductor RSL The H potential cannot be detected on the conductor RBL side. Therefore, the conductor RBL side In this case, it is confirmed that an L potential is maintained at node ND[4] of memory element MC[4]. It can be released.

[0300] [Period T11] Next, during period T11, an H potential is supplied to the conductor RWL[4], and the conductor RWL[5] An L potential is supplied to (see Figure 45). At this time, the node ND[5] of the memory element MC[5] If an H potential is maintained in [ ], then the potential supplied to the conductor RWL[5] is an L potential. However, transistor RTr[5] remains in the ON state. Therefore, conductor RSL and conductor R BL becomes conductive via transistors RTr[1] through RTr[5]. Therefore, the H potential supplied to the conductor RSL can be detected on the conductor RBL side. The potential held at node ND[5] of memory element MC[5] is a high potential. It can be detected.

[0301] On the other hand, when an L potential is maintained at node ND[5] of memory element MC[5], conductor R Since the potential supplied to WL[5] is L potential, transistor RTr[5] is in the OFF state. This is the state in which the conductor RSL and conductor RBL do not conduct electricity, and therefore, the supply to conductor RSL The H potential cannot be detected on the conductor RBL side. Therefore, the conductor RBL side In this case, it is confirmed that an L potential is maintained at node ND[5] of memory element MC[5]. It can be released.

[0302] In this way, by detecting the potential held at nodes ND[1] to ND[5] The information in memory elements MC[1] to MC[5] can be read out. In this embodiment, information is sequentially read from memory element MC[1] to memory element MC[5]. The example shown is not limited to this. Information is sequentially transferred from memory element MC[5] to memory element MC[1]. You may read the report.

[0303] Furthermore, it is not always necessary to read the information from memory elements MC[1] to MC[5]. The information of any memory element MC[i] can be read. At this time, the conductor RWL[ A low potential is supplied to i], and a high potential is supplied to the other conductor RWL, and the conductor RBL side is led Whether or not the potential of the RSL of the electrostatic element can be detected determines whether it is retained in node ND[i] of memory element MC[i]. The generated potential can be detected, and the information from the memory element MC[i] can be read.

[0304] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0305] (Embodiment 3) In this embodiment, an example configuration of a semiconductor device 200 including a storage device 100 will be described.

[0306] Figure 46 shows a block diagram illustrating an example configuration of a semiconductor device 200 according to one aspect of the present invention. The semiconductor device 200 shown in 46 includes a drive circuit 210 and a memory array 220. The memory array 220 has one or more storage devices 100. In Figure 46, the memory array 2 The diagram shows an example having multiple storage devices 100 arranged in a matrix.

[0307] The drive circuit 210 includes PSW241 (power switch), PSW242, and peripheral circuit 2 It has 15. Peripheral circuit 215 is peripheral circuit 211, control circuit 212 (Cont It has a voltage generation circuit ( rol Circuit) and a voltage generation circuit 228. 0 represents memory array 220, PSW241, 242, peripheral circuit 211, control circuit It has elements or circuits with various functions, such as 212 and a voltage generation circuit 228. Therefore, the semiconductor device 200 may be referred to as a system or subsystem.

[0308] In the semiconductor device 200, each circuit, each signal, and each voltage are selected and discarded as necessary. This is possible. Alternatively, other circuits or other signals may be added. Signal BW, signal CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1 Signal PON2 is an external input signal, and signal RDA is an external output signal. CLK is the clock signal.

[0309] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal. These are signals; signal GW is the global write enable signal, and signal BW is the byte write enable signal. This is the write enable signal. Signal ADDR is the address signal. Signal WDA is the write enable signal. The data is as follows, and signal RDA is the read data. Signals PON1 and PON2 are, These are signals for power gating control. Note that signals PON1 and PON2 are control signals. It may also be generated by circuit 212.

[0310] The control circuit 212 has a logic control function that controls the overall operation of the semiconductor device 200. It is a logic circuit. For example, a control circuit uses signals CE, GW, and BW to logic. The system performs calculations to determine the operating mode of the semiconductor device 200 (e.g., write operation, read operation). Determine. Alternatively, the control circuit 212 controls the peripheral so that this operating mode is performed. Generates control signals for circuit 211.

[0311] The voltage generation circuit 228 has the function of generating a negative voltage. The signal WAKE is the power of the signal CLK. It has a function to control the input to the pressure generation circuit 228. For example, as the WAKE signal, it controls the H level. When a signal is applied, the signal CLK is input to the voltage generation circuit 228, and the voltage generation circuit 2 28 generates a negative voltage.

[0312] The peripheral circuit 211 is used to write and read data to and from the storage device 100. This is the circuit. Peripheral circuit 211 is a row decoder 221, column decoder Coder 222 (Column Decoder), Row Driver 223 (Row Driver) er), Column Driver 224, Input Circuit 225 t Cir.), Output circuit 226 (Output Cir.), Sense amplifier 227 (S It has an ense amplifier.

[0313] The row decoder 221 and column decoder 222 have the function of decoding the signal ADDR. The row decoder 221 is a circuit for specifying the row to access, and the column decoder 222 This is a circuit for specifying the column to access. The row driver 223 controls the row decoder 22 It has the function of selecting the conductor WWL specified by 1. The column driver 224 stores data. Function to write to device 100, function to read data from storage device 100, read data It has functions such as holding the tag.

[0314] The input circuit 225 has the function of holding the signal WDA. The data held by the input circuit 225 The output is sent to the column driver 224. The output data from the input circuit 225 is sent to the storage device 100. This is the data (Din) to be written. The column driver 224 read it from the storage device 100. The data (Dout) is output to the output circuit 226. The output circuit 226 retains Dout. It has the function of holding. In addition, the output circuit 226 outputs Dout to the outside of the semiconductor device 200. It has the function of performing an action. The data output from output circuit 226 is the RDA signal.

[0315] PSW241 provides V to peripheral circuit 215 DD It has the function of controlling the supply. PSW242 V to line driver 223 HM It has a function to control the supply of semiconductor devices. A high power supply voltage of 200 is V DD Therefore, the low power supply voltage is GND (ground potential). Also, V HM This is a high power supply voltage used to raise the word line to a high level, V DD Higher The on / off state of PSW241 is controlled by signal PON1, and by signal PON2. The on / off state of PSW242 is controlled. In Figure 46, in peripheral circuit 215, V DD The number of power domains supplied is set to 1, but it can be multiple. In this case, A power switch should be provided for each power domain.

[0316] The drive circuit 210 and the memory array 220 may be provided on the same plane. Also, as shown in Figure 47A The drive circuit 210 and the memory array 220 may be arranged in a stacked manner. By stacking the memory array 220, the signal propagation distance can be shortened. Furthermore, as shown in Figure 47B, multiple memory arrays 220 are stacked on top of the drive circuit 210. That's fine.

[0317] Furthermore, as shown in Figure 47C, the memory array 220 is located on the upper and lower layers of the drive circuit 210. A memory module may be provided. In Figure 47C, one memory module is provided on the upper and lower layers of the drive circuit 210. This shows an example of providing a rear array 220. The drive circuit 210 is used with multiple memory arrays 220. By arranging them in a sandwich-like manner, the signal propagation distance can be further shortened. A memory array 220 is stacked on top of the path 210, and a drive circuit 210 is stacked on the lower layer Each layer of the memory array 220 only needs to be one or more. The number of stacked memory arrays 220 and the memory arrays stacked below the drive circuit 210 It is preferable that the number 220 is equal.

[0318] <Example of cross-sectional configuration of semiconductor device 200> Figure 48 shows an example of the cross-sectional configuration of the semiconductor device 200 shown in Figure 47A. A portion of the semiconductor device 200 is shown.

[0319] Figure 48 shows the transistors 301, 302, and o included in the drive circuit 210. This indicates transistor 303. Furthermore, transistors 301 and 302 are part of the sense amplifier 227. It functions in this way. Also, transistor 303 functions as a column selection switch. Specifically, The conductor RBL included in the memory array 220 is the source and channel of transistor 301. Electrically connected to one side of the rain, the gate of transistor 301 is connected to transistor 302. The gate of transistor 302 is electrically connected to either the source or the drain. Connect electrically to either the source or drain of transistor 301. Also, transistor 3 The source and drain of transistor 01 and the gate of transistor 302 are connected to a column selection switch. It functions as electrically connected to either the source or drain of transistor 303. This makes it possible to reduce the layout area of ​​the semiconductor device 200. See Figure 48. This shows an example where five memory elements (MC) are provided per memory string. Furthermore, the number of memory elements MCs provided in a single memory string is not limited to this. For example, 1 The number of memory elements MC provided in each memory string is 32, 64, 128, or 200. That's fine too.

[0320] The conductor RBL of memory array 220 consists of conductor 715, conductor 714, conductor 705, and A conductor 752 is formed to be embedded in the insulator 726, insulator 722, etc. Through this, the sense amplifier 227 and the transistor 303, which functions as a column selection switch, are connected. They are electrically connected. Note that the circuits and transistors in the drive circuit 210 are just examples. This is not limited to the circuit configuration or transistor structure. In addition to the above, control circuits, row decorators The configuration of the semiconductor device 200, including drivers, line drivers, source line drivers, input / output circuits, etc. Depending on the driving method, appropriate circuits and transistors can be provided.

[0321] Transistors 301, 302, and 303 are located on substrate 311. These are semiconductors provided therein, each consisting of a conductor 316, an insulator 315, and a part of the substrate 311. Region 313, and low-resistance region 314a which functions as a source region or drain region, and has a low-resistance region 314b. Note that, as shown in Figure 48, one low-resistance region is The source region or drain region of one of the transistors 301 and 302 Furthermore, it may be shared as the source or drain area of ​​the other system.

[0322] Transistors 301, 302, and 303 form a channel. The resulting semiconductor region 313 (part of the substrate 311) has a convex shape. The sides and top surface of 13 are provided to be covered by a conductor 316 via an insulator 315. It is present. Furthermore, the conductor 316 may be made of a material that adjusts the work function. Transistor 301, transistor 302, and transistor 303 utilize the protrusions of the semiconductor substrate. It is also called a FIN type transistor because it uses this feature. Furthermore, the upper part of the convex part is in contact with the convex part. It may have an insulator that functions as a mask for forming the part. Also, here it is a semi The example shown involves processing a portion of a conductive substrate to form a protrusion, but the example also shows how to process an SOI substrate to create a protrusion. A semiconductor film having the following characteristics may be formed.

[0323] Transistors 301, 302, and 303 are each p-type Either a channel type or an n-channel type is acceptable. Also, transistor 301 and transistor The ZISTA302 can be transistors with the same polarity, or transistors with different polarities. A transistor would also be acceptable.

[0324] The region where the channel of the semiconductor region 313 is formed, the region near it, the source region, or the do In the low-resistance region 314a and low-resistance region 314b, which are rain regions, silico It is preferable that the semiconductor contains semiconductors such as silicon-based semiconductors, and it is preferable that it contains single-crystal silicon. Alternatively, Ge (germanium), SiGe (silicon germanium), GaAs (galvanium) It may also be formed from materials containing arginine, GaAlAs (gallium aluminum arsenide), etc. By applying stress to the crystal lattice and changing the lattice spacing, silicon with controlled effective mass is produced. The configuration used may also be used. Alternatively, by using GaAs and GaAlAs, etc., the transient Transistor 301, transistor 302, and transistor 303 are HEMT (High El It can also be called an ectron (Mobility Transistor).

[0325] Low-resistance regions 314a and 314b are semiconductor regions applied to semiconductor region 313. In addition to the main material, elements that impart n-type conductivity, such as arsenic and phosphorus, or p-type conductivity, such as boron. It contains elements that impart conductivity.

[0326] Insulator 315 is connected to transistors 301, 302, and 303 It functions as a gate insulating film.

[0327] The conductor 316, which functions as a gate electrode, is a component that imparts n-type conductivity, such as arsenic or phosphorus. Semiconductor materials such as silicon containing elements that impart p-type conductivity, such as boron or other elements. Conductive materials such as metallic materials, alloy materials, or metal oxide materials can be used.

[0328] Furthermore, since the work function is determined by the material of the conductor, changing the material of the conductor will result in... The voltage can be adjusted. Specifically, the conductive material can be titanium nitride or tantalum nitride. It is preferable to use the following material. Furthermore, in order to achieve both conductivity and embedding properties, the conductive material It is preferable to use metal materials such as tansten or aluminum as laminates, and especially tansten. Using gusten is preferable in terms of heat resistance.

[0329] Furthermore, an insulator 317, which functions as an etch stopper, is provided above the conductor 316. It is preferable that the sides of the insulator 315 have an insulating layer that functions as a spacer. It is preferable that a rim 318 is provided. Provide insulators 317 and 318. As a result, the low-resistance region 314a and the low-resistance region 314b are electrically connected to the conductor 328. The region can be defined in a self-consistent manner. Therefore, the low resistance region 314a and the low resistance region can be defined in a self-consistent manner. An alignment error occurred when forming an opening to expose a portion of the anti-region 314b. Even so, an opening can be formed to expose the intended area. By forming a conductor 328 in the formed opening, a low-resistance region 314a and a low-resistance region are created. A good contact with reduced contact resistance is obtained between region 314b and conductor 328. The low-resistance region 314a and the low-resistance region 314b formed in this manner are conductive The contact with body 328 is sometimes called self-aligned contact. Also, the insulator 317 and the conductor 316 are electrically connected so as to be embedded in the insulator 322. An electric unit 329 may be provided.

[0330] An insulator covers transistors 301, 302, and 303. 320, insulator 322, insulator 324, insulator 326, and insulator 327 are stacked in order. It is provided as such.

[0331] As insulators 320, 322, 324, 326, and 327 For example, silicon oxide, silicon nitride oxide, silicon nitride oxide, silicon nitride oxide, silicon oxide Aluminum oxide nitride, aluminum nitride oxide, aluminum nitride, etc. Just be there.

[0332] Insulators 320 and 322 are connected to transistors 301 and the like, located below them. It may also function as a planarizing film that flattens the resulting step. For example, insulation. The upper surfaces of one or both of the body 320 and the insulator 322 are chemically treated to improve flatness. The surface may be flattened by a planarization treatment such as mechanical polishing (CMP).

[0333] Furthermore, the insulator 324 receives memory signals from the substrate 311 or transistor 301, etc. A barrier film is used in the region where I-220 is provided to prevent the diffusion of hydrogen and impurities. It is preferable that they be present.

[0334] As an example of a film that has barrier properties against hydrogen, for example, silica nitride formed by CVD. A semiconductor element can be used. Here, a semiconductor element having an oxide semiconductor such as a memory element MC can be used. The diffusion of hydrogen may degrade the properties of the semiconductor element. Therefore, the memory element It is preferable to use a film that suppresses hydrogen diffusion between the MC and transistor 301, etc. Specifically, a membrane that suppresses hydrogen diffusion is a membrane that releases less hydrogen.

[0335] The amount of hydrogen desorbed can be analyzed, for example, using a thermodynamic desorption gas analysis (TDS) method. For example, the amount of hydrogen desorption from insulator 324 is determined in TDS analysis when the film surface temperature is 5 In the range of 0°C to 500°C, the amount of desorption converted to hydrogen atoms is per unit area of ​​insulator 324. Convert to units, 10 x 10 15 atoms / cm 2 The following is preferably 5 × 10 15 at oms / cm 2 The following is acceptable.

[0336] Furthermore, insulators 326 and 327 have a lower relative permittivity than insulator 324. Preferably, the relative permittivity of insulator 326 and insulator 327 is less than 4. Less than 3 is more preferable. Also, for example, the relative permittivity of insulator 326 and insulator 327 is The dielectric constant of the insulator 324 is preferably 0.7 times or less, and more preferably 0.6 times or less. By using a low-efficiency material as the interlayer film, parasitic capacitance between wiring connections can be reduced.

[0337] Also, insulators 320, 322, 324, 326, and 327 The memory array 220 is electrically connected to conductors 328, 329, and conductors 330 etc. are embedded. Note that conductors 328, 329, and 330 It functions as a plug or wiring. In some cases, conductive materials may have multiple structures grouped together and assigned the same designation. In such cases, the wiring and the plug that electrically connects to the wiring may be a single integrated unit. Furthermore, when a portion of the conductor functions as wiring, and when a portion of the conductor functions as a plug... In some cases, this may be the case.

[0338] The materials of each plug and wiring (conductor 328, conductor 329, and conductor 330, etc.) Conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials. It can be used in a single layer or in a laminated form. Tungsten and other materials that offer both heat resistance and conductivity. It is preferable to use high-melting-point materials such as molybdenum, and it is also preferable to use tungsten. It is preferable to form it with a low-resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using resistive conductive materials.

[0339] A wiring layer may be provided on the insulator 327 and the conductor 330. For example, as shown in Figure 48. Insulators 350, 352, and 354 are arranged in a sequential stack. Furthermore, a conductor 356 is formed on insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring. It can be provided using the same material as conductors 328, 329, and 330. Cut.

[0340] For example, insulator 350 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 356 has barrier properties against hydrogen. It is preferable that it contains a conductor. In particular, the insulator 350 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 301 and the memory element MC can be separated by a barrier layer, This can suppress the diffusion of hydrogen from ZISTA 301 and other sources to the memory element MC.

[0341] For example, tantalum nitride can be used as a conductor that has barrier properties against hydrogen. This is good. Also, by laminating tantalum nitride and highly conductive tungsten, the wiring can be It is possible to suppress the diffusion of hydrogen from transistor 301, etc., while maintaining conductivity. In this case, the tantalum nitride layer, which has barrier properties against hydrogen, acts as a barrier against hydrogen. It is preferable that the structure is in contact with an insulating material 350 having properties.

[0342] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, as shown in Figure 48. Insulators 360, 362, and 364 are arranged in a sequential stack. Furthermore, a conductor 366 is formed on insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. It can be provided using the same material as conductors 328, 329, and 330. Cut.

[0343] For example, insulator 360 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 366 has barrier properties against hydrogen. It is preferable that it contains a conductor. In particular, the insulator 360 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 301 and the memory element MC can be separated by a barrier layer, This can suppress the diffusion of hydrogen from ZISTA 301 and other sources to the memory element MC.

[0344] An insulator 722 is provided on the insulator 364 and the conductor 366, and further insulator 722 Above it, a memory array 220 is provided. Between insulator 364 and insulator 722 Alternatively, a barrier film made of the same material as the insulator 324 may be provided.

[0345] In the above example, the storage device 100 was shown to have a memory string 120, but The embodiments are not limited to those shown. As shown in Figure 49, the storage device 100 is as described in Figure 8. It may have a memory string 120A like that.

[0346] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0347] (Embodiment 4) This embodiment describes an application example of an information processing device according to one aspect of the present invention.

[0348] Generally, a computer consists of components such as a processor on the motherboard and main memory. It has storage and other components, and each component is connected, for example, by bus wiring, They are connected precisely. Therefore, the longer the bus wiring, the greater the parasitic resistance, so The power consumption required to transmit the signal will also increase.

[0349] Specifically, the computer would have a configuration like the one shown in Figure 50A. The computer has a motherboard BD, and on the motherboard BD there is a processing unit (Pro Processor, CPU, etc.) 10, Main memory (DRAM (Dynamic Random) Access Memory) etc.) 30, Storage (NAND type memory with a three-dimensional structure) The device includes 40 (devices, 3D OS NAND type memory devices, etc.) and interfaces 60. Figure 50 shows SRAM (Static) which also functions as main memory. Random Access Memory)20 is also shown in the diagram, but Motherboard B It is not necessary to place it on D.

[0350] Figure 50 illustrates a configuration in which the arithmetic processing unit 10 has registers 11.

[0351] In Figure 50A, the arithmetic processing unit 10 includes SRAM 20, main memory 30, and storage It is electrically connected to interface 40 and interface 60. Also, main memory 30 is electrically connected to SRAM20 and storage40.

[0352] Note that each component of the computer in Figure 50A is electrically connected by bus wiring (BSH). In other words, the more components a computer has, or the larger the motherboard BD, the more... The larger the bus, the longer the BSH bus wiring needs to be routed, and therefore the more power is required for transmission. The price will increase.

[0353] By the way, the computer in Figure 50A has all of its components on a single chip. You can combine them into a monolithic IC (Integrated Circuit). Furthermore, at this time, the information processing device described in the above embodiment is connected to the main memory 30 and It can be applied as storage 40. In this way, the computer in Figure 50A Figure 50B shows the monolithic IC configuration.

[0354] The monolithic IC in Figure 50B has a circuit layer LGC on a semiconductor substrate containing Si. Furthermore, the circuit layer LGC has a memory layer STR on top, and the circuit layer OSC has a memory layer STR on top. To possess.

[0355] The circuit layer LGC is, for example, a Si transistor formed on a Si semiconductor substrate SBT. It has multiple circuits, including the one shown in Figure 50A. This can include an arithmetic processing unit 10, an SRAM 20, etc. Furthermore, the information processing unit may be made When applied as memory 30 and storage 40, as part of the plurality of circuits, This can be the controller 1197 included in the information processing device 50.

[0356] In particular, SRAM20, as an example, uses Si transistors to create SRAM The drive frequency can be increased.

[0357] The memory layer STR is a memory unit having Si transistors and / or OS transistors. It works. As a memory layer STR, for example, a three-dimensional NAND type memory circuit, 3D It can be an OS NAND type memory circuit, etc. Therefore, the memory layer STR is information The processing unit includes a memory unit 1196 and a storage unit 40 in Figure 50A.

[0358] Furthermore, by using a 3D OS NAND type memory circuit, the monolith shown in Figure 50B This can reduce the power consumption of the IC.

[0359] The circuit layer OSC has, for example, a plurality of circuits including OS transistors. As part of this, for example, the arithmetic processing unit 10, SRAM 20, etc., are included in the circuit layer LGC. It can be a circuit different from the existing circuit.

[0360] In the monolithic IC shown in Figure 50B, a bus wiring BSH is provided for routing the connections onto the motherboard. Because they are not connected, the wiring that electrically connects each component to the others becomes shorter. This allows for lower power consumption required for signal transmission.

[0361] Furthermore, the monolithic IC in Figure 50B has an information processing device 50. Therefore, information The processing unit 50 has the roles of storage 40 and main memory 30 in Figure 50A. Therefore, in the monolithic IC of Figure 50B, the memory unit 1 of the memory layer STR functions. 196 can have the function of main memory 30.

[0362] In addition to not providing a bus wiring BSH, the storage unit 1196 is used as a substitute for the main memory 30. In this respect, the monolithic IC in Figure 50B has a larger circuit area than the computer in Figure 50A. This can be reduced.

[0363] Next, we will show an example of the memory hierarchy of the computer in Figure 50A and the monolithic IC in Figure 50B. These are shown in Figures 51A and 51B, respectively.

[0364] Generally, in a memory hierarchy, higher-level memory devices require faster operating speeds, while lower-level devices require faster operating speeds. The more a storage device is used, the greater the storage capacity and the higher the recording density required. Figure 51A shows an example. Then, starting from the top layer, the registers included in the CPU (arithmetic processing unit 10) and the SRAM and The DRAM included in the main memory 30 and the three-dimensional structure included in the storage 40 This shows a NAND type memory circuit.

[0365] The registers and SRAM included in the arithmetic processing unit 10 are used for temporary storage of calculation results, etc. Because it is used for this purpose, it is accessed frequently by the arithmetic processing unit 10. Therefore, rather than memory capacity Fast operating speed is required. Also, registers hold configuration information for the arithmetic processing unit. It also has functions.

[0366] The DRAM included in the main memory 30 is, for example, read from the storage 40. It has the function of holding recorded programs and data. The recording density of DRAM is approximately 0. 1~0.3Gbit / mm 2 That is the case.

[0367] Storage 40 stores data that needs to be stored long-term, as well as various programs used in the processing unit. It has the function of holding data such as m. Therefore, storage 40 has a larger memory capacity than the operating speed. High capacity and high recording density are required. The recording density of the storage device used in storage 40 is: Approximately 0.6 to 6.0 Gbit / mm 2 Therefore, as storage 40 Three-dimensional NAND type memory circuits, hard disk drives (HDDs), etc. are used. It can be done.

[0368] By the way, the monolithic IC in Figure 50B is the same as the storage 40 and main memory in Figure 50A. Because it has the role of R30, the memory hierarchy of the monolithic IC in Figure 50B is shown in Figure 51B. It becomes a ricket.

[0369] In other words, in the monolithic IC of Figure 50B, the storage unit of the information processing device 50 is included These memory cells are not only the cache memory of the storage unit, but also, in the computer shown in Figure 50A, It can be treated as main memory 30. Therefore, the monolithic IC in Figure 50B This eliminates the need to provide main memory 30 such as DRAM, so the monolith shown in Figure 50B This reduces the circuit area of ​​the IC, and also allows for the operation of main memory such as DRAM. This reduces the power consumption required for operation.

[0370] Note that the monolithic IC configuration shown in Figure 50B is just one example and is not limited to one aspect of the present invention. It is not done. The monolithic IC shown in Figure 50B may have its configuration changed depending on the situation. For example, in the monolithic IC shown in Figure 50B, for example, if the SRAM is 1 GHz or higher When high-speed memory is required, SRAM may be integrated into the arithmetic processing unit.

[0371] This embodiment can be appropriately combined with other embodiments shown herein. .

[0372] (Embodiment 5) In this embodiment, Figures 52A and 52B are used to show a semiconductor in which the storage device of the present invention is mounted. An example of a chip 1200, a type of conductive device, is shown. The chip 1200 contains multiple circuits ( The system is implemented. In this way, multiple circuits (systems) are integrated onto a single chip. The combined technologies are referred to as System on Chip (SoC). There is a match.

[0373] As shown in Figure 52A, the chip 1200 is a CPU 1211, a GPU 1212, or Multiple analog arithmetic units 1213, one or more memory controllers 1214, one or It has multiple interfaces 1215, one or more network circuits 1216, etc. .

[0374] The chip 1200 is provided with bumps (not shown), and as shown in Figure 52B, The first side of the Printed Circuit Board (PCB) 1201 and Connect. Also, multiple bumps 1202 are provided on the back surface of the first face of PCB1201. It is connected to the motherboard 1203.

[0375] Motherboard 1203 may also have sensors 1221, power supply circuits 1222, etc. stomach.

[0376] CPU1211 preferably has multiple CPU cores. Also, GPU1212 is It is preferable to have multiple GPU cores. Also, CPU1211 and GPU12 Each of the 12 components may have memory to temporarily store data. Alternatively, the CPU Even if memory common to both 1211 and GPU1212 is provided on chip 1200 Good. Also, the GPU1212 is suitable for parallel computation of large amounts of data, such as image processing and sum-of-products. It can be used for calculations. The GPU1212 is equipped with image processing circuits and multiply-accumulate circuits. This makes it possible to perform image processing and multiply-accumulate operations with low power consumption.

[0377] Furthermore, because the CPU1211 and GPU1212 are located on the same chip, C The wiring between PU1211 and GPU1212 can be shortened, and from CPU1211 Data transfer to GPU1212, CPU1211, and the memory of GPU1212 Data transfer between them, and after calculations on GPU1212, from GPU1212 to CPU121 The result of the calculation to 1 can be transferred at high speed.

[0378] The analog processing unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital) conversion circuit. It has one or both of the analog / analog conversion circuits. Also, the analog arithmetic unit 1213 The above-described sum-of-accumulate circuit may be provided.

[0379] The memory controller 1214 is a controller of a storage device according to one aspect of the present invention, and It has a circuit that functions as a interface.

[0380] Interface 1215 is for display devices, speakers, microphones, cameras, controllers It has an interface circuit for connecting to external devices such as rollers. The controller is a mouse This includes keyboards, game controllers, etc. USB (Universal Serial Bus), HDMI (Registered Trademark) (Hi-Fi) Using gh-Definition Multimedia Interface, etc. It is possible.

[0381] The network circuit 1216 connects to a LAN (Local Area Network), etc. It has a network circuit for connection. It also has a circuit for network security. It may have.

[0382] The above circuit (system) can be formed on chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, increasing the manufacturing process will not increase the number of circuits. This eliminates the need for additional components, allowing for the low-cost production of Chip 1200.

[0383] A PCB 1201 is provided with a chip 1200 having a GPU 1212, a sensor 1221, The motherboard 1203, which is equipped with a power supply circuit 1222, has a GPU module 120 It can be called 4.

[0384] The GPU module 1204 has a chip 1200 that uses SoC technology, It can reduce the size. Also, because it excels at image processing, smartphones Mobile devices such as phones, tablets, laptops, portable game consoles, etc. It is preferable to use it in strip-type electronic devices. Also, in multiply-accumulate circuits using the GPU1212. More specifically, deep neural networks (DNNs), convolutional neural networks ( CNN, Recurrent Neural Network (RNN), Autoencoder, Deep Boltzmann It can implement techniques such as DVM (Deep Belief Network) and DBN (Deep Belief Network). Therefore, the chip 1200 is the AI ​​chip, or the GPU module 1204 is the AI ​​system module. It can be used as a liter.

[0385] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. It is possible.

[0386] (Embodiment 6) This embodiment describes an application example of a semiconductor device using the memory device shown in the previous embodiment. Let me explain. The storage device shown in the above embodiment is a memory card (for example, an SD card), U Various removable storage devices such as SB memory and SSD (Solid State Drive) This can be applied to the following. Figures 53A to 53E show several configurations of removable storage devices. An example is schematically shown. For example, the semiconductor device shown in the above embodiment is packaged It is processed into memory chips and used in various storage devices and removable memory.

[0387] Figure 53A is a schematic diagram of a USB memory device. The USB memory device 1100 consists of a casing 1101 and a cable. It has a 1102, a USB connector 1103, and a circuit board 1104. The circuit board 1104 is It is housed in the enclosure 1101. For example, the circuit board 1104 contains a memory chip 1105, The controller chip 1106 is installed. The memory chip 1105 and others are implemented as described above. A storage device or semiconductor device shown in the form can be incorporated.

[0388] Figure 53B is a schematic diagram of the external appearance of an SD card, and Figure 53C is a schematic diagram of the internal structure of an SD card. This is a diagram. The SD card 1110 consists of the housing 1111, connector 1112, and circuit board 1113. It has. The circuit board 1113 is housed in the housing 1111. For example, the circuit board 1113 has, A memory chip 1114 and a controller chip 1115 are mounted on circuit board 111. By also providing a memory chip 1114 on the back side of 3, the capacity of the SD card 1110 can be increased. This is possible. Furthermore, a wireless chip with wireless communication capabilities may be provided on the substrate 1113. This allows wireless communication between the host device and the SD card 1110 to control the memory chip. This enables reading and writing of data to the 1114. The device can incorporate a storage device or semiconductor device as shown in the embodiment.

[0389] Figure 53D is a schematic diagram of the external appearance of an SSD, and Figure 53E is a schematic diagram of the internal structure of an SSD. The SSD1150 has a housing 1151, a connector 1152, and a circuit board 1153. The board 1153 is housed in the casing 1151. For example, the board 1153 has memory chips. 1154, memory chip 1155, and controller chip 1156 are installed. Memory chip 1155 is the work memory of controller chip 1156, for example DO An SRAM chip can be used. A memory chip 1154 is also provided on the back side of the circuit board 1153. This allows you to increase the capacity of the SSD1150. A storage device or semiconductor device as shown in the embodiment can be incorporated.

[0390] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0391] (Embodiment 7) Figures 54A to 54G show an electric device equipped with a storage device or semiconductor device according to one aspect of the present invention. Here are some specific examples of sub-devices.

[0392] <Electronic Equipment and Systems> A memory device or semiconductor device according to one aspect of the present invention can be mounted on various electronic devices. Yes, it can. Examples of electronic devices include, for example, information terminals, computers, smartphones, and electronic devices. Book terminals, television equipment, digital signage: Electronic signboards, large game machines such as pachinko machines, digital cameras, digital video cameras, Digital photo frames, mobile phones, portable game consoles, recording and playback devices, navigation systems Examples include systems and sound reproduction devices. Note that, here, "computer" refers to a tablet. In addition to laptop computers, notebook computers, and desktop computers, This includes large computers such as server systems.

[0393] An electronic device according to one aspect of the present invention may have an antenna. The antenna receives a signal. This allows the display unit to show images, information, etc. Also, electronic equipment can be used as an antenna and If a secondary battery is present, the antenna may be used for contactless power transmission.

[0394] An electronic device according to one aspect of the present invention includes sensors (force, displacement, position, velocity, acceleration, angular velocity, rotational speed). Distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, (Includes functions for measuring radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation) It's okay to do so.

[0395] An electronic device according to one aspect of the present invention can have various functions. For example, various information ( Functions to display still images, videos, text images, etc. on the display unit, touch panel function, calendar A function to display the date or time, and to run various software (programs). Functions include wireless communication and the ability to read programs or data recorded on a recording medium. They may possess abilities such as [specific abilities / skills].

[0396] [Information terminal] Using a storage device or semiconductor device according to one aspect of the present invention, the process of a microcontroller A memory device for holding gram data can be formed. Therefore, according to one aspect of the present invention, The cross-controller chip can be made smaller.

[0397] Figure 54A illustrates a mobile phone (smartphone), a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102, and an input interface The device features a touch panel on the display unit 5102 and buttons on the housing 5101. This is achieved by using a miniaturized microcontroller according to one aspect of the present invention. This allows for effective use of the limited space inside the mobile phone. Also, the mobile phone's storage A storage device according to one aspect of the present invention may be used for the storage. This allows for a larger storage capacity per unit area.

[0398] Figure 54B shows a notebook-type information terminal 5200. The information terminal comprises a main unit 5201, a display unit 5202, and a keyboard 5203. According to one aspect of the present invention, by using a miniaturized microcontroller, a notebook computer can be used. This allows for effective use of the limited space inside the information terminal. Furthermore, it allows for efficient use of the limited space inside the notebook-type information terminal. A storage device according to one aspect of the present invention may be used for the storage. This allows for a larger storage capacity per unit area.

[0399] In the above, smartphones and notebook computers were used as examples of electronic devices. As shown in Figures 54A and 54B respectively, smartphones and notebook information terminals External information terminals can be used. This includes smartphones and notebook computers. Examples of information terminals include PDAs (Personal Digital Assistants). Examples include ant, desktop information terminals, and workstations.

[0400] [Game console] Figure 54C shows a portable game console 5300, which is an example of a game console. Portable game console 5 300 consists of casing 5301, casing 5302, casing 5303, display unit 5304, and connection unit 530. 5. It has operation keys 5306, etc. Housing 5302 and housing 5303 are housing 5301 It can be removed from the housing 5301. The connection part 5305 provided on the housing 5301 can be connected to another housing By attaching it to the body (not shown), the video output to the display unit 5304 can be displayed on another video device. Output can be sent to (not shown). At this time, housing 5302 and housing 5303 Each of these can function as a control unit. This allows multiple players to play simultaneously. The game can be played. The circuit boards of cabinets 5301, 5302, and 5303 are A memory device or semiconductor device according to one aspect of the present invention is incorporated into a chip or the like. It can be placed inside.

[0401] Figure 54D also shows a home console 5400, which is an example of a game console. The stationary game console 5400 can be connected to controller 5402 wirelessly or via a wired connection. ru.

[0402] In one aspect of the present invention, a game console such as a portable game console 5300 or a home game console 5400 is provided. By using a miniaturized microcontroller, the limited space inside the game console can be utilized. This can be effectively utilized. Furthermore, in one aspect of the present invention, the storage of a portable game console can be used. The storage device or semiconductor device may be used. This allows for a larger storage capacity per unit area.

[0403] Figures 54C and 54D show examples of game consoles, including a handheld game console and a home console. Although the machine is shown in the illustration, a game machine to which a microcontroller according to one aspect of the present invention is applied is this The invention is not limited to the above. A game machine to which a microcontroller according to one aspect of the present invention is applied includes: For example, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) Examples include pitching machines for batting practice installed in sports facilities.

[0404] [Large computer] A storage device or semiconductor device according to one aspect of the present invention can be applied to a large computer. can.

[0405] Figure 54E shows an example of a large computer, the Supercomputer 5500. Yes. Figure 54F shows the rack-mount type computer 5 of the supercomputer 5500. This is a diagram of 502.

[0406] The supercomputer 5500 consists of rack 5501 and multiple rack-mount computers. It has 5502 and, in addition, multiple computers 5502 are stored in rack 5501. Furthermore, the computer 5502 is provided with multiple circuit boards 5504, and the present invention is placed on these circuit boards. A microcontroller according to one embodiment of the present invention can be mounted. By using standardized microcontrollers, the limited space of a large computer can be utilized. It can be used effectively. Furthermore, in one aspect of the present invention, it can be used in the storage of a large computer. The storage device or semiconductor device may be used. This allows for a larger storage capacity per unit area.

[0407] Figures 54E and 54F illustrate a supercomputer as an example of a large-scale computer. However, a large computer to which a microcontroller according to one aspect of the present invention is applied is The present invention is not limited to the application of a microcontroller according to one aspect of the present invention to a large computer. Examples of data sources include computers (servers) that provide services, and large-scale general-purpose computers. Examples include computers (mainframes).

[0408] [electric appliances] Figure 54G shows an example of an electrical appliance, the electric refrigerator-freezer 5800. The storage unit 5800 includes a casing 5801, a door for the refrigerator compartment 5802, a door for the freezer compartment 5803, and the like.

[0409] A storage device or semiconductor device according to one aspect of the present invention is applicable to an electric refrigerator 5800. It is also possible to use a miniaturized electric refrigerator 5800 according to one aspect of the present invention. By applying a microcontroller, the limited space in electric refrigerators and freezers can be utilized effectively. It can be used for this purpose.

[0410] I explained electric refrigerators as an example of electrical appliances, but other electrical appliances include: For example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, and hob. Heating and cooling appliances including heaters, air conditioners, washing machines, dryers, audio equipment Examples include casual equipment.

[0411] The electronic devices described in this embodiment, their functions, and their effects may differ from those of other electronic devices. This can be combined with the description as appropriate.

[0412] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible. [Explanation of Symbols]

[0413] 100 Storage device, 110 Memory cell array, 117 Insulator, 118 Insulator, 119 Conductor , 120 memory string, 121 substrate, 122 conductor, 123 insulator, 124 insulator, 125 Semiconductor, 126 Insulator, 127 Semiconductor, 128 Conductor, 129 Insulator, 130 Conductor Body, 132 insulator, 134 conductor, 136 conductor, 137 conductor, 138 insulator, 141 Opening, 150 insulator, 152 insulator, 156 insulator, 161 conductor, 162 conductor, 16 3 conductors, 164 conductors, 171 conductors, 172 conductors, 173 conductors, 174 conductors, 179 material, 180 material, 181 material, 182 material, 183 material, 184 conductor, 185 Insulators, 186 Insulators, 187 Conductors, 188 Insulators, 189 Insulators, 200 Semiconductors , 2000 drive circuit, 2001 WSL driver, 2002 WBL driver, 2003 RS L driver, 2004 RBL driver, 2005 WWL driver, 2006 RWL driver B, 2007SEL driver

Claims

[Claim 1] First conductor and, The second conductor above the first conductor, The third conductor above the second conductor, The fourth conductor above the third conductor, The fifth conductor above the fourth conductor, The sixth conductor above the fifth conductor, The seventh conductor and, First insulator and, The second insulator and, First semiconductor and, It has a second semiconductor, At least the third conductor and the fourth conductor each have an opening, In each of the openings, the first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in order from the inner side surface. In the region between the third conductor and the second insulator, the seventh conductor is provided between the first semiconductor and the second insulator. The first semiconductor is in contact with the upper surface of the second conductor and the side surface of the fifth conductor. The second semiconductor is in contact with the upper surface of the first conductor and the side surface of the sixth conductor. The third conductor has a region that overlaps with the fourth conductor and a region that does not overlap with the fourth conductor. The fourth conductor has a region that overlaps with the fifth conductor and a region that does not overlap with the fifth conductor. The fifth conductor has a region that overlaps with the sixth conductor and a region that does not overlap with the sixth conductor. The third conductor functions as the gate electrode of the first transistor. The second semiconductor has a region in which the channel of the first transistor is formed, The fourth conductor functions as the gate electrode of the second transistor. The first semiconductor has a region in which the channel of the second transistor is formed. storage device.

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