Method for manufacturing semiconductor devices

Abstract

A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided . A highly reliable semiconductor device is provided. [MEANS FOR SOLVING PROBLEMS] A semiconductor layer containing a metal oxide is formed, and a gate insulating film containing an oxide is formed over the semiconductor layer . A layer is formed, and a metal oxide layer is formed over the gate insulating layer. After forming the metal oxide layer, a heat treatment is performed , and after the heat treatment, the metal oxide layer is removed. After removing the metal oxide layer , a gate electrode overlapping with part of the semiconductor layer is formed over the gate insulating layer. Then, a first element is supplied to a region of the semiconductor layer that does not overlap with the gate electrode through the gate insulating layer . Examples of the first element include phosphorus, boron, magnesium, aluminum, and silicon and the like. The steps performed after removing the metal oxide layer are each preferably performed at a temperature equal to or lower than the temperature of the heat treatment . ​

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. Another aspect of the present invention relates to a display device. And the method of manufacturing the same.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. For example, semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, Input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and Examples of these driving methods, or methods for manufacturing them, can be given. Semiconductor devices This refers to all devices that can function by utilizing semiconductor properties. [Background technology]

[0003] Oxide semiconductors, which use metal oxides, are attracting attention as semiconductor materials applicable to transistors. For example, Patent Document 1 describes stacking multiple oxide semiconductor layers, and the multiple oxide In the semiconductor layer, the oxide semiconductor layer that forms the channel contains indium and gallium, By making the proportion of indium greater than the proportion of gallium, the field effect mobility (simply moving) A semiconductor device with increased (sometimes referred to as μFE) is disclosed.

[0004] Metal oxides that can be used in semiconductor layers can be formed using methods such as sputtering. Therefore, it can be used in the semiconductor layer of transistors that make up large display devices. We have modified and are utilizing some of the production equipment for transistors using polycrystalline silicon and amorphous silicon. Because this is possible, capital investment can be reduced. Also, transistors using metal oxides has higher field-effect mobility than in the case of using amorphous silicon, so a driver circuit can be provided, and a high-performance display device can be realized.

[0005] Further, Patent Document 2 discloses that in a source region and a drain region, an oxide semiconductor film including a low-resistance region containing at least one selected from the group consisting of aluminum, boron, gall ium, indium, titanium, silicon, germanium, tin, and lead as a dopant is applied to a thin film transistor. [Prior Art Documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Unexamined Patent Publication No. 2014-7399 [Patent Document 2] Japanese Unexamined Patent Publication No. 2011-228622 [Summary of Invention] [Problems to be Solved by the Invention]

[0007] An aspect of the present invention is to provide a semiconductor device with favorable electrical characteristics as one of its objects. Another aspect of the present inven tion is to provide a semiconductor device with stable electrical characteristics as one of its objects. A further aspect of the present invention is to provide a highly reliable semiconductor device as one of its objects.

[0008] Note that the description of these objects does not preclude the existence of other objects. One aspect of the present invention does not necessarily need to solve all of these objects. Other objects can be derived from the description of the specification, drawings, and clai ms. [Means for Solving the Problems]

[0009] ​One aspect of the present invention involves forming a semiconductor layer containing a metal oxide, and placing a metal oxide on the semiconductor layer. A gate insulating layer is formed, a metal oxide layer is formed on the gate insulating layer, and after the metal oxide layer is formed... The metal oxide layer is removed after heat treatment, and the metal oxide layer is removed After that, a gate electrode is formed on the gate insulating layer, overlapping with a part of the semiconductor layer, and in the semiconductor layer A semiconductor that supplies the first element to a region where the gate electrodes do not overlap, via a gate insulating layer. This describes the method for manufacturing the device.

[0010] The first element is, for example, phosphorus, boron, magnesium, aluminum, or silicon. be.

[0011] The metal oxide layer preferably has an aluminum oxide film. Alternatively, the metal oxide layer and Preferably, the semiconductor layer has the same metal oxide.

[0012] Each subsequent step after removing the metal oxide layer is performed at a temperature lower than or equal to the temperature of the heat treatment. It is preferable to do so.

[0013] The gate insulating layer consists of a first layer on the semiconductor layer, a second layer on the first layer, and a third layer on the second layer. It is preferable to have a layer. The deposition rate of the first layer is lower than the deposition rate of the second layer. Preferably, the deposition rate of the third layer is lower than the deposition rate of the second layer. [Effects of the Invention]

[0014] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one aspect of the present invention This enables the provision of a semiconductor device with stable electrical characteristics. According to one aspect of the present invention, a highly reliable semiconductor device can be provided. We can provide semiconductor devices.

[0015] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention is It is not necessarily required to have all of these effects. It is possible to extract effects other than those listed above. [Brief explanation of the drawing]

[0016] [Figure 1] (A) Top view showing an example of a transistor. (B), (C) Cross-sectional views showing an example of a transistor. [Figure 2] A cross-sectional view showing an example of a transistor. [Figure 3] (A) Top view showing an example of a transistor. (B), (C) Cross-sectional views showing an example of a transistor. [Figure 4] A cross-sectional view showing an example of a transistor. [Figure 5] A cross-sectional view showing an example of a transistor fabrication method. [Figure 6] A cross-sectional view showing an example of a transistor fabrication method. [Figure 7] A cross-sectional view showing an example of a transistor fabrication method. [Figure 8] A cross-sectional view showing an example of a transistor fabrication method. [Figure 9] A top view showing an example of a display device. [Figure 10] A cross-sectional view showing an example of a display device. [Figure 11] A cross-sectional view showing an example of a display device. [Figure 12] A cross-sectional view showing an example of a display device. [Figure 13] A cross-sectional view showing an example of a display device. [Figure 14] (A) Block diagram showing an example of a display device. (B), (C) Circuit diagrams showing an example of a display device. [Figure 15] (A), (C), (D) Circuit diagrams showing examples of display devices. (B) Timing chart of the display device. [Figure 16] A diagram showing an example of a display module. [Figure 17] A diagram showing an example of an electronic device. [Figure 18] A diagram showing an example of an electronic device. [Figure 19] A diagram showing an example of an electronic device. [Figure 20] A diagram showing an example of an electronic device. [Figure 21] A cross-sectional view showing the transistor of the comparative sample according to Example 1. [Figure 22] A graph showing the electrical characteristics of the transistor according to Example 1. [Figure 23] A graph showing the electrical characteristics of the transistor according to Example 1. [Figure 24] A graph showing the reliability evaluation results of the transistor according to Example 1. [Modes for carrying out the invention]

[0017] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be modified in various ways. It will be easily understood by those skilled in the art to obtain this. Therefore, the present invention is as shown in the embodiments below. The interpretation is not limited to the content stated herein.

[0018] In the configuration of the invention described below, the same part or part having a similar function is used. The same symbol is used consistently across different drawings, and explanations of its repetition are omitted. When referring to a function, the same hatch pattern may be used, and a specific symbol may not be assigned.

[0019] Furthermore, the position, size, and extent of each component shown in the drawings are, for the sake of ease of understanding, actually The location, size, and range may not be described. Therefore, the disclosed invention is not always Furthermore, it is not limited to the location, size, scope, etc., disclosed in the drawings.

[0020] Furthermore, the words "membrane" and "layer" may differ depending on the context or situation. And they can be interchanged. For example, the term "conductive layer" can be replaced with "conductive film." It is possible to change the term to this. Or, for example, the term "insulating film" can be changed to It is possible to change the term to "insulating layer".

[0021] In this specification, the channel length direction of a transistor refers to the source region and the drain region. It refers to one of the directions parallel to the straight line connecting the two points by the shortest distance. In other words, the channel length direction is This corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in the ON state. Furthermore, the channel width direction refers to the direction perpendicular to the channel length direction. Depending on the structure and shape of the zista, the channel length and channel width directions may not be uniquely determined. There are cases where this is the case.

[0022] In this specification, unless otherwise specified, off-current refers to the state in which the transistor is in the off state (non- This refers to the drain current when the circuit is in a conductive state or an interrupted state. The off state is particularly... Unless otherwise specified, in an n-channel transistor, the voltage between the gate and source is V gs Gashi Key value voltage V th Lower than (in p-channel transistors, V th (Higher than) It refers to.

[0023] (Embodiment 1) In this embodiment, Figures 1 to 8 show a semiconductor device and a method for manufacturing the same according to one aspect of the present invention. This will be explained using the following. In this embodiment, the semiconductor device will be a transistor, specifically explain.

[0024] A semiconductor device according to one aspect of the present invention has a semiconductor layer containing a metal oxide, and an oxide is formed on the semiconductor layer. A gate insulating layer containing a material is formed, and a metal oxide layer is formed on the gate insulating layer, and the metal oxide layer After forming, heat treatment is performed, and after the heat treatment, the metal oxide layer is removed, and metal oxidation After removing the material layer, a gate electrode is formed on the gate insulating layer, overlapping with a portion of the semiconductor layer, and then... In the region of the conductive layer where the gate electrodes do not overlap, the first element is supplied via the gate insulating layer. It is formed by supplying (also called adding or injecting) a substance.

[0025] In one aspect of the present invention, after forming a semiconductor layer, a gate insulating layer, and a metal oxide layer, the gate Before forming the electrodes, a heat treatment is performed. In this heat treatment, the gate insulating layer is heated to form the semiconductor layer. It can supply oxygen.

[0026] The metal oxide layer is preferably formed in an oxygen-containing atmosphere. During the deposition of the physical layer, oxygen can be supplied to the gate insulating layer and even to the semiconductor layer.

[0027] The metal oxide layer is preferably impermeable to oxygen. This is because it is contained in the gate insulating layer. This suppresses the release of oxygen to the metal oxide layer and ensures that the oxygen is supplied to the semiconductor layer. This can facilitate the oxygen vacancy (V) in the semiconductor layer. O :oxygen vaca Also called ncy.) It can compensate for this and improve the reliability of the transistor. .

[0028] For example, an aluminum oxide film can be used as the metal oxide layer.

[0029] Alternatively, it is preferable that the metal oxide layer and the semiconductor layer have the same metal oxide.

[0030] If the metal oxide layer is conductive, the metal oxide layer is processed into an island shape and left as is, gate electrode It can be considered to be used as part of [something]. However, depending on the material and processing method of the metal oxide layer... However, processing can be difficult in some cases. For example, if a defect occurs in the shape of the metal oxide layer, the metal oxide... The coverage of the layer formed on top of the material layer will decrease.

[0031] Furthermore, even if the metal oxide layer is insulating, leaving the metal oxide layer intact will result in a loss. When used as part of an insulating layer, it can reduce the reliability of the transistor. For example, Depending on the film quality of the metal oxide layer, the interface between the previously formed gate insulating layer and the metal oxide layer Alternatively, a defect level may be formed in its vicinity.

[0032] Here, one of the indicators used to evaluate the reliability of a transistor is the gate bias heat (Gat There is a stress test (Bias Temperature). The GBT stress test is additional. This is a type of rapid test that quickly assesses the changes in transistor characteristics that occur due to long-term use. It can be evaluated. In particular, the gate has a positive voltage relative to the source potential and drain potential. A test called PBTS (Positive Bias Test) involves applying a potential and holding the device at a high temperature. Temperature stress test: With a negative potential applied to the gate, high A test that involves holding the product under temperature conditions is called NBTS (Negative Bias Temperature Testing). This is called a stress test. It is also called a PBT (Photon-Based Test) performed under light irradiation, such as white LED light. The S trial and the NBTS trial were each conducted using PBTIS (Positive Bias System). Perature Illumination Stress) Test, NBTIS (Ne gative Bias Temperature Illumination Str It's called the ESS exam.

[0033] In an n-type transistor using a metal oxide as the semiconductor layer, the transistor is in the ON state. When the gate is set to a state where current is flowing, a positive potential is applied to it, therefore in PBTS testing... The fluctuation in key voltage is one of the important factors to consider as an indicator of transistor reliability. This is the result.

[0034] If there is a metal oxide layer between the gate electrode and the gate insulating layer, if there is no metal oxide layer Compared to the case where the threshold voltage fluctuation in the transistor's PBTS test is large, Yes (see Example 1).

[0035] Therefore, in one aspect of the present invention, the metal oxide layer is completely removed after the heat treatment. Removing the metal oxide layer can improve the reliability of the transistor.

[0036] The metal oxide layer is preferably removed by wet etching. By using this method, etching of the gate insulating layer simultaneously with the metal oxide layer is suppressed. Yes, it is possible. This suppresses the decrease in the thickness of the gate insulating layer, and the thickness of the gate insulating layer It can be made uniform.

[0037] Subsequently, a gate electrode is formed, and the gate electrode is used as a mask to supply the first element to the semiconductor layer. By doing so, a pair of low-resistance regions can be formed in the semiconductor layer. In other words, the semiconductor layer , a channel formation region overlapping the gate electrode, and a pair of low-resistance regions flanking the channel formation region It is formed to have a region and a .

[0038] The first element is, for example, phosphorus, boron, magnesium, aluminum, or silicon. be.

[0039] Furthermore, the aforementioned heat treatment is performed to supply sufficient oxygen from the gate insulating layer to the semiconductor layer, comparatively It is preferable to carry out the process at a high temperature (e.g., 350°C). On the other hand, after removing the metal oxide layer, Compared to when a metal oxide layer was provided, oxygen escapes from the semiconductor layer and gate insulating layer. In some cases, oxygen may be present in the channel formation region or gate insulating layer of the semiconductor layer. This could lead to diffusion into low-resistance regions or gate electrodes. Therefore, the metal oxide layer is removed. The subsequent steps are preferably carried out at a temperature lower than or equal to the temperature of the aforementioned heat treatment. This suppresses the formation of oxygen vacancies in the semiconductor layer. When oxygen deficiency is low and carrier density is low, the transistor's off-current can be significantly reduced. Furthermore, it can improve the reliability of transistors.

[0040] Generally, to reduce the resistance of silicon, it is necessary to add impurities and then perform a heat treatment. On the other hand, semiconductor layers containing metal oxides become less resistive simply by supplying the first element. Therefore, there is no need for heat treatment to reduce resistance. Consequently, the metal oxide layer is removed. Even after a subsequent process to form a pair of low-resistance regions in the semiconductor layer, oxygen vacancies are not sufficiently reduced. Therefore, a channel formation region with extremely low carrier density and a source region with extremely low electrical resistance and A semiconductor layer can be formed that combines a drain region and a drain region, exhibiting excellent electrical properties, and This enables the realization of highly reliable semiconductor devices.

[0041] Furthermore, in one aspect of the present invention, the first element can also be supplied to the gate insulating layer. Specifically In particular, by using the gate electrode as a mask, in the gate insulating layer, mainly the semiconductor layer The first element is supplied to the region overlapping with the low-resistance region, and overlaps with the channel formation region of the semiconductor layer. The first element is difficult to supply to this part. Therefore, heating treatment is performed after the first element has been supplied. When this process is performed, oxygen is supplied from the gate insulating layer to the channel formation region, and channel formation occurs. The oxygen deficiency in the region is filled. On the other hand, in the low-resistance region, oxygen is supplied from the gate insulating layer. Because it is difficult, the electrical resistance does not increase easily. From this, it can be seen that oxygen deficiency is sufficiently reduced, A channel-forming region with extremely low carrier density, and a source region and drain region with extremely low electrical resistance. It is possible to form a semiconductor layer that combines the in-region and other properties, resulting in excellent electrical characteristics and reliability. This enables the realization of highly efficient semiconductor devices.

[0042] [Configuration Example 1] Figure 1(A) shows a top view of transistor 100. Figure 1(B) shows the same as in Figure 1(A). A cross-sectional view is shown between the dashed line A1 and A2. Figure 1(C) shows the dashed line B1 in Figure 1(A). -A cross-sectional view between B1 and B2 is shown. The dashed line A1-A2 direction is the channel length direction, and the dashed line B1-B The two directions correspond to the channel width direction. Note that Figure 1(A) shows the configuration of transistor 100. Some elements (such as the gate insulating layer) are omitted in the diagram. (Regarding the top view of the transistor) In subsequent drawings, as in Figure 1(A), some of the components will be omitted from the illustration.

[0043] The transistor 100 consists of an insulating layer 103, an island-shaped semiconductor layer 108, a gate insulating layer 110, and a gate It has an electrode 112 and an insulating layer 118.

[0044] The insulating layer 103 is provided on the substrate 102. The semiconductor layer 108 is on the insulating layer 103. It is provided. The gate insulating layer 110 is located on the upper surface of the insulating layer 103 and the semiconductor layer 108 It is in contact with the top and side surfaces. The gate electrode 112 is provided on the gate insulating layer 110. The gate electrode 112 has a portion that overlaps with the semiconductor layer 108 via the gate insulating layer 110. The insulating layer 118 is on the upper surface of the gate insulating layer 110 and the upper surface of the gate electrode 112 and It is installed to cover the sides.

[0045] The transistor 100 is a top-gate type having a gate electrode 112 on a semiconductor layer 108. It is a transistor.

[0046] As shown in Figures 1(A) and (B), the transistor 100 has a conductive layer 12 on an insulating layer 118. It may have conductive layer 0a and conductive layer 120b. Of conductive layer 120a and conductive layer 120b One side functions as the source electrode, and the other side functions as the drain electrode. Conductive layer 120a And the conductive layer 120b is provided in the insulating layer 118 and the gate insulating layer 110 respectively. The opening 141a or the opening 141b is electrically connected to the low-resistance region 108n, which will be described later. It will continue.

[0047] The semiconductor layer 108 has a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor properties. It is preferable to do so.

[0048] The semiconductor layer 108 has a region that overlaps with the gate electrode 112 and a pair of low-resistance regions flanking that region. It has 108n and the region in the semiconductor layer 108 that overlaps with the gate electrode 112 is tra It functions as a channel-forming region where channels can be formed in the inverter 100. A pair of low-resistance The resist region 108n functions as the source region and drain region of transistor 100.

[0049] The low-resistance region 108n is a region with lower resistance than the channel-forming region. Regions with high carrier density, regions with higher oxygen deficiency density than channel formation regions, channel shape This region can also be described as a region with a higher impurity concentration than the compound region, or as a region that is n-type.

[0050] The low-resistance region 108n is a region containing one or more impurity elements. Examples of elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, and aluminum. nium, magnesium, silicon, and noble gases (helium, neon, argon, cryptonium) Examples include boron, phosphorus, and aluminum. The pair of low-resistance regions 108n are boron, phosphorus, aluminum, and aluminum. Preferably contains aluminum, magnesium, or silicon, and boron or phosphorus. It is preferable to do so.

[0051] Furthermore, due to the effects of heat during the manufacturing process, the above-mentioned impurities are included in the low-resistance region 108n. Some of the elemental material may diffuse into the channel-forming region. The concentration of the element is preferably less than one-tenth of the concentration of the impurity element in the low-resistance region 10⁸n. Ideally, it should be less than 1 / 100.

[0052] The gate insulating layer 110 is in contact with the channel formation region of the semiconductor layer 108, and the gate electrode 1 It has a region that overlaps with 12. The gate insulating layer 110 is a pair of low-resistance regions of the semiconductor layer 108. It has a region that is in contact with 108n and does not overlap with the gate electrode 112.

[0053] If the semiconductor layer 108 contains a metal oxide, the gate insulating layer 110 preferably contains an oxide. In particular, it is preferable that the gate insulating layer 110 is an oxide film that can release oxygen when heated. It seems so.

[0054] Heating with a gate insulating layer 110 containing oxide in contact with the upper surface of the semiconductor layer 108. By performing this process, oxygen released from the gate insulating layer 110 is supplied to the semiconductor layer 108. This allows for the elimination of oxygen vacancies in the semiconductor layer 108, and improves reliability. This makes it possible to realize high-performance transistors.

[0055] In one aspect of the present invention, the formation of the gate electrode 112 and the supply of impurity elements to the semiconductor layer 108 Prior to this, a heat treatment is performed to supply oxygen from the gate insulating layer 110 to the semiconductor layer 108. On the other hand, transistors, or semiconductor devices and display devices having such transistors, etc. Depending on the configuration, the formation of the gate electrode 112 and the supply of impurity elements to the semiconductor layer 108 may occur. In some cases, further heat treatment may be performed after this. At this time, the channel shape of the semiconductor layer 108 There is a risk that oxygen contained in the compound region may diffuse into the low-resistance region 108n or the gate electrode 112. There is also the possibility that oxygen is supplied from the gate insulating layer 110 to the low-resistance region 108n. Yes. When oxygen is supplied to the low-resistance region 10⁸n, the carrier density decreases, and the electrical resistance increases. It may rise.

[0056] Therefore, the region of the gate insulating layer 110 that is in contact with the pair of low-resistance regions 108n, that is Preferably, the above-mentioned impurity elements are contained in a region that does not overlap with the gate electrode 112. In the region of the gate insulating layer 110 that does not overlap with the gate electrode 112, the impurity concentration is such that the gate insulating layer It is higher than the region overlapping with the gate electrode 112 in the marginal layer 110, and lower than the low resistance region 108n. It is preferable to have a region with low oxygen content. The oxide film that can release oxygen by heating is provided with the above-mentioned By supplying impurity elements, the amount of oxygen released can be reduced. Therefore, the region of the gate insulating layer 110 that is in contact with the low-resistance region 108n contains the aforementioned impurity elements. If this is the case, oxygen will not be easily supplied from the gate insulating layer 110 to the low-resistance region 108n. The low-resistance region 108n can maintain a low electrical resistance.

[0057] This configuration significantly reduces oxygen deficiency and allows for extremely low carrier density. It combines a channel-forming region with a source region and a drain region with extremely low electrical resistance. This enables the realization of semiconductor devices with excellent electrical properties and high reliability.

[0058] The insulating layer 103 and the gate insulating layer 110 that are in contact with the channel formation region of the semiconductor layer 108 are It is preferable that each contains an oxide. The insulating layer 103 and the gate insulating layer 110 each Therefore, oxide films such as silicon oxide films, silicon oxide nitride films, and aluminum oxide films are used. This allows for insulation during heat treatment and other processes in the manufacturing of transistor 100. Oxygen detached from layer 103 and gate insulating layer 110 is introduced into the channel formation region of semiconductor layer 108. This can supply oxygen and reduce oxygen deficiencies in the semiconductor layer 108.

[0059] Figure 2 shows an enlarged cross-sectional view of the region P enclosed by the dashed line in Figure 1(B).

[0060] The gate insulating layer 110 has a region 110d containing the aforementioned impurity elements. Region 110d This is located at least at or near the interface between the gate insulating layer 110 and the low-resistance region 108n. Region 110d is an area where the semiconductor layer 108 and gate electrode 112 are not provided. In the region, at least at the interface between the gate insulating layer 110 and the insulating layer 103 or in its vicinity It is located. Also, as shown in Figures 1(B), 1(C), and 2, region 110d is Preferably, it is not provided in the portion of the semiconductor layer 108 that is in contact with the channel formation region. .

[0061] The insulating layer 103 has the aforementioned impurity elements at or near the interface with the gate insulating layer 110. It has a region 103d containing an element. Also, as shown in Figure 2, region 103d is an insulating layer It may also be provided at or near the interface where 103 and the low-resistance region 108n come into contact. At this time, in region 103d, the impurity concentration in the part that overlaps with the low-resistance region 108n is The concentration will be lower in the area in contact with the insulating layer 110.

[0062] Here, the impurity concentration in the low-resistance region 108n is higher the closer it is to the gate insulating layer 110. It is preferable to have a concentration gradient that increases the resistance. Since the resistance is lower towards the top, the contact resistance with conductive layer 120a (or conductive layer 120b) is... It can be reduced more effectively. In addition, a uniform concentration can be achieved throughout the entire low-resistance region 10⁸n. Compared to the case where the total amount of impurity elements in the low-resistance region 108n can be reduced, thus enabling fabrication. To keep the amount of impurities that can diffuse into the channel-forming region due to the effects of heat during the process to a minimum. It is possible.

[0063] Furthermore, the impurity concentration in region 110d increases as it approaches the low-resistance region 108n. It is preferable to have a concentration gradient such as that. Apply an oxide film that can release oxygen by heating. In the gate insulating layer 110, in the region 110d containing the aforementioned impurity elements, other regions Compared to the region, oxygen release can be suppressed. Therefore, the low-resistance region of the gate insulating layer 110 Region 110d, located at or near the interface with region 108n, is blocking to oxygen. It functions as a layer and can effectively reduce the oxygen supplied to the low-resistance region 10⁸n. ru.

[0064] The supply of impurity elements is performed by using the gate electrode 112 as a mask to at least the semiconductor layer 108. In response to this, it is preferable to also supply the impurity element to the gate insulating layer 110. This is how the low-resistance region 108n is formed, and at the same time, region 110d is self-aligned. It can be formed.

[0065] In Figure 2, etc., the portion of the gate insulating layer 110 with a high impurity concentration is shown to be in contact with the semiconductor layer 108. To exaggerate its location at or near the interface, region 110d is designated as the gate insulating layer. Although the hatching pattern is shown only in the vicinity of the semiconductor layer 108 in 110, in reality In this case, the above-mentioned impurity elements are contained throughout the entire thickness direction of the gate insulating layer 110.

[0066] The supply of impurity elements can be performed by plasma ion doping or ion implantation. These methods are preferable because they allow for easy adjustment of the depth to which ions are added to the gate insulating layer 1 This makes it easier to add ions to the region including 10 and the semiconductor layer 108.

[0067] The supply conditions for impurity elements are the region of the semiconductor layer 108 on the gate insulating layer 110 side, or the semiconductor the impurity concentration at or near the interface between the body layer 108 and the gate insulating layer 110 is maximized is preferably set. This allows an impurity element of an appropriate concentration to be supplied to both the semiconductor layer 108 and the gate insulating layer 110 in a single step. Furthermore, by supplying the impurity element at a high concentration to the upper portion of the low-resistance region 108n to reduce the resistance, the contact resistance between the low-resistance region 10 8n and the source electrode or the drain electrode can be lowered. In addition, by forming a region with a high impurity element concentration in a portion of the gate insulating layer 1 10 close to the low-resistance region 108n, the oxygen diffusivity in this portion decreases, and diffusion of oxygen in the gate insulating layer 110 toward the low-resistance region 108n side can be further suppressed.

[0068] Each of the low-resistance region 108n and the region 110d preferably has an impurity concentration of 1×10 19 atom s / cm 3 or more and 1×10 23 atoms / cm 3 or less, preferably 5×10 19 atom s / cm 3 or more and 5×10 22 atoms / cm 3 or less, more preferably 1×10 20 at oms / cm 3 or more and 1×10 22 atoms / cm 3 or less. It is preferable to include a region that is In addition, it is preferable that the low-resistance region 108n has a portion with a higher impurity concentration than the region 110d of the gate insulating layer 110, because the electric resistance of the low-resistance region 108n can be further reduced.

[0069] The concentration of the impurity contained in each of the low-resistance region 108n and the region 110d is measured by, for example, secondary ion mass ​Analysis method (SIMS: Secondary Ion Mass Spectrometry) ) and X-ray Photoelectron Spectroscopy (XPS). It can be analyzed using analytical methods such as troscopy. When using XPS analysis... This is achieved by combining ion sputtering from the front or back side with XPS analysis. This allows us to determine the concentration distribution in the depth direction.

[0070] When using elements that readily bond with oxygen as impurity elements, the impurity elements are present in the semiconductor layer 108. It exists in a state bonded with oxygen. In other words, the impurity element removes oxygen from the semiconductor layer 108. As a result, oxygen vacancies are created in the semiconductor layer 108, and these oxygen vacancies combine with hydrogen in the film. Carriers are generated in this way. Furthermore, the impurity elements in semiconductor layer 108 are stable in an oxidized state. Because it exists in a stable state with low electrical resistance, it is less likely to desorb due to heat applied during the process. A low resistance range of 10⁸n can be achieved.

[0071] When using elements that readily bond with oxygen as impurity elements, the gate is formed similarly to semiconductor layer 108. Even in the insulating layer 110, impurity elements exist in a state of being bonded with oxygen. By bonding with other elements and becoming stable, in regions containing impurity elements, oxygen is hardly present even when heated. This results in a state where almost no desorption occurs, and oxygen does not easily diffuse into other layers. While suppressing the supply of oxygen from the insulating layer 110 to the low-resistance region 108n, the channel Oxygen can be supplied to the resistance formation region. Therefore, the resistance of the low-resistance region 108n can be increased. This prevents oxygen deficiency in the channel formation region while reducing it. As a result, the electrical properties are good. This enables the creation of highly reliable transistors.

[0072] The impurity elements are stabilized by bonding with oxygen in the semiconductor layer 108 and the gate insulating layer 110. It is preferable to use elements. For example, elements whose oxides can exist as solids under standard conditions. It is preferable to use the following elements. Particularly preferred elements include noble gases and typical nonmetals other than hydrogen. Examples include elements, typical metal elements, and transition metal elements, particularly boron, phosphorus, and aluminum. Magnesium and silicon are preferred.

[0073] For example, when boron is used as an impurity element, the low resistance region 108n and region 110d are The boron contained can exist in a state of being bound to oxygen. This is evident in XPS analysis. This can be confirmed by observing spectral peaks caused by the B2O3 bond. Furthermore, XPS In the analysis, spectral peaks were observed that were caused by the element boron existing in its elemental form. The peak intensity is either absent or so low that it is buried in the background noise at the lower limit of measurement. It becomes smaller.

[0074] The insulating layer 118 functions as a protective layer to protect the transistor 100. It has the function of preventing oxygen that may be released from the gate insulating layer 110 from diffusing to the outside. This is preferable. For example, inorganic insulating materials such as oxides or nitrides can be used. More specific examples include silicon nitride, silicon nitride oxide, silicon oxide nitride, and silicon oxide. Aluminum oxide, aluminum nitride, aluminum nitride, hafnium oxide, hafnium Inorganic insulating materials such as luminescent materials can be used.

[0075] [Configuration Example 2] Figure 3(A) shows a top view of transistor 100A. Figure 3(B) shows the same as in Figure 3(A). Figure 3(C) shows a cross-sectional view between the dashed line A1 and A2 in Figure 3(A). A cross-sectional view between 1 and B2 is shown. The dashed line A1-A2 direction is the channel length direction, and the dashed line B1- The B2 direction corresponds to the channel width direction.

[0076] The transistor 100A has a conductive layer 106 between the substrate 102 and the insulating layer 103. , it is different from transistor 100. The conductive layer 106 is connected to the semiconductor layer 108 and the gate electrode 112. It has overlapping areas.

[0077] In transistor 100A, the conductive layer 106 is the first gate electrode (bottom gate electrode). It functions as a second gate electrode (also known as the top gate electrode), and the gate electrode 112 has the function of a second gate electrode (top gate electrode). It functions as an electrode. Also, a part of the insulating layer 103 is the first gate insulating layer. It functions as such, and a portion of the gate insulating layer 110 functions as a second gate insulating layer.

[0078] The portion of the semiconductor layer 108 that overlaps with at least one of the gate electrode 112 and the conductive layer 106 , it functions as a channel formation region. For the sake of simplicity, the semiconductor layer 10 The part that overlaps with gate electrode 112 of 8 is sometimes called the channel formation region, but in reality it is The portion that does not overlap with electrode 112 but overlaps with conductive layer 106 (the portion including the low-resistance region 108n) Channels can also be formed there.

[0079] Furthermore, as shown in Figure 3(C), the conductive layer 106 is connected to the gate insulating layer 110 and the insulating layer 103 It may be electrically connected to the gate electrode 112 through an opening 142 provided therein. This allows the conductive layer 106 and the gate electrode 112 to be given the same potential.

[0080] The conductive layer 106 is made of the same material as the gate electrode 112, conductive layer 120a, or conductive layer 120b. Materials can be used. In particular, using a material containing copper in the conductive layer 106 reduces wiring resistance. This is preferable because it allows for this.

[0081] Furthermore, as shown in Figures 3(A) and 3(C), in the channel width direction, gate electrode 1 It is preferable that 12 and the conductive layer 106 protrude outward beyond the edge of the semiconductor layer 108. i. At this time, as shown in Figure 3(C), the entire channel width direction of the semiconductor layer 108 is The gate electrode 112 and conductive layer 106 are covered via insulating layer 110 and insulating layer 103. This will form the structure.

[0082] With this configuration, the semiconductor layer 108 is heated by the electric field generated by the pair of gate electrodes. , it can be electrically surrounded. In particular, the conductive layer 106 and the gate electrode 112 are the same It is preferable to apply a potential. This induces a channel in the semiconductor layer 108. Because the electric field can be applied effectively, the on-current of the 100A transistor can be increased. This makes it possible to miniaturize the 100A transistor.

[0083] Furthermore, the gate electrode 112 and the conductive layer 106 may not be connected. A constant potential is applied to one of the pair's gate electrodes, and a signal is applied to the other to drive transistor 100A. A number may be assigned. At this time, the potential applied to one electrode determines the transistor 100A The threshold voltage when driving with the other electrode can also be controlled.

[0084] [Application Examples] Next, as an example of application, a semiconductor device according to one aspect of the present invention having a transistor and a capacitive element... Next, we will explain using Figure 4. Specifically, the semiconductor layer 108c containing impurities is used as a capacitive element. This section describes an example where one electrode is used, and a transistor and a capacitive element are formed on the same plane. do.

[0085] The capacitive element 130A shown in Figure 4(A) corresponds to transistor 100 (Figures 1(A) to 1(C)). It is installed alongside it.

[0086] The capacitive element 130A shown in Figure 4(B) is the transistor 100A (Figures 3(A) to 3(C)). It is located next to ).

[0087] Capacitive element 130A functions as a dielectric between semiconductor layer 108c and conductive layer 120b. The device has a configuration in which a gate insulating layer 110 and an insulating layer 118 are provided.

[0088] The semiconductor layer 108c is provided on the same plane as the semiconductor layer 108. For example, semiconductor layer 10 8c is formed by processing the same metal oxide film as the semiconductor layer 108, and then the same low-resistance region 108n as 8c. It can be formed by supplying impurity elements.

[0089] This configuration allows for the simultaneous production of transistors and capacitive elements without increasing the manufacturing process. 130A can be produced.

[0090] The capacitive element 130B shown in Figure 4(C) is the transistor 100A (Figures 3(A) to 3(C)). It is located next to ).

[0091] Capacitive element 130B functions as a dielectric between the conductive layer 106c and the semiconductor layer 108c. It has a configuration in which an insulating layer 103 is provided.

[0092] The conductive layer 106c is provided on the same plane as the conductive layer 106. The conductive layer 106c is conductive It can be formed by processing the same conductive film as layer 106.

[0093] Capacitive element 130B can have a thinner dielectric thickness compared to capacitive element 130A, thus enabling larger It can be used as a capacitive element.

[0094] [Components of semiconductor devices] Next, the components included in the semiconductor device of this embodiment will be described in detail. Explanations of components that have already been described may be omitted.

[0095] There are no major restrictions on the material of the substrate 102, but it should at least be able to withstand subsequent heat treatment. It needs to be heat resistant. For example, single crystal semiconductors made from silicon or silicon carbide. Conductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates Glass substrates, ceramic substrates, quartz substrates, sapphire substrates, etc., are used as substrate 102. It is also possible to use a substrate 102 on which semiconductor elements are provided. It's okay to be there.

[0096] Furthermore, a flexible substrate is used as the substrate 102, and the transistor 100 is directly mounted on the flexible substrate. The following may be formed. Alternatively, a release layer may be provided between the substrate 102 and the transistor 100, etc. This is also fine. The delamination layer is applied to the substrate 102 after the semiconductor device has been partially or completely completed on it. It can be separated and used to transfer to another substrate. In this case, transistor 100 etc. It can also be transferred to substrates with poor heat resistance or flexible substrates.

[0097] For example, the insulating layer 103 may be an oxide insulating film or a nitride insulating film, either as a single layer or in multiple layers. It can be formed. Furthermore, in order to improve the interface characteristics with the semiconductor layer 108, the insulating layer 1 In 03, it is preferable that at least the region in contact with the semiconductor layer 108 be formed of an oxide insulating film. Furthermore, it is preferable to use a film that releases oxygen when heated for the insulating layer 103. .

[0098] For example, the insulating layer 103 can be silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride Silicon, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide Any suitable material can be used, and it can be provided in a single layer or in multiple layers.

[0099] Furthermore, on the side of the insulating layer 103 that is in contact with the semiconductor layer 108, there is a silicon nitride film or other oxide film besides the silicon nitride film. When a film is used, the surface in contact with the semiconductor layer 108 is subjected to pretreatment such as oxygen plasma treatment. It is preferable to oxidize the surface or the vicinity of the surface.

[0100] The gate electrode 112, the conductive layer 106 which functions as a gate electrode, and the source electrode and The conductive layers 120a and 120b, which function as rain electrodes, are made of chromium, copper, and aluminum. Um, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel Metal elements selected from iron, cobalt, and the aforementioned metal elements, or alloys composed of the above metal elements, or These can be formed using alloys or the like that combine the aforementioned metallic elements.

[0101] Furthermore, the gate electrode 112, conductive layer 106, conductive layer 120a, and conductive layer 120b are provided with I n-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-T i-Sn oxide, In-Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide Apply oxide conductors (OC) or metal oxides such as the above. It is also possible to do so.

[0102] Furthermore, oxygen vacancies are formed in a metal oxide having semiconductor properties, and hydrogen is added to these oxygen vacancies. Then, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive. It becomes conductive. A metal oxide that has become conductive can be called an oxide conductor (OC). .

[0103] Furthermore, the gate electrode 112 and the conductive layer 106 are made of the above-mentioned oxide conductor (metal oxide). The conductive film may be a laminated structure of a conductive film containing a metal or alloy. By using a conductive film containing an alloy, wiring resistance can be reduced. The side of pole 112 that contacts the gate insulating layer 110 or the side of conductive layer 106 that contacts the insulating layer 103 It is preferable to apply a conductive film containing an oxide conductor to this.

[0104] Furthermore, the gate electrode 112, conductive layer 106, conductive layer 120a, and conductive layer 120b are These are particularly titanium, tungsten, tantalum, and molybdenum among the aforementioned metallic elements. It is preferable to have one or more selected from the following. In particular, tantalum nitride It is preferable to use a film. The tantalum nitride film is conductive and contains copper, oxygen, or Because it has high barrier properties against hydrogen and releases little hydrogen from itself, semiconductor layer 1 It is suitable as a conductive film in contact with 08, or as a conductive film in the vicinity of the semiconductor layer 108.

[0105] The gate insulating layer 110 may be a silicon oxide film, a silicon oxide nitride film, or silicon nitride oxide. Films, silicon nitride films, aluminum oxide films, hafnium oxide films, yttrium oxide films, acids Zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, tantalum oxide An insulating layer containing one or more of the following is used: a cerium oxide film, a neodymium oxide film, and a neodymium oxide film. Yes, it is possible. Furthermore, the gate insulating layer 110 is not limited to a single layer, but can also be a laminated structure of two or more layers. stomach.

[0106] In the gate insulating layer 110, at least the region in contact with the semiconductor layer 108 is an oxide insulating film. It is preferable that there be a region containing an excess of oxygen compared to the stoichiometric composition. It is preferable. In other words, the gate insulating layer 110 is an insulating film that can release oxygen. Yes. For example, forming the gate insulating layer 110 under an oxygen atmosphere, and the gate insulating layer after film formation. Heat treatment, plasma treatment, etc., are performed on the margin layer 110 under an oxygen atmosphere, or The gate insulating layer 110 is formed by depositing an oxide film on the insulating layer 110 under an oxygen atmosphere. It can also supply oxygen to the 10.

[0107] Furthermore, the gate insulating layer 110 has a relative permittivity that is lower than silicon oxide and silicon oxide nitride. High-quality materials such as hafnium oxide can also be used. This allows for the gate insulating layer 110 to form a film. Increasing the thickness can suppress leakage current due to tunnel current. In particular, crystalline HAF oxide Nium is preferred because it has a higher dielectric constant compared to amorphous hafnium oxide.

[0108] The semiconductor layer 108 preferably has an oxide semiconductor. Alternatively, the semiconductor layer 108 may be It may contain silicon. Examples of silicon include amorphous silicon and crystalline silicon. Examples include silicon (low-temperature polysilicon, single-crystal silicon, etc.).

[0109] The semiconductor layer 108 is, for example, made of indium and M (where M is gallium, aluminum, and silico). N, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel Germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium (One or more selected from luminous, tantalum, tungsten, and magnesium), and sub It is preferable that it contains lead. In particular, M is aluminum, gallium, yttrium, It is preferable that the material be one or more selected from tin.

[0110] In particular, the semiconductor layer 108 is composed of indium (In), gallium (Ga), and zinc (Zn). It is preferable to use an oxide containing (also written as IGZO).

[0111] If the semiconductor layer 108 is In-M-Zn oxide, in order to deposit the In-M-Zn oxide film The atomic ratio of the metal elements used in the sputtering target is In:M:Zn = 1:1 :1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn =1:3:4, In:M:Zn=1:3:6, In:M:Zn=2:1:3, In:M: Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, I n:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6 Examples include In:M:Zn=5:2:5.

[0112] When using a target containing a polycrystalline oxide as a sputtering target, the crystal This is preferable because it facilitates the formation of a semiconductor layer 108 having properties. The atomic ratio of 10⁸ is the atomic ratio of the metal elements contained in the above sputtering target. Includes a variation of plus or minus 40%. For example, the sputtering process used for semiconductor layer 108 When the composition of the film is In:Ga:Zn=4:2:4.1 [atomic ratio], the resulting film is semi-semi The composition of the conductive layer 108 is close to In:Ga:Zn=4:2:3 [atomic ratio]. be.

[0113] Furthermore, when the atomic ratio is stated as In:Ga:Zn=4:2:3 or close to it, In When the atomic ratio is set to 4, the atomic ratio of Ga is between 1 and 3, and the atomic ratio of Zn is between 2 and 3. This includes cases where the number of atoms is 4 or less. Also, the atomic ratio is In:Ga:Zn=5:1:6 or When describing them as neighbors, if the atomic ratio of In is 5, then the atomic ratio of Ga is 0.1 This includes cases where the number of atoms of Zn is greater than or equal to 2 and is between 5 and 7. When describing the numerical ratio as In:Ga:Zn = 1:1:1 or close to it, the atoms of In When the numerical ratio is set to 1, the atomic ratio of Ga is greater than 0.1 and less than or equal to 2, and the atomic number of Zn This includes cases where the ratio is greater than 0.1 and less than or equal to 2.

[0114] In semiconductor layer 108, if the atomic ratio of In is higher than the atomic ratio of M (e.g., Ga), This is preferable as it can increase the field-effect mobility of the transistor. Also, in the semiconductor layer 108 Furthermore, if the atomic ratio of M (for example, Ga) is higher than that of In, oxygen vacancies will not form. Hmm, that's nice.

[0115] Furthermore, the semiconductor layer 108 may have multiple metal oxide layers stacked on top of each other. 08 may, for example, have two or more metal oxide layers with different crystalline properties.

[0116] For example, as the first metal oxide film to be formed, the atomic ratio of In is M (e.g., Ga) It forms an In-M-Zn oxide film with a higher atomic ratio, and later forms a second metal oxide film. Then, an In-M-Zn oxide film is created in which the atomic ratio of M (for example, Ga) is higher than the atomic ratio of In. It is preferable to form this. This increases the field-effect mobility of the transistor and semi This suppresses oxygen deficiency in the conductor layer 108, thereby improving the electrical characteristics and reliability of the transistor. can.

[0117] Alternatively, by using the same sputtering target but varying the deposition conditions, exposure to the atmosphere can be reduced. It is preferable to form multiple metal oxide layers continuously without interruption.

[0118] For example, the oxygen flow rate ratio during the formation of the first metal oxide film, which is formed earlier, is set to the ratio of the second film, which is formed later. The oxygen flow rate ratio during the formation of the metal oxide film is made smaller than that during the formation of the metal oxide film. Alternatively, the formation of the first metal oxide film During film formation, conditions are set to prevent oxygen from flowing. This ensures that oxygen is not allowed during the formation of the second metal oxide film. It can effectively supply [the substance]. Also, the first metal oxide film is more [conducive to] the second metal oxide film. It can also be made into a film with low crystallinity and high electrical conductivity. On the other hand, the second is provided on top. By making the metal oxide film more crystalline than the first metal oxide film, the semiconductor layer 10 This can suppress damage that occurs during processing of part 8 and during the deposition of the gate insulating layer 110.

[0119] More specifically, the oxygen flow rate ratio during the deposition of the first metal oxide film is set to 0% or more and less than 50%, More preferably 0% to 30%, more preferably 0% to 20%, and typically 10%. Furthermore, the oxygen flow rate ratio during the deposition of the second metal oxide film is preferably 50% to 100%. More preferably 60% to 100%, more preferably 80% to 100%, even more preferably The percentage is between 90% and 100%, typically 100%. Also, the first metal oxide film and The conditions for deposition, such as pressure, temperature, and power, may be different for the second metal oxide film, but acid By keeping all conditions except the raw flow rate the same, the time required for the film deposition process can be shortened. Therefore, it is preferable.

[0120] Here, we will explain the oxygen vacancies that can be formed in the semiconductor layer 108.

[0121] Oxygen vacancies formed in semiconductor layer 108 are problematic because they affect transistor characteristics. For example, when an oxygen vacancy is formed in the semiconductor layer 108, hydrogen bonds to the oxygen vacancy. It can become a carrier source. When a carrier source is generated in semiconductor layer 108, The electrical characteristics of the ZISTA 100 will fluctuate, typically resulting in a shift in the threshold voltage. In the semiconductor layer 108, the fewer oxygen vacancies there are, the better.

[0122] Therefore, in one embodiment of the present invention, the insulating film near the semiconductor layer 108, specifically the semiconductor The gate insulating layer 110 located above layer 108 and the insulating layer 103 located below it are acid The structure includes a phosphate film. Due to heat during the manufacturing process, the insulating layer 103 and the gate insulating layer 11 By moving oxygen from 0 to semiconductor layer 108, oxygen vacancies in semiconductor layer 108 are reduced. This becomes possible.

[0123] The following section describes metal oxides applicable to semiconductor layers.

[0124] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxi d) may be collectively referred to. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride (met al oxynitride). For example, a metal oxide containing nitrogen such as zinc oxynitride (ZnON) ma y be used for the semiconductor layer.

[0125] Note that in this specification and the like, CAAC (c-axis aligned crystal ) and CAC (Cloud-Aligned Composite) may be described in some case s. CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material composition.

[0126] For example, CAC (Cloud-Aligned Composite)-O S can be used for the semiconductor layer.

[0127] CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in another part of the material, and functions as a semiconductor in the entire material. Note that when CAC-OS or CAC-metal oxide is used for an active layer of a transistor , the conductive function is a function of causing electrons (or holes) serving as carriers to flow , and the insulating function is a function of not causing electrons serving as carriers to flow. The conductive function and the insulating functio n are caused to act complementarily to each other, whereby a switching function (On / Of f function) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating the respective functions , both functions can be maximized.

[0128] Further, CAC-OS or CAC-metal oxide includes a conductive region and an insulating It has regions. The conductive region has the conductive function described above, and the insulating region has the insulating function described above. It has the function of [this]. Furthermore, within the material, the conductive region and the insulating region are at the nanoparticle level. In some cases, they are separated by a rib. Also, conductive regions and insulating regions are located within the material. They may be unevenly distributed. Furthermore, the conductive regions appear blurred around the edges and connected in a cloud-like pattern. There are cases where this occurs.

[0129] Furthermore, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region The marginal region is defined as being between 0.5 nm and 10 nm, preferably between 0.5 nm and 3 nm. These particles may be dispersed in the material at the following sizes.

[0130] Furthermore, CAC-OS or CAC-metal oxide has different band gaps. It is composed of the following components. For example, CAC-OS or CAC-metal oxi de consists of a component with a wide gap due to the insulating region and a component with a wide gap due to the conductive region. It consists of a component having a low gap. In this configuration, when the carrier is flowing... In components with a narrow gap, the carrier mainly flows. A component having a wide gap acts complementaryly with a component having a narrow gap. In conjunction with the components, carriers also flow to components with a wide gap. Therefore, the above C AC-OS or CAC-metal oxide is applied to the channel formation region of the transistor. When used, a high current driving force is required in the transistor's ON state, i.e., a large ON current. Furthermore, a high field-effect mobility can be obtained.

[0131] In other words, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite (metal It can also be called a matrix composite.

[0132] Oxide semiconductors (metal oxides) include single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. It can be divided into two parts. Examples of non-single-crystal oxide semiconductors include CAAC-OS(ca xis aligned crystalline oxide semiconductor tor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxi de semiconductor), pseudo-amorphous oxide semiconductor (a-like OS: (Amorphous-like oxide semiconductor), and amorphous Examples include phosphate oxide semiconductors.

[0133] CAAC-OS has c-axis orientation and multiple nanocrystals are linked in the ab-plane direction. Furthermore, it has a distorted crystal structure. Note that distortion refers to the region where multiple nanocrystals are connected. Within the region, between a region with aligned lattice arrangements and another region with aligned lattice arrangements, This refers to the part where the direction has changed.

[0134] Nanocrystals are based on a hexagonal structure, but they are not necessarily regular hexagons; they can also be non-regular hexagonal. Yes, it exists. Furthermore, the distortion may have a grid arrangement such as pentagons and heptagons. In CAAC-OS, even near strain, clear grain boundaries are present. It is also said that it is difficult to confirm the grain boundaries. In other words, due to the distortion of the lattice arrangement, It can be seen that the formation of is suppressed. This is because the CAAC-OS in the a-b plane direction allows strain to be tolerated due to factors such as the non-dense arrangement of oxygen atoms and the change in interatomic bond distance caused by substitution of metal elements and the like.

[0135] In addition, the CAAC-OS tends to have a layered crystal structure in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M , zinc, and oxygen (hereinafter referred to as a (M, Zn) layer) are stacked (also referred to as a layered structure). Note that indium and the element M can substitute for each other , and when the element M in the (M, Zn) layer is substituted with indium, it can also be expressed as an (In, M, Zn) layer. Further, when indium in the In layer is substituted with the element M, it can also be expressed as an (In, M) layer.

[0136] The CAAC-OS is a metal oxide with high crystallinity. On the other hand, since it is difficult to clearly observe distinct crystal grain boundaries in the CAAC-OS , it can be said that a decrease in electron mobility due to crystal grain boundaries is unlikely to occur. In addition, the crystallinity of a metal oxide may be lowered by entry of impurities, generation of defects, or the like , so the CAAC-OS can also be said to be a metal oxide with few impurities and few defects (such as oxygen vacancies). Accordingly, the metal oxide including the CAAC-OS has stable physical properties. Thus, the metal oxide including the CAAC-OS is resistant to heat and has high reliability.

[0137] The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In the nc-OS, there is no regularity in crystal orientation between different nanocrystals. Therefore, orientation is not observed in the entire film. Thus ​​​​Therefore, depending on the analysis method, nc-OS can be classified as a-like OS or amorphous oxide semiconductor. It can sometimes be difficult to distinguish between them.

[0138] Furthermore, indium is a type of metal oxide containing indium, gallium, and zinc. Moo-gallium zinc oxide (hereinafter referred to as IGZO) is formed into the aforementioned nanocrystals, resulting in a stable structure. In some cases, this may be necessary. In particular, IGZO tends to have difficulty growing crystals in the atmosphere. Smaller crystals (for example) are better than larger crystals (here, crystals of a few millimeters or a few centimeters). In some cases, using the aforementioned nanocrystal structure may result in greater structural stability.

[0139] a-like OS is a metal oxide having a structure between nc-OS and amorphous oxide semiconductors. It is a substance. an a-like OS has porous or low-density regions. That is, a-lik e OS has lower crystallinity compared to nc-OS and CAAC-OS.

[0140] Oxide semiconductors (metal oxides) can take on diverse structures, each possessing different properties. One embodiment of the invention is an oxide semiconductor, an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, and an a-lik It may have two or more of the following: e OS, nc-OS, and CAAC-OS.

[0141] The metal oxide film, which functions as a semiconductor layer, is either an inert gas or an oxygen gas or Both methods can be used to form the film. Note that the oxygen flow rate ratio during metal oxide film formation is also important. There are no particular limitations on the (oxygen partial pressure). However, when obtaining a transistor with high field-effect mobility... In this case, the oxygen flow rate ratio (oxygen partial pressure) during the deposition of the metal oxide film is 0% or more. Preferably 0% or less, more preferably 5% to 30%, and even more preferably 7% to 15%. preferable.

[0142] The metal oxide preferably has an energy gap of 2 eV or more, and more preferably 2.5 eV or more. It is more preferable that it be 3eV or more, and even more preferable that it be 3eV or more. By using metal oxides with a wide energy gap, the off-current of the transistor can be reduced. It is possible.

[0143] [Example of manufacturing method] Next, a method for fabricating a transistor according to one embodiment of the present invention will be explained using Figures 5 to 8. This section describes the method for fabricating transistor 100A as shown in Configuration Example 2. (Figures 5-5) Figure 8 shows the channel length direction and channel width direction at each stage of the transistor fabrication process. The cross-sections are shown side by side.

[0144] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices are produced by sputtering. Chemical vapor deposition (CVD) method, Vacuum deposition, pulsed laser deposition (PLD) ion) method, Atomic Layer Deposition (ALD) It can be formed using methods such as CVD. CVD methods include plasma chemical vapor deposition (PEC). These include the VD (Plasma Enhanced CVD) method and the thermal CVD method. One of the thermal CVD methods is metal-organic chemical vapor deposition (MOCVD). There is also the CVD method.

[0145] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be coated using spin coating, defrosting, and other methods. Tap, spray coating, inkjet, dispensing, screen printing, offset printing Printing, doctor knife, slit coat, roll coat, curtain coat, knife coat, etc. It can be formed by the following method.

[0146] Furthermore, when processing the thin films that make up semiconductor devices, photolithography and other methods are used. It can be done using methods such as nanoimprint lithography, sandblasting, or lift-off lithography. The thin film may be processed by any method. Alternatively, a film deposition method using a shielding mask such as a metal mask may be used. This may be used to directly form island-like thin films.

[0147] There are two main methods of photolithography. One is to process the image A resist mask is formed on a thin film, and the thin film is processed by etching or the like, and the resist This is a method for removing the mask. Another method involves forming a photosensitive thin film and then exposing it to light. This method involves developing the film and then processing it into a desired shape.

[0148] In photolithography, the light used for exposure is, for example, the i-line (wavelength 365 nm), g The light used is a linear light (wavelength 436 nm), an h-line (wavelength 405 nm), or a mixture of these. This can be done using ultraviolet light, KrF laser light, or ArF laser light, etc. This can also be done. Alternatively, exposure may be performed using immersion lithography. Furthermore, the light used for exposure may be... Using extreme ultraviolet (EUV) light and X-rays... This is also acceptable. Furthermore, an electron beam can be used instead of the light used for exposure. Extreme ultraviolet light Using X-rays or electron beams is preferable because it allows for extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not necessary. It is essential.

[0149] Thin film etching can be performed using dry etching, wet etching, or sandblasting. These can be used.

[0150] First, as shown in Figure 5(A), a conductive film is deposited on the substrate 102 and then processed by etching. This forms a conductive layer 106 that functions as a gate electrode.

[0151] Next, an insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (Figure 5(A)).

[0152] A more detailed explanation of the insulating layer 103 will be provided using Figures 6(A) and 6(B).

[0153] The insulating layer 103 shown in Figure 6(A) consists of insulating layer 103a and insulating layer 103 on insulating layer 103a It has a three-layer structure consisting of b and an insulating layer 103c on the insulating layer 103b.

[0154] The insulating layer 103 shown in Figure 6(B) consists of an insulating layer 103e and an insulating layer 103 on top of the insulating layer 103e. a, insulating layer 103b on insulating layer 103a, insulating layer 103c on insulating layer 103b, It has a four-layer structure. The insulating layer 103 shown in Figure 6(B) is the same as the insulating layer 10 shown in Figure 6(A). This configuration adds an insulating layer 103e to step 3.

[0155] The insulating layer 103a and the insulating layer 103b are nitride insulating films with different deposition conditions. Preferably, the insulating layer 103c is an oxide insulating film. The insulating layer 103e is an insulating film. The nitride insulating film has different deposition conditions for the edge layer 103a and the insulating layer 103b, respectively. Preferred. The insulating layer 103e, insulating layer 103a, insulating layer 103b, and insulating layer 103c are It is preferable that the film be formed continuously without contact with the atmosphere. For example, insulating layer 103e, The edge layer 103a, insulating layer 103b, and insulating layer 103c are each subjected to plasma CVD. It is preferable that it be formed more.

[0156] The insulating layers 103e, 103a, and 103b are each made of silicon nitride. Nitrided insulating films such as silicon nitride film, aluminum nitride film, and hafnium nitride film It can be used. As the insulating layer 103c, a silicon oxide film, a silicon oxide nitride film, Silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film, acid Zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, tantalum oxide Oxidizing insulating films such as cerium oxide films and neodymium oxide films can be used.

[0157] For example, the insulating layer 103e, insulating layer 103a, and insulating layer 103b are each made of plastic. A silicon nitride film is formed by the Zuma CVD method, and as an insulating layer 103c, the plasma CVD method... It is preferable to form a silicon oxide nitride film by this method.

[0158] The insulating layer 103a is preferably a film with high dielectric strength and low stress. By having a low-strength film, warping of the substrate can be suppressed. This makes it possible to create a large-format substrate Even when using this method, transportation becomes easier, leading to a reduction in manufacturing time and an improvement in manufacturing yield. Furthermore, the insulating layer 103a is thicker than both the insulating layer 103e and the insulating layer 103b. It is preferable that this is formed. This can increase the productivity of the insulating layer 103.

[0159] The insulating layer 103e and the insulating layer 103b prevent the diffusion of impurities from the substrate 102 side, respectively. It is preferable that the film be dense and able to stop leakage.

[0160] Specifically, the insulating layer 103e blocks the metal elements contained in the conductive layer 106. High conductivity is desirable. For example, if copper is used in the conductive layer 106, the copper is desirable in the semiconductor layer 108. To suppress diffusion, it is preferable to provide an insulating layer 103e. When layer 106 is formed using a metal element that does not easily diffuse into the insulating layer 103, the insulating layer It is not necessary to include 103e.

[0161] The insulating layer 103b is desirable to have low hydrogen emission and high hydrogen blocking properties. It seems that when hydrogen is released from the insulating layer 103, it combines with the oxygen in the semiconductor layer 108 and forms water. Furthermore, the detachment may lead to the formation of oxygen vacancies in the semiconductor layer 108. When hydrogen enters a primary defect, it forms a donor, increasing the carrier density. Insulating layer 1 By suppressing the release of hydrogen from O3, the characteristic fluctuations of the transistor are suppressed, and reliability is improved. It is possible to do so.

[0162] For example, the pressure and / or power during the deposition of the insulating layer 103a may be used for the insulating layer 103b. By lowering the film deposition conditions, the stress of the insulating layer 103a is lower than the stress of the insulating layer 103b. It can be made lower. Also, the insulating layer 103b is made lower to hydrogen than insulating layer 103a. It is possible to create a membrane with high locking properties.

[0163] The insulating layer 103c is a layer that is in contact with the semiconductor layer 108. The insulating layer 103c has defects on its surface. It is an extremely dense film with minimal particles, making it difficult for impurities such as water from the atmosphere to adsorb onto its surface. It is preferable.

[0164] The film-forming gas used for forming each layer constituting the insulating layer 103 includes a source gas containing a depositing gas. At least one of these should be used. In addition to the source gas, the film-forming gas should include dilute argon, helium, nitrogen, etc. It may also contain a decontaminating gas. The ratio of the flow rate of the deposition gas to the total flow rate of the film-forming gas (hereinafter simply By reducing the flow rate (also called the flow ratio), the film deposition rate can be lowered, resulting in a dense film with fewer defects. It can form a film.

[0165] The insulating layer 103a was formed under conditions where the flow rate ratio of the depositing gas was higher compared to the insulating layer 103b. It is preferable that this be done. This increases the film formation rate of the insulating layer 103a and the production of the insulating layer 103. It can increase productivity.

[0166] Insulating layer 103b and insulating layer 103e, respectively, have a greater capacity to absorb sedimentary gases compared to insulating layer 103a. It is preferable that the film is formed under conditions where the flow rate ratio is low. This ensures that the insulating layer 103b and the insulating layer Each of these layers, specifically the marginal layer 103e, can be used to form a dense film with few defects.

[0167] Here, the boundary between insulating layer 103a and insulating layer 103b, and the boundary between insulating layer 103e and insulating layer 103 The boundaries with a may be unclear in each case, therefore, in Figures 6(A) and 6(B) These boundaries are clearly indicated by dashed lines. Note that insulating layer 103a and insulating layer 103b are densely packed. Due to the difference in degree, a transmission electron microscope (TEM) can be used to examine the cross-section of the insulating layer 103. In images such as those from an electron microscope, these boundaries In some cases, the boundary can be observed as a difference in contrast. Similarly, the insulating layer 103e and the insulating layer In some cases, the boundary with 103a can also be observed.

[0168] After forming the insulating layer 103, a process of supplying oxygen to the insulating layer 103 may be performed. Processes that supply oxygen include, for example, plasma treatment under an oxygen atmosphere, under an oxygen atmosphere Heat treatment, treatment using plasma ion doping, and treatment using ion implantation Reasons and other factors can be cited.

[0169] Next, a metal oxide film is formed on the insulating layer 103 and processed to create island-shaped semiconductor layers 108 It forms (Figure 5(B)).

[0170] Metal oxide films can be formed by sputtering using a metal oxide target. preferable.

[0171] It is preferable to use oxygen gas when forming a metal oxide film. When forming a film, in addition to oxygen gas, an inert gas (for example, helium gas, argon gas, etc.) is used. (For example, cenon gas may be mixed in.) The higher the proportion of oxygen gas in the mixture (hereinafter also called the oxygen flow rate ratio), the more the metal oxide film crystals. This improves performance and enables the realization of highly reliable transistors. On the other hand, the oxygen flow rate ratio is low. The lower the crystallinity of the metal oxide film, the larger the on-current of the transistor. can.

[0172] For the deposition conditions of the metal oxide film, the substrate temperature should be between room temperature and 200°C, preferably at a certain temperature. The temperature should be set to be between room temperature and 140°C. For example, the substrate temperature should be between room temperature and 140°C. This is desirable as it increases productivity. Also, the substrate temperature is set to room temperature, or not intentionally heated. By forming a metal oxide film in this state, the crystallinity can be reduced.

[0173] Furthermore, before forming the metal oxide film, water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 103 are removed. It is preferable to perform a process to remove the fractions and a process to supply oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70°C to 200°C under reduced pressure. Yes, it is possible. Alternatively, plasma treatment may be performed in an oxygen-containing atmosphere. When plasma treatment is performed in an atmosphere containing nitrogen dioxide (N2O) gas, the surface of the insulating layer 103 Organic matter can be suitably removed from the surface. After such treatment, the surface of the insulating layer 103 It is preferable to continuously deposit metal oxide films without exposure to the atmosphere.

[0174] For processing metal oxide films, either wet etching or dry etching, or both, are used. The method should be used. At this time, a part of the insulating layer 103 that does not overlap with the semiconductor layer 108 is etched. It may become thinner due to polishing.

[0175] After forming the metal oxide film or processing it into a semiconductor layer 108, the metal oxide film or semiconductor layer Heat treatment may be performed to remove hydrogen and water from 10⁸. The heat treatment temperature is representative. Generally, temperatures above 150°C but below the substrate's strain point, between 250°C and 450°C, or below 300°C. The temperature can be kept below 450°C.

[0176] The heat treatment can be carried out in an atmosphere containing a noble gas or nitrogen. Alternatively, in such an atmosphere After heating, it may be heated in an atmosphere containing oxygen. Furthermore, hydrogen may be added to the atmosphere during the above heating treatment. It is preferable that the product does not contain water or other substances. The heat treatment is carried out using an electric furnace, RTA device, etc. This is possible. By using an RTA device, the heat treatment time can be shortened.

[0177] Next, the gate insulating layer 110 and the metal oxide layer 1 cover the insulating layer 103 and the semiconductor layer 108. Layer 14 is stacked to form a film (Figure 5(C)).

[0178] Before forming the gate insulating layer 110, the surface of the semiconductor layer 108 is subjected to plasma treatment. This is preferable. This removes impurities such as water adsorbed on the surface of the semiconductor layer 108. This can be done. The impurities present at the interface between the semiconductor layer 108 and the gate insulating layer 110 can be reduced. Because it can be reduced, the reliability of the transistor can be improved. In particular, the shape of semiconductor layer 108 Between the formation of the semiconductor layer and the formation of the gate insulating layer 110, the surface of the semiconductor layer 108 is exposed to the atmosphere. It is suitable for use in combination. Plasma treatment can be performed using, for example, oxygen, ozone, nitrogen, nitrous oxide (N2O Plasma treatment can be performed in an atmosphere containing argon, etc. It is preferable to perform the treatment. Furthermore, when N2O plasma treatment is performed, the surface of the semiconductor layer 108 Organic matter can be suitably removed. After plasma treatment, the surface of the semiconductor layer 108 is exposed to the air. It is preferable to continuously form the gate insulating layer 110 without exposure to the light.

[0179] The gate insulating layer 110 may be, for example, a silicon oxide film or a silicon oxide nitride film. It is preferable to form the oxide film by plasma CVD. Alternatively, microwaves may be used. It may also be formed using plasma CVD.

[0180] A more detailed explanation of the gate insulating layer 110 will be provided using Figure 6(C).

[0181] The gate insulating layer 110 shown in Figure 6(C) consists of an insulating layer 110a and an insulating layer on top of the insulating layer 110a. It has a three-layer structure consisting of 110b and an insulating layer 110c on the insulating layer 110b.

[0182] Insulating layer 110a, insulating layer 110b, and insulating layer 110c are each formed using acid under different film formation conditions. It is preferable that it be a dielectric insulating film. In this case, insulating layer 110a, insulating layer 110b, and insulating It is preferable that layer 110c be deposited continuously using the same deposition apparatus. For example, insulating layer 11 Layer 0a, insulating layer 110b, and insulating layer 110c are each produced by plasma CVD. It is preferable to form a silicon oxide nitride film.

[0183] The insulating layer 110a is a layer in contact with the semiconductor layer 108. To reduce the damage to layer 108, the deposition rate of the insulating layer 110a (also known as the deposition rate) is reduced. (It is preferable that the value is low.)

[0184] It is preferable to form the insulating layer 110a under lower power conditions compared to the insulating layer 110b. This makes it possible to minimize the damage inflicted on the semiconductor layer 108.

[0185] Furthermore, it is desirable that the insulating layer 110a has few defects and releases little hydrogen and water. This makes it possible to suppress the formation of oxygen vacancies in the semiconductor layer 108.

[0186] To increase the productivity of the gate insulating layer 110, a high deposition rate for the insulating layer 110b is preferred. Furthermore, compared to insulating layer 110a and insulating layer 110c, insulating layer 110b is It is preferable that it be made thick.

[0187] The insulating layer 110c has few surface defects, and impurities such as water contained in the atmosphere are adsorbed onto the surface. It is preferable that the film is extremely dense and difficult to deform.

[0188] The deposition gas used for forming each layer constituting the gate insulating layer 110 contains a raw material that includes a depositing gas. At least one gas is used. In addition to the source gas, the film-forming gas may be argon, helium, nitrogen, etc. Any diluent gas may be included. The ratio of the flow rate of the deposition gas to the total flow rate of the film-forming gas (hereinafter) By reducing the flow rate (also simply called the flow ratio), the deposition rate can be lowered, resulting in a dense film with fewer defects. A film can be formed.

[0189] For example, the deposition of silicon oxide nitride films involves silicon-containing deposition methods such as silane and disilane. The source gas includes gases and oxidizing gases such as oxygen, ozone, nitrous oxide, and nitrogen dioxide. You can use it.

[0190] The insulating layer 110a was formed under conditions where the flow rate ratio of the depositing gas was lower compared to the insulating layer 110b. It is preferable that this is done so that a dense film with few defects is formed as the insulating layer 110a. It is possible.

[0191] The insulating layer 110b has a deposition rate that is lower than one or both of the insulating layers 110a and 110c. It is preferable that the film is formed under conditions where the flow rate ratio of the chemical gas is high. This results in the insulating layer 110b This increases the film deposition rate and improves the productivity of the gate insulating layer 110.

[0192] The insulating layer 110c, like the insulating layer 110a, has better flow of sedimentary gases compared to the insulating layer 110b. It is preferable that the film is formed under conditions of a low quantity ratio. Note that the insulating layer 110c is the insulating layer 110 Because it is formed on the semiconductor layer 108 via a and the insulating layer 110b, the insulating layer 110c During film formation, the semiconductor layer 108 suffers little damage. Therefore, the insulating layer 110c is an insulating layer. It can be formed under higher power conditions than the margin 110a. The flow rate ratio of the sedimentary gas is low. By depositing the film with relatively high power, a dense film with few surface defects is formed as the insulating layer 110c. It is possible to form a thin film.

[0193] Here, the boundary between insulating layer 110a and insulating layer 110b, and the boundary between insulating layer 110b and insulating layer 110 The boundaries with c may be unclear in each case, therefore, in Figure 6(C), these boundaries are shown. This is clearly indicated by a dashed line. Note that insulating layer 110a and insulating layer 110b have different film densities. In TEM images of the cross-section of the gate insulating layer 110, etc., these boundaries are contrasted. This can sometimes be observed as a difference. Similarly, the boundary between insulating layer 110b and insulating layer 110c In some cases, the world can also be observed.

[0194] The metal oxide layer 114 is formed from a material that is impermeable to oxygen and hydrogen. 14 is the diffusion of oxygen contained in the gate insulating layer 110 to the side opposite to the semiconductor layer 108. It has the function of suppressing hydrogen and water from the outside. It has the function of suppressing diffusion toward the 10 side. The metal oxide layer 114 has at least It is preferable to use a material that is less permeable to oxygen and hydrogen than the insulating layer 110.

[0195] The metal oxide layer 114 may be either an insulating layer or a conductive layer.

[0196] As the metal oxide layer 114, an insulating material with a higher dielectric constant than silicon oxide can be used. Preferred. For example, an aluminum oxide film, a hafnium oxide film, or hafnium aluminum A film or the like can be used.

[0197] For example, the metal oxide layer 114 can be indium oxide, indium tin oxide (ITO ), or conductive oxides such as silicon-containing indium tin oxide (ITSO), You can also use this.

[0198] Furthermore, the metal oxide layer 114 may be an oxide material containing one or more of the same elements as the semiconductor layer 108. It is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108. Preferably, the metal oxide layer 114 is made using the same sputtering process as the semiconductor layer 108. By applying a metal oxide film formed using a ring target, the equipment can be standardized. Therefore, it is preferable.

[0199] Alternatively, both the semiconductor layer 108 and the metal oxide layer 114 may contain indium and gallium. When using metal oxide materials, the gallium composition (content) is higher than that of semiconductor layer 108. Using this material allows for a greater blocking effect against oxygen, which is preferable. At this time, the semiconductor layer 108 contains a material with a higher indium composition than the metal oxide layer 114. By using this material, the field-effect mobility of transistor 100 can be increased.

[0200] The metal oxide layer 114 is preferably formed using a sputtering apparatus. When forming an oxide film using a tarring device, the formation should be carried out in an atmosphere containing oxygen gas. This allows for a suitable supply of oxygen to the gate insulating layer 110 and the semiconductor layer 108.

[0201] The metal oxide layer 114 is preferably formed in an atmosphere containing oxygen, for example. In particular, It is preferable to form it by sputtering in an oxygen-containing atmosphere. Oxygen can be supplied to the gate insulating layer 110 during the formation of the oxide layer 114.

[0202] The metal oxide layer 114 is an oxide target containing a metal oxide, similar to the case of the semiconductor layer 108. When forming using a sputtering method with a t-t, the above method can be applied. .

[0203] For example, by using oxygen as the film deposition gas and a reactive sputtering method with a metal target A metal oxide layer 114 may be formed. For example, aluminum may be used as the metal target. When used, an aluminum oxide film can be formed.

[0204] When forming the metal oxide layer 114, the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus is as follows: The higher the proportion of oxygen flow rate (oxygen flow rate ratio) or the oxygen partial pressure in the deposition chamber, the higher the gate insulating layer 1 The amount of oxygen supplied to 10 can be increased. The oxygen flow rate ratio or oxygen partial pressure can be, for example, 5 0% to 100%, preferably 65% ​​to 100%, more preferably 80% or more The oxygen flow rate ratio should be 100% or less, more preferably 90% to 100%. In particular, the oxygen flow rate ratio should be 10 It is preferable to set the oxygen partial pressure to 0% and bring it as close to 100% as possible.

[0205] Thus, a metal oxide layer 114 is formed by sputtering in an oxygen-containing atmosphere. By doing so, when the metal oxide layer 114 is formed, oxygen is supplied to the gate insulating layer 110. Both methods prevent oxygen from detaching from the gate insulating layer 110. As a result, A very large amount of oxygen can be trapped in the insulating layer 110. Then, the subsequent heat treatment This allows a large amount of oxygen to be supplied to the semiconductor layer 108. As a result, the semiconductor layer 1 This reduces oxygen deficiency in the 08, enabling the creation of highly reliable transistors.

[0206] Next, by performing a heat treatment, oxygen is supplied from the gate insulating layer 110 to the semiconductor layer 108. Preferably, the heat treatment is carried out in an atmosphere containing one or more of nitrogen, oxygen, and noble gases. This can be done at temperatures between 00°C and 400°C.

[0207] After forming the metal oxide layer 114, perform a heat treatment before forming the gate electrode 112. This allows for an effective supply of oxygen from the gate insulating layer 110 to the semiconductor layer 108.

[0208] Next, the metal oxide layer 114 is removed (Figure 5(D)). The subsequent steps are preferably carried out at a temperature lower than or equal to the temperature of the heat treatment described above. This suppresses the desorption of oxygen from the semiconductor layer 108, resulting in an oxygen deficiency in the semiconductor layer 108. This can suppress the formation of losses. Therefore, the reliability of the transistor can be improved. Cut.

[0209] There are no particular limitations on the method for removing the metal oxide layer 114, but if wet etching is used, gold This method suppresses the etching of the gate insulating layer 110 simultaneously with the oxide layer 114. This suppresses a decrease in the thickness of the gate insulating layer 110, and the gate insulating layer 110 The film thickness can be made uniform.

[0210] After removing the metal oxide layer 114, a portion of the gate insulating layer 110 and insulating layer 103 is etched. This creates an opening 142 that reaches the conductive layer 106. The gate electrode 112 and the conductive layer 106 are electrically connected at the opening 142. Yes, it is possible. Furthermore, the opening 142 may be formed before the formation of the metal oxide layer 114.

[0211] Next, a conductive film 112f, which will become the gate electrode 112, is formed on the gate insulating layer 110 (Figure 5(E)). The conductive film 112f is produced by sputtering using a metal or alloy sputtering target. It is preferable to form the film by the puttering method. Here, at the opening 142, the conductive film 112f and the conductive layer 106 are connected.

[0212] Next, a portion of the conductive film 112f is etched to form the gate electrode 112 (Figure 7(A)). ).

[0213] Thus, the gate insulating layer 110 is located on the upper and side surfaces of the semiconductor layer 108, and the insulating layer 10 By covering 3, during etching to form the gate electrode 112, half This prevents the conductor layer 108 and the insulating layer 103 from being etched and becoming thinner. ru.

[0214] Next, using the gate electrode 112 as a mask, impurities are introduced into the gate insulating layer 110 and the semiconductor layer 108. The process of supplying material element 140 is performed, and the low resistance region 108n, region 110d, and region 10 Forming a 3D structure (Figures 7(B) and 7(C)). Semiconductor layer 108 and gate insulating layer 110 In the region overlapping with the gate electrode 112, the gate electrode 112 acts as a mask, and impurities are generated. Base 140 will not be supplied.

[0215] For supplying impurity element 140, plasma ion doping or ion implantation is preferable. These methods can be used to obtain a depth-direction concentration profile, and accelerated ion generation. It can be controlled with high precision by adjusting pressure, dose, etc. (Plasma ion doping method) By using this, productivity can be increased. In addition, ion implantation using mass separation can be used. By using this method, the purity of the supplied impurity elements can be increased.

[0216] In the supply process of impurity element 140, at the interface between the semiconductor layer 108 and the gate insulating layer 110, or the portion of the semiconductor layer 108 near the interface, or the interface in the gate insulating layer 110. It is preferable to control the processing conditions so that the highest concentration is reached in the area closest to this point. Therefore, in a single process, the optimal concentration of impurities can be applied to both the semiconductor layer 108 and the gate insulating layer 110. It can supply element 140.

[0217] The 140 impurity elements are hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, and Examples include luminium, magnesium, silicon, and noble gases. (140 impurity elements) Boron, phosphorus, aluminum, magnesium, or silicon are preferred as such. It is preferable to use boron or phosphorus.

[0218] As the raw material gas for impurity element 140, a gas containing the above-mentioned impurity element can be used. When supplying boron, typical gases such as B2H6 gas and BF3 gas can be used. Furthermore, when supplying phosphorus, pH3 gas can typically be used. Alternatively, a mixed gas obtained by diluting these source gases with a noble gas may be used.

[0219] Other raw material gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, S i2H6, F2, HF, H2, (C5H5)2Mg, and noble gases can be used. Furthermore, the ion source is not limited to gases; solids or liquids may also be heated and vaporized.

[0220] The supply of impurity element 140 affects the composition, density, and thickness of the gate insulating layer 110 and the semiconductor layer 108. By taking these factors into consideration and setting conditions such as acceleration voltage and dose amount, it can be controlled. .

[0221] Furthermore, there are no limitations on the method of supplying impurity element 140; for example, plasma treatment or heating. Treatments utilizing diffusion may also be used. In the case of plasma treatment, the supplied impurity elements are By generating plasma in a gas atmosphere containing impurities and performing plasma processing, the impurity source It can supply the raw materials. The device for generating the above-mentioned plasma is a dry etching device. Using equipment such as ashing equipment, plasma CVD equipment, and high-density plasma CVD equipment. It is possible.

[0222] In one aspect of the present invention, impurity elements 140 are introduced into the semiconductor layer 108 via the gate insulating layer 110. This allows for the supply of impurity elements 140 to be used in the semiconductor layer 108. This suppresses the decrease in crystallinity. Therefore, the decrease in crystallinity does not increase electrical resistance. It is particularly suitable in such cases.

[0223] In the supply process of impurity element 140, it overlaps with the gate electrode 112 of the gate insulating layer 110. Impurity element 140 is also supplied to the parts that are not present. As a result, the gate insulating layer 110 The portion overlapping with electrode 112 and the portion not overlapping with it are affected by the release of oxygen due to heating. A difference in ease of erosion occurs. Therefore, when heat treatment is performed after the supply process of impurity element 140 Even in this case, the supply of oxygen from the gate insulating layer 110 to the low-resistance region 108n can be suppressed. This can suppress the increase in electrical resistance in the low-resistance region of 10⁸n.

[0224] Next, an insulating layer 118 is formed to cover the gate insulating layer 110 and the gate electrode 112 (Figure 8( A)).

[0225] When forming the insulating layer 118 by plasma CVD, if the deposition temperature is too high, the low-resistance region... Impurities contained in region 108n, etc., spread to the peripheral area including the channel formation region of the semiconductor layer 108. There is a risk of dispersion, and the electrical resistance in the low-resistance region 108n may increase. The film temperature is, for example, 150°C to 400°C, preferably 180°C to 360°C. More preferably, the temperature should be between 200°C and 250°C. By depositing the film at high temperatures, even transistors with short channel lengths can exhibit good electrical characteristics. It can be granted.

[0226] Next, a mask is formed by lithography at a desired position on the insulating layer 118, and then the insulating layer 11 By etching part of the gate insulating layer 110, a low-resistance region 108n can be reached. Openings 141a and 141b are formed.

[0227] Next, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b. Then, by processing the conductive film into a desired shape, the conductive layer 120a and the conductive layer 120b are formed. This is achieved (Figure 8(B)).

[0228] By following the above steps, transistor 100A can be manufactured. For example, When applying Ta100A to the pixels of a display device, a protective insulating layer, a planarizing layer, and a surface layer are applied afterwards. The process can be simplified by adding a step to form one or more of the indicator elements and wiring.

[0229] In the semiconductor device manufacturing method of this embodiment, a semiconductor layer, a gate insulating layer, and a metal oxide layer After forming the gate, a heat treatment is performed before forming the gate electrode. Oxygen is introduced onto the gate insulating layer. To provide a metal oxide layer that is difficult to penetrate, oxygen is effectively supplied from the gate insulating layer to the semiconductor layer. This allows for the supply of oxygen. This reduces oxygen vacancies in the channel formation region of the semiconductor layer, and This can improve the reliability of the transistor. Also, after heat treatment, before the gate electrode is formed. Next, the metal oxide layer is removed. This eliminates the processing and residue of the metal oxide layer. This suppresses the degradation of the transistor's characteristics. Therefore, it provides a semiconductor device with excellent electrical properties and high reliability. It can be implemented.

[0230] This embodiment can be appropriately combined with other embodiments. Furthermore, this specification Furthermore, if multiple configuration examples are shown within a single embodiment, the configuration examples may be combined as appropriate. It is possible to do so.

[0231] (Embodiment 2) In this embodiment, a display device having a semiconductor device according to one aspect of the present invention is shown in Figures 9 to 1. I will explain using number 3.

[0232] A semiconductor device according to one aspect of the present invention has good electrical characteristics, and therefore can be used in a display device. The reliability of the display device can be improved. For example, a transistor according to one aspect of the present invention is This can be applied to transistors in either or both of the pixels and the driving circuit of the display device. can.

[0233] A semiconductor device according to one aspect of the present invention is a display device, or a module having said display device. It can be used. A module having the display device may have a flexible cable attached to the display device. Flexible printed circuit board (hereinafter referred to as, FPC (written as FPC) or TCP (Tape Carrier Package) and other connections Modules with a kuta attached, COG (Chip On Glass) system or Modules on which integrated circuits (ICs) are mounted using methods such as COF (Chip On Film). Examples include [mention specific examples].

[0234] [Top view of the display device] Figure 9(A) shows a top view of the display device 700. The display device 700 is sealed by the sealing material 712 It has a first substrate 701 and a second substrate 705 that are bonded together. The area sealed by the substrate 705 and the sealing material 712 contains the pixel section 702 and the source dry A bar 704 and a gate driver 706 are provided. Multiple display elements are provided in the pixel section 702. A system will be established.

[0235] The FPC716 is connected to the portion of the first substrate 701 that does not overlap with the second substrate 705. A PC terminal section 708 is provided. The FPC 716 connects the FPC terminal section 708 and the signal The pixel unit 702, source driver 704, and gate driver 706 are connected via line 710. Various signals are supplied to each of them.

[0236] Multiple gate drivers 706 may be provided. Each source driver 704 is separately formed on a semiconductor substrate and packaged as I The IC chip may be in the form of a C chip. The IC chip may be on the first substrate 701 or on an FPC. It can be implemented in 716.

[0237] The transistors in the pixel unit 702, source driver 704, and gate driver 706 A transistor according to one aspect of the present invention can be applied to this.

[0238] Examples of display elements provided in the pixel section 702 include liquid crystal elements and light-emitting elements. As for the crystal elements, transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements are used. It is possible to do so. Also, as a light-emitting element, an LED (Light Emitting LED) can be used. iode), OLED (Organic LED), QLED (Quantum-dot) Examples include self-luminous light-emitting elements such as LEDs and semiconductor lasers. Also, shutters. MEMS (Micro Electro Mechanical) using either a micro-electromechanical or optical interferometry method. Systems) Elements, microcapsule method, electrophoresis method, electrowetting Using a display element that employs a ping method or an electronic powder fluid (registered trademark) method, etc. It's also possible.

[0239] The display device 700A shown in Figure 9(B) uses a flexible resin instead of the first substrate 701. A display device that can be used as a flexible display, to which layer 743 is applied. This is an example.

[0240] The display device 700A has a pixel section 702 that is not rectangular in shape, but has an arc-shaped corner. The display device 700A consists of a pixel section 702 and a resin layer, as shown in area P1 in Figure 9(B). A portion of 743 has a notched section. A pair of gate drivers 706 are located in the pixel section They are provided on both sides of 702. The gate driver 706 is located at the corner of the pixel portion 702. It is provided along an arc-shaped contour.

[0241] The resin layer 743 has a shape in which the portion where the FPC terminal portion 708 is provided protrudes. Furthermore, a portion of the resin layer 743, including the FPC terminal portion 708, is on the back side in area P2 in Figure 9(B). It can be folded back. By folding back a part of the resin layer 743, the FPC 716 can be folded back to form the pixel section 7 With the 02 placed on top of each other, the display device 700A can be mounted on electronic equipment. This allows for space-saving in electronic devices.

[0242] The FPC716 connected to the display device 700A has the IC717 mounted on it. 17 has, for example, the function of a source driver. At this time, the display device 700A The source driver 704 has fewer protection circuits, buffer circuits, demultiplexer circuits, etc. It can be a configuration that includes at least one.

[0243] The display device 700B shown in Figure 9(C) is suitable for use in electronic devices having a large screen. It is a display device capable of doing so. The display device 700B can be used, for example, in television equipment, monitor equipment, Personal computers (including notebooks and desktops), tablet devices, and It can be suitably used in digital signage and the like.

[0244] The display device 700B includes multiple source driver ICs 721 and a pair of gate drivers 722 It has.

[0245] Multiple source driver IC721s are each attached to the FPC723. One terminal of the FPC723 is connected to the first board 701, and the other terminal is connected to the printed circuit board It is connected to board 724. By bending FPC723, the printed circuit board 724 is formed By placing it on the back side of the element 702, the display device 700B can be mounted on an electronic device. This allows for space-saving in equipment.

[0246] On the other hand, the gate driver 722 is formed on the first substrate 701. This narrows the gap. It is possible to create electronic devices in picture frames.

[0247] This configuration makes it possible to realize a large and high-resolution display device. For example, screen Sizes with a diagonal of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more It can also be applied to display devices. Furthermore, it can handle resolutions such as 4K2K or 8K4K. This makes it possible to realize extremely high-resolution display devices.

[0248] [Cross-sectional configuration of the display device] Figures 10 and 11 show a display device having a liquid crystal element as a display element. Figures 12 and 1 Figure 3 shows a display device having an EL element as a display element. Figures 10, 11, and 12 are These are cross-sectional views between the dashed lines QR shown in Figure 9(A), respectively. Figure 13 is Figure 9(B). This is a cross-sectional view between the dashed lines ST shown.

[0249] The display devices 700 shown in Figures 10 to 12 and the display device 700A shown in Figure 13 are routed The wiring section 711, the pixel section 702, the source driver 704, and the FPC terminal section 708 are It has. The routing section 711 has a signal line 710. The pixel section 702 has a transistor It has a 750 and a capacitive element 790. Figure 11 shows the case without the capacitive element 790. The source driver 704 has a transistor 752.

[0250] Transistors 750 and 752 have an oxide layer in the semiconductor layer where the channel is formed. This is a transistor that uses a semiconductor material. For example, each of the transistors exemplified in Embodiment 1 A transistor can be applied. Also, the display device has a semiconductor layer made of silicon (amorphous silicon). It may have transistors made of (polycrystalline silicon, or monocrystalline silicon). .

[0251] The transistor used in this embodiment is made of highly purified oxide semiconductor material with suppressed oxygen vacancy formation. It has a conductive film. This transistor can reduce the off-current. Therefore, it can handle electrical signals such as image signals. The retention time for signal types can be extended, and the writing interval for image signals and other data can be set to be longer. Therefore, This reduces the frequency of refresh operations, resulting in lower power consumption.

[0252] Furthermore, the transistor used in this embodiment can obtain a relatively high field-effect mobility. High-speed operation is possible. For example, a transistor capable of such high-speed operation can be used in a display device. By using it, the switching transistors in the pixel section and the drivers used in the drive circuit section are used. Transistors can be formed on the same substrate. That is, a separate drive circuit is required. Since it does not require the use of semiconductor devices formed from silicon wafers, etc., it is a component of a display device. The number of points can be reduced. Also, in the pixel section, a transistor capable of high-speed driving is used. By using it, high-quality images can be provided.

[0253] The capacitive element 790 shown in Figures 10 and 12 is identical to the semiconductor layer of the transistor 750. A lower electrode formed by processing a film and having reduced resistance, and the source electrode and drain electrode are the same It has an upper electrode formed by processing a conductive film, and a lower electrode and an upper electrode. Between them, two layers of insulating film are provided to cover the transistor 750. That is, the capacitive element 79 0 is a stacked structure in which an insulating film, which functions as a dielectric film, is sandwiched between a pair of electrodes.

[0254] The capacitive element 790 shown in Figure 13 is identical to the first gate electrode of the transistor 750. The lower electrode is formed by processing a film, and the semiconductor layer is formed by processing the same metal oxide film. It has an upper electrode, and the upper electrode is low resistance, similar to the low resistance region of transistor 750. It is resisted. Also, between the lower electrode and the upper electrode, the first gate of transistor 750 A portion of the insulating film, which functions as an insulating layer, is provided. That is, the capacitive element 790 is It is a stacked structure in which an insulating film, which functions as a dielectric film, is sandwiched between a pair of electrodes. The sub-electrode is obtained by processing the same film as the source and drain electrodes of the transistor. The wiring is connected.

[0255] A planarizing insulating film 77 is applied to transistors 750, 752, and 790. A value of 0 is provided.

[0256] The transistor 750 in the pixel unit 702 and the transistor in the source driver 704 The Ta752 may have different structures from each other. For example, one of them may be a top gate type. One transistor may be used for the other, and a bottom-gate type transistor may be used for the other. The gate driver 706 described above is the same as the source driver 704.

[0257] The signal line 710 uses the same conductive material as the source and drain electrodes of transistors 750 and 752. It is formed of an electrical film. In this case, if a low-resistance material such as a material containing copper is used, the wiring This is preferable because it minimizes signal delays caused by resistance, allowing for display on a large screen.

[0258] The FPC terminal section 708 includes wiring 760, part of which functions as a connecting electrode, and an anisotropic conductive film 780. , and FPC716. The wiring 760 is connected to the FPC71 via the anisotropic conductive film 780. It is electrically connected to the terminals of 6. Here, wiring 760 is connected to transistor 750. It is formed of the same conductive film as the source electrode and drain electrode of 752.

[0259] The first substrate 701 and the second substrate 705 are, for example, a glass substrate or a plastic substrate. Flexible substrates such as acrylic substrates can be used. By using a flexible substrate, flexible A display can be realized. When a flexible substrate is used for the first substrate 701, Between substrate 701 and transistor 750, etc., an insulating material that provides barrier properties against water and hydrogen is placed. It is preferable to provide a border layer.

[0260] On the second substrate 705 side, there is a light-shielding film 738, a colored film 736, and an insulating film 73 in contact with them. 4 and are provided.

[0261] In Figures 10, 11, and 12, between the first substrate 701 and the second substrate 705, A spacer 778 is provided to adjust the distance between the two substrates. The substrate 701 and the second substrate 705 are bonded together by a sealing material 712.

[0262] The display device 700 shown in Figure 10 has a vertical electric field type liquid crystal element 775. It has a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 between them. 4 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is It is electrically connected to the source or drain electrode of transistor 750. The electrode layer 772 is formed on the planarizing insulating film 770 and functions as a pixel electrode.

[0263] The conductive layer 772 is made of a material that is transparent to visible light or reflects visible light. Materials that possess this property can be used. Examples of materials that have transparency to visible light include, for example, It is preferable to use oxide materials containing indium, zinc, tin, etc. Reflectivity to visible light Suitable materials include, for example, aluminum and silver.

[0264] If a material that is reflective to visible light is used for the conductive layer 772, the display device 700 becomes reflective. This will be a liquid crystal display device. On the other hand, the conductive layer 772 will be made of a material that is transparent to visible light. This results in a transmissive liquid crystal display. In the case of a reflective liquid crystal display, a polarizing plate is installed on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates are provided so as to sandwich the liquid crystal element. .

[0265] The display device 700 shown in Figure 11 uses a transverse field system (for example, FFS (Fringe Field)). An example using a liquid crystal element 775 in Switching mode is shown. On the conductive layer 772 A conductive layer 774, which functions as a common electrode, is provided via an insulating layer 773. The electric field generated between 72 and the conductive layer 774 controls the orientation state of the liquid crystal layer 776. It is possible.

[0266] In Figure 11, the laminated structure of conductive layer 772, insulating layer 773, and conductive layer 774 provides the necessary capacitance retention. This allows for the construction of a capacitor element, eliminating the need to provide a separate capacitor element and increasing the aperture ratio. It is possible.

[0267] Although not shown in Figures 10 and 11, the configuration includes an alignment film in contact with the liquid crystal layer 776. It may also be used. In addition, optical components (optical substrates) such as polarizing members, phase difference members, and anti-reflective members, and Light sources such as backlights and sidelights can be provided as needed.

[0268] The liquid crystal layer 776 contains thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, and polymer dispersed liquid crystal. Polymer network liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc., can be used. Furthermore, when employing a transverse electric field method, a liquid crystal exhibiting a blue phase without an alignment layer may be used. .

[0269] The modes of the liquid crystal elements are TN (Twisted Nematic) mode and VA (V (Certical Alignment) mode, IPS (In-Plane-Switc (hing) mode, FFS mode, ASM (Axially Symmetric Al Ignished Micro-cell) mode, OCB (Optical Compensator) ECB (Electrically Assisted Birefringence) mode, Controlled Birefringence mode, VA-IPS mode, You can use modes such as Street Host mode.

[0270] Furthermore, as a method for driving liquid crystal elements, color display is performed based on the time-additive color mixing method, A segmentation display method (also known as a field sequential drive method) may be applied. A configuration without a colored film 736 is possible. When using a time-division display method, for example, For example, it is necessary to provide subpixels that exhibit the respective colors red (R), green (G), and blue (B). Therefore, it is possible to increase the aperture ratio of pixels and the resolution of the display device.

[0271] The display device 700 shown in Figure 12 and the display device 700A shown in Figure 13 have a light-emitting element 782. The light-emitting element 782 has a conductive layer 772, an EL layer 786, and a conductive film 788. The L layer 786 contains a light-emitting material.

[0272] Luminescent materials include substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), and heat Substances that exhibit thermally activated delayed fluorescence (thermally activated d delayed fluorescence (TADF) materials), inorganic compounds (quantum Materials such as dot patterns can be used.

[0273] The display device 700 shown in Figure 12 and the display device 700A shown in Figure 13 have a planarizing insulating film 77 An insulating film 730 is provided on the 0, covering a portion of the conductive layer 772. Here, the light-emitting element 782 is This is a top-emission type light-emitting element having a conductive film 788 that transmits visible light. The light-emitting element 782 has a bottom emission structure that emits light towards the conductive layer 772, and the conductive layer It can also be used as a dual emission structure that emits light from both the 772 side and the conductive film 788 side. stomach.

[0274] In Figure 12, the colored film 736 is provided in a position that overlaps with the light-emitting element 782, and the light-shielding film 738 These are provided in positions overlapping with the insulating film 730, in the routing wiring section 711, and in the source driver 704. Furthermore, the colored film 736 and the light-shielding film 738 are covered with an insulating film 734. Furthermore, the space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. (See Figure 13) As shown, a different EL layer 786 is formed for each subpixel of each color in a side-by-side configuration. When using the method (also known as the color-separation method), it is not necessary to provide the colored film 736.

[0275] In Figure 13, the EL layer 786 of the light-emitting element 782 consists of an insulating film 730 and a conductive layer 77 2 is arranged in an island shape on top. The EL layer 786 is made so that the light emission color differs for each sub-pixel. By doing so, color display can be achieved without using the colored film 736. Also, the light-emitting element A protective layer 741 is provided covering the light-emitting element 782. The protective layer 741 provides water to the light-emitting element 782. It has the function of preventing the diffusion of impurities such as the above. The protective layer 741 uses an inorganic insulating film. It is preferable to have a laminated structure that includes one or more inorganic insulating films and one or more organic insulating films. That is preferable.

[0276] The display device 700A shown in Figure 13 replaces the first substrate 701 shown in Figure 12 with a support substrate It has a structure in which 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744 are laminated together. The transistors 750 and capacitive elements 790, etc., are placed on the insulating layer 744.

[0277] The support substrate 745 is a substrate containing organic resin, glass, etc., and is thin enough to be flexible. The resin layer 743 is a layer containing organic resins such as polyimide and acrylic. The insulating layer 744 is It contains an inorganic insulating film such as silicon oxide, silicon oxide nitride, and silicon nitride. Resin layer 743 The support substrate 745 is bonded together by an adhesive layer 742. The resin layer 743 is a support It is preferable that the substrate is thinner than the holding substrate 745.

[0278] Furthermore, the display device 700A shown in Figure 13 replaces the second circuit board 705 shown in Figure 12 for protection. It has a layer 740. The protective layer 740 is bonded to the sealing film 732. Protective layer 740 For example, glass substrates and resin films can be used. Also, protective layer 740 and And optical components such as polarizing plates and scattering plates, input devices such as touch sensors, or these A configuration with two or more layers stacked on top of each other may also be applied.

[0279] Furthermore, Figure 13 shows the foldable region P2. Region P2 is the support substrate 745 In addition to the adhesive layer 742, there are portions where no inorganic insulating film such as an insulating layer 744 is provided. Furthermore, in region P2, a resin layer 746 is provided covering the wiring 760. In the possible region P2, an inorganic insulating film is provided as little as possible, and a conductive layer containing metal or alloy is provided. By constructing a structure in which only layers containing organic materials are laminated, cracks will occur when bent. This can be prevented. Also, by not providing the support substrate 745 in region P2, it is possible to make it extremely small The radius of curvature allows a portion of the 700A display device to be bent.

[0280] The display device of this embodiment may have an input device such as a touch sensor. The display device of the embodiment may also have the function of a touch panel.

[0281] Sensor types include capacitive, resistive, surface acoustic wave, infrared, and optical. Various methods can be used, such as pressure-sensitive or pressure-sensitive methods. Alternatively, two or more of these can be combined. They may be used together.

[0282] As a touch panel, it is a so-called in-cell type touch panel in which the input device is formed inside a pair of circuit boards. A touch panel, an input device formed on a display device, is a so-called on-cell type touch panel, or a display panel. Examples include so-called out-cell type touch panels that are attached to display devices.

[0283] This embodiment can be combined with other embodiments as appropriate.

[0284] (Embodiment 3) In this embodiment, a display device having a semiconductor device according to one aspect of the present invention is shown in Figure 14. I will explain.

[0285] A semiconductor device according to one aspect of the present invention has good electrical characteristics, and therefore can be used in a display device. The reliability of the display device can be improved. For example, a transistor according to one aspect of the present invention is This can be applied to transistors in either or both of the pixels and the driving circuit of the display device. can.

[0286] The display device shown in Figure 14(A) comprises a pixel unit 502, a drive circuit unit 504, and a protection circuit 506. It has a terminal section 507 and a protective circuit 506.

[0287] Transistors in the pixel section 502 and the drive circuit section 504 are configured according to one aspect of the present invention. A transistor can be applied. Also, a transistor according to one aspect of the present invention can be applied to the protection circuit 506. You may apply this.

[0288] The pixel section 502 consists of multiple pixels arranged in an X row and Y column (where X and Y are independent natural numbers greater than or equal to 2). It has multiple pixel circuits 501 that drive the display elements.

[0289] The drive circuit section 504 is a gate driver that outputs a scan signal to scan lines GL_1 to GL_X. 504a. Source driver 504 that supplies data signals to data lines DL_1 through DL_Y. It has a drive circuit such as b. The gate driver 504a has at least a shift register. The source driver 504b is configured using, for example, multiple analog switches. Alternatively, the source driver 504b may be configured using a shift register or the like.

[0290] Terminal 507 is used to input power, control signals, and image signals, etc., from an external circuit to the display device. This refers to the part that is equipped with terminals for that purpose.

[0291] The protection circuit 506, when a potential outside a certain range is applied to the wiring it connects to, This is a circuit that creates a conductive state between the said wiring and another wiring. The protection circuit 506 shown in Figure 14(A) is For example, the scan line GL is the wiring between the gate driver 504a and the pixel circuit 501, and This is the wiring between the source driver 504b and the pixel circuit 501, including data lines DL and other various wiring. It connects to the network.

[0292] The gate driver 504a and the source driver 504b are based on the same base as the pixel unit 502. They may be formed directly on the board, or formed on another substrate, and COG or TAB (Tape A structure that is mounted on a substrate in which pixel parts are formed by automated bonding. It can be considered a success.

[0293] The multiple pixel circuits 501 shown in Figure 14(A) are, for example, shown in Figures 14(B) and 14(C). The configuration shown can be as follows.

[0294] The pixel circuit 501 shown in Figure 14(B) consists of a liquid crystal element 570, a transistor 550, and a capacitor. It has element 560 and, The pixel circuit 501 has data line DL_n, scan line GL_m, and The supply line VL and others are connected.

[0295] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the data written to it. A common potential is set on one of the pair of electrodes of the liquid crystal element 570 that each of the pixel circuits 501 has. A common potential may be applied. Also, the pair of liquid crystal elements 570 of the pixel circuit 501 in each row may be charged. A different potential may be applied to one of the poles.

[0296] The pixel circuit 501 shown in Figure 14(C) consists of transistors 552 and 554 and a capacitive element 562 It has a light-emitting element 572 and a pixel circuit 501. The pixel circuit 501 has data lines DL_n and scan lines GL _m, potential supply line VL_a, potential supply line VL_b, etc. are connected.

[0297] Of the potential supply lines VL_a and VL_b, a high power supply potential VDD is supplied to one of them. On the other hand, a low power supply potential VSS is applied to the gate of transistor 554. The current flowing through the light-emitting element 572 is controlled according to the potential, thereby controlling the current flowing through the light-emitting element 572. The luminescence of these lights is controlled.

[0298] This embodiment can be combined with other embodiments as appropriate.

[0299] (Embodiment 4) In this embodiment, a display device having a semiconductor device according to one aspect of the present invention is shown in Figure 15. I will explain.

[0300] The pixels of the display device in this embodiment have memory for correcting gradation (luminance value). A transistor according to one aspect of the invention can be applied to a transistor in a pixel. .

[0301] [Pixel circuit] Figure 15(A) shows the circuit diagram of the pixel circuit 400. The pixel circuit 400 uses transistor M1 It has a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 has wiring S 1. Wiring S2, wiring G1, and wiring G2 are connected.

[0302] Transistor M1 has its gate connected to wiring G1, and one of its sources and drains connected to wiring S1, and the other The electrodes of capacitor C1 are connected to each other. Transistor M2 has its gate connected to wiring G 2, one of the source and drain is wiring S2, the other electrode is capacitance C1, and the circuit Connect to 401, respectively.

[0303] Circuit 401 is a circuit that includes at least one display element. Various elements can be used as the display element. While various types can be used, typically light-emitting elements such as organic EL elements and LED elements, and liquid crystal elements are used. Sub-elements, or MEMS elements, etc., can be applied.

[0304] The node connecting transistor M1 and capacitor C1 is N1, and transistor M2 and circuit 401 Let N2 be the node connecting the two points.

[0305] The pixel circuit 400 maintains the potential of node N1 by turning off transistor M1. This is possible. Also, by turning off transistor M2, the potential of node N2 can be changed. It can hold. Also, with transistor M2 in the off state, the transistor By writing a predetermined potential to node N1 via terminal M1, capacitive coupling via capacitor C1 occurs. Therefore, the potential of node N2 can be changed in response to the change in the potential of node N1.

[0306] Here, in one or both of transistors M1 and M2, As illustrated earlier, a transistor using an oxide semiconductor can be applied. By using an extremely small off-current, the potentials of nodes N1 and N2 are maintained for a long period of time. This is possible. However, if the period for which the potential of each node is maintained is short (specifically, the frame When the frequency is 30Hz or higher, a transistor using a semiconductor such as silicon is used. You may also use "ta".

[0307] [Drive method] An example of how the pixel circuit 400 operates will be explained using Figure 15(B). Figure 15(B) is This is a timing chart related to the operation of the pixel circuit 400. For simplicity of explanation, this chart is presented here. Therefore, various resistors such as wiring resistance, parasitic capacitance of transistors and wiring, and transistors The effects of threshold voltage and other factors are not considered.

[0308] In the operation shown in Figure 15(B), one frame period is divided into period T1 and period T2. Period 1 is the period during which the potential is written to node N2, and period T2 is the period during which the potential is written to node N1. It is in between.

[0309] During period T1, a potential is applied to both wire G1 and wire G2 to turn on the transistor. Furthermore, the wiring S1 has a fixed potential V ref The first data is supplied to wiring S2. Potential V w To supply.

[0310] Node N1 receives a potential V from wiring S1 via transistor M1. ref It is given. Furthermore, at node N2, the first data potential V is connected via transistor M2. w It is given. Therefore, the capacitance C1 has a potential difference V w -V ref This state is maintained.

[0311] During period T2, a potential is applied to wiring G1 to turn on transistor M1, and a potential is applied to wiring G2. A potential is applied to turn off the transistor M2. Additionally, a second data potential V is applied to the wiring S1. d ata The following is supplied: A predetermined constant potential is applied to the wiring S2, or it is placed in a floating state. ru.

[0312] Node N1 has a second data potential V via transistor M1. data This is given. At that time, due to capacitive coupling by capacitance C1, the second data potential V data Node N2 The potential changes by a potential dV. That is, in circuit 401, the first data potential V w and electric potential The input will be the potential with dV added. Note that in Figure 15(B), the potential dV is a positive value. Although it is shown as such, it can also be a negative value. That is, the second data potential V data The potential is V ref It can be lower.

[0313] Here, the potential dV is roughly determined by the capacitance value of capacitor C1 and the capacitance value of circuit 401. If the capacitance value of capacitor C1 is sufficiently larger than the capacitance value of circuit 401, the potential dV is the second day. Potential V data The potential will be close to that.

[0314] Thus, the pixel circuit 400 is a circuit that includes a display element, which combines two types of data signals. Since it can generate the potential supplied to 401, grayscale correction is performed within the pixel circuit 400. This becomes possible.

[0315] Furthermore, the pixel circuit 400 generates a potential exceeding the maximum potential that can be supplied to wiring S1 and wiring S2. It also becomes possible to achieve this. For example, when using light-emitting elements, high dynamic range ( It can display HDR (High Dynamic Range) and other functions. Furthermore, when using liquid crystal elements, overdrying can be performed. It can implement features such as drive mechanisms.

[0316] [Pixel circuit with liquid crystal elements] The pixel circuit 400LC shown in Figure 15(C) has circuit 401LC. Circuit 401LC is It has a liquid crystal element LC and a capacitance C2.

[0317] One electrode of the liquid crystal element LC is connected to node N2 and one electrode of capacitor C2, and the other electrode is connected to The poles have a potential of V. com2 Connect to the wiring provided. The other electrode of capacitance C2 is at potential V c om1 Connect to the provided wiring.

[0318] Capacity C2 functions as the retention capacity. Note that capacity C2 can be omitted if it is not needed. ru.

[0319] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, for example, High-speed display is achieved through overdrive, and high-voltage liquid crystal materials are used. It is possible to do things like this. Also, by supplying a correction signal to wiring S1 or wiring S2, The gradation can also be corrected according to factors such as temperature and the degradation state of the liquid crystal elements (LC).

[0320] [Pixel circuit with light-emitting element] The pixel circuit 400EL shown in Figure 15(D) has circuit 401EL. Circuit 401EL is It has a light-emitting element EL, a transistor M3, and a capacitor C2.

[0321] Transistor M3 has its gate connected to one electrode of node N2 and capacitance C2, and its source and drain One side of the input is at potential V. H One is the wiring that is given, and the other is one electrode of the light-emitting element EL, and each They are connected. The other electrode of capacitance C2 has a potential of V com Connect to the provided wiring. The other electrode of the EL photonic element has a potential V L Connect to the provided wiring.

[0322] Transistor M3 has the function of controlling the current supplied to the light-emitting element EL. Capacitor C2 is It functions as a holding capacity. Capacity C2 can be omitted if not needed.

[0323] Note that this configuration shows the anode side of the light-emitting element EL connected to transistor M3. However, transistor M3 may be connected to the cathode side. In that case, the potential V H and potential V L The value can be changed as needed.

[0324] The pixel circuit 400EL generates a light-emitting element by applying a high potential to the gate of transistor M3. Because EL displays can handle large currents, they can enable features such as HDR display. Furthermore, by supplying a correction signal to wiring S1 or wiring S2, the transistor M3 and generator can be controlled. It can also correct for variations in the electrical characteristics of photonic elements (ELs).

[0325] Note that the circuits are not limited to those exemplified in Figures 15(C) and 15(D), and may also include transistors and capacitors. It is also acceptable to include additional elements such as quantity.

[0326] This embodiment can be combined with other embodiments as appropriate.

[0327] (Embodiment 5) In this embodiment, a display module according to one aspect of the present invention will be described with reference to Figure 16. .

[0328] The display module 6000 shown in Figure 16(A) consists of an upper cover 6001 and a lower cover 600 Between 2 and the display device 6006, frame 6009, and printout, FPC6005 is connected. It has a circuit board 6010 and a battery 6011.

[0329] A display device made using a transistor according to one aspect of the present invention is used in the display device 6006. This is possible. The display device 6006 enables the realization of a highly reliable display module. It is possible.

[0330] The upper cover 6001 and the lower cover 6002 are sized to fit the display device 6006. The shape and dimensions can be changed as needed.

[0331] The display device 6006 may also have the functionality of a touch panel.

[0332] Frame 6009 is controlled by the protective function of the display device 6006 and the operation of the printed circuit board 6010. It may also have functions such as blocking the generated electromagnetic waves or acting as a heat sink.

[0333] Printed circuit board 6010 contains power supply circuits and signal outputs for video signals and clock signals. It includes a processing circuit, a battery control circuit, etc. It may also be powered by a battery 6011.

[0334] Figure 16(B) is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. be.

[0335] The display module 6000 includes a light-emitting section 6015 and a light-receiving section provided on the printed circuit board 6010. It has part 6016. It also has an area enclosed by the upper cover 6001 and the lower cover 6002. The region has a pair of light guides (light guide 6017a, light guide 6017b).

[0336] The display device 6006 connects to the printed circuit board 6010 and battery 6 via the frame 6009. It is provided overlapping with 011. The display device 6006 and frame 6009 are connected to the light guide section 601 7a is fixed to the light guide section 6017b.

[0337] Light 6018 emitted from the light-emitting unit 6015 is directed by the light guide unit 6017a to the display device 6006 It passes through the upper part and through the light guide part 6017b to reach the light receiving part 6016. For example, a finger or a bib When light 6018 is blocked by an object to be detected, such as a lath, touch operation can be detected. It is possible.

[0338] Multiple light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. Multiple light-emitting units 6016 are provided at positions opposite to the light-emitting unit 6015. This allows for touch Information about the location where the operation was performed can be obtained.

[0339] The light-emitting section 6015 can use a light source such as an LED element, and in particular, infrared light It is preferable to use a light source that emits light. The light receiving unit 6016 receives the light emitted by the light emitting unit 6015. A photoelectric element that receives light and converts it into an electrical signal can be used. Preferably, one that can receive infrared light. A photodiode can be used.

[0340] Light 6018 is transmitted through the light guides 6017a and 6017b, which connect the light-emitting part 6015 to the receiving part 6015. The light-receiving unit 6016 can be positioned below the display device 6006, and ambient light can be received by the light-receiving unit 6016. This can prevent the touch sensor from malfunctioning by absorbing visible light and infrared light. Using a transparent resin can more effectively suppress malfunctions of touch sensors.

[0341] This embodiment can be combined with other embodiments as appropriate.

[0342] (Embodiment 6) In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to Figures 17 to 20. ru.

[0343] The electronic device of this embodiment has a semiconductor device according to one aspect of the present invention. For example, the electronic device By applying a transistor according to one aspect of the present invention to the transistor of a display device used in the display unit. This is possible. A transistor according to one aspect of the present invention has stable and good electrical characteristics and is highly reliable. Therefore, the reliability of display devices and electronic devices can be improved. Thus, one aspect of the present invention Transistors can be used in a variety of electronic devices.

[0344] The display unit of the electronic device in this embodiment can display, for example, Full HD, 4K2K, 8K4K, It can display video with a resolution of 16K, 8K, or higher.

[0345] Examples of electronic devices include television equipment, desktop or notebook computers, etc. Sony Computer, monitors for computers, digital signage, pachinko machines, etc. In addition to electronic devices with relatively large screens such as large game consoles, digital cameras, and digital cameras Digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals Examples include sound reproduction devices.

[0346] The electronic device of this embodiment is installed in the interior or exterior walls of a house or building, or inside a car. It can be incorporated along the curved surface of the frame or exterior.

[0347] The electronic device of this embodiment may have an antenna. The antenna receives a signal. This allows the display unit to show images, information, etc. Also, the electronic equipment has an antenna and If a secondary battery is present, the antenna may be used for contactless power transmission.

[0348] The electronic device of this embodiment has sensors (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, Distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, radiation (including functions for measuring radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation) It's fine if you do that.

[0349] The electronic device of this embodiment can have various functions. For example, it can display various information (static Functions to display still images, videos, text images, etc. on the display unit, touch panel function, calendar - Functions to display the date or time, and to run various software (programs) Functions, wireless communication functions, and functions to read programs or data recorded on recording media. It may have the following:

[0350] The electronic device 6500 shown in Figure 17(A) is a portable device that can be used as a smartphone. It is an information terminal.

[0351] The electronic device 6500 consists of a housing 6501, a display unit 6502, a power button 6503, and a button 65 04, includes speaker 6505, microphone 6506, camera 6507, and light source 6508, etc. The display unit 6502 is equipped with a touch panel function.

[0352] A display device having a transistor according to one aspect of the present invention can be applied to the display unit 6502. Cut.

[0353] Figure 17(B) is a schematic cross-sectional view of the housing 6501 including the end on the microphone 6506 side.

[0354] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501. Within the space surrounded by the protective member 6510, there is a display panel 6511, an optical member 6512, and a touch The sensor panel 6513, printed circuit board 6517, battery 6518, etc. are located here. .

[0355] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. The 6513 is fixed by an adhesive layer (not shown).

[0356] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back. The FPC6515 is connected to the folded portion. C6516 is mounted. FPC6515 is located on the edge of the printed circuit board 6517. It is connected to the child.

[0357] A flexible display according to one aspect of the present invention can be applied to the display panel 6511. This makes it possible to create extremely lightweight electronic devices. Also, the display panel 6511 is extremely Because it is thin, it is possible to keep the thickness of electronic devices down while also equipping them with a large-capacity 6518 battery. Also, a part of the display panel 6511 is folded back, and the FPC6515 is attached to the back of the pixel area. By positioning the connection points, it is possible to realize electronic devices with narrow bezels.

[0358] Figure 18(A) shows an example of a television system. The television system 7100 is housed in a casing 71 The display unit 7000 is incorporated into 01. Here, the stand 7103 connects to the housing 71 This shows the configuration that supports 01.

[0359] A display device having a transistor according to one aspect of the present invention can be applied to the display unit 7000. Cut.

[0360] The television device 7100 shown in Figure 18(A) is operated by the control switches provided on the housing 7101. This can be done via the switch or a separate remote control unit 7111. Alternatively, the display unit 700 It may also be equipped with a touch sensor, and by touching the display unit 7000 with a finger, etc., the TV will The control device 7100 may be operated. The remote control operator 7111 is the remote control operator 71 It may have a display unit that displays the information output from 11. The channel and volume can be controlled using the built-in control keys or touch panel. The video displayed on the display unit 7000 can be operated.

[0361] The television system 7100 will consist of a receiver and a modem, etc. This allows you to receive regular television broadcasts. Additionally, you can receive them via a modem using either a wired or wireless connection. By connecting to a line communication network, one-way (sender to receiver) or bidirectional communication is possible. It is also possible to communicate information in a direction (between a sender and receiver, or between receivers). ru.

[0362] Figure 18(B) shows an example of a notebook personal computer. The Computer 7200 consists of a casing 7211, a keyboard 7212, and a pointing device 7 It has external connection ports 7214, etc. The display unit 7000 is incorporated into the housing 7211. It is being made.

[0363] A display device having a transistor according to one aspect of the present invention can be applied to the display unit 7000. Cut.

[0364] Figures 18(C) and (D) show examples of digital signage.

[0365] The digital signage 7300 shown in Figure 18(C) consists of a housing 7301, a display unit 7000, and It also has a speaker 7303, etc. Furthermore, it has an LED lamp, operation keys (power switch, and It can have an operating switch, connection terminals, various sensors, a microphone, etc. ru.

[0366] Figure 18(D) shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 is a display unit 7000 that is installed along the curved surface of the column 7401. It has.

[0367] In Figures 18(C) and (D), the display unit 7000 has a transistor according to one embodiment of the present invention. A display device can be applied.

[0368] The larger the display area 7000, the more information can be provided at once. The wider the area (7000), the more easily it catches people's attention, which can, for example, enhance the effectiveness of advertising. Cut.

[0369] By applying a touch panel to the display unit 7000, images or videos can be displayed on the display unit 7000. It is desirable that it not only displays information but also allows users to operate it intuitively. Furthermore, route information is also available. Or, when used for purposes such as providing traffic information, intuitive operation is possible. It can improve usability.

[0370] Furthermore, as shown in Figures 18(C) and 18(D), the digital signage 7300 or Digital signage 7400 is an information terminal 731 such as a smartphone owned by the user. It is preferable that it be possible to communicate with 1 or an information terminal 7411 via wireless communication. For example, Information about advertisements displayed on the display unit 7000 is transmitted to the information terminal 7311 or information terminal 741. It can be displayed on screen 1. Also, information terminal 7311 or information terminal 741 By operating button 1, the display on display unit 7000 can be switched.

[0371] In addition, the information terminal 7 is connected to the digital signage 7300 or digital signage 7400. Execute a game using the screen of either the 311 or the information terminal 7411 as the control device (controller). It is also possible to allow this. This allows a large number of users to participate in the game and enjoy it simultaneously. It is possible.

[0372] Figure 19(A) shows the appearance of the Camera 8000 with the Viewfinder 8100 attached. This is a diagram.

[0373] The camera 8000 consists of the housing 8001, the display unit 8002, the operation buttons 8003, and the shutter button. It has a tan 8004, etc. The camera 8000 also has a detachable lens 8006 attached. It is being removed. Furthermore, even though the camera 8000 has the lens 8006 and the body integrated, good.

[0374] Camera 8000 can be activated by pressing the shutter button 8004, or by using the touch panel. Images can be captured by touching the display unit 8002.

[0375] The housing 8001 has a mount with electrodes, and in addition to the viewfinder 8100, a flash Devices and other equipment can be connected.

[0376] The viewfinder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc.

[0377] The housing 8101 engages with the mount of the camera 8000 via a mount, It is attached to the camera. The viewfinder 8100 displays images and other data received from the camera 8000. This can be displayed on the display unit 8102.

[0378] Button 8103 functions as a power button, etc.

[0379] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are equipped with this product. A display device having a transistor in one aspect can be applied. It may also be a camera 8000 with a built-in ―.

[0380] Figure 19(B) shows the external appearance of the head-mounted display 8200.

[0381] The head-mounted display 8200 consists of the mounting part 8201, the lens 8202, and the main body 820 3. It has a display unit 8204, a cable 8205, etc. Also, the mounting part 8201 has a battery It has a built-in TERI 8206 chip.

[0382] Cable 8205 supplies power from battery 8206 to main unit 8203. Main unit 820 Unit 3 is equipped with a wireless receiver and can display the received video information on the display unit 8204. Furthermore, the main unit 8203 is equipped with a camera and uses information about the user's eyeball and eyelid movements as an input means. It can be used in this way.

[0383] Furthermore, the attachment portion 8201 is positioned in a location that touches the user, and the flow is controlled in accordance with the user's eye movements. It may be provided with multiple electrodes capable of detecting electric current and may have a function to recognize line of sight. The device may also have a function to monitor the user's pulse rate based on the current flowing through the electrode. Furthermore, the mounting section 8201 has various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. It may also have a function to display the user's biometric information on the display unit 8204, and the movement of the user's head. It may also have a function to change the image displayed on the display unit 8204 according to the time.

[0384] A display device having a transistor according to one aspect of the present invention can be applied to the display unit 8204. Cut.

[0385] Figures 19(C), (D), and (E) show the external appearance of the head-mounted display 8300. The head-mounted display 8300 consists of a housing 8301 and a display unit 8302, It comprises a band-shaped fastener 8304 and a pair of lenses 8305.

[0386] The user can view the display on the display unit 8302 through the lens 8305. Oh, by arranging the display unit 8302 in a curved shape, the user can experience a high level of realism. Therefore, it is preferable. Also, another image displayed in a different area of ​​the display unit 8302 is displayed by the lens 83 By viewing through 05, it is also possible to perform 3D displays using parallax. The configuration is not limited to having one display unit 8302, but can also have two display units 8302, allowing one of the users to... You may place one display unit per eye.

[0387] A display device having a transistor according to one aspect of the present invention can be applied to the display unit 8302. To do so. Using a transistor according to one aspect of the present invention, a display device with extremely high resolution can be manufactured. This is also possible. For example, as shown in Figure 19(E), the display can be magnified using lens 8305. Even when visible, the pixels are difficult for the user to see. In other words, using the display unit 8302 This allows users to perceive highly realistic images.

[0388] The electronic device shown in Figures 20(A) to 20(F) consists of a housing 9000, a display unit 9001, and a speaker. -Cable 9003, operation key 9005 (including power switch or operation switch), connection terminal Child 9006, Sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, radiation, (Including functions for measuring flow rate, humidity, gradient, vibration, odor, or infrared radiation), Microwave It has 9008, etc.

[0389] The electronic devices shown in Figures 20(A) to 20(F) have various functions. For example, various Functions for displaying information (still images, videos, text images, etc.) on the display unit, touch panel function, A function that displays a calendar, date, or time, and various software (programs) Therefore, the function that controls the process, the wireless communication function, the program recorded on the recording medium or It can have functions such as reading and processing data. It is not limited to these and can have a variety of functions. Electronic devices have multiple display units. It is permissible to have a camera or similar device installed on an electronic device to capture still images or videos and record them on an external recording medium. It has functions such as saving to (or built into the camera), displaying captured images on the display unit, etc. It's fine if you do that.

[0390] The details of the electronic equipment shown in Figures 20(A) to 20(F) will be explained below.

[0391] Figure 20(A) is a perspective view showing the personal digital assistant (PDA) 9101. The PDA 9101 is a personal digital assistant (PDA). For example, it can be used as a smartphone. Note that the mobile information terminal 9101 is a speaker. A connector 9003, connection terminal 9006, sensor 9007, etc. may be provided. Also, a portable information terminal The end 9101 can display text and image information on its multiple surfaces. As shown in Figure 20(A) This shows an example displaying three icons 9050. Also, information 90 is shown by a dashed rectangle. 51 can also be displayed on other sides of the display unit 9001. An example of information 9051 is: Notifications for incoming emails, social media messages, and phone calls; subject lines and sender names for emails and social media messages. This includes the date and time, battery level, and antenna signal strength. Alternatively, see Information 9051. You may also display icon 9050 or similar in the location where the symbol is displayed.

[0392] Figure 20(B) is a perspective view showing the personal digital assistant (PDA) 9102. The PDA 9102 is, The display unit 9001 has the function of displaying information on three or more sides. Here, information 9052, information This shows an example where Report 9053 and Information 9054 are displayed on different sides. For example, user This is with the personal digital assistant 9102 stored in the breast pocket of the clothing, and the personal digital assistant 9102 The user can also check the information 9053 displayed in a position that can be observed from above. Without taking the 9102 personal digital assistant out of your pocket, you can check the display and, for example, answer a phone call. It allows you to decide whether or not to do it.

[0393] Figure 20(C) is a perspective view showing a wristwatch-type personal information terminal 9200. Personal information terminal 9 200 can be used, for example, as a smartwatch. Also, the display unit 9001 is The display surface is curved, allowing the display to follow the curved surface. The mobile information terminal 9200 is to communicate with, for example, a wireless headset. Therefore, hands-free calling is also possible. In addition, the mobile information terminal 9200 has a connection terminal Child 9006 enables mutual data transmission with other information terminals and also allows charging. Yes, it can. Furthermore, charging may be performed via wireless power supply.

[0394] Figures 20(D), (E), and (F) are perspective views showing a foldable portable information terminal 9201. Yes. Also, Figure 20(D) shows the mobile information terminal 9201 in its unfolded state, and Figure 20(F) shows it folded. In its folded state, Figure 20(E) shows the transition from one of Figures 20(D) and 20(F) to the other. This is a perspective view of the device in its folded state. The 9201 portable information terminal offers excellent portability when folded and unfolded. When open, the seamless, wide display area provides excellent readability. (Portable Information Terminal 9) The display unit 9001 of 201 is connected by a hinge 9055 to three housings 900 It is supported by 0. For example, the display unit 9001 has a radius of curvature of 0.1 mm or more and 150 mm or less. It can be bent downwards.

[0395] This embodiment can be appropriately combined with other embodiments and examples. [Examples]

[0396] In this embodiment, a transistor is fabricated using a transistor fabrication method according to one aspect of the present invention. Next, I will explain the evaluation results. Two types of samples were prepared.

[0397] As sample A to which one aspect of the present invention is applied, the transistor shown in Figures 3(A) to 3(C) is shown. A laminated structure corresponding to the structure of 100A was formed. Specifically, a conductive layer 1 was formed on the substrate 102. 06, insulating layer 103, semiconductor layer 108, gate insulating layer 110, gate electrode 112, insulating layer 118, conductive layer 120a, and conductive layer 120b were formed. Furthermore, insulating layer 118, conductive A planarization film (not shown) was formed on layer 120a and conductive layer 120b.

[0398] As comparative sample B, a stacked structure corresponding to the transistor structure shown in Figure 21 was formed. Figure 21 shows cross-sections of the transistor in the channel length direction and channel width direction side by side. Specifically, the substrate 102 has a conductive layer 106, an insulating layer 103, a semiconductor layer 108, and a gate insulating layer. 110, metal oxide layer 114, gate electrode 112, insulating layer 118, conductive layer 120a, and A conductive layer 120b was formed. Furthermore, an insulating layer 118, a conductive layer 120a, and a conductive layer 120 A planarization film (not shown) was formed on b.

[0399] In sample A to which one aspect of the present invention is applied, as shown in Embodiment 1, the gate insulating layer 1 A metal oxide layer 114 is formed on 10, and after heat treatment, the metal oxide layer 114 is completely It was removed. On the other hand, in comparative sample B, after heat treatment, the metal oxide layer 114 was removed. He didn't leave.

[0400] The specific method for fabricating transistors will be explained below using Figures 5 to 8.

[0401] First, a tungsten film with a thickness of approximately 100 nm is spat onto a glass substrate (corresponding to substrate 102). A conductive layer 106 was formed by the tarring method and then processed (Figure 5(A)).

[0402] Next, an insulating layer 103 was formed on the substrate 102 and the conductive layer 106 (Figures 5(A) and 6). (A)). In this embodiment, the insulating layer 103 is as shown in Figure 6(A), a, insulating layer 103b on insulating layer 103a, insulating layer 103c on insulating layer 103b, A silicon nitride film with a thickness of approximately 240 nm was formed as the insulating layer 103a. As b, a silicon nitride film with a thickness of approximately 60 nm, and as the insulating layer 103c, a film with a thickness of approximately 5 nm. The silicon oxide nitride films were formed using plasma CVD (Chemical Vapor Deposition).

[0403] Next, an IGZO film with a thickness of approximately 40 nm is formed on the insulating layer 103 and processed to create a semiconductor Body layer 108 was formed (Figure 5(B)). The IGZO film was formed by sputtering, resulting in a number of atoms Using a metal oxide target with an In:Ga:Zn ratio of 1:1:1, the oxygen flow rate ratio was 5 The film was formed at 0% humidity and a substrate temperature of 100°C. After forming the IGZO film, it was subjected to 3°C under a nitrogen atmosphere. The material is heated at 50°C for 1 hour, and then subsequently heated at 350°C in a mixed atmosphere of oxygen and nitrogen. A 1-hour heat treatment was performed.

[0404] Next, plasma treatment is performed for 20 seconds in an atmosphere containing N2O gas, and then insulation is applied. A gate insulating layer 110 was formed on layer 103 and semiconductor layer 108 (Figures 5(C) and 6). (C)). In this embodiment, the gate insulating layer 110 is as shown in Figure 6(C), insulating layer 110a, insulating layer 110b on insulating layer 110a, and insulating layer 110c on insulating layer 110b And, was formed. As the insulating layer 110a, a silicon oxidizide film with a thickness of approximately 5 nm was formed as the insulating layer As 110b, a silicon oxidizide film with a thickness of approximately 140 nm is used, and as the insulating layer 110c, thickness A silicon oxidizride film approximately 5 nm thick was formed by plasma CVD. Layer 110a and insulating layer 110c are each deposited under conditions where the deposition rate is lower than that of insulating layer 110b. It was formed by [this method].

[0405] Next, a metal oxide layer 114 is placed on the gate insulating layer 110 in an oxygen-containing atmosphere. An aluminum oxide film with a thickness of approximately 5 nm was formed by sputtering (Figure 5(C)). ). By forming the metal oxide layer 114 in an oxygen-containing atmosphere, the gate insulating layer 110 Oxygen can be supplied to it. The substrate temperature during the deposition of the aluminum oxide film is 170°C. After forming the aluminum oxide film, it was heated in a mixed atmosphere of oxygen and nitrogen at 350°C for 1 The treatment involved heating over time.

[0406] Here, in sample A, the metal oxide layer 114 is completely removed (Figure 5(D)), and then... The process proceeded to the next step. On the other hand, in comparative sample B, the metal oxide layer 114 was not removed, and the next step was performed. It progressed to a certain extent.

[0407] Next, in sample A, the conductive material is applied on the gate insulating layer 110, and in comparative sample B, it is applied on the metal oxide layer 114. A molybdenum film with a thickness of approximately 100 nm was formed as film 112f by sputtering. Figure 5(E)), the gate electrode 112 was formed by processing (Figure 7(A)).

[0408] Next, boron (B) was supplied using a plasma ion doping device (Figure 7(B) and (Figure 7(C)). In this process, the gate electrode 112 is used as a mask, and the semiconductor layer 108 and Boron is supplied to the gate insulating layer 110 (and also to the metal oxide layer 114 in comparative sample B). It was supplied. B2H6 gas was used to supply boron, and the acceleration voltage was 40kV. The amount is 2 x 10 15 ions / cm 2 That's what I decided.

[0409] Next, an insulating layer 118 is applied to the gate insulating layer 110 and the gate electrode 112, with a thickness of approximately 30 A 0 nm silicon oxidnitride film was formed by plasma CVD (Figure 8(A)).

[0410] Next, a portion of the gate insulating layer 110 and insulating layer 118 was opened. In comparative sample B, the metal acid A portion of the ionized layer 114 was also opened. Then, a molybdenum film with a thickness of approximately 100 nm was sputtered. Conductive layers 120a and 120b were formed by forming and processing using a molding method. Figure 8(B)).

[0411] Subsequently, an acrylic film with a thickness of approximately 1.5 μm was formed as a planarization film (not shown), and nitrogen The material was subjected to a heat treatment at 250°C for 1 hour under controlled conditions.

[0412] Based on the above, each sample was prepared.

[0413] Next, the Id-Vg characteristics of the transistors were measured for each sample. See Figure 22(A) and Figure 22(A) and Figure 22(A). Figure 23(A) shows the transient of sample A, and Figures 22(B) and 23(B) show the transient of comparative sample B. The Id-Vg characteristic results for the TA are shown. Figures 22(A) and 22(B) show the channel length (L) These are the results for a transistor with a 2 μm channel and a channel width (W) of 3 μm, as shown in Figures 23(A) and 2. 3(B) is a transistor with a channel length (L) of 3 μm and a channel width (W) of 3 μm. It is the result.

[0414] The measurement conditions for the Id-Vg characteristics of the transistor are as follows: the voltage applied to the gate electrode 112 ( Gate voltage (Vg) and voltage applied to the conductive layer 106 (back gate voltage (Vbg)) The voltage was applied in 0.25V steps from -15V to +20V. Also, a mark was made on the source electrode. The applied voltage (source voltage (Vs)) is set to 0V (comm), and the voltage applied to the drain electrode is... The voltage (drain voltage (Vd)) was set to 0.1V and 10V.

[0415] In Figures 22 and 23, the vertical axis represents the drain current (Id(A)), and the horizontal axis represents the gate voltage (V). This represents g(V)).

[0416] As shown in Figures 22 and 23, there is no significant difference in Id-Vg characteristics between sample A and comparative sample B. No abnormalities were observed, and both exhibited favorable characteristics.

[0417] Next, a stress test was performed on the transistors in each sample.

[0418] For stress testing, a gate-biased thermal (GBT) stress test was used. This shows the results of the PBTS test and NBTIS test. In the PBTS test, the transistors The formed substrate is kept at 60°C, and 0V is applied to the source and drain of the transistor, and the gate A voltage of 45V was applied and this condition was maintained for 3600 seconds. In the NBTIS test, the traction The substrate on which the radiator is formed is kept at 60°C and irradiated with 10,000 lx white LED light. With the transistor in this state, apply a voltage of 0V to the source and drain and -45V to the gate. This state was maintained for 3600 seconds.

[0419] Figure 24 shows the results of the PBTS test and NBTIS test for sample A and comparative sample B. Figure 2 4 is the result for a transistor with a channel length (L) of 2 μm and a channel width (W) of 3 μm. ru.

[0420] As shown in Figure 24, compared to comparative sample B, sample A showed a threshold voltage in the PBTS test. The pressure fluctuation (ΔVth) was approximately 1 / 6, indicating extremely high reliability.

[0421] In this way, by completely removing the metal oxide layer 114 after heat treatment, the degradation of PBTS is significantly reduced. Significant improvements were observed.

[0422] From the above, by completely removing the metal oxide layer 114 after heat treatment, the electrical properties and It was found that transistors with good reliability could be fabricated. [Explanation of Symbols]

[0423] 100 transistors 100A Transistor 102 circuit boards 103 Insulating layer 103a Insulating layer 103b Insulating layer 103c insulating layer 103d area 103e insulating layer 106 Conductive layer 106c conductive layer 108 Semiconductor layer 10⁸c semiconductor layer 108n low resistance region 110 Gate Insulation Layer 110a insulating layer 110b Insulating layer 110c insulating layer 110d area 112 gates 112f conductive film 114 Metal oxide layer 118 Insulating layer 120a conductive layer 120b conductive layer 130A capacitive element 130B Capacitive element 140 Impurity Elements 141a opening 141b opening 142 Opening 400-pixel circuit 400EL pixel circuit 400LC pixel circuit 401 Circuit 401EL circuit 401LC circuit 501 Pixel Circuit 502 pixel section 504 Drive Circuit Section 504a Gate Driver 504b Source Driver 506 Protection circuit 507 Terminal section 550 transistors 552 transistors 554 transistors 560 Capacitive elements 562 Capacitance element 570 liquid crystal elements 572 Light-emitting element 700 Display device 700A display device 700B display unit 701 First substrate 702 pixel section 704 Source Driver 705 Second substrate 706 Gate Driver 708 FPC terminal section 710 signal line 711 Wiring section 712 Sealant 716 FPC 717 IC 721 Source Driver IC 722 Gate Driver 723 FPC 724 Printed Circuit Boards 730 Insulating Film 732 Encapsulation film 734 Insulating Film 736 Colored film 738 Light-shielding film 740 protective layer 741 Protective layer 742 Adhesive layer 743 Resin layer 744 Insulating layer 745 Support substrate 746 Resin layer 750 transistors 752 transistors 760 Wiring 770 Planarizing Insulator 772 Conductive layer 773 Insulating layer 774 Conductive layer 775 liquid crystal elements 776 Liquid Crystal Layer 778 Spacer 780 Anisotropic conductive film 782 Light-emitting element 786 EL layer 788 Conductive film 790 Capacitive elements 6000 Display Module 6001 Top cover 6002 Lower cover 6005 FPC 6006 Display device 6009 Frame 6010 Printed Circuit Board 6011 Battery 6015 Light-emitting part 6016 Light receiving section 6017a Light guiding part 6017b Light guiding part 6018 light 6500 Electronic equipment 6501 enclosure 6502 Display section 6503 Power button 6504 button 6505 Speaker 6506 Mike 6507 Camera 6508 Light source 6510 Protective component 6511 Display Panel 6512 Optical components 6513 Touch Sensor Panel 6515 FPC 6516 IC 6517 Printed circuit board 6518 Battery 7000 Display 7100 Television equipment 7101 enclosure 7103 Stand 7111 Remote Control Unit 7200 Notebook Personal Computer 7211 enclosure 7212 Keyboard 7213 Pointing device 7214 External connection port 7300 Digital Signage 7301 enclosure 7303 Speaker 7311 Information terminal 7400 Digital Signage 7401 pillars 7411 Information terminal 8000 Camera 8001 enclosure 8002 Display section 8003 Operation Buttons 8004 Shutter button 8006 Lens 8100 Finder 8101 enclosure 8102 Display section 8103 button 8200 Head-Mounted Display 8201 Mounting part 8202 Lens 8203 Main Unit 8204 Display section 8205 Cable 8206 Battery 8300 Head-Mounted Display 8301 enclosure 8302 Display section 8304 Fixtures 8305 Lens 9000 cabinets 9001 Display section 9003 Speaker 9005 Operation Keys 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Icon 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9101 Mobile Information Terminal 9102 Mobile Information Terminal 9200 Mobile Information Terminal 9201 Mobile Information Terminal

Claims

[Claim 1] Form an oxide semiconductor layer containing In, Ga, and Zn. A gate insulating layer containing silicon oxide is formed above the oxide semiconductor layer. A metal oxide layer is formed above the gate insulating layer. After forming the aforementioned metal oxide layer, heat treatment is performed. After the heat treatment, the metal oxide layer is removed. After removing the metal oxide layer, a gate electrode having a region overlapping with the oxide semiconductor layer is formed on the gate insulating layer. After forming the gate electrode, the gate electrode is used as a mask to supply the first element to the gate insulating layer and the oxide semiconductor layer. The first element, when supplied to the oxide semiconductor, has the function of reducing the electrical resistance of the oxide semiconductor layer. Method for manufacturing semiconductor devices.

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