Laminate, multilayer substrate, method for manufacturing a laminate, and method for manufacturing a multilayer substrate

Abstract

The present invention provides a laminate with improved allowable current values ​​and reliable bonding strength, a multilayer substrate obtained by stacking multiple such laminates, a method for manufacturing the laminate, and a method for manufacturing the multilayer substrate. [Solution] A laminate 56 comprising a first layer having a second metal layer 22 and one insulating layer 24, 26 formed to cover the second metal layer 22, and a second layer laminated on the first layer having a first metal layer 40 and another insulating layer 44 formed to cover the first metal layer 40, wherein the first layer has plated vias 34 that electrically connect the second metal layer 22 and the first metal layer 40, and the second layer has conductive paste vias 54 that electrically connect the first metal layer 40 and an external metal layer.

Description

Technical Field

[0001] The present invention relates to a laminate, a multilayer substrate, a method for producing a laminate, and a method for producing a multilayer substrate.

Background Art

[0002] Circuit boards having a multilayer structure (hereinafter sometimes referred to as "multilayer substrates") are generally widely known.

[0003] For example, Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2021-190602) discloses a multilayer substrate in which a plurality of laminates each having two metal layers are stacked. Conventional build-up type multilayer substrates, as they are made multilayer, have the yield per layer reflected in the overall yield as a multiplier of the number of layers, but the multilayer substrate disclosed in Patent Document 1 can achieve the above-described improvement in yield by fabricating laminates in advance.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of Invention

Problems to be Solved by the Invention

[0005] By the way, the multilayer substrate as disclosed in Patent Document 1 is manufactured by stacking a plurality of laminates in which conductive paste vias are continuously arranged, but using only conductive paste vias causes problems that the interlayer resistance value increases and the allowable current value decreases, and there is also a problem in terms of bonding strength as compared with a multilayer substrate having plated vias.

Means for Solving the Problems

[0006] Therefore, the present invention has been made to solve the above problems, and its objective is to provide a laminate that has an improved allowable current value and reliable bonding strength, a multilayer substrate obtained by stacking multiple such laminates, a method for manufacturing the laminate, and a method for manufacturing the multilayer substrate.

[0007] The laminate according to the present invention comprises a first layer having a second metal layer and an insulating layer formed to cover the second metal layer, and a second layer laminated on the first layer having a first metal layer and another insulating layer formed to cover the first metal layer, wherein the first layer has plated vias that electrically connect the second metal layer and the first metal layer, and the second layer has conductive paste vias that electrically connect the first metal layer and an external metal layer.

[0008] The laminate according to the present invention comprises: a first layer having a second metal layer and an insulating layer formed to cover the second metal layer so that the second metal layer is exposed on its lower surface; and a second layer laminated on top of the first layer, having a first metal layer formed on the upper surface of the insulating layer and another insulating layer formed to cover the first metal layer, wherein the first layer has plated vias that electrically connect the second metal layer and the first metal layer, and the second layer has conductive paste vias that electrically connect the first metal layer and an external metal layer.

[0009] The multilayer substrate according to the present invention is characterized by being constructed by stacking a plurality of laminates described in claim 1 or claim 2.

[0010] Furthermore, the bottom layer of the multilayer substrate is laminated with a bottom layer laminate, and the bottom layer laminate is characterized by having a metal layer, an insulating layer laminated on the metal layer, and conductive paste vias that electrically connect the metal layer to a second metal layer of another laminate arranged above the bottom layer laminate.

[0011] According to the manufacturing method of the laminate according to the present invention, the steps are: to form a patterned second metal layer by etching the copper foil of a three-layer metal foil consisting of copper foil, metal foil, and a metal support; to laminate a first insulating layer on the second metal layer so as to embed the second metal layer; to laminate a flat metal layer on the first insulating layer; to form a first through-hole that penetrates the flat metal layer and the first insulating layer and reaches the second metal layer; to form a first via, which is a plated via, in the first through-hole; and to etch the flat metal layer to form a patterned The invention is characterized by comprising the steps of: forming a first metal layer; laminating other insulating layers on the patterned first metal layer so as to embed the patterned first metal layer; removing the metal foil and the metal support from the three layers of metal foil; laminating an upper insulating layer and a resin film on the other insulating layers; forming a second through-hole that penetrates the resin film, the upper insulating layer and the other insulating layers and reaches the first metal layer; and filling the second through-hole with conductive paste to form a second via which is a paste via.

[0012] The method for manufacturing a multilayer substrate according to the present invention is characterized by including a step of stacking multiple laminates manufactured in the method for manufacturing a laminate described in claim 4 to obtain a multilayer substrate.

[0013] Furthermore, the process of obtaining the multilayer substrate is characterized by including a step of stacking so that the bottom layer is the bottom layer, the bottom layer having a metal layer, an insulating layer stacked on the metal layer, and conductive paste vias that electrically connect the metal layer and a second metal layer of the stacked laminate above it. [Effects of the Invention]

[0014] According to the present invention, the allowable current value is improved and reliable joint strength is achieved. [Brief explanation of the drawing]

[0015] [Figure 1]FIG. 1 is a schematic cross-sectional view (Part 1) showing an example of the method for manufacturing a multilayer substrate according to the first embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view (Part 2) showing an example of the method for manufacturing a multilayer substrate according to the first embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view (Part 3) showing an example of the method for manufacturing a multilayer substrate according to the first embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view (Part 4) showing an example of the method for manufacturing a multilayer substrate according to the first embodiment. [Figure 5] FIG. 5 is a schematic cross-sectional view (Part 5) showing an example of the method for manufacturing a multilayer substrate according to the first embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view (Part 6) showing an example of the method for manufacturing a multilayer substrate according to the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view (Part 7) showing an example of the method for manufacturing a multilayer substrate according to the first embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view (Part 8) showing an example of the method for manufacturing a multilayer substrate according to the first embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view (Part 9) showing an example of the method for manufacturing a multilayer substrate according to the first embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view (Part 10) showing an example of the method for manufacturing a multilayer substrate according to the first embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view (Part 11) showing an example of the method for manufacturing a multilayer substrate according to the first embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view (Part 12) showing an example of the method for manufacturing a multilayer substrate according to the first embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view (Part 13) showing an example of the method for manufacturing a multilayer substrate according to the first embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view (Part 14) showing an example of the method for manufacturing a multilayer substrate according to the first embodiment. [Figure 15] FIG. 15 is a schematic cross-sectional view (Part 15) showing an example of a method for manufacturing a multilayer substrate according to the first embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view (Part 16) showing an example of a method for manufacturing a multilayer substrate according to the first embodiment. [Figure 17] FIG. 17 is a schematic cross-sectional view (Part 17) showing an example of a method for manufacturing a multilayer substrate according to the first embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view (Part 18) showing an example of a method for manufacturing a multilayer substrate according to the first embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view (Part 19) showing an example of a method for manufacturing a multilayer substrate according to the first embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view (Part 20) showing an example of a method for manufacturing a multilayer substrate according to the first embodiment. [Figure 21] FIG. 21 is a schematic cross-sectional view (Part 21) showing an example of a method for manufacturing a multilayer substrate according to the first embodiment. [Figure 22] FIG. 22 is a schematic cross-sectional view (Part 22) showing an example of a method for manufacturing a multilayer substrate according to the first embodiment. [Figure 23] FIG. 23 is a schematic cross-sectional view (Part 23) showing an example of a method for manufacturing a multilayer substrate according to the second embodiment. [Figure 24] FIG. 24 is a schematic cross-sectional view (Part 24) showing an example of a method for manufacturing a multilayer substrate according to the second embodiment. [Figure 25] FIG. 25 is a schematic cross-sectional view (Part 25) showing an example of a method for manufacturing a multilayer substrate according to the second embodiment. [Figure 26] FIG. 26 is a schematic cross-sectional view (Part 26) showing an example of a method for manufacturing a multilayer substrate according to the second embodiment. [Figure 27] FIG. 27 is a schematic cross-sectional view (Part 27) showing an example of a method for manufacturing a multilayer substrate according to the second embodiment. [Figure 28]Figure 28 is a schematic cross-sectional view (28th of its kind) showing an example of a method for manufacturing a multilayer substrate in the second embodiment. [Figure 29] Figure 29 is a schematic cross-sectional view (29th of its kind) showing an example of a method for manufacturing a multilayer substrate in the second embodiment. [Figure 30] Figure 30 is a schematic cross-sectional view (No. 30) showing an example of a method for manufacturing a multilayer substrate in the second embodiment. [Figure 31] Figure 31 is a schematic cross-sectional view (No. 31) showing an example of a method for manufacturing a multilayer substrate in the second embodiment. [Figure 32] Figure 32 is a schematic cross-sectional view (No. 32) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 33] Figure 33 is a schematic cross-sectional view (No. 33) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 34] Figure 34 is a schematic cross-sectional view (No. 34) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 35] Figure 35 is a schematic cross-sectional view (number 35) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 36] Figure 36 is a schematic cross-sectional view (No. 36) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 37] Figure 37 is a schematic cross-sectional view (No. 37) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 38] Figure 38 is a schematic cross-sectional view (No. 38) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 39] Figure 39 is a schematic cross-sectional view (No. 39) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 40] Figure 40 is a schematic cross-sectional view (No. 40) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 41] Figure 41 is a schematic cross-sectional view (No. 41) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 42] Figure 42 is a schematic cross-sectional view (No. 42) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 43] Figure 43 is a schematic cross-sectional view (No. 43) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 44] Figure 44 is a schematic cross-sectional view (No. 44) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 45] Figure 45 is a schematic cross-sectional view (number 45) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 46] Figure 46 is a schematic cross-sectional view (number 46) showing an example of a method for manufacturing a multilayer substrate in the third embodiment. [Figure 47] Figure 47 is a schematic cross-sectional view of a semiconductor package. [Modes for carrying out the invention]

[0016] The multilayer substrates 200, 300, and 400 in each embodiment will be described in detail below with reference to the drawings. Figure 22 is a diagram showing an example of a manufacturing method for the multilayer substrate 200 in the first embodiment, and is a schematic cross-sectional view of the multilayer substrate 200. Figure 31 is a diagram showing an example of a manufacturing method for the multilayer substrate 300 in the second embodiment, and is a schematic cross-sectional view of the multilayer substrate 300. Figure 46 is a diagram showing an example of a manufacturing method for the multilayer substrate 400 in the third embodiment, and is a schematic cross-sectional view of the multilayer substrate 400. In all the diagrams used to explain each embodiment, components having the same function are denoted by the same reference numerals, and repeated explanations may be omitted.

[0017] Furthermore, in multilayer substrates 200, 300, and 400, for convenience, the terms "upper layer" or "lower layer" may be used based on the vertical direction in the drawing. However, the upper or lower layer in multilayer substrates 200, 300, and 400 may not necessarily correspond to the actual vertical orientation.

[0018] Furthermore, in multilayer substrates 200, 300, and 400, for convenience, the terms "top surface" or "bottom surface" may be used based on the vertical direction in the drawing. However, the top and bottom surfaces of multilayer substrates 200, 300, and 400 may not necessarily correspond to the actual vertical orientation. Additionally, in multilayer substrates 200, 300, and 400, the term "side surface" may be used. This refers to the side surface relative to the top and bottom surfaces described above.

[0019] <First Embodiment> <<Multilayer board>> As shown in Figure 22, the multilayer substrate 200 in the first embodiment has a configuration in which multiple laminates 56 are stacked. More specifically, the multilayer substrate 200 comprises multiple laminates 56, a metal layer 72 located at the top, and a laminate 58 located at the bottom.

[0020] <<<First insulating layer>>> The laminate 56 has a first insulating layer 26 on which a patterned first metal layer 40 is formed on the first surface 26a.

[0021] The first insulating layer 26 is usually in the form of a flat plate. The average thickness of the first insulating layer 26 may be, for example, 10 μm to 200 μm or 30 μm to 100 μm, but there are no particular restrictions and it can be appropriately selected according to the purpose.

[0022] Furthermore, the first insulating layer 26 is not particularly limited as long as it is an insulating layer used in a multilayer substrate, and can be appropriately selected according to the purpose. As an example, the first insulating layer 26 can be an inorganic substrate such as an inorganic woven fabric or inorganic nonwoven fabric using glass cloth, or an organic substrate such as an organic woven fabric or organic nonwoven fabric with enhanced hardness.

[0023] Furthermore, the first insulating layer 26 can, more specifically, be made of a glass epoxy substrate (a glass woven fabric substrate impregnated with epoxy resin, a glass nonwoven fabric substrate impregnated with epoxy resin), a glass woven fabric substrate impregnated with bismaleimidotriazine resin, an aramid nonwoven fabric substrate impregnated with epoxy resin, a glass woven fabric substrate impregnated with modified polyphenylene ether resin, and the like.

[0024] Furthermore, while at least the second insulating layer 24 and the fourth insulating layer 48, as described later, are made of materials with low dielectric loss tangent, the first insulating layer 26 may also be made of a material with low dielectric loss tangent, as described later. This allows for even faster transmission of data from the multilayer substrate 200. When a material with low dielectric loss tangent is used for the first insulating layer 26, the first insulating layer 26 is in close contact with the first via 34, as described later.

[0025] <<<First metal layer>>> A first metal layer 40 in a predetermined pattern is formed on the first surface of the first insulating layer 26 (the upper surface of the first insulating layer 26 in Figure 22). The first metal layer 40 is formed to a thickness of approximately 10 μm to 60 μm, as an example, but is not limited to this and can be appropriately selected depending on the purpose.

[0026] Furthermore, while it is preferable that the first metal layer 40 has been subjected to a surface roughening treatment, it is not limited to this and can be appropriately selected depending on the purpose.

[0027] <<<Second insulating layer>>> A second insulating layer 24 is laminated on the second surface of the first insulating layer 26 (in Figure 22, the lower surface of the first insulating layer 26, which is the surface opposite to the first surface 26a).

[0028] Furthermore, the average thickness of the second insulating layer 24 may, for example, be 10 μm or more and 200 μm or 30 μm or more and 100 μm or less, but there are no particular restrictions and it can be appropriately selected according to the purpose.

[0029] Furthermore, the second insulating layer 24 is made of a material with a low dielectric loss tangent. Here, a material with a low dielectric loss tangent refers, for example, to a material (particularly a resin material) whose dielectric loss tangent at 10 GHz is 0.002 or less. Therefore, it is preferable that the second insulating layer 24 has a dielectric loss tangent at 10 GHz of 0.002 or less. In addition, the material with a low dielectric loss tangent here is also a material that adheres to the metal layer that has not undergone roughening treatment. Therefore, it is preferable that the second insulating layer 24 is a material that adheres to the metal layer that has not undergone roughening treatment. That is, the second insulating layer 24 adheres to the second metal layer 22, which will be described later. Furthermore, the lower limit of the dielectric loss tangent is not particularly limited, but is usually 0.0009 or higher.

[0030] <<<Second metal layer>>> A predetermined patterned second metal layer 22 is formed on the third surface 24a of the second insulating layer 24 (in Figure 22, this is the lower surface of the second insulating layer 24, the surface opposite to the opposing first insulating layer 26). More specifically, a predetermined patterned second metal layer 22 is embedded in the third surface of the second insulating layer 24. The second metal layer 22 is formed to a thickness of approximately 10 μm to 60 μm, as an example, but is not limited to this and can be appropriately selected depending on the purpose.

[0031] Furthermore, it is preferable that the second metal layer 22 does not undergo surface roughening treatment. As a result, the surface of the second metal layer 22 does not have a structure with fine irregularities, thus preventing transmission delays caused by such irregularities.

[0032] As described above, because the second metal layer 22 is covered and in close contact with the second insulating layer 24, high-speed transmission of the second metal layer 22 can be achieved without applying a chemical adhesion film to the second metal layer 22.

[0033] <<<Third insulating layer>>> A third insulating layer 44 is laminated on the first surface 26a of the first insulating layer 26 such that the first metal layer 40 is embedded within it.

[0034] The third insulating layer 44 is not particularly limited as long as it is an insulating substrate used in multilayer substrates, and can be appropriately selected according to the purpose. More specifically, the third insulating layer 44 can be a thermosetting resin, for example. Preferred thermosetting resins include fluororesin, polyphenylene ether resin (PPE / PPO resin), polyimide resin (PI resin), and bismaleimide triazine resin (BT resin).

[0035] Furthermore, the third insulating layer 44 may be an inorganic substrate such as an inorganic woven fabric or inorganic nonwoven fabric using glass cloth, or a substrate whose hardness has been strengthened by an organic substrate such as an organic woven fabric or organic nonwoven fabric. More specifically, the third insulating layer 44 may be a glass epoxy substrate, a glass woven fabric substrate impregnated with bismaleimide triazine resin, an aramid nonwoven fabric substrate impregnated with epoxy resin, or a glass woven fabric substrate impregnated with modified polyphenylene ether resin.

[0036] Furthermore, the third insulating layer 44 may be made of a material with a low dielectric loss tangent. This allows for even faster transmission of signals from the multilayer substrate 200. When a material with a low dielectric loss tangent is used for the third insulating layer 44, the third insulating layer 44 is in close contact with the second via 54, which will be described later.

[0037] <<<Fourth insulating layer>>> Furthermore, a fourth insulating layer 48 is laminated on the third insulating layer 44.

[0038] The fourth insulating layer 48 is made of a material with a low dielectric loss tangent. More specifically, it is preferable that the fourth insulating layer 48 has a dielectric loss tangent of 0.002 or less at 10 GHz. Furthermore, it is preferable that the fourth insulating layer 48 is made of a material that adheres to metal layers that have not undergone roughening treatment. That is, the fourth insulating layer 48 adheres to the second metal layer 22 in the other laminates. As an example, the same material as the second insulating layer 24 described above can be used for the fourth insulating layer 48, but it is not limited to this, and can be appropriately selected depending on the purpose.

[0039] Furthermore, as will be described later, the fourth insulating layer 48 is in a semi-cured state when multiple laminates 56 are laminated, and it serves as an adhesive layer.

[0040] <<<First Via>>> Through holes 32 are drilled in the first insulating layer 26 and the second insulating layer 24, and a first via 34 is formed in the through holes 32 to electrically connect the first metal layer 40 and the second metal layer 22.

[0041] Furthermore, the size (opening diameter) of the through-hole 32 may, for example, be 50 μm or more and 500 μm or 100 μm or more and 300 μm or less, but is not limited to these and can be appropriately selected according to the purpose.

[0042] Furthermore, the through-hole 32 is formed, for example, in a shape where its diameter gradually decreases from the side where it is drilled (tapered shape), but is not limited to this and can be appropriately selected depending on the purpose. In other examples, the through-hole 32 may be a through-hole drilled perpendicular to the first insulating layer 26 and the second insulating layer 24.

[0043] The through-hole 32 is filled with a first via 34. The first via 34 is, for example, a plated via containing copper, but is not limited to this and can be appropriately selected depending on the purpose.

[0044] The first via 34 may also be a conductive paste, as an example. The conductive paste may, for example, contain a conductive filler and a binder resin, but is not limited to this, and can be appropriately selected depending on the purpose. As the conductive filler, for example, metal particles such as copper, gold, silver, palladium, nickel, tin, and bismuth may be used, and these metal particles may be used individually or as a mixture of two or more types. Furthermore, as the binder resin, for example, epoxy resin or polyimide resin, which are types of thermosetting resins, may be used, but is not limited to this, and can be appropriately selected depending on the purpose.

[0045] <<<Second Beer>>> Furthermore, through holes 52 are drilled in the third insulating layer 44 and the fourth insulating layer 48, and second vias 54 are formed in the through holes 52 to electrically connect the first metal layer 40 to the second metal layer 22 or metal layer 72 of the other laminate 56.

[0046] Furthermore, the size (opening diameter) of the through-hole 52 may, for example, be 50 μm or more and 500 μm or 100 μm or more and 300 μm or less, but is not limited to these and can be appropriately selected according to the purpose.

[0047] Furthermore, the through-hole 52 is formed, for example, in a shape where its diameter gradually decreases from the side where it is drilled (tapered shape), but is not limited to this and can be appropriately selected depending on the purpose. Another example of the through-hole 52 is a through-hole drilled perpendicular to the third insulating layer 44 and the fourth insulating layer 48.

[0048] The through hole 52 is filled with a second via 54. The second via 54 may, for example, be the conductive paste described as the first via 34, but is not limited to this and can be appropriately selected depending on the purpose. Another example of the second via 54 is the plated via described as the first via 34.

[0049] <<<Metal layer>>> Furthermore, a predetermined patterned metal layer 72 is formed on the upper surface of the top layer laminate 56. The metal layer 72 is formed to a thickness of approximately 10 μm to 60 μm, for example, but is not limited to this and can be appropriately selected depending on the purpose.

[0050] <<<Lowest layer of stacked material>>> In the multilayer substrate 200, if the number of metal layers is even, a laminate 58 is laminated at the bottom. The laminate 58, as an example, has a ninth insulating layer 64 on which a patterned third metal layer 74 is formed on its lower surface, a tenth insulating layer 66 laminated on the ninth insulating layer 64, and a third via 68 formed through the ninth insulating layer 64 and the tenth insulating layer 66. The third metal layer 74 is electrically connected to the second metal layer 22 of the laminate 56 directly above it via the third via 68.

[0051] The ninth insulating layer 64 can be the same as the first insulating layer 26 described above, and the tenth insulating layer 66 can be the same as the fourth insulating layer 48 described above. Furthermore, the third metal layer 74 can be the same as the first metal layer 40 or the second metal layer 22 described above, but it is preferable that the third metal layer 74 is exposed from the ninth insulating layer 64. In addition, the third via 68 can be the same as the first via 34 or the second via 54 described above.

[0052] In the case of a multilayer substrate 200 with an odd number of metal layers, the laminate 58 is not laminated, and the configuration of the bottom laminate 56 is different (not shown). That is, it is preferable that the metal layer 22 of the bottom laminate 56 is exposed from the second insulating layer 24.

[0053] The multilayer substrate 200 in this embodiment, as described above, can achieve high-speed transmission without requiring roughening treatment and chemical adhesion coating on the second metal layer 22. This is particularly advantageous when the second metal layer 22 is used as the signal layer and the first metal layer 40 as the ground layer, as in the multilayer substrate 200 of this embodiment.

[0054] <<Manufacturing method for multilayer substrates>> Next, the method for manufacturing the multilayer substrate 200 in the first embodiment will be described in detail. The method for manufacturing the multilayer substrate 200 comprises a laminate formation step of forming a laminate 56 and a fifth lamination step of stacking a plurality of laminates 56.

[0055] As shown in Figure 1, first, a three-layer metal foil 10 is prepared. The three-layer metal foil 10, as an example, consists of a copper foil 12, a metal foil 14 different from the copper foil 12, and a metal support (particularly a copper support) 16, all laminated in this order. The metal foil 14 is not particularly limited as long as it is a metal that can be selectively etched with a selective etching agent that does not react with the copper foil 12 or the copper support 16, and can be appropriately selected according to the purpose.

[0056] Next, as shown in Figures 2 to 4, a second metal layer 22 is formed on the three-layer metal foil 10 (second metal layer formation step). Specifically, as shown in Figure 2, a film-like dry film resist 18 is attached to the surface of the copper foil 12 and exposed to light in a predetermined pattern corresponding to the pattern of the second metal layer 22 to remove unwanted portions. Next, as shown in Figure 3, the metal foil 12 is etched (half-etched) to form a second metal layer 22 in a predetermined pattern. Next, as shown in Figure 4, the dry film resist 18 is removed from the surface of the second metal layer 22.

[0057] Next, as shown in Figure 5, a second insulating layer (especially an uncured second insulating layer) 24 is laminated on the second metal layer 22 so as to embed the second metal layer 22 (first lamination step). Then, a first insulating layer (especially an uncured first insulating layer) 26 and a metal foil 28 are laminated on the second insulating layer 24 in this order (second lamination step).

[0058] Next, as shown in Figures 6 to 10, a first via 34 is formed on the first insulating layer 26 and the second insulating layer 24 (first via formation step).

[0059] Specifically, first, as shown in Figure 6, a film-like dry film resist 30 is attached to the surface of the metal foil 28, and the area corresponding to the opening of the through hole 32 of the first via 34 is exposed to light to remove the unnecessary portion. Next, as shown in Figure 7, etching (half etching) is performed to form a metal layer 28 in areas other than those corresponding to the through hole 32. Then, as shown in Figure 8, the dry film resist 30 is removed from the surface of the metal layer 28.

[0060] Next, as shown in Figure 9, through holes 32 are drilled in the first insulating layer 26 and the second insulating layer 24. The through holes 32 can be made by laser processing, for example. Examples of laser processing methods include CO2 lasers and YAG lasers, but are not limited to these, and can be appropriately selected depending on the purpose.

[0061] Next, as shown in Figure 10, plating (copper plating) 34 is applied to the through hole 32 by a plating process to form the first via (plated via) 34. Alternatively, conductive paste may be used instead of the plated via.

[0062] In the case of the first via 34 being a plated via, the metal layer on the first surface 26a of the first insulating layer 26 may become too thick. In this case, as shown in Figure 11, it is preferable to adjust the metal layer to a predetermined thickness by half-etching.

[0063] Next, as shown in Figures 12 to 13, a first metal layer 40 is formed on the first surface 26a of the first insulating layer 26 (first metal layer formation step). Specifically, as shown in Figure 12, a film-like dry film resist 38 is attached to the surface of the metal layer 28 and exposed to light in a predetermined pattern corresponding to the pattern of the first metal layer 40 to remove unwanted portions. Then, as shown in Figure 13, the metal layer 28 is formed into a first metal layer 40 in a predetermined pattern by etching (half etching), and the dry film resist 18 is removed from the surface of the first metal layer 40.

[0064] Next, as shown in Figure 14, a third insulating layer 44 is laminated on the first insulating layer 26 so that the first metal layer 40 is embedded (third lamination step). A metal layer 46 is further laminated on the third insulating layer 44. This ensures the flatness of the third insulating layer 44 and improves the reliability of the multilayer substrate.

[0065] Next, as shown in Figure 15, the metal layer 46 and the metal support 16 are removed by etching, and then, as shown in Figure 16, the metal foil 14 is removed by etching (particularly selective etching) (etching process).

[0066] Next, as shown in Figure 17, the fourth insulating layer 48 is laminated onto the third insulating layer 44 (fourth lamination step). More specifically, the semi-cured fourth insulating layer 48 and the resin film 50 are laminated on the third insulating layer 44 in this order.

[0067] Next, as shown in Figures 18 to 19, second vias 54 are formed in the third insulating layer 44 and the fourth insulating layer 48 (second via formation step). Specifically, as shown in Figure 18, through holes 52 are drilled in the third insulating layer 44 and the fourth insulating layer 48. The through holes 52 can be made by laser processing, for example. Examples of laser processing methods include CO2 lasers and YAG lasers, but are not limited to these, and can be appropriately selected depending on the purpose. Next, as shown in Figure 19, conductive paste 54 is filled into the through holes 52. The laminate 56 is completed by these steps.

[0068] Next, as shown in Figures 20 and 21, multiple laminates 56 are stacked (fifth stacking step). More specifically, if the multilayer substrate 200 has an even number of layers, the laminate 58, multiple laminates 56, and metal layer 70 are stacked and thermocompressed in this order. If the multilayer substrate 200 has an odd number of layers, a laminate (not shown) in which the second metal layer 22 before etching is exposed from the second insulating layer 24, multiple laminates 56, and metal layer 70 are stacked and thermocompressed in this order. In either of the above cases, the second via 54 in one laminate 56 is electrically connected to the metal layer 70 or the second metal layer 22 in the other laminate 56.

[0069] Next, as shown in Figure 22, etching is used to form predetermined patterned metal layers 72 and 74 on the multilayer substrate 200 after lamination (thermocompression bonding).

[0070] <Second Embodiment> <<Multilayer board>> Next, the multilayer substrate 300 in the second embodiment will be described in detail. The multilayer substrate 300 in the second embodiment has a fifth insulating layer 76, a sixth insulating layer 78, and a seventh insulating layer 82 instead of the third insulating layer 44 and the fourth insulating layer 48 of the multilayer substrate 200 in the first embodiment. In addition, at least the second insulating layer 24, the fifth insulating layer 76, and the seventh insulating layer 82 are made of a material with a low dielectric loss tangent. The other configurations of the multilayer substrate 300 are the same as those of the multilayer substrate 200. The fifth insulating layer 76, the sixth insulating layer 78, and the seventh insulating layer 82 will be described below.

[0071] <<<Fifth insulating layer>>> A fifth insulating layer 76 is laminated on the first surface 26a of the first insulating layer 26 such that the first metal layer 40 is embedded within it.

[0072] The fifth insulating layer 76 is made of a material with a low dielectric loss tangent. More specifically, it is preferable that the fifth insulating layer 76 has a dielectric loss tangent of 0.002 or less at 10 GHz. Furthermore, it is preferable that the fifth insulating layer 76 is made of a material that adheres to the metal layer even if it has not undergone roughening treatment. That is, the fifth insulating layer 76 adheres to the first metal layer 40. As an example, the same material as the second insulating layer 24 described above can be used for the fifth insulating layer 76, but it is not limited to this, and can be appropriately selected depending on the purpose.

[0073] In this embodiment, it is preferable that the first metal layer 40 has not undergone any surface roughening treatment.

[0074] <<<Sixth insulating layer>>> A sixth insulating layer 78 is laminated on the surface of the fifth insulating layer 76. The sixth insulating layer 78 can have the same configuration as the first insulating layer 26.

[0075] <<<Seventh insulating layer>>> A seventh insulating layer 82 is laminated on the surface of the sixth insulating layer 78. The seventh insulating layer 82 can employ the same configuration as the fourth insulating layer 48.

[0076] As described above, the multilayer substrate 300 in this embodiment can achieve high-speed transmission of each metal layer without requiring roughening treatment or chemical adhesion coating on the first metal layer 40 and the second metal layer 22.

[0077] <<Manufacturing method for multilayer substrates>> Next, the method for manufacturing a multilayer substrate in the second embodiment will be described in detail. The method for manufacturing the multilayer substrate 300 comprises a laminate formation step for forming a laminate 90 and a fifth lamination step for stacking a plurality of laminates 90. Furthermore, the method for manufacturing the multilayer substrate 300 in the second embodiment differs from the method for manufacturing a multilayer substrate in the first embodiment in the steps from the third lamination step onward, but the other configurations are the same as those for manufacturing the multilayer substrate 200 in the first embodiment.

[0078] In the manufacturing method of the multilayer substrate according to the second embodiment, following the first metal layer formation step, as shown in Figure 23, the fifth insulating layer 76 and the sixth insulating layer 78 are laminated on the first insulating layer 26 such that the first metal layer 40 is embedded (third lamination step). A metal layer 80 is further laminated on the sixth insulating layer 78. This ensures the flatness of the fifth insulating layer 76 and the sixth insulating layer 78, thereby improving the reliability of the multilayer substrate.

[0079] Next, as shown in Figure 24, the metal layer 80 and the metal support 16 are removed by etching, and then, as shown in Figure 25, the metal foil 14 is removed by etching (particularly selective etching) (etching process).

[0080] Next, as shown in Figure 26, the seventh insulating layer 82 is laminated onto the sixth insulating layer 78 (fourth lamination step). More specifically, the semi-cured seventh insulating layer 82 and the resin film 84 are laminated on the sixth insulating layer 78 in this order.

[0081] Next, as shown in Figures 27 to 28, second vias 88 are formed in the fifth insulating layer 76, the sixth insulating layer 78, and the seventh insulating layer 82 (second via formation step). Specifically, as shown in Figure 27, through holes 86 are drilled in the fifth insulating layer 76, the sixth insulating layer 78, and the seventh insulating layer 82. The through holes 86 can be made by laser processing, for example. Examples of laser processing methods include CO2 lasers and YAG lasers, but are not limited to these, and can be appropriately selected depending on the purpose. Next, as shown in Figure 28, conductive paste 88 is filled into the through holes 86. The laminate 90 is completed by the steps up to this point.

[0082] Next, as shown in Figures 29 and 30, multiple laminates 90 are stacked (fifth stacking step). More specifically, if the multilayer substrate 300 has an even number of layers, the laminate 92, multiple laminates 90, and metal layer 104 are stacked and thermocompressed in this order. If the multilayer substrate 300 has an odd number of layers, a laminate (not shown) in which the second metal layer 22 before etching is exposed from the second insulating layer 24, multiple laminates 90, and metal layer 104 are stacked and thermocompressed in this order. In either of the above cases, the second via 54 in one laminate 90 is electrically connected to the metal layer 104 or the second metal layer 22 in the other laminate 90.

[0083] Next, as shown in Figure 31, etching is used to form predetermined patterned metal layers 108 and 106 on the multilayer substrate 300 after lamination (thermocompression bonding).

[0084] <Third Embodiment> <<Multilayer board>> Next, the multilayer substrate 400 in the third embodiment will be described in detail. The multilayer substrate 400 in the third embodiment has a first insulating layer 26 and an eighth insulating layer 120 instead of the first insulating layer 26 of the multilayer substrate 300 in the second embodiment. In addition, at least the second insulating layer 24, the fifth insulating layer 76, the seventh insulating layer 82, and the eighth insulating layer 120 are made of a material with a low dielectric loss tangent. The other configurations of the multilayer substrate 400 are the same as those of the multilayer substrate 300. The first insulating layer 26, the fifth insulating layer 76, and the eighth insulating layer 120 will be described in detail below.

[0085] <<<First insulating layer>>> In the third embodiment, instead of forming a patterned metal layer on the first surface 26a of the first insulating layer 26, an eighth insulating layer 120 is laminated thereon. It is preferable that the first insulating layer 26 is formed thinner than the first insulating layer 26 in the first and second embodiments due to the lamination of the eighth insulating layer 120.

[0086] A patterned first metal layer 40 is formed on the fourth surface 120a of the eighth insulating layer 120 (i.e., the surface of the eighth insulating layer 120 opposite to the first insulating layer 26). Therefore, the first via 34 is formed to penetrate the first insulating layer 26, the second insulating layer 24, and the eighth insulating layer 120, and is configured to electrically connect the first metal layer 40 and the second metal layer 22.

[0087] <<<8th insulating layer>>> Furthermore, the eighth insulating layer 120 is made of a material with a low dielectric loss tangent. More specifically, it is preferable that the eighth insulating layer 120 has a dielectric loss tangent of 0.002 or less at 10 GHz. It is also preferable that the eighth insulating layer 120 is made of a material that adheres to metal layers that have not undergone roughening treatment. That is, the eighth insulating layer 120 adheres to the first metal layer 40 (particularly the back side of the first metal layer 40). As an example, the eighth insulating layer 120 can be made of the same material as the second insulating layer 24 described above, but is not limited to this, and can be appropriately selected according to the purpose.

[0088] As described above, the multilayer substrate 400 in this embodiment can achieve high-speed transmission of each metal layer without requiring roughening treatment or chemical adhesion coating on the first metal layer 40 and the second metal layer 22.

[0089] <<Manufacturing method for multilayer substrates>> Next, the method for manufacturing a multilayer substrate in the third embodiment will be described in detail. The method for manufacturing the multilayer substrate 400 comprises a laminate formation step for forming a laminate 130 and a fifth lamination step for stacking a plurality of laminates 130. Furthermore, the method for manufacturing the multilayer substrate 400 in the third embodiment differs from the method for manufacturing the multilayer substrate 300 in the second embodiment in the second lamination step, the first via formation step, and the first metal layer formation step, but the other configurations are the same as those of the method for manufacturing the multilayer substrate 300 in the second embodiment.

[0090] In the second lamination step of the third embodiment, as shown in Figures 32 and 33, the first insulating layer (particularly the first insulating layer that has not yet been cured) 26 and the eighth insulating layer (particularly the eighth insulating layer that has not yet been cured) 120 are laminated on the second insulating layer 24 in this order.

[0091] Next, in the first via formation step of the third embodiment, as shown in Figures 34 to 35, the first via 34 is formed on the first insulating layer 26 and the eighth insulating layer 120.

[0092] Specifically, first, as shown in Figure 34, through holes 32 are drilled in the first insulating layer 26, the second insulating layer 24, and the eighth insulating layer 120. The through holes 32 can be drilled by laser processing, for example. Examples of laser processing methods include CO2 lasers and YAG lasers, but are not limited to these; appropriate lasers can be selected depending on the purpose.

[0093] Next, as shown in Figure 35, the through-hole 32 and the surface of the eighth insulating layer 120 are plated (copper plated) to form the first via (plated via) 34. At this time, copper plating is also applied to the upper surface of the first via 34 and the eighth insulating layer 120. Note that conductive paste may be filled instead of plated vias.

[0094] <<<First metal layer formation process>>> Next, in the first metal layer formation step of the third embodiment, as shown in Figures 36 to 37, the first metal layer 40 is formed on the first surface 120a of the eighth insulating layer 120. The method for forming the first metal layer 40 can be carried out in the same way as the first metal layer formation step in the first and second embodiments.

[0095] As shown in Figures 38 to 46, a laminate 130 can be obtained by sequentially carrying out the third lamination process and subsequent processes, and a multilayer substrate 400 can be formed by a fifth lamination process in which multiple laminates 130 are stacked.

[0096] <Electronic equipment> Next, the electronic equipment 500 in each embodiment will be described. The electronic equipment 500 comprises at least a multilayer substrate 200, a multilayer substrate 300, or a multilayer substrate 400 and electronic components, and further comprises other members as necessary.

[0097] There are no particular restrictions on what constitutes an electronic device 500, and they can be selected appropriately according to the purpose. Examples include personal computers (notebook computers, desktop computers), telephones, mobile phones, tablet devices, smartphones, photocopiers, fax machines, various printers, digital cameras, televisions, video equipment, CD players, DVD players, air conditioners, and remote control devices.

[0098] Figure 47 shows a schematic cross-sectional view of a semiconductor package. The semiconductor package in Figure 47 includes a motherboard 460 having solder balls 455, an interposer 470 connected to the motherboard 460 via bumps 465, and semiconductor elements 480 arranged on the interposer 470. Examples of semiconductor elements 480 include FPGA (Field Programmable Gate Array) chips.

[0099] Here, the multilayer substrate 200, multilayer substrate 300, or multilayer substrate 400 can be used as the motherboard 460 in Figure 47, as the interposer 470, and also as the circuit board constituting the semiconductor element 480.

[0100] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are possible without departing from the scope of the present invention. [Explanation of Symbols]

[0101] 22 Second metal layer 24 Second insulating layer 24a 3rd surface 26. First insulating layer 26a 1st surface 26b 2nd surface 40 1st metal layer 42 Third insulating layer 48. Fourth insulating layer 56 Laminate 76 Fifth insulating layer 78. Sixth insulating layer 82. Seventh insulating layer 120 Eighth insulating layer 120a Fourth surface 130 Laminate 200 Multilayer board 300 multilayer board 400 multilayer board 500 Electronic equipment

Claims

1. A first layer having a second metal layer and an insulating layer formed to cover the second metal layer, A laminate comprising a second layer laminated on the first layer and having a first metal layer and another insulating layer formed to cover the first metal layer, The first layer has plated vias that electrically connect the second metal layer and the first metal layer. The laminate is characterized in that the second layer has conductive paste vias that electrically connect the first metal layer and the external metal layer.

2. A first layer having a second metal layer and an insulating layer formed to cover the second metal layer so that the second metal layer is exposed on its lower surface, A laminate comprising a first metal layer formed on the upper surface of the first insulating layer, and a second layer laminated on top of the first layer, having another insulating layer formed to cover the first metal layer, The first layer has plated vias that electrically connect the second metal layer and the first metal layer. The laminate is characterized in that the second layer has conductive paste vias that electrically connect the first metal layer and the external metal layer.

3. A multilayer substrate characterized by being constructed by stacking a plurality of laminates according to claim 1 or claim 2.

4. The bottom layer of the multilayer substrate according to claim 3 is laminated with a bottom layer laminate, The aforementioned bottom layer laminate is A multilayer substrate characterized by having a metal layer, an insulating layer laminated on the metal layer, and conductive paste vias that electrically connect the metal layer to a second metal layer of another laminate arranged above the bottommost laminate.

5. A process of etching the copper foil in a three-layer metal foil consisting of copper foil, metal foil, and a metal support to form a patterned second metal layer, A step of laminating an insulating layer on the second metal layer such that the second metal layer is embedded in it, The process involves laminating a flat metal layer onto the aforementioned insulating layer, A step of forming a first through-hole that penetrates the flat metal layer and the first insulating layer and reaches the second metal layer, A step of forming a first via, which is a plated via, in the first through hole, The process of etching the aforementioned flat metal layer to form a patterned first metal layer, A step of laminating another insulating layer on the patterned first metal layer such that the patterned first metal layer is embedded therein, A step of removing the metal foil and the metal support from the three layers of metal foil, A step of laminating the uppermost insulating layer and the resin film on the other insulating layer, A step of forming a second through-hole that penetrates the resin film, the uppermost insulating layer, and the other insulating layers and reaches the first metal layer, A method for manufacturing a laminate, comprising the step of filling the second through-hole with a conductive paste to form a second via which is a paste via.

6. A method for manufacturing a multilayer substrate, characterized by including a step of stacking a plurality of laminates manufactured according to the method for manufacturing a laminate according to claim 5 to obtain a multilayer substrate.

7. The process of obtaining the multilayer substrate is as follows: A method for manufacturing a multilayer substrate according to claim 6, characterized by including a step of laminating so that the bottom layer is a laminate having a metal layer, an insulating layer laminated on the metal layer, and conductive paste vias that electrically connect the metal layer and a second metal layer of a laminate laminated on the upper side.

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