Memory system

Abstract

This system enables dynamic control of the processing load required to equalize the number of erasure cycles. [Solution] In response to the execution of a data erasure operation, the controller obtains a first difference between a first erasure count and a second erasure count among the erasure counts of each of the multiple blocks, compares the first difference with a first threshold, compares the cumulative amount of data written with a second threshold, and if the first difference exceeds the first threshold and the cumulative amount of data written exceeds the second threshold, the controller performs a copy operation to copy a first amount of data, copying the valid data stored in the first block, which has the fewest erasure counts among the blocks in which valid data is stored, to the second block, which does not store valid data and has a higher erasure count than the first block.

Description

Technical Field

[0001] Embodiments of the present invention relate to a technology for controlling a nonvolatile memory.

Background Art

[0002] In recent years, memory systems including nonvolatile memories have become widely prevalent. In a nonvolatile memory, data writing is performed in units of pages. On the other hand, data erasing is performed in units of blocks each including a plurality of pages. To prevent the lifespan of the memory system from being excessively shortened, a technology capable of dynamically controlling the processing amount for leveling the erase count of a plurality of blocks is required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] A problem to be solved by one embodiment of the present invention is to provide a memory system capable of dynamically controlling the processing amount for leveling erase counts.

Means for Solving the Problems

[0005] According to one embodiment, the memory system is connectable to a host. The memory system comprises a non-volatile memory and a controller. The non-volatile memory includes a plurality of blocks, each of which is a unit of data erasure operation. The controller is configured to perform a data erasure operation on blocks that do not contain valid data and to assign the blocks on which the data erasure operation has been performed as destination blocks for data received from the host. In response to the execution of the data erasure operation, the controller obtains a first difference between a first erasure count and a second erasure count among the erasure counts of each of the plurality of blocks, compares the first difference with a first threshold, compares the cumulative amount of data written with a second threshold, and if the first difference exceeds the first threshold and the cumulative amount of data written exceeds the second threshold, the controller performs a copy operation to copy a first amount of data, copying the valid data stored in the first block, which has the fewest erasure counts among the blocks containing valid data, to the second block, which does not contain valid data and has a more erasure count than the first block. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example configuration of an information processing system including a memory system according to the first embodiment. [Figure 2] A block diagram showing an example configuration of each of the multiple memory dies included in the non-volatile memory of the memory system according to the first embodiment. [Figure 3] A figure showing an example of a wear-leveling copy operation performed in the memory system according to the first embodiment. [Figure 4] A diagram showing the settings used in the wear-leveling copy operation performed in the memory system according to the first embodiment. [Figure 5] This figure shows the distribution of the number of block erases when the wear-leveling copy operation performed in the memory system according to the first embodiment is set to normal mode. [Figure 6]This figure shows the distribution of the number of block erases when the wear-leveling copy operation performed in the memory system according to the first embodiment is set to accelerated mode. [Figure 7] A sequence diagram showing the procedure for the wear-leveling copy operation performed in the memory system of the comparative example. [Figure 8] A sequence diagram showing the procedure for the wear-leveling copy operation performed in the memory system according to the first embodiment. [Figure 9A] A flowchart showing a portion of the procedure for the wear-leveling copy operation performed in the memory system according to the first embodiment. [Figure 9B] A flowchart illustrating the other parts of the procedure for the wear-leveling copy operation performed in the memory system according to the first embodiment. [Figure 10] This figure shows the settings used in the wear-leveling copy operation performed in the memory system according to the second embodiment. [Figure 11] A sequence diagram showing the procedure for the wear-leveling copy operation performed in the memory system according to the second embodiment. [Figure 12A] A flowchart showing a portion of the procedure for the wear-leveling copy operation performed in the memory system according to the second embodiment. [Figure 12B] A flowchart illustrating the other parts of the procedure for the wear-leveling copy operation performed in the memory system according to the second embodiment. [Figure 13] This figure shows the settings used in the wear-leveling copy operation performed in the memory system according to the third embodiment. [Figure 14] This figure shows the distribution of the number of block erases in the first case where the wear-leveling copy operation performed in the memory system according to the third embodiment is set to normal mode. [Figure 15] This figure shows the distribution of the number of block erases in the second case where the wear-leveling copy operation performed in the memory system according to the third embodiment is set to normal mode. [Figure 16]The diagram showing the distribution of block erase counts when the wear leveling copy operation executed in the memory system according to the third embodiment is set to the acceleration mode. [Figure 17] The sequence diagram showing the procedure of the wear leveling copy operation executed in the memory system according to the third embodiment. [Figure 18A] The flowchart showing a part of the procedure of the wear leveling copy operation executed in the memory system according to the third embodiment. [Figure 18B] The flowchart showing the other part of the procedure of the wear leveling copy operation executed in the memory system according to the third embodiment. [Figure 19] The diagram showing each set value used in the wear leveling copy operation executed in the memory system according to the fourth embodiment. [Figure 20] The sequence diagram showing the procedure of the wear leveling copy operation executed in the memory system according to the fourth embodiment. [Figure 21A] The flowchart showing a part of the procedure of the wear leveling copy operation executed in the memory system according to the fourth embodiment. [Figure 21B] The flowchart showing the other part of the procedure of the wear leveling copy operation executed in the memory system according to the fourth embodiment. [Modes for Carrying Out the Invention]

[0007] Hereinafter, each embodiment will be described with reference to the drawings.

[0008] In the following, it is assumed that the memory system according to each embodiment is implemented as a solid state drive (SSD). The memory system may also be implemented as a universal flash storage memory (UFS memory), and in that case, the SSD in the following embodiments can be read as UFS memory.

[0009] (First Embodiment) Figure 1 is a block diagram showing an example configuration of an information processing system 1 including a memory system according to the first embodiment. The information processing system 1 includes a host (host device) 2 and an SSD 3. The host 2 and the SSD 3 are connected via a bus 7.

[0010] Host 2 is an information processing device. Host 2 can be, for example, a personal computer, a server computer, or a mobile terminal. Host 2 accesses SSD 3. Specifically, Host 2 sends write commands to SSD 3, which are commands to write data. Host 2 also sends read commands to SSD 3, which are commands to read data.

[0011] SSD3 is a storage device that can be connected to host 2. SSD3 includes non-volatile memory. SSD3 writes data to the non-volatile memory. SSD3 also reads data from the non-volatile memory.

[0012] Communication between host 2 and memory system 3 is performed via bus 7. Bus 7 is, for example, PCI Express. TM (PCIe TM This is a bus. Host 2 sends data and input / output (I / O) commands to SSD3 via bus 7. SSD3 also sends data and responses to Host 2 via bus 7. I / O commands are commands for writing data to or reading data from non-volatile memory. Examples of I / O commands are write commands and read commands.

[0013] For example, a standard for the logical interface connecting host 2 and memory system 3 is NVM Express. TM (NVMe TM The ) standard or the Serial Attached SCSI (SAS) standard is used.

[0014] Next, we will describe the configuration of Host 2.

[0015] Host 2 includes a processor 21 and memory 22. The processor 21 and memory 22 are interconnected via an internal bus 20.

[0016] The processor 21 is, for example, a CPU (Central Processing Unit). The processor 21 executes software (host software) that is loaded into memory 22. The host software is loaded into memory 22 from SSD 3 or another storage device located on or connected to host 2. The host software includes an operating system, file system, device drivers, application programs, etc.

[0017] Memory 22 is, for example, volatile memory. Memory 22 is also called main memory, system memory, or host memory. Memory 22 is, for example, random access memory such as DRAM (Dynamic Random Access Memory). A portion of the memory area of ​​memory 22 is used as a data buffer. The data buffer stores write data to be written to SSD3 or read data transferred from SSD3.

[0018] Next, we will describe the internal configuration of memory system 3. In the following, we will assume that the non-volatile memory within memory system 3 is implemented as NAND flash memory.

[0019] The memory system 3 includes a controller 4 and NAND flash memory (hereinafter simply referred to as NAND memory) 5. The SSD 3 may further include random access memory, such as dynamic random access memory (DRAM) 6.

[0020] Controller 4 is a memory controller. Controller 4 is a control circuit, such as in a System-on-a-Chip (SoC). Controller 4 is electrically connected to the NAND memory 5. Controller 4 performs data writing to and reading data from the NAND memory 5. A physical interface connecting Controller 4 and the NAND memory 5 is, for example, a toggle switch. A NAND flash interface or an open NAND flash interface (ONFI) is used. The functions of each part of the controller 4 can be realized by dedicated hardware, a processor that runs programs, or a combination of these. The controller 4 is also communicatively connected to the DRAM 6. The controller 4 performs data writing to and reading from the DRAM 6. The controller 4 also communicates with the host 2 via the bus 7.

[0021] NAND memory 5 is a non-volatile memory. NAND memory 5 is, for example, a two-dimensional flash memory or a three-dimensional flash memory. NAND memory 5 includes, for example, multiple memory dies. A memory die is also called a memory chip. Each of the multiple memory dies is implemented as a NAND type flash memory die. Hereafter, a memory die will be referred to as a NAND die. Figure 1 shows an example where NAND memory 5 includes 32 NAND dies #0 to #31. Each of NAND dies #0 to #31 contains multiple blocks. Each of the multiple blocks is the smallest unit of a data erasure operation. A data erasure operation is the operation of erasing data stored in NAND memory 5.

[0022] DRAM6 is volatile memory. DRAM6 includes, for example, a memory area used as a write buffer (WB)61, a memory area that stores a logical-to-physical address translation table (L2P table)62, a memory area that stores a free block list63, and a memory area that stores an active block list64. WB61 is a memory area that temporarily stores write data received from host 2. L2P table62 is a table that stores mapping information. Mapping information is information that shows the mapping between each logical address and each physical address of NAND memory 5 in units of a predetermined management size. A logical address is an address used by host 2 to access SSD3. For example, a logical block address (LBA) is used as a logical address. A physical address is an address that indicates the storage location in NAND memory 5. Free block list63 is a list that manages free blocks. A free block is a block that does not store valid data, and the data stored in a free block is only invalid data. Valid data is data stored in the memory area indicated by a physical address mapped to a logical address. Invalid data is data stored in the memory area indicated by a physical address that is not mapped to a logical address. In other words, invalid data is data that will never be read by host 2. The active block list 64 is a list that manages active blocks. An active block is a block that contains at least valid data.

[0023] Next, the internal configuration of the controller 4 will be described. The controller 4 includes, for example, a host interface circuit (host I / F) 41, static RAM (SRAM) 42, a CPU 43, an error correction circuit 44, a NAND interface circuit (NAND I / F) 45, and a DRAM interface circuit (DRAM I / F) 46. These host interface circuit 41, SRAM 42, CPU 43, error correction circuit 44, NAND interface circuit 45, and DRAM interface circuit 46 are interconnected via an internal bus 40.

[0024] The host interface circuit 41 is a hardware interface circuit. The host interface circuit 41 performs communication with the host 2.

[0025] SRAM42 is volatile memory. The memory area of ​​SRAM42 is used as a work area for the CPU43. SRAM42 includes, for example, a memory area that stores information indicating the number of erase cycles for each of several blocks, and a memory area that stores setting values ​​used for a copy operation to equalize the number of erase cycles for several blocks contained in the NAND memory 5. Hereinafter, the copy operation for equalizing the number of erase cycles will be referred to as a wear-leveling copy operation.

[0026] The CPU 43 is a processor. The CPU 43 controls the host interface circuit 41, SRAM 42, error correction circuit 44, NAND interface circuit 45, and DRAM interface circuit 46. The CPU 43 loads a control program (firmware) from a ROM or NAND memory 5 (not shown) into the SRAM 42. The CPU 43 performs various processes by executing the control program (firmware). The firmware may also be loaded into the DRAM 6.

[0027] The CPU 43, for example, as the flash translation layer (FTL), performs tasks such as managing the data stored in the NAND memory 5 and managing the blocks contained in the NAND memory 5. Managing the data stored in the NAND memory 5 includes, for example, managing mapping information that shows the correspondence between each logical address and each physical address. The CPU 43 manages the mapping information using the L2P table 62. Managing the blocks contained in the NAND memory 5 includes, for example, wear leveling, garbage collection, and management of bad blocks contained in the NAND memory 5.

[0028] Wear leveling is a process that equalizes the number of erase operations performed on each block in the NAND memory 5. Wear leveling monitors the number of data erase operations performed on each block in the NAND memory 5 and equalizes the number of data erase operations for each block. Therefore, among the free blocks, blocks with fewer data erase operations are preferentially selected as the destination blocks for writing data. The number of data erase operations performed on a block is also called the program / erase cycle (P / E cycle). Hereafter, the number of data erase operations performed on a block will simply be referred to as the number of erase operations.

[0029] The error correction circuit 44 performs encoding when data is written to the NAND memory 5. During encoding, the error correction circuit 44 adds an error correction code (ECC) as redundant code to the data to be written to the NAND memory 5. When data is read from the NAND memory 5, the error correction circuit 44 performs decoding. During decoding, the error correction circuit 44 uses the ECC added to the data read from the NAND memory 5 to perform error correction on the data.

[0030] The NAND interface circuit 45 is a circuit that controls the NAND memory 5. The NAND interface circuit 45 is electrically connected to multiple NAND dies included in the NAND memory 5.

[0031] Each NAND die can operate independently. Therefore, NAND dies function as parallel-operating units. The NAND interface circuit 45 includes, for example, NAND controllers 451-0, 451-1, ..., 451-15. NAND controllers 451-0, 451-1, ..., 451-15 are connected to channels ch0, ch1, ..., ch15, respectively. Each of the NAND controllers 451-0, 451-1, ..., 451-15 is connected to one or more NAND dies via its corresponding channel. Figure 1 illustrates a case where two NAND dies are connected to each of channels ch0, ch1, ..., ch15. In this case, NAND controller 451-0 is connected to NAND dies #0 and #16 via channel ch0.

[0032] NAND controller 451-1 is connected to NAND dies #1 and #17 via channel ch1. NAND controller 451-15 is connected to NAND dies #15 and #31 via channel ch15. NAND dies #0, #1, ..., #15 are treated as bank BNK0 by controller 4. Similarly, NAND dies #16, #17, ..., #31 are treated as bank BNK1 by controller 4. A bank is a unit that allows multiple NAND dies to operate in parallel through interleaved operation.

[0033] In the NAND memory 5 configuration shown in Figure 1, the controller 4 can access NAND dies #0 to #31 in parallel using 16 channels and bank interleaving. Therefore, the controller 4 can perform parallel data writing or reading operations on up to 32 NAND dies (parallel access count = 32). Note that each of the NAND dies #0 to #31 may have a multi-plane configuration with multiple planes. For example, if each of the NAND dies #0 to #31 contains two planes, the controller 4 can perform parallel data writing or reading operations on up to 64 planes (parallel access count = 64).

[0034] The DRAM interface circuit 46 is a circuit that controls the DRAM 6. The DRAM interface circuit 46 stores data in the DRAM 6. The DRAM interface circuit 46 also reads data stored in the DRAM 6.

[0035] Next, the functional configuration of the CPU 43 will be described. In addition to the components that function as FTL, the CPU 43 includes a command processing unit 431, a consumption leveling copy enable / disable unit 432, and a consumption leveling copy control unit 433. Parts or all of each of the command processing unit 431, the consumption leveling copy enable / disable unit 432, and the consumption leveling copy control unit 433 may be implemented by dedicated hardware of the controller 4.

[0036] The command processing unit 431 performs read operations by processing each read command received from host 2. The read operation includes, for example, the process of converting a logical address specified by a read command to a physical address by referring to the L2P table 62, the process of reading data from the storage location in the NAND memory 5 indicated by the physical address, and the process of transferring the read data to the memory 22 of host 2.

[0037] The command processing unit 431 executes write operations by processing each write command received from the host 2. The write operation includes, for example, retrieving the write data associated with the write command from the host 2's memory 22, writing the write data to a storage location in the NAND memory 5, and updating the L2P table 62 to map the physical address indicating the storage location where the write data was written to the logical address specified by the write command. Based on the write commands received from the host 2, the command processing unit 431 manages a cumulative value indicating the amount of data written to the NAND memory 5.

[0038] When data is written to the NAND memory 5, the command processing unit 431 updates the cumulative value indicating the amount of data written to the NAND memory 5. Hereafter, the cumulative value will be referred to as the cumulative data write amount. The cumulative data write amount is the amount of data written to the NAND memory 5 based on the write command received from the host 2. When data is written to the NAND memory 5, the command processing unit 431 adds the amount of data written to the NAND memory 5 to the cumulative data write amount and updates the cumulative data write amount. Then, when the wear-leveling copy operation is performed, the cumulative data write amount is reset to its initial value (for example, 0).

[0039] In the wear-leveling copy operation, valid data stored in the block with the fewest erase cycles (also referred to as the first block) among the blocks containing valid data is copied to a block that does not contain valid data (free block) and has been erased more times than the first block (also referred to as the second block). Here, for example, the free block with the second highest number of erase cycles may be selected as the second block.

[0040] The wear-leveling copy enable / disable unit 432 enables or disables the wear-leveling copy operation. In response to a data erasure operation being performed on a block to be allocated as a new write destination block, the wear-leveling copy enable / disable unit 432 checks the number of erasures for each block. The wear-leveling copy enable / disable unit 432 compares the difference between the maximum and minimum number of erasures for each of the multiple blocks of the NAND memory 5 (also referred to as the first difference) with a first threshold. The first threshold may be set in advance, for example, as a setting value A. If the first difference is greater than the setting value A, the wear-leveling copy enable / disable unit 432 enables the wear-leveling copy operation. If the first difference is less than or equal to the setting value A, the wear-leveling copy enable / disable unit 432 disables the wear-leveling copy operation.

[0041] The consumption leveling copy control unit 433 controls the consumption leveling copy operation. Depending on whether the consumption leveling copy operation is enabled, the consumption leveling copy control unit 433 compares a first difference with a second threshold. The second threshold is a value greater than the first threshold. The second threshold may be set in advance, for example, as a set value A' (>A). If the first difference is less than or equal to the set value A', the consumption leveling copy control unit 433 sets the consumption leveling copy operation to normal mode. Normal mode is also referred to as the first mode. If the first difference is greater than the set value A', the consumption leveling copy control unit 433 sets the consumption leveling copy operation to accelerated mode. Accelerated mode is also referred to as the second mode.

[0042] When the wear-leveling copy operation is set to normal mode, the wear-leveling copy control unit 433 executes the wear-leveling copy operation. At this time, the wear-leveling copy control unit 433 sets the ratio of the amount of data copied to the NAND memory 5 by the wear-leveling copy to the amount of data written to the NAND memory 5 by the write operation to a first ratio. The amount of data written to the NAND memory 5 by the write operation is the amount of data written to the NAND memory 5 based on multiple write commands received from the host 2, that is, the amount of host writes. For example, in normal mode, if the cumulative amount of data written exceeds a third threshold, the wear-leveling copy control unit 433 executes the wear-leveling copy operation to copy a first amount of valid data. In other words, if the cumulative amount of data written exceeds a third threshold, the wear-leveling copy control unit 433 executes the wear-leveling copy operation so that the valid data stored in the first block is copied to the second block by a first amount.

[0043] A third threshold may be pre-set, for example, as setting value B. The first quantity may be pre-set, for example, as setting value C. If the amount of valid data stored in the first block is less than the first quantity, the valid data stored in the first block may be copied to the second block, and then the block containing the valid data with the fewest erase cycles may be selected again as the new first block.

[0044] When the wear leveling copy operation is set to the acceleration mode, the wear leveling copy control unit 433 executes the wear leveling copy operation. At this time, the wear leveling copy control unit 433 sets the ratio of the amount of data copied to the NAND memory 5 by the wear leveling copy operation to the amount of data written to the NAND memory 5 by the write process to a second ratio. The second ratio is a value larger than the first ratio in the normal mode. For example, in the acceleration mode, when the cumulative data write amount exceeds a fourth threshold value, the wear leveling copy control unit 433 executes the wear leveling copy operation to copy a first amount of valid data. That is, when the cumulative data write amount exceeds the fourth threshold value, the wear leveling copy control unit 433 executes the wear leveling copy operation such that the valid data stored in the first block is copied to the second block by the first amount.

[0045] The fourth threshold value is a value smaller than the third threshold value. The fourth threshold value may be set in advance as, for example, a set value B' (<B). Thereby, in the acceleration mode, the wear leveling copy operation is executed every time a smaller amount of host writing is performed, compared with the normal mode. In other words, in the acceleration mode, the wear leveling copy operation is executed at a higher frequency compared with the normal mode.

[0046] Next, the configuration of the NAND die will be described. Figure 2 is a block diagram showing a configuration example of each of a plurality of NAND dies included in the NAND flash memory 5.

[0047] The NAND die #n is any NAND die among NAND dies #0 to #31. The NAND die #n includes a plurality of blocks BLK0 to BLKx-1. Each of the blocks BLK0 to BLKx-1 includes a plurality of pages (here, pages P0 to Py-1). Each page includes a plurality of memory cells. Each of the blocks BLK0 to BLKx-1 is a unit of a data erase operation for erasing data. Each of the pages P0 to Py-1 is a unit of a data write operation and a data read operation.

[0048] Next, we will describe wear-leveling copying. Figure 3 shows an example of wear-leveling copying operation performed in the memory system according to the first embodiment.

[0049] First, the controller 4 writes the data stored in the write buffer (WB) 61 to the destination block in response to the write command. The controller 4 stores mapping information in the L2P table 62 that shows the correspondence between the logical address specified by the write command and the physical address indicating the storage location in the destination block. If old data corresponding to this logical address is already stored in another active block, the physical address indicating the storage location where this old data is stored loses its correspondence with the logical address. In other words, this old data becomes invalid data. This type of write operation is also called data overwriting.

[0050] Controller 4 selects a block from the free blocks to be assigned as a new write destination block. At this time, Controller 4 prioritizes selecting a block with a low number of erase cycles from among the blocks registered in the free block list 63 as the new write destination block. For example, Controller 4 selects the block with the fewest erase cycles among the free blocks. Controller 4 performs a data erase operation on the selected block. This makes the selected block a block on which data can be written. Controller 4 assigns the erased block as a write destination block and registers it in the active block list 64. At this time, Controller 4 checks the number of erase cycles for each of the multiple blocks in response to the data erase operation and performs a process to determine whether to enable or disable the wear-leveling copy operation.

[0051] Furthermore, if there is no more memory available to write new data to the destination block, the controller 4 releases the allocation of that block from the destination block. The released block simply becomes a block managed as an active block.

[0052] Once the data writing process is complete, the controller 4 determines whether the wear-leveling copy operation is enabled. If the wear-leveling copy operation is enabled, the controller 4 executes a wear-leveling copy operation to copy the amount of valid data specified by the setting value C stored in the source block to the destination block. If the total size of the valid data stored in the source block is less than the setting value C, the controller 4 selects an additional source block from the active blocks. Alternatively, during the execution of the wear-leveling copy operation, the controller 4 may select an additional source block from the active blocks in response to the depletion of valid data stored in the source block. In this case, the controller 4 selects, for example, the block with the fewest erase cycles among the active blocks registered in the active block list 64.

[0053] In the wear-leveling copy operation, the controller 4 may, instead of copying only the valid data stored in the source block to the destination block, copy all the data stored in the source block to the destination block. As the wear-leveling copy operation progresses, the source block becomes a block that does not store valid data and is registered in the free block list 63. As a result, blocks with a low number of erase cycles become free blocks that can be newly assigned to the destination block.

[0054] Furthermore, if there is no more memory space available to store new data in the destination block, the controller 4 selects a block with a high number of erase counts from among the blocks registered in the free block list 63 and assigns it to the destination block. In this case, the controller 4 selects a free block with at least more erase counts than the block selected as the source block and assigns it to the destination block. For example, the controller 4 selects the block with the second highest number of erase counts from among the free blocks registered in the free block list 63 and assigns it to the destination block.

[0055] Data stored in active blocks with a low number of deletions is expected to be data that is updated infrequently. Therefore, by copying data that is expected to be updated infrequently to blocks with a high number of deletions, it is possible to suppress a further increase in the number of deletions of those blocks.

[0056] Next, the settings used in the wear-leveling copy operation will be described. Figure 4 is a diagram showing the settings used in the wear-leveling copy operation performed in the memory system according to the first embodiment.

[0057] Each setting may be pre-configured during the manufacturing of the SSD3, or it may be updated during the operation of the SSD3.

[0058] First, setting value A is a threshold for determining whether or not to enable the wear-leveling copy operation. Setting value A is compared with the difference between the maximum and minimum number of erases for each block. When checking the number of erases for each of multiple blocks, controller 4 compares the difference between the maximum and minimum number of erases (also called the erase count difference) with setting value A. If the erase count difference is greater than setting value A, controller 4 enables the wear-leveling copy operation. If the erase count difference is less than or equal to setting value A, controller 4 disables the wear-leveling copy operation. In other words, when setting value A is set to a large value, a relatively large difference between the maximum and minimum number of erases is tolerated. On the other hand, when setting value A is set to a small value, the wear-leveling copy operation is enabled so that the difference between the maximum and minimum number of erases is relatively small.

[0059] Setting value A' is a threshold for determining whether or not to set the wear-leveling copy operation to accelerated mode. Setting value A' is greater than setting value A. When the wear-leveling copy operation is enabled, controller 4 compares the difference between the maximum number of erases and the minimum number of erases with setting value A'. If the difference in the number of erases is less than or equal to setting value A', controller 4 sets the wear-leveling copy operation to normal mode. If the difference in the number of erases is greater than setting value A', controller 4 sets the wear-leveling copy operation to accelerated mode.

[0060] Setting value B is the threshold for the cumulative data write amount used in normal mode. When the wear-leveling copy operation is set to normal mode, the controller 4 compares the cumulative data write amount with setting value B as the cumulative data write amount is updated. If the cumulative data write amount exceeds setting value B, the controller 4 performs the wear-leveling copy operation. If the cumulative data write amount is less than or equal to setting value B, the controller 4 does not perform the wear-leveling copy operation. In other words, setting value B is related to how often the wear-leveling copy operation is performed. When setting value B is set to a small value, the controller 4 performs the wear-leveling copy operation relatively frequently. Conversely, when setting value B is set to a large value, the controller 4 performs the wear-leveling copy operation relatively infrequently.

[0061] The setting value B' is the threshold for the cumulative data write amount used in accelerated mode. The setting value B' is smaller than the setting value B. When the wear-leveling copy operation is set to accelerated mode, the controller 4 compares the cumulative data write amount with the setting value B as the cumulative data write amount is updated. If the cumulative data write amount exceeds the setting value B', the controller 4 performs the wear-leveling copy operation. If the cumulative data write amount is less than or equal to the setting value B', the controller 4 does not perform the wear-leveling copy operation. Since the setting value B' is smaller than the setting value B, when the wear-leveling copy operation is set to accelerated mode, the controller 4 performs the wear-leveling copy operation more frequently than the wear-leveling copy operation in normal mode.

[0062] The setting value C is the amount of data copied from the source block to the destination block in a single wear-leveling copy operation. When the controller 4 performs a wear-leveling copy operation, it copies the amount of data specified by setting value C from the source block to the destination block. Setting value C is, for example, 1 / 100th the size of a single block. If setting value C is set to a small value, the time required for a single wear-leveling copy operation is short, and therefore the latency of the write operation caused by the wear-leveling copy operation is relatively small. Conversely, if setting value C is set to a large value, the time required for a single wear-leveling copy operation is longer, but the ability to equalize the number of erases of multiple blocks in a single wear-leveling copy operation is relatively greater.

[0063] Next, the distribution of the number of block erases when the wear-leveling copy operation is set to normal mode will be described. Figure 5 is a diagram showing the distribution of the number of block erases when the wear-leveling copy operation performed in the memory system according to the first embodiment is set to normal mode.

[0064] The vertical axis represents the number of times a block has been cleared. The horizontal axis shows the block number. In Figure 5, the number of times each of the 100 blocks, numbered from 1 to 100, has been cleared is plotted.

[0065] Here, we assume that setting value A is set to 200 and setting value A' is set to 400.

[0066] Of the various blocks, the block with the highest number of erases is block number 10 (hereinafter referred to as block 10). Block 10 has been erased 502 times.

[0067] On the other hand, among the various blocks, the block with the fewest number of erasures is block number 28 (hereinafter referred to as block 28). Block 28 has been erased 298 times.

[0068] Let's consider the case where a check is performed on the number of times each block has been erased, given the distribution of erase counts shown in Figure 5.

[0069] First, controller 4 determines whether to enable the wear-leveling copy operation by comparing the difference between the maximum number of erases and the minimum number of erases with setting value A. The difference between the maximum number of erases and the minimum number of erases is the difference between the number of erases for block 10 and the number of erases for block 28. In other words, the difference in the number of erases is 502 - 298 = 204. Comparing the difference in the number of erases with setting value A, the difference in the number of erases is greater than setting value A (204 > 200), so controller 4 enables the wear-leveling copy operation.

[0070] Next, the controller 4 compares the difference in the number of erase cycles with the set value A' to determine whether to set the wear-leveling copy operation to normal mode or accelerated mode. Comparing the difference in the number of erase cycles with the set value A', the difference in the number of erase cycles is less than or equal to the set value A' (204 < 400), so the controller 4 sets the wear-leveling copy operation to normal mode.

[0071] Next, the distribution of the number of block erases when the wear-leveling copy operation is set to accelerated mode will be described. Figure 6 is a diagram showing the distribution of the number of block erases when the wear-leveling copy operation performed in the memory system according to the first embodiment is set to accelerated mode.

[0072] The vertical axis represents the number of times a block has been cleared. The horizontal axis shows the block number. In Figure 5, the number of times each of the 100 blocks, numbered from 1 to 100, has been cleared is plotted.

[0073] Here, we assume that setting value A is set to 200 and setting value A' is set to 400.

[0074] Of the various blocks, the block with the highest number of erases is block number 9 (hereinafter referred to as block 9). Block 9 has been erased 802 times.

[0075] On the other hand, among the various blocks, the block with the fewest number of erasures is block number 82 (hereinafter referred to as block 82). Block 82 has been erased 201 times.

[0076] Let's consider the case where a check of the number of times each block has been erased is performed on the distribution of erase counts shown in Figure 6.

[0077] First, controller 4 determines whether to enable the wear-leveling copy operation by comparing the difference between the maximum number of erases and the minimum number of erases with setting value A. The difference between the maximum number of erases and the minimum number of erases is the difference between the number of erases for block 9 and the number of erases for block 82. Therefore, the difference in the number of erases is 802 - 201 = 601. Comparing the difference in the number of erases with setting value A, since the difference in the number of erases is greater than setting value A (601 > 200), controller 4 enables the wear-leveling copy operation.

[0078] Next, the controller 4 compares the difference in the number of erase cycles with the setting value A' to determine whether to set the wear-leveling copy operation to normal mode or accelerated mode. Comparing the difference in the number of erase cycles with the setting value A', the controller 4 finds that the difference in the number of erase cycles is greater than the setting value A' (601 > 400), so the controller 4 sets the wear-leveling copy operation to accelerated mode.

[0079] Next, we will describe the procedure for wear-leveling copy operation when acceleration mode is not used. Figure 7 is a sequence diagram showing the procedure for wear-leveling copy operation performed in the memory system of the comparative example.

[0080] First, the host issues a write command to the memory system controller (step S11). In S11, the host sends data along with the write command.

[0081] At this point, we consider the case where there is no more memory space available to write new data to the destination block.

[0082] The controller selects a block from the free blocks to be allocated as a new write destination block for the NAND memory, and performs a data erasure operation on the selected block (step S12). Then, the controller allocates the selected block as the write destination block.

[0083] The controller checks the number of erase cycles of the NAND memory blocks (step S13). In S13, the controller determines whether the erase cycle difference, which is the difference between the maximum and minimum erase cycles, is greater than or equal to the set value A. If the erase cycle difference is greater than or equal to the set value A, the controller enables the wear-leveling copy operation. If the erase cycle difference is less than or equal to the set value A, the controller disables the wear-leveling copy operation.

[0084] The controller writes data to the NAND memory based on the write command received in S11 (step S14).

[0085] The controller updates the cumulative data write amount according to the amount of data written to the NAND memory in S14 (step S15).

[0086] If the wear-leveling copy operation is enabled and the cumulative data write amount updated in S15 exceeds the set value B, the controller performs a wear-leveling copy operation to copy valid data to the NAND memory by the amount of set value C (step S16).

[0087] If the wear-leveling copy operation is performed in S16, the controller resets the cumulative data write amount to an initial value (e.g., 0) (step S17).

[0088] Next, the procedure for the wear-leveling copy operation when using the acceleration mode will be described. Figure 8 is a sequence diagram showing the procedure for the wear-leveling copy operation performed in the memory system according to the first embodiment.

[0089] First, host 2 issues a write command to the controller 4 of memory system 3 (step S21). In S21, host 2 transmits data along with the write command.

[0090] At this point, we consider the case where there is no more memory space available to write new data to the destination block.

[0091] The controller 4 selects a block from the free blocks to be allocated as a new write destination block for the NAND memory 5, and performs a data erasure operation on the selected block (step S22). Then, the controller 4 allocates the selected block as the write destination block.

[0092] The controller 4 checks the number of erase cycles for each block of the NAND memory 5 (step S23). In S23, the controller 4 determines whether the erase cycle difference, which is the difference between the maximum and minimum erase cycles, is greater than or equal to the set value A. If the erase cycle difference is less than or equal to the set value A, the controller 4 disables the wear-leveling copy operation. If the erase cycle difference is greater than or equal to the set value A, the controller 4 enables the wear-leveling copy operation. Once the wear-leveling copy operation is enabled, the controller 4 determines whether the erase cycle difference is greater than or equal to the set value A'. If the erase cycle difference is less than or equal to the set value A' (i.e., the erase cycle difference is greater than or equal to the set value A, and also less than or equal to the set value A'), the wear-leveling copy operation is set to normal mode. If the erase cycle difference is greater than or equal to the set value A', the wear-leveling copy operation is set to accelerated mode.

[0093] The controller 4 writes data to the NAND memory 5 based on the write command received in S21 (step S24).

[0094] The controller 4 updates the cumulative data write amount according to the amount of data written to the NAND memory 5 in S24 (step S25).

[0095] If the wear-leveling copy operation is enabled and the cumulative data write amount meets the conditions, the controller 4 performs the wear-leveling copy operation on the NAND memory 5 (step S26). If the wear-leveling copy operation is in normal mode, the controller 4 determines whether the cumulative data write amount updated in S25 exceeds the set value B. If the cumulative data write amount exceeds the set value B, the controller 4 performs the wear-leveling copy operation to copy valid data by the amount of set value C. If the wear-leveling copy operation is in accelerated mode, the controller 4 determines whether the cumulative data write amount updated in S25 exceeds the set value B'. If the cumulative data write amount exceeds the set value B', the controller 4 performs the wear-leveling copy operation to copy valid data by the amount of set value C.

[0096] If the wear-leveling copy operation is performed in S26, the controller 4 resets the cumulative data write amount to an initial value (e.g., 0) (step S27).

[0097] Next, the procedure for the wear-leveling copy operation will be described. Figures 9A and 9B are flowcharts showing the procedure for the wear-leveling copy operation performed in the memory system according to the first embodiment.

[0098] First, the controller 4 determines whether or not it has received a write command from the host 2 (step S301).

[0099] If no write command is received (No in S301), controller 4 waits until it receives a write command from host 2.

[0100] If a write command is received (Yes in S301), the controller 4 determines whether a new destination block is required based on the write command received in S301 (step S302).

[0101] If a new destination block is needed (Yes in S302), the controller 4 selects a new destination block from the free blocks and performs a data erasure operation on the new destination block (step S303).

[0102] If a new destination block is not needed (No in S302), controller 4 skips steps S303 through S309 described below.

[0103] After executing the data erasure operation in S303, the controller 4 determines whether the erasure count difference, which is the difference between the maximum and minimum erasure counts for each of the multiple blocks, is greater than the set value A (step S304).

[0104] If the difference in the number of erase cycles is greater than the set value A (Yes in S304), the controller 4 enables the wear-leveling copy operation (step S305).

[0105] If the difference in the number of erase cycles is less than or equal to the set value A (No in S304), the controller 4 disables the wear-leveling copy operation (step S306).

[0106] After disabling the wear-leveling copy operation in S306, the controller 4 skips the steps from S307 to S309 described below.

[0107] After enabling the wear-leveling copy operation in S305, the controller 4 determines whether the difference in the number of erase cycles is greater than the set value A' (step S307).

[0108] If the difference in the number of erase cycles is greater than the set value A' (Yes in S307), the controller 4 sets the wear-leveling copy operation to accelerated mode (step S308).

[0109] If the difference in the number of erase cycles is less than or equal to the set value A' (No in S307), the controller 4 sets the wear-leveling copy operation to normal mode (step S309).

[0110] Then, the controller 4 executes a write operation based on the write command received in S301 (step S310 in Figure 9B).

[0111] Once the write operation in S310 is complete, the controller 4 updates the cumulative data write amount according to the amount of data written to the NAND memory 5 (step S311).

[0112] Controller 4 determines whether the wear-leveling copy operation is enabled (step S312).

[0113] If the wear-leveling copy operation is not enabled (No in S312), the controller 4 skips the steps from S313 onwards described below and terminates the wear-leveling copy operation.

[0114] If the wear-leveling copy operation is enabled (Yes in S312), the controller 4 determines whether the wear-leveling copy operation is in normal mode or accelerated mode (step S313).

[0115] If the wear-leveling copy operation is in normal mode (normal mode in S313), the controller 4 determines whether the cumulative amount of data written exceeds the set value B (step S314).

[0116] If the cumulative amount of data written exceeds the set value B (Yes in S314), the controller 4 performs a copy operation to copy valid data by the amount of set value C (step S315).

[0117] Then, controller 4 resets the cumulative data write amount (step S316).

[0118] Furthermore, if the cumulative amount of data written is less than or equal to the set value B (No in S314), the controller 4 skips S315 and S316 and terminates the wear-leveling copy operation.

[0119] If the wear-leveling copy operation is in accelerated mode (accelerated mode in S313), the controller 4 determines whether the cumulative amount of data written exceeds the set value B' (step S317).

[0120] If the cumulative amount of data written exceeds the set value B' (Yes in S317), the controller 4 performs a copy operation to copy valid data by the amount of set value C (step S315).

[0121] Then, controller 4 resets the cumulative data write amount (step S316).

[0122] Furthermore, if the cumulative amount of data written is less than or equal to the set value B' (No in S317), the controller 4 skips S315 and S316 and terminates the wear-leveling copy.

[0123] As described above, according to the first embodiment, when a write operation is performed to write data to the NAND memory 5 based on a write command received from the host 2, the controller 4 checks the number of erase operations for each block in accordance with whether a data erase operation has been performed. The controller 4 determines whether the difference between the maximum number of erase operations and the minimum number of erase operations for each of the multiple blocks is greater than the set value A. If this difference in the number of erase operations is greater than the set value A, the controller 4 enables the wear-leveling copy operation and determines whether the difference in the number of erase operations is greater than the set value A'. Here, the set value A' is a value greater than the set value A.

[0124] If the difference in the number of erase cycles is greater than setting value A and less than or equal to setting value A', controller 4 sets the wear-leveling copy operation to normal mode. When the wear-leveling copy operation is set to normal mode, controller 4 performs wear-leveling copies by the amount of setting value C when the cumulative amount of data written exceeds setting value B.

[0125] Furthermore, if the difference in the number of erase cycles is greater than the set value A', the controller 4 determines that the difference in the number of erase cycles of multiple blocks is too large and cannot be handled by the normal mode wear-leveling copy operation. The controller 4 then sets the wear-leveling copy operation to accelerated mode. When the wear-leveling copy operation is set to accelerated mode and the cumulative amount of data written exceeds the set value B', the controller 4 performs the wear-leveling copy operation for an amount equal to the set value C.

[0126] The setting value B' is smaller than the setting value B. Therefore, while wear-leveling copy is set to accelerated mode, the controller 4 performs wear-leveling copy operations more frequently than in normal mode. The amount of data copied in a single wear-leveling copy operation is the amount of setting value C, in both normal mode and accelerated mode. Therefore, in accelerated mode, the ratio of the amount of data copied to NAND memory 5 by wear-leveling copy operations to the amount of data written to NAND memory 5 based on write commands received from host 2 is larger than in normal mode.

[0127] In this way, the controller 4 can select two modes of wear-leveling copy operation based on the difference in the number of erase cycles. The proportion of the amount of data copied to the NAND memory 5 differs between these two modes of wear-leveling copy operation. This allows the amount of processing required to level the number of erase cycles of a block to be dynamically controlled based on the current distribution of the number of erase cycles of the block.

[0128] (Second Embodiment) Next, we will describe a memory system according to a second embodiment that controls the ratio of the amount of data copied to the NAND memory 5 by a wear-leveling copy operation to the amount of data written to the NAND memory 5 based on a write command received from the host 2, by changing the amount of data written to the NAND memory 5 by a single wear-leveling copy operation between normal mode and accelerated mode.

[0129] In the following sections, we will focus on the differences from the first embodiment.

[0130] In the second embodiment, the wear-leveling copy control unit 433 of the SSD3 executes a wear-leveling copy operation to copy a second amount of valid data stored in the first block to the second block when the wear-leveling copy operation is set to accelerated mode and the cumulative amount of data written exceeds a third threshold. The third threshold is the same value as the setting value B used in normal mode. The second amount is a larger value than the first amount used in normal mode. The second amount may be set in advance, for example, as the setting value C'. As a result, in the wear-leveling copy operation set to accelerated mode, the amount of data copied in a single wear-leveling copy operation is greater than in the wear-leveling copy operation set to normal mode.

[0131] The settings used in the wear-leveling copy operation will now be described. Figure 10 shows the settings used in the wear-leveling copy operation performed in the memory system according to the second embodiment.

[0132] The setting values ​​A and A' are the same as the setting values ​​used in the first embodiment described with reference to Figure 4.

[0133] Setting value B is a threshold for the cumulative data write amount used in both normal mode and accelerated mode. When wear-leveling copy operation is enabled, controller 4 compares the cumulative data write amount with setting value B as the cumulative data write amount is updated. If the cumulative data write amount exceeds setting value B, controller 4 performs the wear-leveling copy operation. If the cumulative data write amount is less than or equal to setting value B, controller 4 does not perform the wear-leveling copy operation.

[0134] The setting value C is the amount of data copied in a single wear-leveling copy operation, which is used in normal mode. When the wear-leveling copy operation is set to normal mode, the controller 4 copies an amount of valid data equal to the setting value C from the source block to the destination block when executing the wear-leveling copy operation.

[0135] The setting value C' is the amount of data copied in a single wear-leveling copy operation used in accelerated mode. When the wear-leveling copy operation is set to accelerated mode, the controller 4 copies an amount of data equal to setting value C' from the source block to the destination block when executing the wear-leveling copy operation. Setting value C' is a larger value than setting value C. In other words, the wear-leveling copy operation in accelerated mode copies a larger amount of data in a single wear-leveling copy operation compared to the wear-leveling copy operation in normal mode.

[0136] Next, the procedure for the wear-leveling copy operation when using the acceleration mode in the second embodiment will be described. Figure 11 is a sequence diagram showing the procedure for the wear-leveling copy operation performed in the memory system according to the second embodiment.

[0137] In the processes from S41 to S45, the same processes as those described in Figure 8 for processes S21 to S25 are executed.

[0138] If the wear-leveling copy operation is enabled and the cumulative data write amount meets the conditions, the controller 4 performs the wear-leveling copy operation on the NAND memory 5 (step S46). If the wear-leveling copy operation is in normal mode, the controller 4 determines whether the cumulative data write amount updated in S45 exceeds the set value B. If the cumulative data write amount exceeds the set value B, the controller 4 performs the wear-leveling copy operation, which copies the amount of valid data equal to the set value C from the source block to the destination block.

[0139] Furthermore, even when the wear-leveling copy operation is in accelerated mode, the controller 4 determines whether the cumulative data written amount updated in S45 exceeds the set value B, just as it does in normal mode. If the cumulative data written amount exceeds the set value B, the controller 4 executes a wear-leveling copy operation that copies an amount of valid data equal to the set value C' from the source block to the destination block.

[0140] If a wear-leveling copy is performed in S46, the controller 4 resets the cumulative data write amount to an initial value (e.g., 0) (step S47).

[0141] Next, the procedure for the wear-leveling copy operation will be described. Figures 12A and 12B are flowcharts showing the procedure for the wear-leveling copy operation performed in the memory system according to the second embodiment.

[0142] In the processes from S501 to S512, the same processes as those described in Figures 9A and 9B, from S301 to S312, are executed.

[0143] If the wear-leveling copy operation is enabled (Yes in S512), the controller 4 determines whether the wear-leveling copy operation is in normal mode or accelerated mode (step S513).

[0144] If the wear-leveling copy operation is in normal mode (normal mode in S513), the controller 4 determines whether the cumulative amount of data written exceeds the set value B (step S514).

[0145] If the cumulative amount of data written exceeds the set value B (Yes in S514), the controller 4 performs a copy operation to copy valid data by the amount of set value C (step S515).

[0146] Then, controller 4 resets the cumulative data write amount to its initial value (step S516).

[0147] Furthermore, if the cumulative amount of data written is less than or equal to the set value B (No in S514), the controller 4 skips S515 and S516 and terminates the wear-leveling copy operation.

[0148] If the wear-leveling copy operation is in accelerated mode (accelerated mode in S513), the controller 4 determines whether the cumulative amount of data written exceeds the set value B (step S517).

[0149] If the cumulative amount of data written exceeds the set value B (Yes in S517), the controller 4 performs a copy operation to copy valid data by the amount of set value C' (step S518).

[0150] Then, controller 4 resets the cumulative data write amount to its initial value (step S516).

[0151] Furthermore, if the cumulative amount of data written is less than or equal to the set value B (No in S317), the controller 4 skips S518 and S516 and terminates the wear-leveling copy operation.

[0152] As explained above, according to the second embodiment, when the wear-leveling copy is set to accelerated mode and the cumulative data write amount exceeds the set value B, the controller 4 executes a wear-leveling copy operation that copies the amount of data stored in the source block to the destination block by the amount of the set value C'. The set value C' is a larger value than the set value C, which corresponds to the amount of data copied from the source block to the destination block in a single wear-leveling copy in normal mode. Therefore, while the wear-leveling copy operation is set to accelerated mode, the amount of data written by the controller 4 in a single wear-leveling copy is greater than in normal mode. The threshold for the cumulative data write amount, which is related to the frequency of wear-leveling copy execution, is the set value B in both normal mode and accelerated mode. Therefore, in accelerated mode, the ratio of the amount of data copied to the NAND memory 5 by the wear-leveling copy to the amount of data written to the NAND memory 5 based on write commands received from the host 2 is larger than in normal mode.

[0153] Thus, even in the configuration described in the second embodiment, the controller 4 can select two modes of wear-leveling copy operation based on the difference in the number of erase cycles. The proportion of the amount of data copied to the NAND memory 5 differs between these two wear-leveling copy operations. This allows for dynamic control of the amount of processing required to level the number of erase cycles of a block, based on the current distribution of the number of erase cycles of the block.

[0154] In the configurations described in the first and second embodiments, if the difference between the maximum and minimum number of erases for each of the multiple blocks is greater than the set value A', the controller 4 sets the wear-leveling mode to the accelerated mode. In this case, even if the number of erases for only a few specific blocks is extremely high or low, the wear-leveling mode will be set to the accelerated mode. Since it is possible to perform a wear-leveling copy operation for a small number of blocks using normal mode processing, it is undesirable for the wear-leveling copy operation to be set to the accelerated mode in such cases. Therefore, in the third and fourth embodiments described below, we will explain the case in which the average number of erases is used instead of the minimum or maximum number of erases to set the wear-leveling copy operation to normal mode or accelerated mode. (Third Embodiment) Next, a third embodiment will be described in which, when checking the number of times a block has been erased, the difference between the maximum number of erases (or the minimum number of erases) and the average number of erases is used to set the wear-leveling copy operation to normal mode or accelerated mode.

[0155] In the following sections, we will focus on the differences from the first embodiment.

[0156] In the third embodiment, the wear-leveling copy control unit 433 of the SSD3 compares the difference between either the maximum number of erases or the minimum number of erases and the average number of erases for each block of the SSD3 with a fifth threshold, depending on whether the wear-leveling copy operation is enabled. The difference between either the maximum number of erases or the minimum number of erases and the average number of erases for each block of the SSD3 is also referred to as the second difference. The fifth threshold may be set in advance, for example, as a set value D. If the second difference is less than or equal to the set value D, the wear-leveling copy control unit 433 sets the wear-leveling copy operation to normal mode. If the second difference is greater than the set value D, the wear-leveling copy control unit 433 sets the wear-leveling copy operation to accelerated mode. The following describes the case in which the difference between the maximum number of erases and the average number of erases is used, but instead of this difference, the difference between the minimum number of erases and the average number of erases may be used.

[0157] The settings used in the wear-leveling copy operation will now be explained. Figure 13 shows the settings used in the wear-leveling copy operation performed in the memory system according to the third embodiment.

[0158] The settings A, B, B', and C are the same as those used in the first embodiment described with reference to Figure 4.

[0159] Setting value D is a threshold for determining whether or not to set the wear-leveling copy operation to accelerated mode. When the wear-leveling copy operation is enabled, the controller 4 compares the difference between the maximum number of erases and the average number of erases with setting value D. If this difference is less than or equal to setting value D, the controller 4 sets the wear-leveling copy operation to normal mode. If this difference is greater than setting value D, the controller 4 sets the wear-leveling copy operation to accelerated mode. In other words, for each of the erase counts of multiple blocks, if the difference between the maximum number of erases and the minimum number of erases is greater than setting value A, and the difference between the maximum number of erases and the average number of erases is less than or equal to setting value D, the controller 4 sets the wear-leveling copy operation to normal mode. Also, if the difference between the maximum number of erases and the minimum number of erases is greater than setting value A, and the difference between the maximum number of erases and the average number of erases is greater than setting value D, the controller 4 sets the wear-leveling copy operation to accelerated mode.

[0160] Next, the distribution of the number of block erases when the wear-leveling copy operation is set to normal mode will be described. Figure 14 is a diagram showing the distribution of the number of block erases in the first case in which the wear-leveling copy operation performed in the memory system according to the third embodiment is set to normal mode.

[0161] The vertical axis represents the number of times a block has been cleared. The horizontal axis shows the block number of the block. In Figure 14, the number of times each of the 100 blocks, numbered from 1 to 100, has been cleared is plotted.

[0162] Here, we assume that setting value A is set to 200 and setting value D is set to 180.

[0163] Of the various blocks, the block with the highest number of erases is block number 10 (hereinafter referred to as block 10). Block 10 has been erased 502 times.

[0164] On the other hand, among the various blocks, the block with the fewest number of erasures is block number 28 (hereinafter referred to as block 28). Block 28 has been erased 298 times.

[0165] Additionally, the average number of times blocks were cleared was 397.

[0166] Let's consider the case where a check of the number of times each block has been erased is performed on the distribution of erase counts shown in Figure 14.

[0167] First, controller 4 determines whether to enable the wear-leveling copy operation by comparing the difference between the maximum number of erases and the minimum number of erases with setting value A. The difference between the maximum number of erases and the minimum number of erases is the difference between the number of erases for block 10 and the number of erases for block 28. Therefore, the difference in the number of erases is 502 - 298 = 204. Comparing the difference in the number of erases with setting value A, since the difference in the number of erases is greater than setting value A (204 > 200), controller 4 enables the wear-leveling copy operation.

[0168] Next, the controller 4 determines whether to set the wear-leveling copy operation to normal mode or accelerated mode by comparing the difference between the maximum number of erases and the average number of erases with the set value D. Since the maximum number of erases is the number of erases for block 10, the difference between the maximum number of erases and the average number of erases is 502 - 397 = 105. Comparing the difference between the maximum number of erases and the average number of erases with the set value D, the controller 4 sets the wear-leveling copy operation to normal mode because the difference between the maximum number of erases and the average number of erases is less than or equal to the set value D (105 < 180).

[0169] Next, we will describe the distribution of the number of block erases in the second case where the wear-leveling copy operation is set to normal mode. Figure 15 is a diagram showing the distribution of the number of block erases in the second case where the wear-leveling copy operation performed in the memory system according to the third embodiment is set to normal mode.

[0170] The vertical axis represents the number of times a block has been cleared. The horizontal axis shows the block number. In Figure 15, the number of times each of the 100 blocks, numbered from 1 to 100, has been cleared is plotted.

[0171] Here, we assume that setting value A is set to 200 and setting value D is set to 180.

[0172] Of the various blocks, the block with the highest number of erases is block number 10 (hereinafter referred to as block 10). Block 10 has been erased 502 times.

[0173] On the other hand, among the number of erasures for each of the multiple blocks, the block with the fewest erasures is block number 14 (hereinafter referred to as block 14). The number of erasures for block 14 is 2.

[0174] Additionally, the average number of times blocks were cleared was 399.

[0175] Let's consider the case where a check is performed on the number of times each block has been erased, given the distribution of erase counts shown in Figure 15.

[0176] First, controller 4 determines whether to enable the wear-leveling copy operation by comparing the difference between the maximum number of erases and the minimum number of erases with setting value A. The difference between the maximum number of erases and the minimum number of erases is the difference between the number of erases for block 10 and the number of erases for block 14. Therefore, the difference in the number of erases is 502 - 2 = 500. Comparing the difference in the number of erases with setting value A, since the difference in the number of erases is greater than setting value A (500 > 200), controller 4 enables the wear-leveling copy operation.

[0177] Next, the controller 4 compares the difference between the maximum number of erases and the average number of erases with the set value D to determine whether to set the wear-leveling copy operation to normal mode or accelerated mode. Since the maximum number of erases is the number of erases for block 10, the difference between the maximum number of erases and the average number of erases is 502 - 399 = 103. When the controller 4 compares the difference between the maximum number of erases and the average number of erases with the set value D, it finds that the difference between the maximum number of erases and the average number of erases is less than or equal to the set value D (103 < 180), so the controller 4 sets the wear-leveling copy operation to normal mode.

[0178] Thus, when only a specific block has a small number of erase cycles, the difference between the maximum and minimum erase cycles will significantly exceed the setting value A, but this does not affect the overall wear of SSD3. Therefore, by using the average number of erase cycles instead of the minimum erase cycle, it is possible to consider the total number of erase cycles for all blocks in SSD3 and determine whether or not to set the wear-leveling copy operation to accelerated mode.

[0179] Next, the distribution of the number of block erases when the wear-leveling copy operation is set to accelerated mode will be described. Figure 16 is a diagram showing the distribution of the number of block erases when the wear-leveling copy operation performed in the memory system according to the third embodiment is set to accelerated mode.

[0180] The vertical axis represents the number of times a block has been cleared. The horizontal axis shows the block number. In Figure 16, the number of times each of the 100 blocks, numbered from 1 to 100, has been cleared is plotted.

[0181] Here, we assume that setting value A is set to 200 and setting value D is set to 180.

[0182] Of the various blocks, the block with the highest number of erases is block number 9 (hereinafter referred to as block 9). Block 9 has been erased 802 times.

[0183] On the other hand, among the various blocks, the block with the fewest number of erasures is block number 82 (hereinafter referred to as block 82). Block 82 has been erased 201 times.

[0184] Additionally, the average number of times blocks were cleared was 511.

[0185] Let's consider the case where a check of the number of times each block has been erased is performed on the distribution of erase counts shown in Figure 16.

[0186] First, controller 4 determines whether to enable the wear-leveling copy operation by comparing the difference between the maximum number of erases and the minimum number of erases with setting value A. The difference between the maximum number of erases and the minimum number of erases is the difference between the number of erases for block 9 and the number of erases for block 82. Therefore, the difference in the number of erases is 802 - 201 = 601. Comparing the difference in the number of erases with setting value A, since the difference in the number of erases is greater than setting value A (601 > 200), controller 4 enables the wear-leveling copy operation.

[0187] Next, the controller 4 determines whether to set the wear-leveling copy operation to normal mode or accelerated mode by comparing the difference between the maximum number of erases and the average number of erases with the setting value D. Since the maximum number of erases is the number of erases for block 10, the difference between the maximum number of erases and the average number of erases is 802 - 511 = 291. Comparing the difference between the maximum number of erases and the average number of erases with the setting value D, the controller 4 sets the wear-leveling copy operation to accelerated mode because the difference between the maximum number of erases and the average number of erases is greater than the setting value D (291 > 180).

[0188] Next, the procedure for the wear-leveling copy operation will be described. Figure 17 is a sequence diagram showing the procedure for the wear-leveling copy operation performed in the memory system according to the third embodiment.

[0189] The processes in S61 and S62 perform the same operations as those in S21 and S22 as described in Figure 8.

[0190] The controller 4 checks the number of erase cycles for the blocks of the NAND memory 5 (step S63). In S63, the controller 4 determines whether the difference between the maximum number of erase cycles and the minimum number of erase cycles is greater than or equal to the set value A. If the difference between the maximum number of erase cycles and the minimum number of erase cycles is less than or equal to the set value A, the controller 4 disables the wear-leveling copy operation. If the difference between the maximum number of erase cycles and the minimum number of erase cycles is greater than the set value A, the controller 4 enables the wear-leveling copy operation.

[0191] When the wear-leveling copy operation is enabled, the controller 4 determines whether the difference between the maximum number of erases and the average number of erases is greater than the set value D. If the difference between the maximum number of erases and the average number of erases is less than or equal to the set value D (i.e., the difference between the maximum number of erases and the minimum number of erases is greater than the set value A, and the difference between the maximum number of erases and the average number of erases is less than or equal to D), the wear-leveling copy operation is set to normal mode. If the difference between the maximum number of erases and the average number of erases is greater than the set value D (i.e., the difference between the maximum number of erases and the minimum number of erases is greater than the set value A, and the difference between the maximum number of erases and the average number of erases is greater than D), the wear-leveling copy operation is set to accelerated mode.

[0192] Processes S64 through S67 execute the same processes as those described in Figure 8 for processes S24 through S27.

[0193] Next, the procedure for the wear-leveling copy operation will be described. Figures 18A and 18B are flowcharts showing the procedure for the wear-leveling copy operation performed in the memory system according to the third embodiment.

[0194] The processes from S701 to S703 execute the same processes as those described in Figure 9A, from S301 to S303.

[0195] After performing the data erasure operation in S703, the controller 4 determines whether the erasure count difference, which is the difference between the maximum and minimum erasure counts for each of the multiple blocks, is greater than the set value A (step S704).

[0196] If the difference between the maximum number of erase cycles and the minimum number of erase cycles is greater than the set value A (Yes in S704), the controller 4 enables the wear-leveling copy operation (step S705).

[0197] If the difference between the maximum number of erases and the minimum number of erases is less than or equal to the set value A (No in S704), the controller 4 disables the wear-leveling copy operation (step S706).

[0198] After disabling the wear-leveling copy operation in S706, the controller 4 skips the steps from S707 to S709 described below.

[0199] After enabling the wear-leveling copy operation in S705, the controller 4 determines whether the difference between the maximum number of erases and the average number of erases is greater than the set value D (step S707).

[0200] If the difference between the maximum number of erases and the average number of erases is greater than the set value D (Yes in S707), the controller 4 sets the wear-leveling copy operation to accelerated mode (step S708).

[0201] If the difference between the maximum number of erases and the average number of erases is less than or equal to the set value D (No in S707), the controller 4 sets the wear-leveling copy operation to normal mode (step S709).

[0202] The processes from S710 to S716 in Figure 18B are the same as the processes from S310 to S316 described in Figure 9B.

[0203] As described above, according to the third embodiment, the controller 4 can determine whether to set the wear-leveling copy operation to normal mode or accelerated mode based on the average number of erase counts for each of the multiple blocks. This prevents the wear-leveling copy operation from being unnecessarily set to accelerated mode even if only a small number of specific blocks have a low number of erase counts. In other words, by using the average number of erase counts, the mode of the wear-leveling copy operation can be set based on the bias in the number of erase counts across all blocks of the SSD 3.

[0204] Furthermore, the controller 4 may compare the difference between the average number of erases and the minimum number of erases with the set value D, instead of the difference between the maximum number of erases and the average number of erases. In this case, even if only a few specific blocks have a high number of erases, it is possible to avoid unnecessarily setting the wear-leveling copy to accelerated mode. (Fourth Embodiment) Next, a memory system according to the fourth embodiment will be described. In the fourth embodiment, similar to the third embodiment, the ratio of the amount of data copied to the NAND memory 5 by the wear-leveling copy operation is controlled according to the amount of data written to the NAND memory 5 by a write command. The memory system of the fourth embodiment determines whether to set the wear-leveling copy operation to normal mode or accelerated mode using the average of the number of erases for each of the multiple blocks, and changes the amount of data written to the NAND memory 5 by a single wear-leveling copy operation between normal mode and accelerated mode.

[0205] In the following sections, we will focus on explaining the differences from the third embodiment.

[0206] In the fourth embodiment, the wear-leveling copy control unit 433 of the SSD3 executes a wear-leveling copy operation to copy a second amount of valid data stored in the first block to the second block when the wear-leveling copy operation is set to accelerated mode and the cumulative amount of data written exceeds a third threshold. The third threshold is the same value as the setting value B used in normal mode. The second amount is a larger value than the first amount used in normal mode. The second amount may be set in advance, for example, as the setting value C'. As a result, in the wear-leveling copy operation set to accelerated mode, the amount of data copied in a single wear-leveling copy operation is greater than in the wear-leveling copy operation set to normal mode.

[0207] The settings used in the wear-leveling copy operation will be explained. Figure 19 is a diagram showing the settings used in the wear-leveling copy operation of the memory system according to the fourth embodiment.

[0208] The setting values ​​A and D are the same as the setting values ​​used in the third embodiment described with reference to Figure 13.

[0209] Setting value B is a threshold for the cumulative data write amount used in both normal mode and accelerated mode. When wear-leveling copy operation is enabled, controller 4 compares the cumulative data write amount with setting value B as the cumulative data write amount is updated. If the cumulative data write amount exceeds setting value B, controller 4 performs the wear-leveling copy operation. If the cumulative data write amount is less than or equal to setting value B, controller 4 does not perform the wear-leveling copy operation.

[0210] The setting value C is the amount of data copied in a single wear-leveling copy operation, which is used in normal mode. When the wear-leveling copy operation is set to normal mode, the controller 4 copies an amount of valid data equal to the setting value C from the source block to the destination block when executing the wear-leveling copy operation.

[0211] The setting value C' is the amount of data copied in a single wear-leveling copy operation used in accelerated mode. When the wear-leveling copy operation is set to accelerated mode, the controller 4 copies an amount of data equal to setting value C' from the source block to the destination block when executing the wear-leveling copy operation. Setting value C' is a larger value than setting value C. In other words, the wear-leveling copy operation in accelerated mode copies a larger amount of data in a single wear-leveling copy operation compared to the wear-leveling copy operation in normal mode.

[0212] Next, the procedure for the wear-leveling copy operation when using the acceleration mode in the fourth embodiment will be described. Figure 20 is a sequence diagram showing the procedure for the wear-leveling copy operation performed in the memory system according to the fourth embodiment.

[0213] Processes S81 through S85 execute the same processes as those described in Figure 17 for processes S61 through S65.

[0214] If the wear-leveling copy operation is enabled and the cumulative data write amount meets the conditions, the controller 4 performs the wear-leveling copy operation on the NAND memory 5 (step S86). If the wear-leveling copy operation is in normal mode, the controller 4 determines in S85 whether the cumulative data write amount updated exceeds the set value B. If the cumulative data write amount exceeds the set value B, the controller 4 performs the wear-leveling copy operation to copy an amount of valid data equal to the set value C from the source block to the destination block. Similarly, if the wear-leveling copy operation is in accelerated mode, the controller 4 also determines in S85 whether the cumulative data write amount updated exceeds the set value B. If the cumulative data write amount exceeds the set value B, the controller 4 performs the wear-leveling copy operation to copy an amount of valid data equal to the set value C' from the source block to the destination block.

[0215] If a wear-leveling copy is performed in S86, the controller 4 resets the cumulative data write amount to an initial value (e.g., 0) (step S87).

[0216] Next, the procedure for the wear-leveling copy operation will be described. Figures 20A and 20B are flowcharts showing the procedure for the wear-leveling copy operation performed in the memory system according to the fourth embodiment.

[0217] In the processes from S901 to S912, the same processes as those described in Figures 18A and 18B, from S701 to S712, are executed.

[0218] If the wear-leveling copy operation is enabled (Yes in S912), the controller 4 determines whether the wear-leveling copy operation is in normal mode or accelerated mode (step S913).

[0219] If the wear-leveling copy operation is in normal mode (normal mode in S913), the controller 4 determines whether the cumulative amount of data written exceeds the set value B (step S914).

[0220] If the cumulative amount of data written exceeds the set value B (Yes in S914), the controller 4 performs a copy operation, copying the amount of valid data equal to the set value C from the source block to the destination block (step S915).

[0221] Then, controller 4 resets the cumulative data write amount to its initial value (step S916).

[0222] Furthermore, if the cumulative amount of data written is less than or equal to the set value B (No in S914), the controller 4 skips S915 and S916 and terminates the wear-leveling copy operation.

[0223] If the wear-leveling copy operation is in accelerated mode (accelerated mode in S913), the controller 4 determines whether the cumulative amount of data written exceeds the set value B (step S917).

[0224] If the cumulative amount of data written exceeds the set value B (Yes in S917), the controller 4 performs a copy operation, copying the amount of valid data equal to the set value C' from the source block to the destination block (step S918).

[0225] Then, controller 4 resets the cumulative data write amount to its initial value (step S916).

[0226] Furthermore, if the cumulative amount of data written is less than or equal to the set value B (No in S917), the controller 4 skips S918 and S916 and terminates the wear-leveling copy operation.

[0227] As explained above, according to the fourth embodiment, when the wear-leveling copy operation is set to accelerated mode and the cumulative data write amount exceeds the set value B, the controller 4 executes a wear-leveling copy operation that copies the amount of data stored in the source block to the destination block by the amount of the set value C'. The set value C' is a larger value than the set value C, which corresponds to the amount of data copied from the source block to the destination block in a single wear-leveling copy in normal mode. Therefore, while the wear-leveling copy operation is set to accelerated mode, the amount of data that the controller 4 writes to the NAND memory 5 in a single wear-leveling copy is greater than in normal mode. The threshold for the cumulative data write amount, which is related to the frequency of wear-leveling copy execution, is the set value B in both normal mode and accelerated mode. Therefore, in accelerated mode, the ratio of the amount of data copied to the NAND memory 5 by wear-leveling copy to the amount of data written to the NAND memory 5 based on write commands received from the host 2 is larger than in normal mode.

[0228] Furthermore, the settings used in the first to fourth embodiments are not limited to pre-set values. Each setting may be changed as needed.

[0229] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a variety of other forms, and various omissions, substitutions, and modifications are permitted without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as described in the claims. [Explanation of symbols]

[0230] 1... Information processing system, 2... Host, 3... SSD, 4... Controller, 5... NAND flash memory, 6... DRAM, 7... Bus, 20... Internal bus, 21... Processor, 22... Memory, 40... Internal bus, 41... Host interface circuit, 42... SRAM, 43... CPU, 44... Error correction circuit, 45... NAND interface circuit, 46... DRAM interface circuit, 61... Write buffer, 62... L2P table, 63... Free block list, 64... Active block list, 431... Command processing unit, 432... Consumption leveling copy enable / disable unit, 433... Consumption leveling copy control unit.

Claims

1. A memory system that can be connected to a host, Non-volatile memory containing multiple blocks, each of which is a unit of data erasure operation, A controller configured to perform a data erasure operation on blocks that do not contain valid data, and to assign the blocks on which the data erasure operation has been performed as the destination blocks for writing data received from the host, The aforementioned controller, In response to the execution of the aforementioned data erasure operation, Obtain a first difference between the first number of erasures and the second number of erasures among the number of erasures for each of the plurality of blocks, and compare the first difference with a first threshold. The cumulative amount of data written is compared with the second threshold, If the first difference exceeds the first threshold and the cumulative amount of data written exceeds the second threshold, a copy operation is performed to copy the valid data stored in the first block, which has the fewest erase cycles among the blocks where valid data is stored, to the second block, which does not store valid data and has a higher erase cycle than the first block, thereby copying a first amount of data. Memory system.

2. The cumulative amount of data written is the amount of data written to the non-volatile memory based on one or more write commands received from the host. The memory system according to claim 1.

3. The first erasure count is the minimum erasure count among the multiple erasure counts for each block. The second erasure count is the maximum erasure count among the multiple erasure counts for each block. The memory system according to claim 1.

4. The controller is configured to reset the cumulative data write amount after the copy operation is performed if the cumulative data write amount exceeds the second threshold. The memory system according to claim 1.

5. The aforementioned controller, In response to the execution of the aforementioned data erasure operation, The first difference is compared with the first threshold and a third threshold that is greater than the first threshold. The cumulative amount of data written is compared with the second threshold, If the first difference is greater than the first threshold, and the first difference is less than the third threshold, and the cumulative amount of data written is greater than the second threshold, the copy operation is performed to copy the second amount of data. The memory system according to claim 1.

6. The aforementioned controller, If the first difference is greater than the third threshold and the cumulative amount of data written is greater than the second threshold, the copy operation is performed to copy the third amount of data. The memory system according to claim 5.

7. The data for the third quantity is larger than the data for the second quantity. The memory system according to claim 6.

8. The aforementioned controller, A fourth threshold is compared to a second difference between the maximum or minimum number of erases for each of the multiple blocks and the average number of erases for each of the multiple blocks. The cumulative amount of data written is compared with the second threshold, If the first difference is greater than the first threshold, the second difference is less than or equal to the fourth threshold, and the cumulative amount of data written is greater than the second threshold, the copy operation is performed to copy the fourth amount of data. The memory system according to claim 1.

9. The aforementioned controller, If the first difference is greater than the first threshold, the second difference is greater than the fourth threshold, and the cumulative amount of data written is greater than the second threshold, the copy operation is performed to copy a fifth amount of data. The memory system according to claim 8.

10. The data for the fifth quantity is greater than the data for the fourth quantity. The memory system according to claim 9.

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