Interface circuits and semiconductor devices

Abstract

It provides an effective interface circuit in terms of size. [Solution] The interface circuit (3) comprises an upper driver element (50B) configured as a P-channel MOSFET and a lower driver element (50A) configured as an N-channel MOSFET, and includes at least one of a lower diode element (4A) whose third terminal (Tg) is connected to the anode and second terminal (To) is connected to the cathode, and an upper diode element (4B) whose first terminal (Tv) is connected to the cathode and second terminal is connected to the anode, and at least one of a first protection element region (24) where the lower diode element is located and a second protection element region (25) where the upper diode element is located are located between an NMOS region (210) where the lower driver element is located and a PMOS region (22) where the upper driver element is located in a first direction.

Description

[Technical Field]

[0001] This disclosure relates to an interface circuit. [Background technology]

[0002] ESD (Electrostatic Discharge) is a phenomenon in which static electricity discharge occurs. If ESD pulses enter the interior of an IC due to ESD, it can cause malfunctions in the IC. Therefore, conventionally, ICs are sometimes equipped with countermeasures to suppress malfunctions caused by ESD.

[0003] Conventionally, MOS transistors (MOSFETs (metal-oxide-semiconductor field-effect transistors)) have been known to be used as ESD protection elements (for example, Patent Document 1). When ESD occurs, a surge current is passed through the MOS transistor to suppress adverse effects on the IC. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2003-179226

[0005] [overview] In the interface circuit with ESD protection functionality, there was room for improvement in terms of size.

[0006] An interface circuit relating to one aspect of this disclosure is, A first terminal configured to receive a power supply voltage, A second terminal configured to receive an output signal, A third terminal configured to have a ground potential applied, An upper driver element configured as a P-channel MOSFET, with the first terminal connected to the source and the second terminal connected to the drain, The lower driver element is configured as an N-channel MOSFET with the third terminal connected to the source and the second terminal connected to the drain, Equipped with, The device comprises at least one of a lower diode element whose third terminal is connected to the anode and whose second terminal is connected to the cathode, and an upper diode element whose first terminal is connected to the cathode and whose second terminal is connected to the anode. In a plan view, the direction in which the gate of the lower driver element or the upper driver element extends is defined as the first direction. The configuration includes a first protection element region where the lower diode element is located and a second protection element region where the upper diode element is located, which are positioned between the NMOS region where the lower driver element is located and the PMOS region where the upper driver element is located in a first direction. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of a semiconductor device configuration. [Figure 2] Figure 2 is a plan view showing the layout of a standard I / O cell related to a comparative example. [Figure 3] Figure 3 shows the circuit configuration of the interface circuit in the comparative example. [Figure 4A] Figure 4A shows the surge current generated in the interface circuit of the comparative example. [Figure 4B] Figure 4B is a vertical structural diagram illustrating the operation of a parasitic bipolar transistor. [Figure 5] Figure 5 is a plan view showing the layout of a standard I / O cell according to the embodiment of this disclosure. [Figure 6] Figure 6 shows the circuit configuration of an interface circuit according to an embodiment of this disclosure. [Figure 7] Figure 7 shows the surge current generated in the interface circuit according to the embodiment of this disclosure. [Figure 8]Figure 8 is a diagram for explaining the effect when the breakdown of a MOSFET is not used for ESD protection. [Figure 9] Figure 9 is a diagram showing a vertical structure of a standard I / O cell according to an embodiment of the present disclosure. [Figure 10] Figure 10 is a diagram showing a vertical structure according to a reference example. [Figure 11] Figure 11 is a plan view showing in more detail protection element regions 24 and 25 in the standard I / O cell according to the embodiment of the present disclosure. [Figure 12] Figure 12 is an enlarged diagram showing the configuration in the protection element region 24. [Figure 13] Figure 13 is an enlarged diagram showing the configuration in the protection element region 25.

[0008] [Detailed Description] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <Semiconductor Device> Figure 1 is a diagram showing one configuration example of a semiconductor device. The semiconductor device 1 of this configuration example is an LSI in which a CMOS [complementary MOS] circuit (logic / analog mixed circuit) that is driven mainly at 5V or lower is integrated. At the outermost peripheral portion of the semiconductor device 1, an I / O [input / output] circuit 10 responsible for an ESD protection function and a signal input / output function is arranged.

[0010] In addition to the I / O circuit 10, various internal circuits are integrated in the semiconductor device 1. Described in accordance with this figure, as various internal circuits, a logic circuit LOGIC, an analog circuit ANALOG, an interface circuit I / F, a nonvolatile memory NVM, a volatile memory SRAM, a digital / analog converter DAC, an analog / digital converter ADC, and a regulator LDO are integrated in the semiconductor device 1.

[0011] The I / O circuit 10 is arranged so as to surround the above internal circuits in a plan view of the semiconductor device 1 They may be arranged along the four sides of the semiconductor device 1.

[0012] Examples of semiconductor devices 1 include an integrated communication IC (IC) for automotive applications that receives commands via an in-vehicle network and controls controllers (such as ECUs [electronic control units]) mounted on various terminal devices (such as LED [light emitting diode] lamps, motors, or switches). In this case, the interface circuit I / F may conform to any in-vehicle network (e.g., LIN [local interconnect network], CXPI [clock extension peripheral interface], and CAN [controller area network]).

[0013] <Comparative Example> Here, comparative examples will be described for comparison with the embodiments of this disclosure.

[0014] <<Standard I / O Cell>> The I / O circuit 10 is composed of a combination of standard I / O cells. A standard I / O cell is the unit that makes up the I / O circuit 10, and as will be described later, it is composed of various MOSFETs (metal-oxide-semiconductor field-effect transistors) arranged in a row. By appropriately wiring the standard I / O cells, interface functions with the outside of the device (ESD protection function and signal input / output function) can be provided.

[0015] Figure 2 is a plan view showing the layout of a standard I / O cell 20 relating to a comparative example. In Figure 2 (and other drawings), the first direction (X direction) and the second direction (Y direction) are shown as mutually orthogonal. The standard I / O cell 20 has an NMOS region 21, a PMOS region 22, and a control circuit region 23.

[0016] As shown in Figure 2, the NMOS region 21 includes a dedicated protection element region Ra and a protection element selection region Rb, which are regions where protection elements are placed.

[0017] In the protection-dedicated element region Ra, protection elements Ma, which function solely as ESD protection elements, are placed. Each protection element Ma is configured as an N-channel MOSFET and multiple Ma are arranged side by side in the second direction, as shown in Figure 2. Each protection element Ma has a gate Ga, as shown in Figure 2, with a gate width in the first direction and a gate length in the second direction.

[0018] The protection element selection region Rb is adjacent to the protection-dedicated element region Ra in the first direction. A protection element Mb that provides ESD protection is placed in the protection element selection region Rb. The protection element Mb is configured as an N-channel MOSFET and multiple Mb are arranged side by side in the second direction as shown in Figure 2. As shown in Figure 2, the protection element Mb has a gate Gb having a gate width in the first direction and a gate length in the second direction.

[0019] In the protection element selection region Rb, it is possible to select from among multiple protection elements Mb whether to choose a protection element Mb that serves both as an ESD protection element and a driver element (driver and protection element), or a protection element Mb that only provides ESD protection (protection-only element). This selection is made by changing the wiring to the gate Gb.

[0020] Of the multiple protection elements Mb, for example, one protection element Mb can be selected as a driver / protection element, and the remaining protection elements Mb can be selected as protection-only elements. Alternatively, for example, all of the protection elements Mb can be selected as driver / protection elements. The number of driver / protection elements is selected according to the required current capacity. When an ESD occurs, surge current flows through both the driver / protection elements and the protection-only elements, activating a function to protect the inside of the IC.

[0021] The PMOS region 22 is adjacent to the NMOS region 21 in the first direction. In the PMOS region 22, multiple protection elements Mc, each composed of a P-channel MOSFET, are arranged in a row in the second direction. Each protection element Mc has a gate Gc. Some of the multiple protection elements Mc can be used as driver-protection elements, while the remaining protection elements Mc can be used as protection-only elements.

[0022] The control circuit region 23 is adjacent to the PMOS region 22 in the first direction. By appropriately wiring to the control circuit region 23, interface circuits for various functions can be configured.

[0023] <<Output Circuit>> Figure 3 shows the circuit configuration of the interface circuit 30 according to the comparative example. The interface circuit 30 is configured as an output circuit using a standard I / O cell 20 and includes an ESD protection unit 40 and an output driver 50. The interface circuit 30 also includes a power terminal Tv, an output terminal To, and a ground terminal Tg.

[0024] The ESD protection unit 40 includes a lower protection element 40A and an upper protection element 40B.

[0025] The lower protection element 40A uses protection element Ma in the protection-only element region Ra and protection element Mb (protection-only element) in the protection element selection region Rb, and is configured as an N-channel MOSFET. The drain of the lower protection element 40A is connected to the output terminal To. The source of the lower protection element 40A is connected to the ground terminal Tg. The gate-source of the lower protection element 40A is short-circuited. The back gate-source of the lower protection element 40A is short-circuited.

[0026] The upper protection element 40B uses a protection element Mc (dedicated protection element) in the PMOS region 22 and is configured as a P-channel MOSFET. The drain of the upper protection element 40B is connected to the output terminal To. The source of the upper protection element 40B is connected to the power supply terminal Tv. The gate-source of the upper protection element 40B is short-circuited. The back gate-source of the upper protection element 40B is short-circuited.

[0027] The output driver 50 includes a lower driver element 50A and an upper driver element 50B.

[0028] The lower driver element 50A uses a protection element Mb (driver and protection element) in the protection element selection region Rb, and is configured as an N-channel MOSFET. The drain of the lower driver element 50A is connected to the output terminal To. The source of the lower driver element 50A is connected to the ground terminal Tg. The back gate and source of the lower driver element 50A are short-circuited.

[0029] The upper driver element 50B uses a protection element Mc (driver and protection element) in the PMOS region 22 and is configured as a P-channel MOSFET. The drain of the upper driver element 50B is connected to the output terminal To. The source of the upper driver element 50B is connected to the power supply terminal Tv. The back gate and source of the upper driver element 50B are short-circuited.

[0030] The power supply voltage is applied to the power supply terminal Tv. The ground potential is applied to the ground terminal Tg. The gates of the lower driver element 50A and the upper driver element 50B are controlled by a control circuit (not shown, included in the interface circuit 30), and an output signal is output from the output terminal To.

[0031] Furthermore, a power supply-to-ground protection element 35 is provided outside the interface circuit 30. The power supply-to-ground protection element 35 is composed of an N-channel MOSFET with the gate-to-source and back-gate-to-source connections short-circuited, respectively. The drain of the power supply-to-ground protection element 35 is connected to the power supply terminal Tv. The source of the power supply-to-ground protection element 35 is connected to the ground terminal Tg.

[0032] ESD protection in interface circuit 30 is performed as follows. Figure 4A shows the various surge currents that flow during ESD protection in interface circuit 30.

[0033] When a positive surge voltage is applied to the ground terminal Tg relative to the output terminal To, a surge current I1 is generated that flows from the ground terminal Tg through the parasitic diode (body diode) BD1 of the lower protection element 40A to the output terminal To. At this time, a surge current also flows through the parasitic diode BD3 of the lower driver element 50A.

[0034] When a positive surge voltage is applied to the output terminal To relative to the power terminal Tv, a surge current I2 is generated that flows from the output terminal To through the parasitic diode BD2 of the upper protection element 40B to the power terminal Tv. At this time, a surge current also flows through the parasitic diode BD4 of the upper driver element 50B.

[0035] When a positive surge voltage is applied to the output terminal To relative to the ground terminal Tg, the parasitic bipolar transistor in the lower protection element 40A activates, generating a surge current I3 that flows from the output terminal To through the lower protection element 40A to the ground terminal Tg. At this time, the parasitic bipolar transistor in the lower driver element 50A also activates, causing a surge current to flow through the lower driver element 50A as well.

[0036] Here, the operation of the parasitic bipolar transistor will be explained using Figure 4B. Figure 4B shows the longitudinal structure of the protection elements Ma and Mb. The protection elements Ma and Mb are formed in the P region PR in the N region. As shown in Figure 4B, in the protection elements Ma and Mb, + Region Drain D, P region PR, and N + A parasitic bipolar transistor Tr1 is formed by the NPN junction of the source S in the region. In addition, in the protective elements Ma and Mb, P + The back gate BG of the region is connected to the ground terminal Tg.

[0037] The drain D of the protection element Ma,Mb is connected to the output terminal To, and a surge voltage is applied to the output terminal To. As a result, the PN junction (reverse bias diode) between the drain D and the P region PR breaks down, generating a leakage current. This leakage current flows to the back gate BG through the resistive component R1 of the P region PR and also becomes the base current of the parasitic bipolar transistor Tr1, causing an emitter current to flow and turning on the parasitic bipolar transistor Tr1. Therefore, the surge current is led from the source S to the ground terminal Tg.

[0038] Returning to the explanation in Figure 4A, when a positive surge voltage is applied to the power supply terminal Tv relative to the output terminal To, the parasitic bipolar transistor of the power supply-ground protection element 35 operates, generating a surge current I4 that flows from the power supply terminal Tv through the power supply-ground protection element 35 to the parasitic diode BD1 and the output terminal To.

[0039] <Embodiments of this Disclosure> In the standard I / O cell 20 (Figure 2) in the above comparative example, it was necessary to ensure a distance L20 between the NMOS region 21 and the PMOS region 22 to suppress the operation of the parasitic thyristor structure and prevent latch-up, which resulted in a larger size for the standard I / O cell 20.

[0040] Therefore, the standard I / O cell according to the embodiment of this disclosure has the following configuration. Figure 5 is a plan view showing the layout of the standard I / O cell 2 according to the embodiment of this disclosure. The standard I / O cell 2 comprises an NMOS region 210, a PMOS region 22, a control circuit region 23, a protection element region 24, and a protection element region 25.

[0041] The NMOS region 210 is the same region as the protection element selection region Rb in the standard I / O cell 20 (Figure 2) in the comparative example, and in the NMOS region 210, it is possible to select between a driver / protection element and a protection-only element. The protection element region 24 is the region where the lower diode element 4A, described later as a protection element, is placed, and is provided adjacent to the NMOS region 210.

[0042] The PMOS region 22 and the control circuit region 23 are the same as those in the standard I / O cell 20 in the comparative example. The protection element region 25 is the region where the upper diode element 4B, described later as a protection element, is located, and is provided adjacent to the PMOS region 22.

[0043] As described above, in this embodiment, the dedicated protection element region Ra (included in the NMOS region 21) in the standard I / O cell 20 (Figure 2) of the comparative example is replaced with a protection element region 24, and a protection element region 25 is added to the PMOS region 22. The protection element regions 24 and 25 are then positioned between the NMOS region 210 and the PMOS region 22 in the first direction. This ensures a distance L2 between the NMOS region 210 and the PMOS region 22, suppressing latch-up, while also allowing the size to be reduced (shrinked) from the standard I / O cell 20 of the comparative example, as shown by the arrow SH in Figure 5.

[0044] Figure 6 shows the circuit configuration of the interface circuit 3 according to the embodiment of this disclosure. The interface circuit 3 is configured as an output circuit using a standard I / O cell 2 and includes an ESD protection unit 4 and an output driver 50. The interface circuit 3 also includes a power terminal Tv, an output terminal To, and a ground terminal Tg.

[0045] The output driver 50 is the same as the interface circuit 30 (Figure 3) in the comparative example, and includes a lower driver element 50A and an upper driver element 50B.

[0046] The lower driver element 50A uses a driver / protection element (N-channel MOSFET) in the NMOS region 210 (protection element selection region). Note that some of the protection elements in the NMOS region 210 may be designated as protection-only elements.

[0047] The upper driver element 50B uses a driver and protection element (P-channel MOSFET) in the PMOS region 22. Note that some of the protection elements in the PMOS region 22 may be dedicated protection elements.

[0048] The ESD protection unit 4 includes a lower diode element 4A and an upper diode element 4B.

[0049] The lower diode element 4A uses the protection element in the protection element region 24 (Figure 5). The anode of the lower diode element 4A is connected to the ground terminal Tg. The cathode of the lower diode element 4A is connected to the output terminal To. The lower diode element 4A compensates for the current capacity that the parasitic diode in the lower driver element 50A lacks during ESD protection.

[0050] The upper diode element 4B uses the protection element in the protection element region 25 (Figure 5). The anode of the upper diode element 4B is connected to the output terminal To. The cathode of the upper diode element 4B is connected to the power supply terminal Tv. The upper diode element 4B compensates for the current capacity that the parasitic diode in the upper driver element 50B does not have during ESD protection.

[0051] ESD protection in interface circuit 3 is performed as follows. Figure 7 shows the various surge currents that flow during ESD protection in interface circuit 3.

[0052] When a positive surge voltage is applied to the ground terminal Tg relative to the output terminal To, a surge current Ia is generated that flows from the ground terminal Tg through the lower diode element 4A to the output terminal To. At this time, a surge current also flows through the parasitic diode of the lower driver element 50A.

[0053] When a positive surge voltage is applied to the output terminal To relative to the power terminal Tv, a surge current Ib is generated that flows from the output terminal To through the upper diode element 4B to the power terminal Tv. At this time, a surge current also flows through the parasitic diode of the upper driver element 50B.

[0054] When a positive surge voltage is applied to the output terminal To relative to the ground terminal Tg, a surge current Ic is generated that flows from the output terminal To through the upper diode element 4B and the power supply-ground protection element 35 to the ground terminal Tg. At this time, a surge current also flows through the parasitic diode of the upper driver element 50B.

[0055] Thus, in the comparative example interface circuit 30 (Figure 4), the breakdown of the parasitic diodes of the N-channel MOSFETs (40A, 50A) was utilized when a surge current I3 flowed. However, in this embodiment, the breakdown of the parasitic diodes of the lower diode element 4A and the N-channel MOSFET (50A) is not utilized when a surge current Ic flows.

[0056] By not utilizing the breakdown of parasitic diodes in an N-channel MOSFET, the following advantages can be enjoyed. First, when utilizing breakdown, the layout of the N-channel MOSFET requires careful consideration. Specifically, as shown on the left side of Figure 8, the drain width Wd1 and source width Ws1 must be widened and a silicide blocking region SB added to the drain in order to secure the current capability after breakdown. This increases the size of the MOSFET. In contrast, when breakdown is not utilized, as shown on the right side of Figure 8, the silicide blocking region SB is unnecessary, and the drain width Wd2 and source width Ws2 can be smaller, allowing for a smaller MOSFET size.

[0057] Furthermore, by not utilizing breakdown, an ESD layer becomes unnecessary, resulting in cost reduction. If an ESD layer is added, an additional step of injecting ESD implantation is required at the added location. The effects of injecting ESD implantation include making the MOSFET more prone to breakdown, thereby lowering the voltage required for the protection element to operate and expanding the range of ESD protection, and making it easier for the entire element to break down simultaneously when the MOSFET breaks down, thus reducing the likelihood of localized current concentration.

[0058] Furthermore, as shown in Figure 7, when a positive surge voltage is applied to the power supply terminal Tv relative to the output terminal To, the parasitic diode of the power supply-ground protection element 35 breaks down, generating a surge current Id that flows from the power supply terminal Tv through the parasitic diode to the lower diode element 4A and the output terminal To.

[0059] Figure 9 shows the vertical structure of a standard I / O cell 2 according to an embodiment of the present disclosure. As shown in Figure 9, the lower driver element 50A (N-channel MOSFET) and the lower diode element 4A are formed in the P region (e.g., the P-well region) PR. The back gate BG(P) in the lower driver element 50A + Region), Source S(N + Region), drain D(N + The region, and gate G are formed on the surface of region P PR. The lower diode element 4A is P + Region (anode) and N + It has a region (cathode).

[0060] In this embodiment, as shown in Figure 9, the lower diode element 4A is formed using the back gate BG1 of the lower driver element 50A (N-channel MOSFET). That is, the back gate BG1 is shared by the lower driver element 50A and the lower diode element 4A. This makes it possible to reduce the size compared to a structure in which the MOSFET and diode are separated, as shown in the vertical structure in Figure 10.

[0061] Further, as shown in FIG. 9, the upper driver element 50B (P-channel type MOSFET) and the upper diode element 4B are formed in an N region (for example, an N well region) NR. The back gate BG (N + region), the source S (P + region), the drain D (P + region), and the gate G of the upper driver element 50B are formed on the surface of the N region NR. The upper diode element 4B has a P + region (anode) and an N + region (cathode).

[0062] Here, in the present embodiment, as shown in FIG. 9, the upper diode element 4B is formed using the back gate BG2 of the upper driver element 50B (P-channel type MOSFET). That is, the back gate BG2 is shared by the upper driver element 50B and the upper diode element 4B. This enables size reduction.

[0063] FIG. 11 is a plan view showing in more detail the protection element regions 24 and 25 in the standard I / O cell 2 (FIG. 5) according to the present embodiment.

[0064] The protection element region 24 for forming the lower diode element 4A shares the back gate BG1 in the NMOS region 210 as described above. FIG. 12 shows an enlarged view of the configuration in the protection element region 24, and as such, in the protection element region 24, the P active region (P + region) PA1 including the back gate BG1 is arranged such that a large number of units each configured to surround the N active region (N + region) NA1 are continuously arranged side by side in the second direction. Thereby, the area efficiency with respect to the current capability in the protection element region 24 can be improved.

[0065] The protection element region 25 for forming the upper diode element 4B shares the back gate BG2 in the PMOS region 22, as described above. Figure 13 shows an enlarged view of the configuration in the protection element region 25, and as shown, the protection element region 25 has an N active region (N) including the back gate BG2. + Region)NA2 is P active region (P + A large number of units surrounding region PA2 are arranged in a continuous line in the second direction. This improves the area efficiency with respect to current capacity in the protection element region 25.

[0066] <Other> Furthermore, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of this disclosure should be understood to include all modifications that fall within the meaning and scope equivalent to the claims, rather than being limited to the embodiments described above.

[0067] For example, if the current capacity allows, one of the lower diode element 4A and the upper diode element 4B may be omitted.

[0068] <Note> As described above, the interface circuit (3) according to one aspect of this disclosure is A first terminal (Tv) configured to receive a power supply voltage, A second terminal (To) is configured to receive an output signal, A third terminal (Tg) configured to have a ground potential applied, The upper driver element (50B) is configured as a P-channel type MOSFET with the first terminal connected to the source and the second terminal connected to the drain, The lower driver element (50A) is configured as an N-channel MOSFET with the third terminal connected to the source and the second terminal connected to the drain, Equipped with, The device comprises at least one of a lower diode element (4A) whose third terminal is connected to the anode and whose second terminal is connected to the cathode, and an upper diode element (4B) whose first terminal is connected to the cathode and whose second terminal is connected to the anode. In a plan view, the direction in which the gate of the lower driver element or the upper driver element extends is defined as the first direction. The configuration is such that at least one of a first protection element region (24) where the lower diode element is located and a second protection element region (25) where the upper diode element is located is located between the NMOS region (210) where the lower driver element is located and the PMOS region (22) where the upper driver element is located (first configuration).

[0069] With this configuration, the current capability during ESD protection in the NMOS region can be reinforced by the first protection element region, and the first protection element region can be constructed in a smaller area than if it were constructed using only N-channel MOSFETs. When a space is left between the NMOS region and the PMOS region in the first direction to suppress latch-up, the size of the I / O cell can be reduced by placing the first protection element region in this space. Furthermore, the current capability during ESD protection in the PMOS region can be reinforced by the second protection element region, and placing the second protection element region in the aforementioned space is advantageous for the size of the I / O cell.

[0070] Furthermore, in the first configuration described above, both the first protection element region and the second protection element region may be arranged between the NMOS region and the PMOS region in a first direction (second configuration).

[0071] Furthermore, in the first or second configuration described above, a power-to-ground protection element (35) can be connected between the first terminal and the third terminal outside the interface circuit. In the third configuration, when a positive surge voltage is applied to the second terminal, a surge current flows from the second terminal through at least the first parasitic diode of the upper diode element and the first parasitic diode of the upper driver element toward the third terminal, thereby providing ESD protection, and the breakdown of the second parasitic diode of the lower driver element is not utilized for the ESD protection.

[0072] Furthermore, in any of the first to third configurations described above, the lower diode element may be configured to share the first back gate (BG1) in the NMOS region (fourth configuration).

[0073] Furthermore, in any of the first to fourth configurations described above, the first protective element region may be configured such that multiple units, each consisting of a first P active region (PA1) surrounding a first N active region (NA1), are arranged in a plan view (fifth configuration).

[0074] Furthermore, in any of the first to fifth configurations described above, the upper diode element may be configured to share the second back gate (BG2) in the PMOS region (sixth configuration).

[0075] Furthermore, in any of the first to sixth configurations described above, the second protective element region may be configured such that multiple units, each consisting of a second N active region (NA2) surrounding a second P active region (PA2), are arranged in a plan view (seventh configuration).

[0076] Furthermore, a semiconductor device (1) according to one aspect of the present disclosure has an interface circuit comprising any of the first to seventh configurations described above (the eighth configuration). [Explanation of Symbols]

[0077] 1 Semiconductor device 2 Standard I / O Cells 3 Interface Circuit 4 ESD protection section 4A Lower Diode Element 4B Upper diode element 10 I / O circuit 20 standard I / O cells 21 NMOS area 22 PMOS area 23 Control Circuit Domain 24,25 Protection element area 30 Interface Circuits 35 Power supply / ground protection element 40 ESD protection section 40A Lower protective element 40B Upper protective element 50 Output Drivers 50A Lower Driver Element 50B Upper Driver Element 210 NMOS area BD1~BD4 Parasitic Diodes Ma protective element Mb protection element Mc protective element Ra protection dedicated element area Rb protection element selection region Tg Ground terminal To output terminal TV power terminal Tr1 Parasitic bipolar transistor

Claims

1. A first terminal configured to receive a power supply voltage, A second terminal configured to receive an output signal, A third terminal configured to have a ground potential applied, The upper driver element is configured as a P-channel MOSFET with the first terminal connected to the source and the second terminal connected to the drain, The lower driver element is configured as an N-channel MOSFET, with the third terminal connected to the source and the second terminal connected to the drain, Equipped with, The device comprises at least one of a lower diode element whose third terminal is connected to the anode and whose second terminal is connected to the cathode, and an upper diode element whose first terminal is connected to the cathode and whose second terminal is connected to the anode. In a plan view, the direction in which the gate of the lower driver element or the upper driver element extends is defined as the first direction. An interface circuit in which at least one of a first protection element region where the lower diode element is located and a second protection element region where the upper diode element is located is located, is located between the NMOS region where the lower driver element is located and the PMOS region where the upper driver element is located in a first direction.

2. The interface circuit according to claim 1, wherein both the first protection element region and the second protection element region are arranged between the NMOS region and the PMOS region in a first direction.

3. Outside the interface circuit, a power supply-to-ground protection element can be connected between the first terminal and the third terminal. The interface circuit according to claim 1, wherein when a positive surge voltage is applied to the second terminal with respect to the third terminal, a surge current flows from the second terminal through at least the first parasitic diode of the upper diode element and the first parasitic diode of the upper driver element toward the third terminal, thereby providing ESD protection, and the breakdown of the second parasitic diode of the lower driver element is not utilized for the ESD protection.

4. The interface circuit according to claim 1, wherein the lower diode element shares the first back gate in the NMOS region.

5. The interface circuit according to claim 1, wherein in the first protection element region, a plurality of units, each comprising a first P active region surrounding a first N active region, are arranged in a plan view.

6. The interface circuit according to claim 1, wherein the upper diode element shares the second back gate in the PMOS region.

7. The interface circuit according to claim 1, wherein, in the second protection element region, a plurality of units, each comprising a second N active region surrounding a second P active region, are arranged in a plan view.

8. A semiconductor device comprising the interface circuit described in any one of claims 1 to 7.

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