Power control devices, DC / DC converters, and vehicles

Abstract

The present invention provides a power control device that can effectively suppress output voltage overshoot during recovery from an abnormality through an effective configuration. [Solution] The power control device (2A) includes a clamp circuit (12) configured to clamp the amplifier output voltage (Vc) to a predetermined voltage, and the clamp circuit clamps the amplifier output voltage to a voltage higher than the ramp voltage (Ramp) with the ramp voltage (Ramp) as a reference.

Description

Technical Field

[0001] The present disclosure relates to a power supply control device.

Background Art

[0002] One type of DC / DC converter includes a high-side transistor and a low-side transistor connected in series to each other, and a rectifying and smoothing circuit having an inductor and an output capacitor connected to a connection node of the high-side transistor and the low-side transistor. An input voltage is applied between the high-side transistor and the low-side transistor. A rectangular wave voltage generated by alternately turning on and off the high-side transistor and the low-side transistor is rectified and smoothed by the rectifying and smoothing circuit, whereby an output voltage lower than the input voltage is obtained.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] In in-vehicle battery-driven devices, a cold crank phenomenon in which the internal impedance of a lead battery decreases and the battery voltage drops significantly in cold regions and the like is a generally known event. There is a demand in the market for suppressing output overshoot of a DC / DC converter directly connected to an in-vehicle battery at the time of recovery from the cold crank phenomenon.

[0005] A power supply control device according to one aspect of the present invention is a high-side transistor having a first terminal connected to an application terminal of an input voltage, a low-side transistor having a first terminal connected to a second terminal of the high-side transistor at a first node, an inductor connected to the first node, A power supply control device for use in a DC / DC converter comprising: An error amplifier configured to receive a feedback voltage based on the output voltage of the DC / DC converter and a reference voltage as inputs, A comparator configured to receive a voltage based on the amplifier output voltage output from the error amplifier and a ramp voltage as inputs, A clamping circuit configured to clamp the amplifier output voltage to a predetermined voltage, A reset signal output from the comparator and a switching control unit configured to switch the high-side transistor and the low-side transistor by PWM based on the set signal, Equipped with, The clamp circuit is configured to clamp the amplifier output voltage to a voltage higher than the lamp voltage, using the lamp voltage as a reference. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is an overall configuration diagram of a DC / DC converter according to an embodiment of this disclosure. [Figure 2] Figure 2 is a perspective view of the power supply IC. [Figure 3] Figure 3 shows the configuration of a DC / DC converter with a power supply IC. [Figure 4] Figure 4 is a schematic diagram showing various signal waveforms related to the generation of switching voltage. [Figure 5] Figure 5 is a schematic waveform diagram showing an example of DC / DC converter operation when a clamping circuit is not provided. [Figure 6] Figure 6 shows the configuration of a clamp circuit in a comparative example. [Figure 7] Figure 7 is a schematic waveform diagram showing an example of operation when using the clamp circuit configured as shown in Figure 6. [Figure 8] Figure 8 shows the configuration of the clamp circuit according to the first embodiment. [Figure 9] Figure 9 is a waveform diagram showing the clamping of the amplifier output voltage. [Figure 10]FIG. 10 is a schematic waveform diagram showing an operation example of the power supply IC according to the first embodiment. [Figure 11] FIG. 11 is a flowchart relating to the frequency division operation function. [Figure 12] FIG. 12 is a diagram showing a configuration of a clamp circuit in the power supply IC according to the second embodiment. [Figure 13] FIG. 13 is a schematic waveform diagram showing an operation example of the power supply IC according to the second embodiment. [Figure 14] FIG. 14 is a diagram schematically showing signal waveforms when the frequency division operation is in an on state. [Figure 15] FIG. 15 is an external view showing an example of a vehicle.

[0007] [Detailed Description] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0008] <Configuration of DC / DC Converter> FIG. 1 is an overall configuration diagram of a DC / DC converter 1 according to an embodiment of the present disclosure. The DC / DC converter 1 in FIG. 1 includes a power supply IC 2 serving as a power supply control device, and a plurality of discrete components externally connected to the power supply IC 2. The plurality of discrete components include a capacitor C1 as an output capacitor, a capacitor C2 as a bootstrap capacitor, resistors R1 and R2 as feedback resistors, and an inductor L1. The DC / DC converter 1 is configured as a step-down DC / DC converter that generates a desired output voltage Vout from an input voltage Vin supplied from the outside. The output voltage Vout is generated at the output terminal OUT. That is, the output terminal OUT is a terminal to which the output voltage Vout is applied (a terminal to which the output voltage VoutT is applied). The output voltage Vout is supplied to a load LD connected to the output terminal OUT.

[0009] The input voltage Vin and the output voltage Vout are positive DC voltages, and the output voltage Vout is lower than the input voltage Vin. For example, when the input voltage Vin is 12V, the output voltage Vout can be stabilized at a desired target voltage lower than 12V (e.g., 5V) by adjusting the resistance values of resistors R1 and R2.

[0010] FIG. 2 shows an external perspective view of the power supply IC 2 (power supply control device). The power supply IC 2 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that accommodates the semiconductor chip, and a plurality of external terminals exposed from the housing to the outside of the power supply IC 2. The power supply IC 2 is formed by encapsulating the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the power supply IC 2 and the type of housing of the power supply IC 2 shown in FIG. 2 are merely examples, and they can be designed arbitrarily. The output stage circuit MM, the main control block 3, and the rectifying element D1 shown in FIG. 1 are included in the semiconductor integrated circuit. The output stage circuit MM may be provided outside the power supply IC 2.

[0011] In FIG. 1, only the input terminal IN, the switch terminal SW, the feedback terminal FB, the output monitoring terminal OS, the boot terminal BOOT, and the ground terminal GND are shown as part of the plurality of external terminals provided in the power supply IC 2 (the same applies to FIG. 3 and the like described later), but other external terminals (e.g., an enable terminal and a power good terminal) may also be provided in the power supply IC 2.

[0012] The external configuration of the power supply IC 2 will be described. An input voltage Vin is supplied to the input terminal IN from the outside of the power supply IC 2. An inductor L1 is interposed in series between the switch terminal SW and the output terminal OUT. That is, one end of the inductor L1 is connected to the switch terminal SW, and the other end of the inductor L1 is connected to the output terminal OUT. Further, the output terminal OUT is connected to the ground via a capacitor C1. That is, one end of the capacitor C1 is connected to the output terminal OUT, and the other end of the capacitor C1 is connected to the ground. Furthermore, the output terminal OUT is connected to one end of a resistor R1, and the other end of the resistor R1 is connected to the ground via a resistor R2. A connection node between the resistor R1 and the resistor R2 is connected to the feedback terminal FB. The ground terminal GND is connected to the ground. A capacitor C2 is provided between the terminal BOOT and the terminal SW. That is, one end of the capacitor C2 is connected to the boot terminal BOOT, and the other end of the capacitor C2 is connected to the switch terminal SW. Note that the current flowing through the inductor L1 is referred to as an inductor current IL.

[0013] The internal configuration of the power supply IC 2 will be described. The power supply IC 2 includes an output stage circuit MM, a main control block 3 for controlling the output stage circuit MM, and a rectifying element D1.

[0014] The output stage circuit MM includes a high-side transistor M1 and a low-side transistor M2. Here, it is assumed that the transistors M1 and M2 are each an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The transistors M1 and M2 are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (in other words, the ground), and by being switching-driven, the input voltage Vin is switched so that a rectangular-wave switching voltage Vsw appears at the switch terminal SW. Specifically, the drain of the transistor M1 is connected to the input terminal IN to which the input voltage Vin is applied, and the source of the transistor M1 and the drain of the transistor M2 are commonly connected to the switch terminal SW. The source of the transistor M2 is connected to the ground terminal GND.

[0015] The high-side transistor M1 functions as an output transistor, and the low-side transistor M2 functions as a synchronous rectifier transistor. The inductor L1 and capacitor C1 form a rectifier-smoothing circuit that rectifies and smooths the rectangular waveform switching voltage Vsw appearing at the switch terminal SW to generate the output voltage Vout. Resistors R1 and R2 form a voltage divider circuit that divides the output voltage Vout, and a feedback voltage Vfb, which is the divided voltage of the output voltage Vout, is generated at the connection node between resistors R1 and R2. The connection node between resistors R1 and R2 is connected to the feedback terminal FB, so the feedback voltage Vfb is input to the feedback terminal FB.

[0016] The gates of transistors M1 and M2 are supplied with gate signals G1 and G2, respectively. Transistors M1 and M2 are turned on and off according to the gate signals G1 and G2. When gate signal G1 is high, high-side transistor M1 is on, and when gate signal G1 is low, high-side transistor M1 is off. Similarly, when gate signal G2 is high, low-side transistor M2 is on, and when gate signal G2 is low, low-side transistor M2 is off. Basically, transistors M1 and M2 are switched on complementaryly. However, a simultaneous off period (dead time) in which both transistors M1 and M2 are off may be provided.

[0017] The main control block 3 is connected to the gates of transistors M1 and M2, the switch terminal SW, and the feedback terminal FB. Based on the feedback voltage Vfb, the main control block 3 controls the on / off state of transistors M1 and M2 through level control of gate signals G1 and G2, thereby generating an output voltage Vout at the output terminal OUT that corresponds to the feedback voltage Vfb.

[0018] The power supply IC2 is provided with an internal power supply circuit (not shown) that generates an internal power supply voltage Vreg based on the input voltage Vin. The internal power supply voltage Vreg has a predetermined positive DC voltage value. In the example in Figure 1, the rectifier element D1 is a diode. In this case, the anode of the diode as the rectifier element D1 is connected to the application terminal of the internal power supply voltage Vreg, and the cathode is connected to the boot terminal BOOT. The rectifier element D1 may also be a switching element that is turned on during the ON period of transistor M2. The rectifier element D1 and capacitor C2 form a bootstrap circuit. The voltage applied to the boot terminal BOOT is called the boot voltage Vboot. The main control block 3 can be driven based on the internal power supply voltage Vreg or the boot voltage Vboot.

[0019] When the output stage circuit MM is in the output low state (high-side transistor M1 is off, low-side transistor M2 is on), the capacitor C2 is charged through the rectifier element D1 based on the internal power supply voltage Vreg, causing the boot voltage Vboot to be higher than the switching voltage Vsw by the voltage across capacitor C2. Subsequently, even when the output stage circuit MM is set to the output high state (high-side transistor M1 is on, low-side transistor M2 is off), the boot voltage Vboot remains higher than the switching voltage Vsw by the voltage across capacitor C2.

[0020] The gate signal G1 is a signal referenced to the potential of the switch terminal SW. Specifically, a low-level gate signal G1 has the potential of the switch terminal SW, and a high-level gate signal G1 is higher than the potential of the switch terminal SW by the difference between the voltages Vboot and Vsw. The main control block 3 can generate a high-level gate signal G1 based on the boot voltage Vboot. On the other hand, the gate signal G2 is a signal referenced to the ground potential. Specifically, a low-level gate signal G2 has the ground potential, and a high-level gate signal G2 is higher than the ground potential by a predetermined voltage (e.g., the internal power supply voltage Vreg).

[0021] Figure 3 shows the configuration of DC / DC converter 1 with power supply IC2A. Power supply IC2A is an example of power supply IC2. All of the above-mentioned points regarding power supply IC2 apply to power supply IC2A, unless otherwise contradictory.

[0022] The main control block 3 in power supply IC2A comprises an error amplifier 11, a clamp circuit 12, a clock generation circuit 13, a ramp voltage generation circuit 14, a comparator 15, a logic circuit 16, and a driver 17. Power supply IC2A performs switching operation using PWM (pulse width modulation). The function and operation of each part are described below.

[0023] The error amplifier 11 is a current-output type transconductance amplifier. The error amplifier 11 has an inverting input terminal (-), a non-inverting input terminal (+), and an output terminal. The output terminal of the error amplifier 11 is connected to wiring WR1. The inverting input terminal of the error amplifier 11 is connected to the feedback terminal FB and receives a feedback voltage Vfb. A predetermined reference voltage Ref is supplied to the non-inverting input terminal of the error amplifier 11. The reference voltage Ref is a DC voltage with a predetermined positive voltage value and is generated by a reference voltage generation circuit (not shown) in the power supply IC 2A.

[0024] The error amplifier 11 outputs a current signal I1 from its output terminal corresponding to the difference between the feedback voltage Vfb and the reference voltage Ref, thereby generating an amplifier output voltage Vc in the wiring WR1 corresponding to the difference between the feedback voltage Vfb and the reference voltage Ref. The charge due to the current signal I1 is input and output to the wiring WR1. Specifically, when the reference voltage Ref is higher than the feedback voltage Vfb, the error amplifier 11 outputs a current due to the current signal I1 to the wiring WR1 so that the potential of the wiring WR1 rises, and when the reference voltage Ref is lower than the feedback voltage Vfb, the error amplifier 11 draws a current due to the current signal I1 from the wiring WR1 to the error amplifier 11 so that the potential of the wiring WR1 falls. As the absolute value of the difference between the feedback voltage Vfb and the reference voltage Ref increases, the magnitude of the current due to the current signal I1 also increases.

[0025] Furthermore, a phase compensation circuit (not shown in Figure 3) is provided between the wiring WR1 and ground, and compensates for the phase of the amplifier output voltage Comp upon input of the current signal I1. This phase compensation circuit includes a series circuit of a resistor and a capacitor. Specifically, one end of the resistor is connected to the wiring WR1, and the other end of the resistor is connected to one end of the capacitor. The other end of the capacitor is connected to ground. By appropriately setting the resistance value of the resistor and the capacitance value of the capacitor, the phase of the amplifier output voltage Vc can be compensated to prevent oscillation of the output feedback loop.

[0026] The clock generation circuit 13 generates and outputs a set signal Set as a clock signal. The set signal Set is a square wave signal having a predetermined switching frequency fsw, and alternates between low and high signal levels. The set signal Set is output from the clock generation circuit 13 to the ramp voltage generation circuit 14 and the logic circuit 16.

[0027] The ramp voltage generation circuit 14 generates the ramp voltage Ramp. The ramp voltage Ramp has a sawtooth-shaped voltage waveform, as an example, as described later. The ramp voltage may also have a triangular waveform, etc. The ramp voltage Ramp depends on the set signal Set.

[0028] The amplifier output voltage Vc is applied to the inverting input terminal of comparator 15. The ramp voltage Ramp is applied to the non-inverting input terminal of comparator 15. Comparator 15 compares the amplifier output voltage Vc and the ramp voltage Ramp and outputs a reset signal Rst. The reset signal Rst is supplied to logic circuit 16.

[0029] The logic circuit 16 controls gate signals G1 and G2 by controlling the driver 17 based on the set signal Set and the reset signal Rst. The driver 17, under the control of the logic circuit 16, supplies gate signals G1 and G2 based on the signals Set and Rst to transistors M1 and M2, thereby causing the output stage circuit MM to perform a switching operation. In the switching operation, transistors M1 and M2 are alternately turned on and off based on the signals Set and Rst. The error amplifier 11 generates a current signal I1 such that the feedback voltage Vfb and the reference voltage Ref are equal, and through the execution of the switching operation, the output voltage Vout is stabilized at a predetermined target voltage corresponding to the reference voltage Ref and the voltage division ratio by resistors R1 and R2.

[0030] <Generating switching voltage> Figure 4 is a schematic diagram showing various signal waveforms related to the generation of the switching voltage Vsw. In Figure 4, the waveforms of the ramp voltage Ramp, amplifier output voltage Vc, reset signal Rst, set signal Set, and switching voltage Vsw are shown in order from top to bottom.

[0031] At the moment the set signal Set rises to a high level and then falls, the switching voltage Vsw rises, and the ramp voltage Ramp also rises. The ramp voltage Ramp rises and then begins to rise in a sloping manner. Then, when the ramp voltage Ramp exceeds the amplifier output voltage Vc, the reset signal Rst rises. This causes the switching voltage Vsw to fall. The ramp voltage Ramp falls after a predetermined time has elapsed since its rise, and at this time the reset signal Rst also falls. Subsequently, the falling edge of the set signal Set causes the switching voltage Vsw to rise again. The switching voltage Vsw is generated by repeating this operation. When the high-side transistor M1 is ON and the low-side transistor M2 is OFF, the switching voltage Vsw is at a high level, and when the high-side transistor M1 is OFF and the low-side transistor M2 is ON, the switching voltage Vsw is at a low level. By adjusting the duty cycle of the switching voltage Vsw, PWM control of the output voltage Vout is performed. The duty cycle is the ratio of the on-period Ton, during which the switching voltage Vsw is high, to the switching period Tsw (period of the set signal Set). The relationship between the input voltage Vin and the output voltage Vout is expressed by the following equation. Vout = Duty × Vin (1)

[0032] <Challenges of clamp circuits> Next, the clamp circuit 12 will be described. Here, Figure 5 is a schematic waveform diagram showing an example of the operation of the DC / DC converter 1 when the clamp circuit is not provided. In Figure 5, the waveforms of the input voltage Vin, output voltage Vout, amplifier output voltage Vc, and ramp voltage Ramp are shown in order from top to bottom. The same applies to Figures 7, 10, and 13 which will be described later.

[0033] Figure 5 shows an example of operation when the input voltage Vin decreases. As shown in Figure 5, the ramp voltage circuit 14 generates the ramp voltage Ramp such that the slope of the ramp voltage Ramp becomes gentler as the input voltage Vin decreases. This is because, when the input voltage Vin decreases, the duty cycle of the switching voltage Vsw increases if the output voltage Vout remains constant according to equation (1) above, but by making the slope of the ramp voltage Ramp gentler, the amplifier output voltage Vc can be kept as constant as possible.

[0034] As the input voltage Vin decreases, the duty cycle increases, and at some point, the duty cycle reaches its maximum duty cycle. In logic circuit 16, when the duty cycle exceeds a predetermined maximum duty cycle, the duty cycle is limited to the maximum duty cycle. Because it is limited by the maximum duty cycle, if the input voltage Vin continues to decrease, the output voltage Vout will fall below the target value OUT_Ref. Then, the amplifier output voltage Vc rises to a voltage considerably higher than the ramp voltage Ramp (the maximum value of the amplifier output voltage Vc). If the ramp voltage Ramp cannot reach the amplifier output voltage Vc, the duty cycle is controlled as the maximum duty cycle.

[0035] Subsequently, when the input voltage Vin recovers and rises, the output voltage Vout also rises, and when the output voltage Vout exceeds the target value OUT_Ref, the amplifier output voltage Vc drops to a steady state. However, there was a problem where an overshoot OS (overshoot) of the output voltage Vout occurred because there was a delay in the amplifier output voltage Vc dropping to a steady state.

[0036] Therefore, a clamp circuit 12 is provided in the power supply IC 2A. Figure 6 shows the configuration of the clamp circuit 12 according to the comparative example. The clamp circuit 12 shown in Figure 6 has a PMOS transistor PM and resistors R3 and R4. The PMOS transistor PM is a P-channel type MOSFET. The source of the PMOS transistor PM is connected to the output terminal of the error amplifier 11. The drain of the PMOS transistor PM is connected to ground. Resistors R3 and R4 are connected in series between the power supply voltage VREF and ground. The node between resistors R3 and R4 is connected to the gate of the PMOS transistor PM.

[0037] With this clamp circuit 12 configuration, the amplifier output voltage Vc is clamped to A + Vth or less, where A is the voltage obtained by dividing the power supply voltage VREF by resistors R3 and R4, and Vth is the threshold voltage of the PMOS transistor PM. Note that the clamp circuit is not limited to a P-channel MOSFET, but may also be constructed using an N-channel MOSFET or a bipolar transistor, etc.

[0038] Figure 7 is a schematic waveform diagram showing an example of operation when using the clamp circuit 12 configured as shown in Figure 6. Figure 7 shows an example of operation when the input voltage Vin decreases. Even when the input voltage Vin decreases and the output voltage Vout falls below the target value OUT_Ref, the amplifier output voltage Vc is clamped to the clamp voltage Vclp (=A+Vth). As a result, when the input voltage Vin recovers and rises, the amplifier output voltage Vc can quickly return to a steady value, and the overshoot OS of the output voltage Vout can be suppressed.

[0039] However, in the configuration of the clamp circuit 12 in the comparative example described above, clamping is performed independently of the lamp voltage Ramp. Therefore, if there is variation in the lamp voltage Ramp, it is not possible to set the clamp voltage Vclp close to the lamp voltage Ramp, and the clamp voltage Vclp had to be set higher than the peak voltage of the lamp voltage Ramp with a margin of safety.

[0040] <First Embodiment> In view of the above issues, the power supply IC2A according to this embodiment implements the clamp circuit 12 configuration described below. Figure 8 is a diagram showing the configuration of the clamp circuit 12 according to the first embodiment.

[0041] The clamp circuit 12 shown in Figure 8 includes an amplifier 12A, an NMOS transistor 12B, and a resistor 12C. A ramp voltage Ramp is applied to the inverting input terminal of amplifier 12A. A resistor 12C is connected between the non-inverting input terminal of amplifier 12A and the output terminal of error amplifier 11. The NMOS transistor 12B is an N-channel MOSFET. The drain of the NMOS transistor 12B is connected to the non-inverting input terminal of amplifier 12A. The source of the NMOS transistor 12B is connected to ground. The gate of the NMOS transistor 12B is connected to the output terminal of amplifier 12A.

[0042] In this configuration, the clamp circuit 12 attempts to lower the amplifier output voltage Vc by drawing (sinking) the current Iamp from the line where the amplifier output voltage Vc is generated when the amplifier output voltage Vc is higher than the ramp voltage Ramp. Conversely, the clamp circuit 12 does not operate when the amplifier output voltage Vc is lower than the ramp voltage Ramp. When the clamp circuit 12 is operating, the amplifier output voltage Vc is clamped to a voltage ΔVclp higher than the ramp voltage Ramp, as shown in the schematic waveform in Figure 9. Here, ΔVclp is expressed by the following formula. ΔVclp = ofs + Iamp × R However, ofs is the input offset of amplifier 12A, and R is the resistance value of resistor 12C.

[0043] Even if the input offset ofs varies and its sign becomes negative, resistor 12C can make ΔVclp a positive value. Since ΔVclp can be set to a small value, the amplifier output voltage Vc can be clamped to a value slightly higher than the ramp voltage Ramp. Because the clamping is dependent on the ramp voltage Ramp, variations in the ramp voltage Ramp due to the manufacturing process and the influence of the ramp voltage Ramp's temperature characteristics can be reflected in the clamping.

[0044] Furthermore, if the size ratio of the input transistor pair in the differential input section of amplifier 12A is set to, for example, 2:1, and an input offset is intentionally introduced, then the sign can always be positive even if the input offset ofs varies, and resistor 12C can be omitted.

[0045] An example of the operation of the power supply IC2A according to this first embodiment will be explained using the schematic waveform diagram shown in Figure 10. In Figure 10, the ramp voltage Ramp is shown as a solid line waveform, and the amplifier output voltage Vc is shown as a dashed line waveform.

[0046] When the input voltage Vin is decreasing, the clamp circuit 12 clamps the amplifier output voltage Vc to a voltage slightly higher than the ramp voltage Ramp while the ramp voltage Ramp rises and increases in a sloping manner. When the amplifier output voltage Vc is at a steady state, the ramp voltage Ramp exceeds the amplifier output voltage Vc. This causes the reset signal Rst to rise and adjusts the duty cycle of the switching voltage Vsw. At this time, the clamp circuit 12 does not operate.

[0047] As the input voltage Vin decreases, the duty cycle increases, and when the duty cycle is limited by the maximum duty cycle, the output voltage Vout falls below the target value OUT_Ref. This causes the amplifier output voltage Vc to try to increase, but the clamp circuit 12 clamps the amplifier output voltage Vc to a voltage slightly higher than the ramp voltage Ramp. At this point, the clamping occurs across the entire slope of the ramp voltage Ramp, and the duty cycle is limited to the maximum duty cycle.

[0048] Subsequently, when the input voltage Vin recovers and rises, and the output voltage Vout also rises and exceeds the target value OUT_Ref, the ramp voltage Ramp exceeds the amplifier output voltage Vc, and the duty cycle is adjusted.

[0049] In this way, the amplifier output voltage Vc is clamped to a value close to the ramp voltage Ramp, which can further suppress the overshoot OS that occurs in the output voltage Vout when the input voltage Vin returns to normal.

[0050] <Second Embodiment> Next, the frequency division function provided in the power supply IC2A according to the second embodiment will be described. The frequency division operation is performed in order to regulate the output voltage Vout even when a decrease (power reduction) occurs in the input voltage Vin.

[0051] As the input voltage Vin decreases, the duty cycle of the switching voltage Vsw increases, and the off period Toff (the period when the switching voltage Vsw is at a low level), as shown in Figure 4, becomes shorter. Here, since it is necessary to ensure that the low-side transistor M2 is in the ON state for bootstrapping, the minimum off period Toffmin is set, which is the minimum off period Toff.

[0052] Here, the frequency division operation will be explained with reference to the flowchart in Figure 11. First, if the logic circuit 16 determines in step S1 that the off period Toff is greater than or equal to the minimum off period Toffmin (Y in step S1), the process proceeds to step S2, where the low-side transistor M2 is switched to the ON state (the high-side transistor M1 is switched to the OFF state). In this case, it can be determined that the remaining off period Toff in the switching period Tsw is greater than or equal to the minimum off period Toffmin at the timing when the reset signal Rst is asserted.

[0053] On the other hand, if it is determined in step S1 that the off period Toff is shorter than the minimum off period Toffmin (N in step S1), the process proceeds to step S3. In this case, either the remaining off period Toff in the switching period Tsw is shorter than the minimum off period Toffmin at the time the reset signal Rst is asserted, or the amplifier output voltage Vc is not reached before the ramp voltage Ramp falls, resulting in an off period Toff = 0 in the switching period Tsw.

[0054] If the process proceeds to step S3, the high-side transistor M1 remains on without being turned off (the low-side transistor M2 remains off). In step S3, a frequency divider counter (not shown) starts counting. The frequency divider counter counts the number of switching cycles. In step S3, the frequency divider operation switches to the ON state.

[0055] Then, if the ramp voltage Ramp reaches the amplifier output voltage Vc in step S4 (Y in step S4), proceed to step S5, where the low-side transistor M2 is switched on (high-side transistor M1 is switched off). At this point, the frequency divider operation is switched off. After step S5, return to step S1.

[0056] On the other hand, if the ramp voltage Ramp does not reach the amplifier output voltage Vc in step S4 (N in step S4), the process proceeds to step S6. If the count value of the frequency divider counter does not reach a predetermined value (e.g., 16) in step S6 (N in step S6), the process returns to step S4. On the other hand, if the count value reaches the predetermined value while the ramp voltage Ramp does not reach the amplifier output voltage Vc (Y in step S6), the process proceeds to step S7, where the low-side transistor M2 is turned on for the minimum off period Toffmin (the high-side transistor M1 is turned off). After step S7, the process returns to step S1, and depending on the determination made in step S1, the frequency divider operation either remains on or switches to the off state.

[0057] As a result, when the input voltage Vin decreases and the off period Toff becomes shorter than the minimum off period Toffmin, frequency division operation is initiated, and the turn-on of the low-side transistor M2 in the switching cycle is skipped for at least one switching cycle. The skip occurs for a maximum of 1 fewer switching cycles than the predetermined value (for example, 15 times if the predetermined value = 16). If the skip occurs for the maximum number of switching cycles, the minimum off period Toffmin is ensured in the last switching cycle after the skip. Therefore, frequency division operation increases the maximum duty cycle by lowering the switching frequency and regulates the output voltage Vout.

[0058] Figure 12 shows the configuration of the clamp circuit 12 in the power supply IC 2A according to the second embodiment. The difference between the configuration shown in Figure 12 and the first embodiment is that the operation and stopping of the amplifier 12A are switched according to the control signal Ctr from the logic circuit 13. Specifically, when the frequency division operation is in the off state, the operation of the amplifier 12A is stopped by the control signal Ctr, and when the frequency division operation is in the on state, the operation of the amplifier 12A is enabled by the control signal Ctr.

[0059] An example of the operation of the power supply IC2A according to this second embodiment will be explained using the schematic waveform diagram shown in Figure 13. In Figure 13, the ramp voltage Ramp is shown as a solid line waveform, and the amplifier output voltage Vc is shown as a dashed line waveform.

[0060] When the input voltage Vin decreases, and the input voltage Vin is in a state where it can output the set output voltage Vout at a constant switching frequency, the frequency divider operation is off, and the amplifier 12A in the clamp circuit 12 is not operating. At this time, the amplifier output voltage Vc is at a steady value, and the duty cycle of the switching voltage Vsw is adjusted by the ramp voltage Ramp and the amplifier output voltage Vc. As the input voltage Vin decreases, the duty cycle increases, and when the off period Toff becomes shorter than the minimum off period Toffmin, the frequency divider operation switches to the on state. As a result, the operation of amplifier 12A, i.e., the clamp circuit 12, becomes active. Then, the amplifier output voltage Vc is clamped by the clamp circuit 12 to a voltage slightly higher than the ramp voltage Ramp.

[0061] Figure 14 schematically shows the waveform when the frequency divider operation is ON. In Figure 14, the waveforms of the amplifier output voltage Vc, ramp voltage Ramp, reset signal Rst, set signal Set, and switching voltage Vsw are shown in order from top to bottom. At the falling edge of the set signal Set (timing ta), the logic circuit 16 starts monitoring the reset signal Rst, but since the amplifier output voltage Vc is clamped to a voltage slightly higher than the ramp voltage Ramp over the entire slope of the ramp voltage Ramp, the ramp voltage Ramp never exceeds the amplifier output voltage Vc, and the reset signal Rst is not asserted. As a result, the logic circuit 16 maintains the ON state of the high-side transistor M1 (the OFF state of the low-side transistor M2) and maintains a high level of the switching voltage Vsw (timing tb). The high level of the switching voltage Vsw is maintained until the falling edge of the set signal Set (timing tc). In other words, the turn-on of the low-side transistor M2 is skipped.

[0062] Returning to the explanation in Figure 13, with the frequency divider operation on, the output voltage Vout falls below the target value OUT_Ref, and the amplifier output voltage Vc remains clamped. Subsequently, when the input voltage Vin recovers and rises, the output voltage Vout rises and exceeds the target value OUT_Ref. Then, the ramp voltage Ramp exceeds the amplifier output voltage Vc, and the frequency divider operation switches to the off state. As a result, the operation of amplifier 12A, i.e., clamp circuit 12, is stopped. From this point onward, the amplifier output voltage Vc is not clamped, and the duty cycle of the switching voltage Vsw is adjusted by the amplifier output voltage Vc and the ramp voltage Ramp.

[0063] Thus, when the frequency divider is on, the amplifier output voltage Vc is clamped to a voltage slightly higher than the ramp voltage Ramp, which suppresses the frequency divider from switching to the off state. At this time, the effects of fluctuations (variations, etc.) in the ramp voltage Ramp can be reflected in the clamp. In addition, because the amplifier output voltage Vc is clamped near the ramp voltage Ramp, when the frequency divider switches to the off state during the recovery of the input voltage Vin, the overshoot of the output voltage Vout can be suppressed.

[0064] Even if the power supply IC has a frequency division function, the clamp circuit 12 may always be enabled regardless of whether the frequency division function is on or off.

[0065] <Application to vehicles> Figure 15 is an external view of vehicle X. In this configuration example, vehicle X is equipped with a DC / DC converter 1 that includes a power supply IC 2A supplied with the battery voltage output from battery B1 as the input voltage Vin. As shown in Figure 15, various electronic devices X11 to X18 are mounted on vehicle X. At least one of the electronic devices X11 to X18 operates based on the output voltage Vout output from the DC / DC converter 1. The mounting positions of the electronic devices X11 to X18 in Figure 15 may differ from the actual positions for illustrative purposes.

[0066] Electronic device X11 is an engine control unit that performs engine-related controls (such as injection control, electronic throttle control, idle control, oxygen sensor heater control, and auto cruise control).

[0067] Electronic device X12 is a lamp control unit that controls the on / off state of lights such as HID (high-intensity discharged lamps) and DRL (daytime running lamps).

[0068] Electronic device X13 is a transmission control unit that performs control related to the transmission.

[0069] The electronic device X14 is a braking unit that performs control related to the motion of the vehicle X (such as ABS [anti-lock brake system] control, EPS [electric power steering] control, and electronic suspension control).

[0070] Electronic device X15 is a security control unit that controls the operation of door locks, burglary alarms, and other devices.

[0071] Electronic equipment X16 consists of electronic components that are installed in vehicle X at the factory as standard equipment or manufacturer options, including wipers, power door mirrors, power windows, dampers (shock absorbers), power sunroof, and power seats.

[0072] Electronic equipment X17 is an electronic device that can be optionally installed in vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0073] Electronic equipment X18 is a type of electronic equipment equipped with high-voltage motors, such as automotive blowers, oil pumps, water pumps, and battery cooling fans.

[0074] By installing power supply IC2A in vehicle X in this way, even if a cold crank phenomenon occurs where the battery voltage drops, the overshoot of the output voltage Vout can be suppressed by clamping the amplifier output voltage Vc when the battery voltage recovers.

[0075] <Other> The various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. That is, the embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of the present invention should be understood to be not limited to the embodiments described above, but to include all modifications that fall within the meaning and scope equivalent to the claims.

[0076] For example, the power supply IC according to this disclosure can suppress overshoot of the output voltage Vout not only when the input voltage Vin decreases, but also when the DC / DC converter's output (Vout) recovers from a ground fault.

[0077] <Note> As described above, the power control device (2A) according to one aspect of this disclosure is A high-side transistor (M1) whose first terminal is connected to the input voltage (Vin) application terminal, A low-side transistor (M2) whose first end is connected at the first node to the second end of the high-side transistor, The inductor (L1) connected to the first node, A power control device used in a DC / DC converter (1) equipped with, An error amplifier (11) is configured to receive a feedback voltage (Vfb) based on the output voltage (Vout) of the DC / DC converter and a reference voltage (Ref), A comparator (15) is configured to receive a voltage based on the amplifier output voltage (Vc) output from the error amplifier and a ramp voltage (Ramp) as inputs. A clamp circuit (12) configured to clamp the amplifier output voltage to a predetermined voltage, A switching control unit (16) is configured to switch the high-side transistor and the low-side transistor by PWM based on a reset signal (Rst) output from the comparator and a set signal (Set), Equipped with, The clamp circuit is configured to clamp the amplifier output voltage to a voltage higher than the lamp voltage, using the lamp voltage as a reference (first configuration).

[0078] With this configuration, the effects of fluctuations (variations, etc.) in the ramp voltage can be reflected in the clamping of the amplifier output voltage. Furthermore, the amplifier output voltage can be clamped near the ramp voltage, which can suppress output voltage overshoot when recovering from abnormalities such as a drop in input voltage.

[0079] Furthermore, in the first configuration described above, if the amplifier output voltage is higher than the lamp voltage, the clamp circuit may attempt to lower the amplifier output voltage by drawing current from the line where the amplifier output voltage is generated, and if the amplifier output voltage is lower than the lamp voltage, the clamp circuit may not operate (second configuration).

[0080] Furthermore, in the first or second configuration described above, the clamp circuit is A resistor (12C) whose first end is connected to the output terminal of the error amplifier, An amplifier (12A) in which the non-inverting input terminal is connected to the second terminal of the resistor and the inverting input terminal is connected to the terminal to which the ramp voltage is applied, The configuration may also include an NMOS transistor (12B) whose drain is connected to the non-inverting input terminal, whose source is connected to ground, and whose gate is connected to the output terminal of the amplifier (third configuration).

[0081] Furthermore, in the first or second configuration described above, the clamp circuit is An amplifier in which the non-inverting input terminal is connected to the output terminal of the error amplifier and the inverting input terminal is connected to the terminal to which the ramp voltage is applied, The configuration may also include an NMOS transistor whose drain is connected to the non-inverting input terminal, whose source is connected to ground, and whose gate is connected to the output terminal of the amplifier (fourth configuration).

[0082] Furthermore, in the fourth configuration described above, the input offset of the amplifier may be set by the size ratio of the input transistor pair in the differential input section included in the amplifier (fifth configuration).

[0083] Furthermore, in any of the above configurations 1 to 5, the power control device has a frequency division function in which the switching control unit performs a skip operation to maintain the ON state of the high-side transistor by skipping the turn-on of the low-side transistor at least once during the switching cycle. If the ramp voltage does not reach the amplifier output voltage during the switching cycle, the ON state of the frequency divider operation is maintained. The clamp circuit may be configured to be enabled or disabled depending on the ON / OFF state of the frequency division operation (sixth configuration).

[0084] Furthermore, a DC / DC converter (1) according to one aspect of the present disclosure comprises a power control device (2A) with any of the first to sixth configurations described above, the high-side transistor, the low-side transistor, and the inductor (seventh configuration).

[0085] Furthermore, a vehicle (X) according to one aspect of the present disclosure comprises a DC / DC converter (1) as described in the seventh configuration above, and a battery (B1) configured to output the battery voltage as the input voltage (eighth configuration). [Industrial applicability]

[0086] This disclosure can be used, for example, in DC / DC converters for various applications. [Explanation of Symbols]

[0087] 1 DC / DC converter 2,2A power IC 3. Main control block 11 Error Amplifier 12. Clamp Circuit 12A Amplifier 12B NMOS transistor 12C resistance 13. Clock generation circuit 14. Lamp voltage generation circuit 15 Comparator 16 Logic Circuits 17 Drivers B1 Battery C1 output capacitor D1 Rectifier element L1 Inductor LD load M1 High-Side Transistor M2 Low-Side Transistor MM output stage circuit PM PMOS transistor R1,R2 resistance R3,R4 resistance WR1 Wiring X Vehicle X11~X18 Electronic equipment

Claims

1. A high-side transistor whose first terminal is connected to the terminal to which the input voltage is applied, A low-side transistor, the first end of which is connected at the first node to the second end of the high-side transistor, An inductor connected to the first node, A power control device used in a DC / DC converter equipped with, An error amplifier configured to receive a feedback voltage based on the output voltage of the DC / DC converter and a reference voltage as inputs, A comparator configured to receive a voltage based on the amplifier output voltage output from the error amplifier and a ramp voltage as inputs, A clamping circuit configured to clamp the amplifier output voltage to a predetermined voltage, A reset signal output from the comparator and a switching control unit configured to switch the high-side transistor and the low-side transistor by PWM based on the set signal, Equipped with, The clamp circuit is a power control device that clamps the amplifier output voltage to a voltage higher than the lamp voltage, using the lamp voltage as a reference.

2. The power supply control device according to claim 1, wherein if the amplifier output voltage is higher than the lamp voltage, the clamp circuit attempts to lower the amplifier output voltage by drawing current from the line where the amplifier output voltage is generated, and if the amplifier output voltage is lower than the lamp voltage, the clamp circuit does not operate.

3. The clamping circuit is A resistor whose first end is connected to the output terminal of the error amplifier, An amplifier in which the non-inverting input terminal is connected to the second terminal of the resistor and the inverting input terminal is connected to the terminal to which the ramp voltage is applied, An NMOS transistor whose drain is connected to the non-inverting input terminal, whose source is connected to ground, and whose gate is connected to the output terminal of the amplifier, A power control device according to claim 1, having the following features.

4. The clamping circuit is An amplifier whose non-inverting input terminal is connected to the output terminal of the error amplifier and whose inverting input terminal is connected to the terminal to which the ramp voltage is applied, An NMOS transistor whose drain is connected to the non-inverting input terminal, whose source is connected to ground, and whose gate is connected to the output terminal of the amplifier, A power control device according to claim 1, having the following features.

5. The power supply control device according to claim 4, wherein the input offset of the amplifier is set by the size ratio of the input transistor pair in the differential input section included in the amplifier.

6. The power control device has a frequency divider function in which the switching control unit performs a skip operation to maintain the on state of the high-side transistor by skipping the turn-on of the low-side transistor at least once during the switching cycle. If the ramp voltage does not reach the amplifier output voltage during the switching cycle, the ON state of the frequency divider operation is maintained. The power control device according to claim 1, wherein the clamp circuit can be switched on or off depending on the on or off state of the frequency division operation.

7. A DC / DC converter comprising a power control device according to any one of claims 1 to 6, the high-side transistor, the low-side transistor, and the inductor.

8. A vehicle comprising the DC / DC converter described in claim 7 and a battery configured to output the battery voltage as the input voltage.

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