Indication device

Abstract

A display device according to one embodiment of this specification includes a substrate on which a plurality of subpixels and a plurality of contact regions between the plurality of subpixels are defined, a light-emitting element disposed in each of the plurality of subpixels, a side reflector disposed in each of the plurality of subpixels and surrounding the light-emitting element, a first connecting electrode electrically connected to the first electrode of the light-emitting element, a planarization layer pattern covering the first connecting electrode and the light-emitting element, and a second connecting electrode disposed on the planarization layer pattern, wherein the first connecting electrode and the second connecting electrode are disposed apart from each other with the planarization layer pattern in between. [Effect] The planarization layer pattern that separates the first and second connecting electrodes prevents short-circuit failures between the first and second connecting electrodes.

Description

TECHNICAL FIELD

[0001] The present specification relates to a display device, and more particularly, to a display device using a Light Emitting Diode (LED).

BACKGROUND ART

[0002] Display devices used in computer monitors, TVs, mobile phones and the like include self-luminous organic light-emitting displays (OLEDs) and the like, and liquid crystal displays (LCDs) that require a separate light source and the like.

[0003] The scope of application of display devices has diversified to not only computer monitors and TVs but also personal portable devices, and research on display devices that have a large display area while having reduced volume and weight is ongoing.

[0004] In recent years, display devices including LEDs have attracted attention as next-generation display devices. Since LEDs are made of inorganic substances rather than organic substances, they have excellent reliability and a longer service life than liquid crystal display devices and organic light-emitting display devices. In addition, LEDs not only have a fast lighting speed, but also have excellent luminous efficiency, strong impact resistance, excellent stability, and can display high-brightness images.

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] The problem to be solved by the present specification is to provide a display device with improved luminance uniformity in terms of light extraction efficiency and viewing angle.

[0006] Another problem to be solved by the present specification is to provide a display device capable of self-aligning the electrodes of a light-emitting element and connection electrodes.

[0007] Another problem that this specification seeks to solve is to provide a display device that prevents the side reflectors from floating.

[0008] Another problem that this specification seeks to solve is to provide a display device that prevents short-circuit failures between the first and second connecting electrodes using a variety of insulating layers.

[0009] Another problem that this specification seeks to solve is to provide a display device that enables direct contact inspection of light-emitting elements.

[0010] Another problem that this specification seeks to solve is to provide a display device that incorporates pads for inspecting light-emitting elements.

[0011] The problems described herein are not limited to those mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0012] A display device according to one embodiment of this specification includes a substrate on which a plurality of subpixels and a plurality of contact areas between the plurality of subpixels are defined, a light-emitting element disposed on each of the plurality of subpixels, a side reflector disposed on each of the plurality of subpixels and surrounding the light-emitting element, a first connecting electrode electrically connected to the first electrode of the light-emitting element, a planarization layer pattern covering the first connecting electrode and the light-emitting element, and a second connecting electrode disposed on the planarization layer pattern, wherein the first connecting electrode and the second connecting electrode are disposed apart from each other with the planarization layer pattern in between. Therefore, the planarization layer pattern separating the first connecting electrode and the second connecting electrode can prevent short-circuit failures between the first connecting electrode and the second connecting electrode.

[0013] Specific details of other embodiments are included in the detailed description and drawings.

[0014] According to this specification, side reflectors can be formed to improve the light extraction efficiency of light-emitting elements.

[0015] According to the present specification, the luminance uniformity depending on the viewing angle can be improved.

[0016] According to the present specification, floating of the side reflector can be prevented to avoid defects caused by static electricity.

[0017] According to the present specification, short-circuit defects of the first connection electrode and the second connection electrode can be prevented.

[0018] According to the present specification, self-alignment between the electrode of the light emitting element and the connection electrode can be achieved.

[0019] According to the present specification, a lighting inspection can be performed by directly applying an inspection signal to the light emitting element.

[0020] The effects according to the present specification are not limited to the contents exemplified above, and further various effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] [Figure 1] This is a schematic configuration diagram of a display device according to an embodiment of the present specification. [Figure 2] This is a partial cross-sectional view of a display device according to an embodiment of the present specification. [Figure 3] This is a schematic enlarged plan view of a display region of a display device according to an embodiment of the present specification. [Figure 4] This is a schematic enlarged plan view of a display region of a display device according to an embodiment of the present specification. [Figure 5] This is a cross-sectional view of the display device taken along line A-A' of Figure 3. [Figure 6a] This is an enlarged cross-sectional view showing region X of Figure 5. [Figure 6b] This is a graph for explaining the luminance of a light emitting element according to viewing angle. [Figure 6c] This is an exemplary cross-sectional view of a second planarization layer and a third planarization layer of a display device according to an embodiment of the present specification. [Figure 7] This is a schematic enlarged plan view of a display region of a display apparatus according to another embodiment of the present specification. [Figure 8] This is a cross-sectional view of the display apparatus taken along line B-B' of FIG. 7. [Figure 9] This is a cross-sectional view of a display apparatus according to still another embodiment of the present specification. [Figure 10] This is a cross-sectional view of a display apparatus according to still another embodiment of the present specification. DESCRIPTION OF EMBODIMENTS FOR CARRYING OUT THE INVENTION

[0022] The advantages and features of the present specification, as well as methods for achieving the same, will become clear with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but may be embodied in various different forms, and these embodiments are merely provided to make the disclosure of the present specification complete, and to fully inform those of ordinary skill in the art to which the present specification pertains of the scope of the invention.

[0023] The shapes, areas, ratios, angles, numbers and the like disclosed in the drawings for describing the embodiments of the present specification are illustrative, and thus the present specification is not limited to the illustrated matters. Throughout the specification, the same reference numerals refer to the same constituent elements. Further, in describing the present specification, when it is determined that a specific description of related known techniques may unnecessarily obscure the gist of the present specification, the detailed description thereof will be omitted. When terms such as "comprising", "having", and "formed" referred to in the present specification are used, other parts may be added as long as "only" is not used. When a constituent element is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

[0024] In interpreting the constituent elements, they shall be construed to include a tolerance range even without separate explicit description.

[0025] When describing a spatial relationship, for example, when describing the positional relationship between two parts using phrases like "on top," "above," "below," or "next to," it is acceptable for one or more other parts to be located between the two parts, as long as "immediately" or "directly" is not used.

[0026] When an element or layer is referred to as "on" another element or layer, this includes cases where another layer or other element is interposed immediately above or between the other element.

[0027] Furthermore, while terms such as "first," "second," etc., are used to describe a variety of components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0028] Throughout the specification, the same reference numeral refers to the same component.

[0029] The area and thickness of each component shown in the drawings are provided for illustrative purposes only, and this specification is not necessarily limited to the area and thickness of the components shown.

[0030] The features of each of the various embodiments described herein can be combined or combined with one another, either partially or as a whole, enabling a variety of technically diverse interoperability and drive, and each embodiment may be implemented independently of the others or together in relation to one another.

[0031] In the following, this specification will be described with reference to the drawings.

[0032] Figure 1 is a schematic diagram of a display device according to one embodiment of this specification. Figure 2 is a partial cross-sectional view of a display device according to one embodiment of this specification. In Figure 1, for the sake of explanation, only the display panel PN, gate drive unit GD, data drive unit DD, and timing controller TC are shown among the various components of the display device 100.

[0033] Referring to Figure 1, the display device 100 includes a display panel PN containing a plurality of subpixels SP, a gate drive unit GD and a data drive unit DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate drive unit GD and the data drive unit DD.

[0034] The gate drive unit GD supplies multiple scan signals to multiple scan wirings SL based on multiple gate control signals provided by the timing controller TC. In Figure 1, one gate drive unit GD is shown spaced apart on one side of the display panel PN, but the number and arrangement of gate drive units GD are not limited to this.

[0035] The data drive unit DD supplies data voltages to multiple data lines DL based on multiple data control signals and video data provided by the timing controller TC. The data drive unit DD can convert video data into data voltages using a reference gamma voltage and supply the converted data voltages to the multiple data lines DL.

[0036] The timing controller TC aligns the video data input from an external source and supplies it to the data drive unit DD. The timing controller TC can generate gate control signals and data control signals using synchronization signals input from an external source, such as a dot clock signal, a data enable signal, and horizontal / vertical synchronization signals. The timing controller TC can then control the gate drive unit GD and the data drive unit DD by supplying the generated gate control signals and data control signals to the gate drive unit GD and the data drive unit DD, respectively.

[0037] The display panel PN is a configuration for displaying images to the user and includes multiple sub-pixels SP. Multiple scan lines SL and multiple data lines DL intersect each other in the display panel PN, and multiple sub-pixels SP may be formed at the intersection points of the scan lines SL and data lines DL.

[0038] Display panel PN may have a display area AA and a non-display area NA defined within it.

[0039] Display area AA is the area on the display device 100 where an image is displayed. Display area AA may contain multiple subpixels SP that constitute multiple pixels PX, and pixel circuits for driving the multiple subpixels SP. Multiple subpixels SP are the smallest units that constitute display area AA, and n subpixels SP can constitute one pixel PX. Circuits for driving multiple light-emitting elements LEDs may be provided for each of the multiple subpixels SP. Multiple light-emitting elements LEDs may be defined differently depending on the type of display panel PN. For example, if the display panel PN is an inorganic light-emitting display panel PN, the light-emitting elements LEDs may be LEDs (Light-emitting Diodes) or micro-LEDs (Micro Light-emitting Diodes).

[0040] Multiple signal lines are arranged in the display area AA to transmit various signals to multiple sub-pixels SP. For example, the multiple signal lines may include multiple data lines DL that supply data voltage to each of the multiple sub-pixels SP, and multiple scan lines SL that supply scan signals to each of the multiple sub-pixels SP. Multiple scan lines SL may extend from the display area AA in one direction and be connected to the multiple sub-pixels SP, and multiple data lines DL may extend from the display area AA in directions other than one direction and be connected to the multiple sub-pixels SP. In addition, power lines, reference lines, etc. may be further arranged in the display area AA, but are not limited to these.

[0041] The non-display area NA is an area where no image is displayed and can be defined as an area extending from the display area AA. The non-display area NA may contain link wiring and pad electrodes for transmitting signals to the subpixels SP of the display area AA, as well as drive ICs such as gate driver ICs and data driver ICs. The non-display area NA may be located on the back of the display panel PN, i.e., the side without subpixels SP, or it may be omitted, and is not limited to what is shown in the drawing.

[0042] On the other hand, drive units such as the gate drive unit GD, data drive unit DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate drive unit GD may be implemented in the non-display area NA using the GIP (Gate In Panel) method, or it may be implemented in the display area AA between multiple sub-pixels SP using the GIA (Gate In Active Area) method.

[0043] For example, the data drive unit DD and the timing controller TC can be formed on a separate flexible film and printed circuit board 110. The display panel PN and the data drive unit DD and timing controller TC can then be electrically connected by bonding the flexible film and printed circuit board 110 to pad electrodes formed in the non-display area NA of the display panel PN.

[0044] To give another example, if the gate drive unit GD is implemented inside the display area AA using the GIA method, and side wiring SRL is formed to connect the signal wiring on the front of the display panel PN to the pad electrodes on the back of the display panel PN, and the flexible film and printed circuit board 110 are bonded to the back of the display panel PN, the non-display area NA on the front of the display panel PN can be minimized. Therefore, when the gate drive unit GD, data drive unit DD, and timing controller TC are connected to the display panel PN in the manner described above, it may be possible to realize a zero-bezel system where there is virtually no bezel.

[0045] Multiple pad electrodes are arranged in the non-display area NA of the display panel PN to transmit various signals to multiple sub-pixels SP. For example, a first pad electrode PE1 for transmitting signals to multiple sub-pixels SP is arranged in the non-display area NA on the front of the display panel PN, and a second pad electrode PE2 which is electrically connected to a drive component such as a flexible film and a printed circuit board 110 is arranged in the non-display area NA on the back of the display panel PN.

[0046] In this case, although not shown in the drawing, various signal wirings connected to multiple sub-pixels SP, such as scan wiring SL and data wiring DL, can extend from the display area AA to the non-display area NA and be electrically connected to the first pad electrode PE1.

[0047] Then, a side wiring SRL is positioned along the side of the display panel PN. The side wiring SRL can electrically connect the first pad electrode PE1 on the front of the display panel PN to the second pad electrode PE2 on the back of the display panel PN. Thus, signals from the drive components on the back of the display panel PN can be transmitted to multiple subpixels SP through the second pad electrode PE2, the side wiring SRL, and the first pad electrode PE1. In this way, a signal transmission path can be formed from the front to the sides and back of the display panel PN, minimizing the area of ​​the non-display region NA on the front of the display panel PN.

[0048] Therefore, by using side wiring SRL to connect drive components to the back of the display panel PN, the area of ​​the non-display area NA can be reduced, and a display device 100 with a minimized bezel can be realized. Furthermore, when multiple display devices 100 with minimized bezels are arranged to form a tiling display device 100, the seam area between two adjacent display devices 100 where images are not displayed can be minimized, potentially improving display quality.

[0049] In the following, the subpixels SP of the display device 100 according to one embodiment of this specification will be described in more detail with reference to Figures 3 to 6.

[0050] Figure 3 is a schematic enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. Figure 4 is a schematic enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. Figure 5 is a cross-sectional view of the display device along line A-A' in Figure 3. Figure 6a is an enlarged cross-sectional view of area X in Figure 5. Figure 6b is a graph illustrating the brightness of the light-emitting element with respect to the viewing angle. Figure 6c is an exemplary cross-sectional view of the second and third planarization layers of a display device according to one embodiment of this specification.

[0051] Referring to Figures 3 to 5, a pixel PX containing multiple subpixels SP is arranged in the display area AA. Each of the multiple subpixels SP includes a light-emitting element LED and can emit light independently. The multiple subpixels SP may be arranged in a matrix configuration with multiple rows and multiple columns, but the embodiments herein are not limited to this.

[0052] Multiple subpixels SP include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. For example, one or more first subpixels SP1, one or more second subpixels SP2, and one or more third subpixels SP3 can constitute a single pixel PX. For example, one of the first subpixel SP1, second subpixel SP2, and third subpixel SP3 may be a red subpixel, another a green subpixel, and the rest blue subpixels, but is not limited to this.

[0053] A contact area CA is located within the display area AA. The contact area CA is the region where the power supply wiring VDD and the second connecting electrode CE2 are electrically connected to each other. The contact area CA may be located between multiple pixels PX. A more detailed explanation of the contact area CA will follow later.

[0054] Referring to Figure 5, the substrate 110 is a member that supports other components of the display device 100. For example, the substrate 110 may be made of glass or resin. Alternatively, the substrate 110 may be made of polymer or plastic, and in some embodiments, the substrate 110 may be made of a flexible plastic material.

[0055] A light-shielding layer LS is placed on the substrate 110 for each of the multiple subpixels SP. The light-shielding layer LS can block light incident on the active layer ACT of the drive transistor DT, thereby minimizing leakage current. The light-shielding layer LS may, but is not limited to, an opaque conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0056] A buffer layer 111 is placed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 is positioned to cover one surface of the substrate 110, thereby reducing the penetration of moisture or impurities through the substrate 110. The buffer layer 111 may, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx).

[0057] In each of the multiple subpixels SP, a drive transistor DT is placed on the buffer layer 111. The drive transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. On the other hand, although not shown in the drawings, each of the multiple subpixels SP may also have other components in addition to the drive transistor DT, such as a switching transistor, a sensing transistor, a light emission control transistor, a storage capacitor Cst, etc.

[0058] The active layer ACT of the drive transistor DT is placed on the buffer layer 111. The active layer ACT may, but is not limited to, a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon.

[0059] A gate insulating layer 112 is placed on the active layer ACT. The gate insulating layer 112 is an insulating layer for insulating the active layer ACT from the gate electrode GE. For example, the gate insulating layer 112 may, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx).

[0060] A gate electrode GE is positioned on the gate insulating layer 112. The gate electrode GE may be positioned superimposed on the active layer ACT. The gate electrode GE may, but is not limited to, a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0061] A first interlayer insulating layer 113a and a second interlayer insulating layer 113b are arranged on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer 113a and the second interlayer insulating layer 113b for the source electrode SE and the drain electrode DE to connect to the active layer ACT, respectively. The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are insulating layers for protecting the underlying structure and may, but are not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx).

[0062] A source electrode SE and a drain electrode DE are arranged on the second interlayer insulating layer 113b. The source electrode SE and the drain electrode DE can be electrically connected to the active layer ACT through contact holes formed in the first interlayer insulating layer 113a, the second interlayer insulating layer 113b, and the gate insulating layer 112. The source electrode SE and the drain electrode DE may, but are not limited to, a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0063] An intermediate electrode TM is placed on the first interlayer insulating layer 113a. The intermediate electrode TM is positioned so as to overlap with the gate electrode GE of the drive transistor DT, with the first interlayer insulating layer 113a in between, and together with the gate electrode GE of the drive transistor DT, it can form a capacitor, but is not limited to this.

[0064] An auxiliary electrode LE is placed on the gate insulating layer 112. The auxiliary electrode LE is an electrode that electrically connects the light-shielding layer LS below the buffer layer 111 to either the source electrode SE or the drain electrode DE of the drive transistor DT on the second interlayer insulating layer 113b. For example, the light-shielding layer LS is electrically connected to either the source electrode SE or the drain electrode DE through the auxiliary electrode LE and ceases to operate as a floating gate, thereby minimizing threshold voltage fluctuations of the drive transistor DT caused by the floating light-shielding layer LS.

[0065] A capacitor Cst is placed on the gate insulating layer 112. The capacitor Cst includes a first capacitor electrode Cst1 and a second capacitor electrode Cst2.

[0066] A first capacitor electrode Cst1 may be placed on the gate insulating layer 112. The first capacitor electrode Cst1 may, but is not limited to, being placed on the same layer as the gate electrode GE and being made of the same material.

[0067] A second capacitor electrode Cst2 may be placed on the first interlayer insulating layer 113a. The second capacitor electrode Cst2 may be placed on the same layer as the intermediate electrode TM and may be made of the same material. The second capacitor electrode Cst2 may be placed so as to overlap the first capacitor electrode Cst1 with the first interlayer insulating layer 113a in between. The second capacitor electrode Cst2 may be electrically connected to the source electrode SE of the drive transistor DT.

[0068] A power supply wiring VDD is placed on the second interlayer insulating layer 113b. The power supply wiring VDD can drive the light-emitting element LED together with the drive transistor DT. The power supply wiring VDD may, but is not limited to, a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0069] A passivation layer 114 is placed on the drive transistor DT and the power supply wiring VDD. The passivation layer 114 can protect the drive transistor DT and the power supply wiring VDD from impurities or moisture. The passivation layer 114 may, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx).

[0070] An overcoating layer 115 is placed on the passivation layer 114. The overcoating layer 115 can flatten the upper part of the substrate 110 on which the drive transistor DT is located. The overcoating layer 115 may consist of a single layer or multiple layers, and may, for example, be made of a photoresist or an acrylic-based organic material, but is not limited thereto.

[0071] Multiple reflective electrodes RE are arranged on the overcoating layer 115. The multiple reflective electrodes RE electrically connect the light-emitting element LED to the power supply wiring VDD and the drive transistor DT, and at the same time function as reflectors that reflect the light emitted by the light-emitting element LED towards the top of the light-emitting element LED. The multiple reflective electrodes RE are formed of a conductive material with excellent reflective properties, and can reflect the light emitted by the light-emitting element LED towards the top of the light-emitting element LED.

[0072] Multiple reflective electrodes RE can include a variety of conductive layers, taking into account light reflection efficiency and resistance. For example, multiple reflective electrodes RE can use opaque conductive layers such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof, along with transparent conductive layers such as ITO (Indium Tin Oxide), but the structure and materials of the reflective electrodes RE are not limited thereto.

[0073] Multiple reflective electrodes RE include a first reflective electrode RE1 and a second reflective electrode RE2.

[0074] The first reflective electrode RE1 can electrically connect the drive transistor DT and the light-emitting element LED. The first reflective electrode RE1 can be electrically connected to the source electrode SE or drain electrode DE of the drive transistor DT through contact holes formed in the passivation layer 114 and the overcoating layer 115. Furthermore, the first reflective electrode RE1 can be electrically connected to the first electrode 124 of the light-emitting element LED through the first connecting electrode CE1.

[0075] The second reflective electrode RE2 can electrically connect the power supply wiring VDD and the light-emitting element LED. The second reflective electrode RE2 is located in the contact area CA and can be connected to the power supply wiring VDD. The second reflective electrode RE2 can be electrically connected to the power supply wiring VDD through contact holes formed in the passivation layer 114 and the overcoating layer 115. The second reflective electrode RE2 can be electrically connected to the second electrode 125 of the light-emitting element LED through the second connecting electrode CE2.

[0076] An adhesive layer 116 is placed on multiple reflective electrodes RE. The adhesive layer 116 is formed on the front surface of the substrate 110 and can fix light-emitting elements LEDs placed on the adhesive layer 116. The adhesive layer 116 may consist of a photocurable or thermosetting adhesive material that can be cured by light or heat. For example, the adhesive layer 116 may consist of an acrylic series material containing a photosensitive agent, but is not limited thereto.

[0077] Multiple light-emitting LEDs can be arranged on each of the multiple subpixels SP on the adhesive layer 116. The multiple light-emitting LEDs are elements that emit light when an electric current is applied, and may include light-emitting LEDs that emit red light, green light, blue light, etc., and various hues of light, including white light, can be realized by combinations of these. For example, the multiple light-emitting LEDs may be LEDs (Light Emitting Diodes) or micro LEDs (micro LEDs), but are not limited to these.

[0078] Referring to Figure 5, the first light-emitting element 120 may include a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and an insulating film 126.

[0079] A first semiconductor layer 121 is placed on an adhesive layer 116, and a second semiconductor layer 123 is placed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be semiconductor layers doped with n-type and p-type impurities, respectively. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may each be layers doped with n-type and p-type impurities in a substance such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurities may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurities may be silicon (Si), germanium, tin (Sn), etc., but are not limited to these.

[0080] A portion of the first semiconductor layer 121 may be positioned to protrude outside the second semiconductor layer 123. The upper surface of the first semiconductor layer 121 may consist of a portion that overlaps with the lower surface of the second semiconductor layer 123 and a portion positioned outside the lower surface of the second semiconductor layer 123, and the light-emitting element LED may be a lateral light-emitting element LED. However, the size and shape of the first semiconductor layer 121 and the second semiconductor layer 123 can be varied and are not limited thereto.

[0081] A light-emitting layer 122 is disposed between a first semiconductor layer 121 and a second semiconductor layer 123. The light-emitting layer 122 can emit light by receiving holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 can be a single layer or a multi-quantum well (MQW) structure, and may be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0082] One or more first electrodes 124 may be arranged on the first semiconductor layer 121. The first electrode 124 is an electrode for electrically connecting the drive transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 is a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 may be arranged on the upper surface of the first semiconductor layer 121 exposed from the light-emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be composed of one of the following conductive materials, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), or copper (Cu), but is not limited to these.

[0083] A second electrode 125 is placed on the upper surface of the second semiconductor layer 123. The second electrode 125 is an electrode for electrically connecting the power supply wiring VDD to the second semiconductor layer 123. Since the second semiconductor layer 123 is placed on the first semiconductor layer 121, the second electrode 125 placed on the upper surface of the second semiconductor layer 123 may be positioned higher than the first electrode 124. In this case, the second semiconductor layer 123 is a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be made of a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0084] Next, an insulating film 126 may be placed surrounding the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The insulating film 126 is made of an insulating material and can protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. Contact holes are formed in the insulating film 126 to expose the first electrode 124 and the second electrode 125, and the first and second electrodes 124 and 125 can be electrically connected to the first and second electrodes CE1 and CE2 which are formed later.

[0085] On the other hand, the second light-emitting element 130 and the third light-emitting element 140 may also have the same configuration as the first light-emitting element 120. For example, the second light-emitting element 130 and the third light-emitting element 140 may also include the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, one or more first electrodes 124, second electrodes 125, and insulating film 126 of the first light-emitting element 120.

[0086] In this case, the second light-emitting element 130 and the third light-emitting element 140 include the same configuration as the first light-emitting element 120, but their shapes may be different in order to distinguish them from each other. For example, the planar shape of the first light-emitting element 120 may be circular, the planar shape of the second light-emitting element 130 may be elliptical, and the planar shape of the third light-emitting element 140 may be elliptical with a longer major axis than that of the second light-emitting element 130, but is not limited to this.

[0087] A first planarization layer 117a is placed on the adhesive layer 116. The first planarization layer 117a is positioned to surround a portion of the lower side surface of the multiple light-emitting LEDs, thereby fixing and protecting the multiple light-emitting LEDs. The first planarization layer 117a may consist of a single layer or multiple layers, and may, for example, be made of a photoresist or an acrylic-based organic material, but is not limited thereto.

[0088] The first planarization layer 117a is positioned to surround the insulating film 126 located on the lower edge of the light-emitting element LED, thereby preventing the first connecting electrode CE1 from being disconnected due to peeling of the insulating film 126. For example, during the process of separating the wafer from the light-emitting element LED, a portion of the insulating film 126 may be peeled off at the lower edge of the light-emitting element LED. As a result, a portion of the first semiconductor layer 121 at the lower edge of the light-emitting element LED may be exposed from the insulating film 126. In this case, if the first connecting electrode CE1 is positioned to surround the side surface of the insulating film 126, the step created by the peeling of the insulating film 126 may cause the first connecting electrode CE1 to be disconnected. Therefore, by positioning the first planarization layer 117a to surround the lower edge of the light-emitting element LED before forming the first connecting electrode CE1, the lower edge of the light-emitting element LED and the first connecting electrode CE1 can be separated. Even if an undercut structure is formed on the lower edge of the light-emitting LED due to peeling of the insulating film 126, the first planarization layer 117a contacts at least a portion of the side surface of the light-emitting LED and fills the undercut structure, thereby minimizing the phenomenon of the first connecting electrode CE1 being disconnected due to the undercut structure.

[0089] Next, a first connecting electrode CE1 is placed on the first planarization layer 117a in each of the multiple subpixels SP. The first connecting electrode CE1 is an electrode for electrically connecting the light-emitting element LED and the drive transistor DT. The first connecting electrode CE1 is connected to the first reflective electrode RE1 through contact holes formed in the first planarization layer 117a and the adhesive layer 116, and the first connecting electrode CE1 can be electrically connected to either the source electrode SE or the drain electrode DE of the drive transistor DT through the first reflective electrode RE1. The first connecting electrode CE1 is also positioned to cover the side portion of the light-emitting element LED and the first electrode 124, and can be electrically connected to the first electrode 124. The first connecting electrode CE1 may be made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0090] A second planarization layer 117b is placed on the first planarization layer 117a, the first connecting electrode CE1, and the first contact electrode CE1A, and a third planarization layer 117c is placed on the second planarization layer 117b. The second planarization layer 117b and the third planarization layer 117c, together with the first planarization layer 117a, can planarize the upper part of the substrate 110 on which the light-emitting element LED is placed. The second planarization layer 117b and the third planarization layer 117c may be single-layer or multi-layer, and may, for example, be made of photoresist or acrylic-based organic material, but are not limited thereto.

[0091] The second flattening layer 117b and the third flattening layer 117c may have openings that overlap with each of the multiple light-emitting LEDs. The openings allow the sides of the second flattening layer 117b and the third flattening layer 117c to be spaced apart from the light-emitting LEDs. The openings may have a planar shape that corresponds to the planar shape of the light-emitting LEDs. The distance from the sides of the second flattening layer 117b and the third flattening layer 117c that form the openings to the light-emitting LEDs may be constant. The sides of the second flattening layer 117b and the third flattening layer 117c facing the light-emitting LEDs in the openings may provide inclined surfaces on which side reflectors SREs are placed.

[0092] Next, a planarization layer pattern 117i is placed on the first connecting electrode CE1 and surrounds the light-emitting element LED. The planarization layer pattern 117i is positioned to surround a portion of the first connecting electrode CE1 that covers the light-emitting element LED and the upper portion of the light-emitting element LED. The uppermost second electrode 125 of the light-emitting element LED may be exposed from the planarization layer pattern 117i. The planarization layer pattern 117i positioned to cover the first connecting electrode CE1 can separate the first connecting electrode CE1 and the second connecting electrode CE2, thereby preventing short-circuit failures between the first connecting electrode CE1 and the second connecting electrode CE2.

[0093] The planarization layer pattern 117i can be formed from either the second planarization layer 117b or the third planarization layer 117c. For example, the planarization layer pattern 117i may be formed together with the second planarization layer 117b, or together with the third planarization layer 117c.

[0094] A side reflector SRE is placed on the third planarization layer 117c for each of the multiple subpixels SP. The side reflector SRE can reflect light emitted by the light-emitting element LED that is directed in the lateral direction to the upper part of the substrate 110. The side reflector SRE is placed in the lateral region of the light-emitting element LED. The side reflector SRE may be placed on the side of the second planarization layer 117b and the side of the third planarization layer 117c that face the light-emitting element LED.

[0095] The side reflector SRE can be electrically connected to the first connecting electrode CE1 through contact holes in the second planarization layer 117b and the third planarization layer 117c. The side reflector SRE is connected to the first connecting electrode CE1 and can prevent static electricity and other issues that may occur in a floating state. For example, the side reflector SRE may contain conductive materials with excellent reflective properties such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof, which have high reflective efficiency, but the composition of the side reflector SRE is not limited thereto.

[0096] Referring to Figures 4 and 5, the side reflectors (SREs) are arranged to surround each of the multiple light-emitting LEDs, and the side reflectors (SREs) have openings that overlap the multiple light-emitting LEDs. The planar shape of the openings in the side reflectors (SREs) may have a planar shape that corresponds to the light-emitting LEDs. Therefore, when viewed from a plane, the distance from the side reflectors (SREs) to the light-emitting LEDs can be configured to be at equal intervals.

[0097] For example, the side reflector SRE of the first subpixel SP1 may have a circular opening corresponding to the planar shape of the first light-emitting element 120, the side reflector SRE of the second subpixel SP2 may have an elliptical opening corresponding to the planar shape of the second light-emitting element 130, and the side reflector SRE of the third subpixel SP3 may have an elliptical opening corresponding to the planar shape of the third light-emitting element 140. The distance between the first light-emitting element 120 and the side reflector SRE may be the same as a, the distance between the second light-emitting element 130 and the side reflector SRE may be the same as b, and the distance between the third light-emitting element 140 and the side reflector SRE may be the same as c. For example, the distances (a, b, c) may have different values ​​from each other, but are not limited to this. Therefore, by configuring the distance between the side reflector SRE and the light-emitting element LED to be constant, the improvement in light efficiency by the side reflector SRE can be achieved at the same level at all angles. Furthermore, the light reflected by the side reflector (SRE) is concentrated at the center of the SRE's opening, towards the light-emitting LED, which can further improve the central brightness of the light-emitting area.

[0098] A fourth planarization layer 117d is placed on the side reflector SRE and the second contact electrode SREA. An opening may be formed in the fourth planarization layer 117d that overlaps with the light-emitting element LED and the planarization layer pattern 117i. The opening in the fourth planarization layer 117d may expose the planarization layer pattern 117i and the second electrode 125 of the light-emitting element LED. The fourth planarization layer 117d may be a single layer or a multi-layer, and may, for example, be made of a photoresist or an acrylic-based organic material, but is not limited thereto.

[0099] A second connecting electrode CE2 is placed on the fourth planarization layer 117d. The second connecting electrode CE2 is an electrode for electrically connecting the light-emitting element LED and the power supply wiring VDD. The second connecting electrode CE2 can be electrically connected to the power supply wiring VDD through the first contact electrode CE1A, the second contact electrode SREA, and the second reflective electrode RE2 of the contact region CA. The second connecting electrode CE2 can be electrically connected to the second electrode 125 of the light-emitting element LED through an opening in the fourth planarization layer 117d. The second connecting electrode CE2 may, but is not limited to, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0100] On the other hand, the planarization layer pattern 117i can guide the second connecting electrode CE2 so that it self-aligns with the second electrode 125 of the light-emitting element LED. Since only the second electrode 125 of the light-emitting element LED is exposed from the fourth planarization layer 117d and the planarization layer pattern 117i in the region of multiple subpixels SP, the second connecting electrode CE2 can be formed over the entire subpixel SP region to connect the second electrode 125 and the second connecting electrode CE2 to each other. Therefore, it is not necessary to precisely align the light-emitting element LED and the second electrode 125, and the second connecting electrode CE2 can be formed covering the top of the light-emitting element LED with only the second electrode 125 exposed from the planarization layer pattern 117i in advance, so that the second electrode 125 and the second connecting electrode CE2 self-align.

[0101] Next, a first contact electrode CE1A is placed on the first planarization layer 117a in the contact region CA. The first contact electrode CE1A is an electrode for electrically connecting the light-emitting element LED and the power supply wiring VDD. For example, in the first contact region CA1, the first contact electrode CE1A can be electrically connected to the second reflective electrode RE2 through contact holes formed in the first planarization layer 117a and the adhesive layer 116. In both the first contact region CA1 and the second contact region CA2, the first contact electrode CE1A can also be electrically connected to the second contact electrode SREA.

[0102] The first contact electrode CE1A is located in the same layer as the first connecting electrode CE1 and may, but is not limited to, being made of the same material. The first contact electrode CE1A may, but is not limited to, being made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0103] In contact region CA, a second contact electrode SREA is positioned on the third planarization layer 117c. The second contact electrode SREA, together with the first contact electrode CE1A, is an electrode for electrically connecting the light-emitting element LED and the power supply wiring VDD. For example, in the first contact region CA1 and the second contact region CA2, the second contact electrode SREA can be connected to the first contact electrode CE1A through contact holes formed in the second planarization layer 117b and the third planarization layer 117c, respectively. In the third contact region CA3, the second contact electrode SREA can be electrically connected to the second connecting electrode CE2 through a contact hole in the fourth planarization layer 117d.

[0104] The second contact electrode SREA may be made of the same material and in the same layer as the side reflector SRE. The second contact electrode SREA may be made of a conductive material with excellent reflective properties, such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof, but is not limited to these.

[0105] Furthermore, the power supply wiring VDD can be electrically connected to the second connecting electrode CE2 through multiple contact electrodes and a second reflective electrode RE2 in each of the multiple contact regions CA. Thus, the numerous contact structures can reduce the resistance between the power supply wiring VDD and the second connecting electrode CE2, thereby improving the stability of the electrical connection.

[0106] For example, the second connecting electrode CE2 may extend into the contact region CA through multiple subpixels SP. The second connecting electrode CE2 may be electrically connected to the second reflective electrode RE2 and the power supply wiring VDD through multiple contact electrodes in the contact region CA. Specifically, in the first contact region CA1, the second connecting electrode CE2, the second contact electrode SREA, the first contact electrode CE1A, the second reflective electrode RE2, and the power supply wiring VDD may be electrically connected to each other. In the second contact region CA2, the second connecting electrode CE2, the second contact electrode SREA, and the first contact electrode CE1A may be electrically connected to each other. Finally, in the third contact region CA3, the second connecting electrode CE2 and the second contact electrode SREA may be electrically connected to each other.

[0107] Therefore, even if a connection failure occurs in some contact areas CA, the power supply wiring VDD and the second connecting electrode CE2 can still be electrically connected to each other through the remaining contact areas CA. In addition, the second connecting electrode CE2 may come into contact with multiple contact electrodes in multiple contact areas CA, thereby reducing the resistance of the second connecting electrode CE2.

[0108] Next, a bank 118 is placed on the second connecting electrode CE2 and the fourth planarization layer 117d. The bank 118 may be placed in the remaining area excluding the area where the multiple light-emitting elements (LEDs) are located. The area exposed from the bank 118 may be defined as the light-emitting region. For example, the bank 118 may define the light-emitting region by covering the edges of the second connecting electrode CE2 connected to each light-emitting element (LED). The bank 118 may contain a black component with high light absorption to prevent color mixing between adjacent subpixels SP, and may consist of a black bank 118. For example, the bank 118 may, but is not limited to, polyimide resin, acrylic resin, or benzocyclobutene (BCB) resin.

[0109] A protective layer 119 is placed on bank 118. The protective layer 119 is placed on the front surface of the substrate 110 and can protect the components beneath it. The protective layer 119 may, but is not limited to, be called a capping layer. The protective layer 119 may consist of a single layer or multiple layers, and may, but is not limited to, a photoresist or an acrylic-based organic material.

[0110] On the other hand, in the display device 100 according to one embodiment of this specification, the angle of the side reflector SRE is determined by the angle of the side surface of the second flattening layer 117b and the angle of the side surface of the third flattening layer 117c. In this case, the brightness distribution with respect to the viewing angle may change depending on the angle of the side reflector SRE.

[0111] Referring to Figure 6a, in the display device 100 according to one embodiment of this specification, the side surface of the second flattening layer 117b has a first angle α, and the side surface of the third flattening layer 117c has a second angle β, and the first angle α and the second angle β may be angles of 60 degrees or less. For example, the first angle α and the second angle β may be about 55 degrees.

[0112] Figure 6b is a graph showing the brightness distribution by viewing angle for each of the Example, Comparative Example 1, and Comparative Example 2. The Example is a case where the side reflector SRE has a structure like that of the display device 100 according to one embodiment of this specification, Comparative Example 1 is a case where the side reflector SRE is absent in the display device 100 according to one embodiment of this specification, and Comparative Example 2 is a case where the first angle α and second angle β on the sides of the second flattening layer 117b and third flattening layer 117c on which the side reflector SRE is arranged are 60 degrees or more in the display device 100 according to one embodiment of this specification. In the graph, the light-emitting element LED is located at 0 degrees, and the brightness distribution from 0 degrees to 90 degrees above the light-emitting element LED can be observed. At this time, the brightness is displayed as the relative brightness distribution of the Example and Comparative Example 2, assuming that the brightness at the center of the light-emitting element LED is 100% in Comparative Example 1.

[0113] First, in Comparative Example 1, there is no side reflector (SRE), and some of the light does not concentrate towards the center of the light-emitting LED but may be directed towards the sides of the light-emitting LED. Therefore, in Comparative Example 1, it can be confirmed that the brightness in the side direction is higher than the brightness at the top of the light-emitting LED.

[0114] In this embodiment, the side reflector SRE is placed on a second flattening layer 117b and a third flattening layer 117c having sides at a first angle α and a second angle β, allowing some of the light emitted by the light-emitting element LED that travels in the lateral direction to converge toward the center of the light-emitting element LED. Therefore, in this embodiment, it can be confirmed that the brightness at the top of the light-emitting element LED and the brightness in the lateral direction have an overall uniform distribution.

[0115] In Comparative Example 2, although a side reflector (SRE) is present, the SRE has a higher inclination than in the Example, which can cause more light directed to the sides to concentrate at the center of the light-emitting element (LED). As a result, the brightness at the top of the light-emitting element (LED) may increase compared to the brightness in other viewing angle regions, potentially causing a brightness deviation depending on the viewing angle.

[0116] Accordingly, in the display device 100 according to one embodiment of this specification, the first angle α on the side surface of the second flattening layer 117b on which the side reflector SRE is arranged and the second angle β on the side surface of the third flattening layer 117c are formed to an angle of 60 degrees or less, for example, about 55 degrees, thereby uniformly forming the brightness distribution according to the viewing angle.

[0117] On the other hand, referring to Figure 6a, the first angle α of the side surface of the second flattening layer 117b and the second angle β of the side surface of the third flattening layer 117c may be affected by the thickness of the second flattening layer 117b and the third flattening layer 117c. For example, the steeper the slope of the side surface may be formed as the thickness of the second flattening layer 117b and the third flattening layer 117c increases, and the gentler the slope of the side surface may be formed as the thickness of the second flattening layer 117b and the third flattening layer 117c decreases.

[0118] For example, the second flattening layer 117b may have a first thickness t1, and the third flattening layer 117c may have a second thickness t2. In this case, the first thickness t1 and the second thickness t2 can be formed at the same level, so that the first angle α of the side surface of the second flattening layer 117b and the second angle β of the side surface of the third flattening layer 117c are at the same level.

[0119] Furthermore, the third flattening layer 117c can be formed on the upper surface of the second flattening layer 117b, and the thickness of the third flattening layer 117c can be adjusted so that it does not become excessively thick. In this case, the sides of the third flattening layer 117c may be positioned on the upper surface of the second flattening layer 117b, and the sides of the second flattening layer 117b may be exposed from the third flattening layer 117c. Considering alignment errors and process margins, the sides of the third flattening layer 117c may be positioned at a distance from the sides of the second flattening layer 117b. If the third flattening layer 117c is formed to completely cover the sides of the second flattening layer 117b, the thickness of the third flattening layer 117c may increase, the slope of the sides of the third flattening layer 117c may be made steeper, and the angle of the side reflector SRE may also increase. In this case, the brightness at the center of the light-emitting LED may increase compared to the brightness in other viewing angle regions, potentially resulting in an uneven brightness distribution.

[0120] Therefore, the side surface of the third flattening layer 117c can be formed on the inside of the upper surface of the second flattening layer 117b so that the third flattening layer 117c does not cover the side surface of the second flattening layer 117b and have a thick and sharp side surface. The side surface of the third flattening layer 117c and the side surface of the second flattening layer 117b may have a gap of D. Considering the alignment error and process margin of the second flattening layer 117b and the third flattening layer 117c respectively, the gap between the side surface of the third flattening layer 117c and the side surface of the second flattening layer 117b can be designed to have a gap of at least D. In this case, the gap D may be a value even larger than the margin of alignment error that occurs during the exposure process of the second flattening layer 117b and the third flattening layer 117c. Therefore, the side surface of the third flattening layer 117c facing the light-emitting element LED is positioned on the second flattening layer 117b, and the second flattening layer 117b and the third flattening layer 117c can form a stepped structure.

[0121] Referring to Figure 6c, the edges of the second flattening layer 117b and the third flattening layer 117c may be formed to be curved depending on the manufacturing process requirements, etc. For example, the second flattening layer 117b may include a first lower edge F1 between the bottom surface and the side surface and a first upper edge E1 between the top surface and the side surface, and the first lower edge F1 and the first upper edge E1 may be arc-shaped. The first lower edge F1 may have a concave arc-shaped surface, and the first upper edge E1 may have a convex arc-shaped surface. The third flattening layer 117c may include a second lower edge F2 between the bottom surface and the side surface and a second upper edge E2 between the top surface and the side surface, and the second lower edge F2 and the second upper edge E2 may also be arc-shaped. The second lower edge F2 may have a concave arc-shaped surface, and the second upper edge E2 may have a convex arc-shaped surface.

[0122] The second flattening layer 117b and the third flattening layer 117c have a staircase-like structure, but the arc portion of the first upper edge E1 of the second flattening layer 117b and the arc portion of the second lower edge F2 of the third flattening layer 117c can be arranged continuously from the point where the arc of the first upper edge E1 of the second flattening layer 117b ends, without any flat portion of the staircase shape. The first upper edge E1 and the second lower edge F2 can be arranged continuously. The first upper edge E1 and the second lower edge F2 can form a staircase shape.

[0123] If the first thickness t1 of the second flattening layer 117b and the second thickness t2 of the third flattening layer 117c are the same, and the first angle α of the side surface of the second flattening layer 117b and the second angle β of the side surface of the third flattening layer 117c are the same, then the first upper edge E1 of the second flattening layer 117b and the second upper edge E2 of the third flattening layer 117c may have the same curvature. That is, the first upper edge E1 and the second upper edge E2 may be made into arc shapes with the same radius. Furthermore, the arc of the first lower edge F1 of the second flattening layer 117b may have a smaller radius than the arc of the second lower edge F2 of the third flattening layer 117c. Therefore, the curvature of the arc of the first lower edge F1 may be greater than the curvature of the arc of the second lower edge F2, and the degree of curvature of the first lower edge F1 may be even greater than the degree of curvature of the second lower edge F2.

[0124] The first lower edge F1 and first upper edge E1 of the second flattening layer 117b and the second lower edge F2 and second upper edge E2 of the third flattening layer 117c can be formed into a curved shape, thereby allowing a portion of the side reflector SRE formed along the surfaces of the second flattening layer 117b and the third flattening layer 117c to be formed in a curved shape. The side reflector SRE can be formed along the surface shapes of the second flattening layer 117b and the third flattening layer 117c, and a portion of the side reflector SRE covering the first lower edge F1, first upper edge E1, second lower edge F2 and second upper edge E2 can be made into a curved shape. Therefore, by configuring at least a portion of the side reflector SRE as a curved surface, the reflection efficiency of the side reflector SRE can be increased, and the brightness uniformity can also be improved.

[0125] Accordingly, in the display device 100 according to one embodiment of this specification, the side surface of the third flattening layer 117c is formed in a stepped structure on the upper surface of the second flattening layer 117b, so that the thickness of the third flattening layer 117c does not become excessively thick, and the side surface angle of the third flattening layer 117c can be easily adjusted. The angle of the side surfaces of the second flattening layer 117b and the third flattening layer 117c, on which the side reflector SRE is arranged, can be formed within a target range to maximize the light extraction efficiency of the light-emitting element LED by the side reflector SRE. For example, the side surface of the third flattening layer 117c is arranged in a region on the second flattening layer 117b, and the third flattening layer 117c is formed such that it has a distance of at least D from the side surface of the second flattening layer 117b, so that the second angle β of the side surface of the third flattening layer 117c can be easily formed to a level of about 55 degrees.

[0126] In addition, in the display device 100 according to one embodiment of this specification, a side reflector SRE is arranged around each of the multiple subpixels SP, with the side reflector SRE being equally spaced from the side reflector SRE, thereby enabling the formation of a uniform brightness distribution across viewing angles. By maintaining a constant distance between the side reflector SRE and the side reflector SRE and the side reflector SRE, the reflection of light emitted by the side reflector SRE is at the same level at all angles, thereby improving the uniformity of brightness across viewing angles.

[0127] Figure 7 is a schematic enlarged plan view of the display area of ​​a display device according to another embodiment of this specification. Figure 8 is a cross-sectional view of the display device along line B-B' in Figure 7. The display devices 700 in Figures 7 and 8 are substantially identical in other configurations to the display devices 100 in Figures 1 to 5, except that they further include an inspection area APA and an inspection pad; therefore, redundant explanations are omitted.

[0128] Referring to Figures 7 and 8, an inspection area APA is formed in each of the multiple subpixels SP. The inspection area APA is an area where inspection pads are placed for testing the lighting of multiple light-emitting LEDs. Without driving the drive transistor DT, an inspection signal can be applied directly to the light-emitting LEDs using the inspection pads in the inspection area APA. For example, the inspection pad is a pad connected to the first connecting electrode CE1, and an inspection signal can be applied to the first connecting electrode CE1 and the first electrode 124 of the light-emitting LED through the inspection pad.

[0129] The inspection pad includes a first inspection pad SREP and a second inspection pad CE2P. The first inspection pad SREP is placed on the third planarization layer 117c, and the second inspection pad CE2P is placed on the fourth planarization layer 117d. The first inspection pad SREP can be electrically connected to the side reflector SRE through the second inspection pad CE2P. The first inspection pad SREP and the second inspection pad CE2P can be electrically connected to the first connecting electrode CE1 through the side reflector SRE. The second inspection pad CE2P can be electrically connected to the first inspection pad SREP and the side reflector SRE through the contact hole in the fourth planarization layer 117d. Thus, the first inspection pad SREP and the second inspection pad CE2P can be electrically connected to the first electrode 124 of the light-emitting element LED through the side reflector SRE and the first connecting electrode CE1.

[0130] The first inspection pad SREP may be made of the same material and in the same layer as the side reflector SRE, and the second inspection pad CE2P may be made of the same material and in the same layer as the second connecting electrode CE2.

[0131] Multiple light-emitting LEDs are transferred onto the adhesive layer 116, and after forming the first planarization layer 117a, the first connecting electrode CE1, the second planarization layer 117b, the third planarization layer 117c, the side reflector SRE and the first inspection pad SREP, the fourth planarization layer 117d, the second connecting electrode CE2 and the second inspection pad CE2P, a lighting test can be performed. During the lighting test, an inspection signal can be applied directly to the second inspection pad CE2P in the inspection area APA to apply an inspection signal to the first electrode 124 of the light-emitting LED. Then, an inspection signal can be applied directly to the second connecting electrode CE2 to apply an inspection signal to the second electrode 125 of the light-emitting LED. The light-emitting LEDs can emit light in response to the inspection signals applied to the first electrode 124 and the second electrode 125, and defective light-emitting LEDs that do not emit light can be detected in this process. Finally, after the lighting test is completed, a bank 118 and a protective layer 119 are formed on the inspection pad and the second connecting electrode CE2 to complete the manufacturing process of the display device 700.

[0132] Therefore, by directly applying a signal to the inspection pad and the second connecting electrode CE2, the lighting test of the light-emitting LED can be performed before the formation of bank 118. Alternatively, without driving the drive transistor DT and the power supply wiring VDD, the lighting test of the light-emitting LED can be performed by contacting the inspection pad and the second connecting electrode CE2 connected to the first electrode 124 and the second electrode 125 of the light-emitting LED with probe pins. If there is a defect in the pixel circuit including the drive transistor DT or the power supply wiring VDD, it may be difficult to properly inspect the light-emitting LED. Therefore, by directly applying an inspection signal to the drive transistor DT and the power supply wiring VDD, as well as to the separate inspection pad and the second connecting electrode CE2, the lighting test can be performed to detect defects in the light-emitting LED at an early stage.

[0133] Next, the first connecting electrode CE1 can make contact with the side reflector SRE and multiple inspection pads at least once, thereby reducing the resistance of the first connecting electrode CE1. For example, multiple contact holes are formed in the second planarization layer 117b and the third planarization layer 117c, allowing the first connecting electrode CE1 to make contact with the side reflector SRE and inspection pads multiple times. Thus, the resistance of the first connecting electrode can be reduced by the numerous contact structures, and the stability of the electrical connection can be improved.

[0134] Accordingly, in the display device 700 according to other embodiments of this specification, each of the multiple sub-pixels SP is provided with an inspection area APA, making it easy to detect defects in the light-emitting element LED. An inspection pad is formed in the inspection area APA, directly connected to the first connecting electrode CE1 connected to the first electrode 124 of the light-emitting element LED, and a second connecting electrode CE2 is formed connected to the second electrode 125 of the light-emitting element LED. After this, the lighting inspection can proceed. By directly applying an inspection signal to the inspection pad and the second connecting electrode CE2, the lighting defect can be detected by applying the inspection signal to the first electrode 124 and the second electrode 125 of the light-emitting element LED. In this case, since the inspection signal is not applied through the drive transistor DT, inspection errors due to defects in the drive transistor DT can be prevented. Accordingly, each of the multiple sub-pixels SP has a built-in inspection area APA, making it possible to quickly and accurately detect defects in the light-emitting element LED.

[0135] Figure 9 is a cross-sectional view of a display device according to yet another embodiment of this specification. The display device 900 in Figure 9 is substantially identical to the display devices 700 in Figures 7 and 8, except for the planarization layer patterns 117ia and 117ib, so a redundant explanation will be omitted.

[0136] Referring to Figure 9, a first planarization layer pattern 117ia and a second planarization layer pattern 117ib are arranged on the first connecting electrode CE1, surrounding the light-emitting element LED. The first planarization layer pattern 117ia and the second planarization layer pattern 117ib are arranged to cover a portion of the first connecting electrode CE1 that covers the light-emitting element LED and the upper portion of the light-emitting element LED. The second electrode 125 of the light-emitting element LED can be exposed from the first planarization layer pattern 117ia and the second planarization layer pattern 117ib and connected to the second connecting electrode CE2.

[0137] The first planarization layer pattern 117ia is the same layer and made of the same material as the second planarization layer 117b, and the second planarization layer pattern 117ib may be the same layer and made of the same material as the third planarization layer 117c.

[0138] The first planarization layer pattern 117ia and the second planarization layer pattern 117ib allow the first connecting electrode CE1 and the second connecting electrode CE2 to be placed in different layers from each other, thereby preventing short-circuit failures between the first connecting electrode CE1 and the second connecting electrode CE2.

[0139] Accordingly, in the display device 900 according to another embodiment of this specification, the upper portion of the light-emitting element LED can be covered with multiple planarization layer patterns 117ia, 117ib. The upper portion of the light-emitting element LED can be easily covered using multiple planarization layer patterns 117ia, 117ib. In particular, the multiple planarization layer patterns 117ia, 117ib can completely cover the first connecting electrode CE1 at the opening of the fourth planarization layer 117d, and short-circuit failure between the first connecting electrode CE1 and the second connecting electrode CE2 can be prevented. Accordingly, multiple planarization layer patterns 117ia, 117ib can be used taking into account the step height of the light-emitting element LED.

[0140] Figure 10 is a cross-sectional view of a display device according to another embodiment of this specification. The display device 1000 in Figure 10 differs from the display devices 700 in Figures 7 and 8 only in that it does not include the planarization layer pattern 117i, and only the second planarization layer 1017b, the third planarization layer 1017c, and the fourth planarization layer 1017d are different, with the other components being substantially the same, so redundant explanations will be omitted.

[0141] Referring to Figure 10, the side surface of the second flattening layer 1017b has a first angle α, and the side surface of the third flattening layer 1017c has a second angle β, and the first angle α and the second angle β may be different from each other. For example, the second angle β may be an angle of 60 degrees or less, and the first angle α may be a smaller angle than the second angle β. For example, the second angle β may be about 55 degrees, and the first angle α may be a smaller angle than the second angle β.

[0142] The first angle α on the side surface of the second flattening layer 1017b and the second angle β on the side surface of the third flattening layer 1017c can be configured to be different from each other. In this case, both the first angle α and the second angle β may be angles of 60 degrees or less, and at least one of the first angle α and the second angle β may have an angle of approximately 55 degrees. The brightness uniformity of the display device 1000 can be improved by designing at least one of the first angle α and the second angle β to an angle that can compensate for brightness non-uniformity due to viewing angle.

[0143] Next, the fourth planarization layer 1017d is positioned to cover the light-emitting element LED and the first connecting electrode CE1. The fourth planarization layer 1017d is positioned to cover the upper portion of the light-emitting element LED and can separate the first connecting electrode CE1 and the second connecting electrode CE2. Only the second electrode 125 of the light-emitting element LED is exposed by the fourth planarization layer 1017d, and the second electrode 125 and the second connecting electrode CE2 can be connected to each other. Thus, the fourth planarization layer 1017d can function as an insulating layer separating the first connecting electrode CE1 and the second connecting electrode CE2 and as a planarization layer pattern 117i that guides the second electrode 125 and the second connecting electrode CE2 to self-align.

[0144] Accordingly, in the display device 1000 according to another embodiment of this specification, the fourth planarization layer 1017d can be used as a planarization layer pattern 117i for self-alignment of the light-emitting element LED and the second connecting electrode CE2, thereby simplifying the structure of the display device 1000.

[0145] The various embodiments of this specification may be described as follows.

[0146] A display device according to one embodiment of this specification includes a substrate on which a plurality of subpixels and a plurality of contact regions between the plurality of subpixels are defined, a light-emitting element disposed in each of the plurality of subpixels, a side reflector disposed in each of the plurality of subpixels and surrounding the light-emitting element, a first connecting electrode electrically connected to the first electrode of the light-emitting element, a planarization layer pattern covering the first connecting electrode and the light-emitting element, and a second connecting electrode disposed on the planarization layer pattern, wherein the first connecting electrode and the second connecting electrode are disposed apart from each other with the planarization layer pattern in between.

[0147] According to other features of this specification, the light-emitting element further includes a first semiconductor layer on which a first electrode is disposed on its upper surface, a light-emitting layer on the first semiconductor layer, a second semiconductor layer on the light-emitting layer, and a second electrode on the upper surface of the second semiconductor layer, the second electrode being exposed from a planarization layer pattern and connected to a second connecting electrode.

[0148] According to other features of this specification, the invention further includes a first planarization layer disposed below a first connecting electrode and surrounding the lower portion of the light-emitting element, a second planarization layer disposed on the first connecting electrode, a third planarization layer disposed between the second planarization layer and a side reflector, and a fourth planarization layer disposed between the side reflector and the second connecting electrode, wherein the second and third planarization layers include openings that overlap with the light-emitting element, and the sides of the second planarization layer and the sides of the third planarization layer at the openings may be disposed apart from the light-emitting element.

[0149] According to other features of this specification, the planarization layer pattern may consist of the same material as either the second planarization layer or the third planarization layer.

[0150] According to other features of this specification, the planarization layer pattern may include a first planarization layer pattern of the same material as the second planarization layer, and a second planarization layer pattern disposed on the first planarization layer pattern and of the same material as the third planarization layer.

[0151] According to other features of this specification, the planarization layer pattern may be exposed from the fourth planarization layer.

[0152] According to other features of this specification, the planarization layer pattern may be made integral with the fourth planarization layer.

[0153] According to other features of this specification, the sides of the third flattening layer are positioned on the second flattening layer and spaced apart from the sides of the second flattening layer, and the sides of the second flattening layer and the sides of the third flattening layer may form a stepped structure.

[0154] According to other features of this specification, the side surface of the second flattening layer has a first angle, the side surface of the third flattening layer has a second angle, and the first and second angles may be 60 degrees or less.

[0155] According to other features of this specification, the first angle and the second angle may be different.

[0156] According to other features of this specification, the side reflectors are positioned on the sides of the second planarization layer and the third planarization layer at the opening, and the distance between the side reflector and the light-emitting element may be constant for one of the multiple subpixels.

[0157] According to other features of this specification, the side reflector may be electrically connected to the first connecting electrode through a plurality of contact holes.

[0158] According to other features of this specification, the present invention further includes a drive transistor located in each of a plurality of subpixels, a first reflective electrode located on and electrically coupled to the drive transistor, power wiring located in a plurality of contact regions, a second reflective electrode located on the power wiring in the plurality of contact regions and electrically coupled to the power wiring, a first contact electrode located in the same layer as the first connecting electrode and electrically coupled to the second reflective electrode, and a second contact electrode located in the same layer as the side reflector and electrically coupled to the first contact electrode, wherein the second connecting electrode may extend to a plurality of contact regions in the plurality of subpixels and be electrically coupled to the second contact electrode.

[0159] According to other features of this specification, the plurality of contact regions may include a first contact region in which a second reflective electrode, a first contact electrode, a second contact electrode, and a second connecting electrode are electrically connected to each other, a second contact region in which the first contact electrode, a second contact electrode, and a second connecting electrode are electrically connected to each other, and a third contact region in which the second contact electrode and a second connecting electrode are electrically connected to each other.

[0160] According to other features of this specification, the invention further includes an inspection area disposed in each of a plurality of subpixels, a first inspection pad disposed on a third planarization layer in the inspection area, and a second inspection pad disposed on a fourth planarization layer in the inspection area, wherein the first and second inspection pads may be electrically connected to a first connecting electrode.

[0161] According to other features of this specification, the first inspection pad may be electrically connected to the first connecting electrode through a side reflector, and the second inspection pad may be electrically connected to the first inspection pad through a contact hole in the fourth planarization layer.

[0162] According to other features of this specification, the second flattening layer includes a first lower edge having a concave arc shape and a first upper edge having a convex arc shape, and the third flattening layer may include a second lower edge having a concave arc shape and a second upper edge having a convex arc shape.

[0163] According to other features of this specification, the first upper edge and the second upper edge may be arc-shaped with the same radius.

[0164] According to another feature of this specification, the curvature of the first lower edge may be greater than the curvature of the second upper edge.

[0165] According to other features of this specification, the arc of the second lower edge may be positioned at the end of the arc of the first upper edge.

[0166] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments and can be modified and implemented in various ways without deviating from the technical concept of this specification. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Accordingly, the embodiments described above should be understood to be illustrative and non-limiting in all respects. All technical concepts within the scope equivalent to the claims of this specification should be construed as being included in the scope of rights of this specification.

Claims

1. A substrate in which multiple subpixels are defined, Each of the aforementioned plurality of subpixels is an illuminated element, A side reflector is placed in each of the plurality of subpixels and surrounds the light-emitting element. A first connecting electrode electrically connected to the first electrode of the light-emitting element, The first connecting electrode and the planarization layer pattern disposed on the light-emitting element, and Includes a second connecting electrode disposed on the planarization layer pattern, A display device in which the first connecting electrode and the second connecting electrode are arranged spaced apart from each other with the planarization layer pattern in between.

2. The light-emitting element is A first semiconductor layer on which the first electrode is arranged on the upper surface, The light-emitting layer on the aforementioned first semiconductor layer, The second semiconductor layer on the aforementioned light-emitting layer, and The second electrode further includes the upper surface of the second semiconductor layer, The display device according to claim 1, wherein the second electrode is exposed from the planarization layer pattern and connected to the second connecting electrode.

3. A first planarization layer is positioned below the first connecting electrode and surrounds the lower portion of the light-emitting element. A second planarization layer disposed on the first connecting electrode, A third flattening layer disposed between the second flattening layer and the side reflector, and The present invention further includes a fourth planarizing layer disposed between the side reflector and the second connecting electrode, The display device according to claim 2, wherein the second planarization layer and the third planarization layer include an opening that overlaps with the light-emitting element, and the side surfaces of the second planarization layer and the side surfaces of the third planarization layer are arranged to be separated from the light-emitting element at the opening.

4. The display device according to claim 3, wherein the planarization layer pattern is made of the same material as either the second planarization layer or the third planarization layer.

5. The planarization layer pattern is, A first planar layer pattern made of the same material as the second planar layer, and The display device according to claim 3, further comprising a second planarization layer pattern disposed on the first planarization layer pattern and made of the same material as the third planarization layer.

6. The display device according to claim 3, wherein the planarization layer pattern is exposed from the fourth planarization layer.

7. The display device according to claim 3, wherein the planarization layer pattern is integral with the fourth planarization layer.

8. The display device according to claim 3, wherein the side surface of the third flattening layer is arranged on the second flattening layer and spaced apart from the side surface of the second flattening layer, and the side surface of the second flattening layer and the side surface of the third flattening layer form a stepped structure.

9. The side surface of the second flattening layer has a first angle, and the side surface of the third flattening layer has a second angle. The display device according to claim 8, wherein the first angle and the second angle are 60 degrees or less.

10. The display device according to claim 9, wherein the first angle and the second angle are different.

11. The side reflectors are arranged on the side surfaces of the second flattening layer and the third flattening layer at the opening. The display device according to claim 8, wherein the distance between the side reflector and the light-emitting element is constant in one of the plurality of subpixels.

12. The display device according to claim 8, wherein the side reflector is electrically connected to the first connecting electrode through a plurality of contact holes.

13. The substrate further includes a plurality of contact regions arranged between the plurality of subpixels, The aforementioned display device is A drive transistor arranged in each of the aforementioned multiple subpixels, A first reflective electrode is placed on the drive transistor and electrically connected to the drive transistor, Power wiring arranged in the plurality of contact areas, A second reflective electrode is arranged on the power supply wiring in the plurality of contact regions and is electrically connected to the power supply wiring. A first contact electrode, which is arranged in the same layer as the first connecting electrode and is electrically connected to the second reflecting electrode, and It further includes a second contact electrode, which is arranged in the same layer as the side reflector and is electrically connected to the first contact electrode. The display device according to claim 8, wherein the second connecting electrode extends from the plurality of subpixels to the plurality of contact regions and is electrically connected to the second contact electrode.

14. The aforementioned multiple contact areas are The first contact region in which the second reflective electrode, the first contact electrode, the second contact electrode, and the second connecting electrode are electrically connected to each other, The first contact electrode, the second contact electrode, and the second connecting electrode are electrically connected to each other in a second contact region, and The display device according to claim 13, further comprising a third contact region to which the second contact electrode and the second connecting electrode are electrically connected.

15. Inspection area arranged in each of the aforementioned multiple subpixels, In the inspection area, the first inspection pad is placed on the third planarization layer, and The inspection area further includes a second inspection pad disposed on the fourth flattening layer, The display device according to claim 3, wherein the first inspection pad and the second inspection pad are electrically connected to the first connecting electrode.

16. The first inspection pad is electrically connected to the first connecting electrode through the side reflector, The display device according to claim 15, wherein the second inspection pad is electrically connected to the first inspection pad through the contact holes of the fourth planarization layer.

17. The second flattening layer includes a first lower edge having a concave arc shape and a first upper edge having a convex arc shape. The display device according to claim 8, wherein the third flattening layer includes a second lower edge having a concave arc shape and a second upper edge having a convex arc shape.

18. The display device according to claim 17, wherein the first upper edge and the second upper edge are arc-shaped with the same radius.

19. The display device according to claim 17, wherein the curvature of the first lower edge is greater than the curvature of the second upper edge.

20. The display device according to claim 17, wherein the arc of the second lower edge is continuously arranged at the end of the arc of the first upper edge.

Images