EMBEDDED SHIELD STRUCTURE FOR POWER SEMICONDUCTOR DEVICES INCLUDING A SEGMENTED SUPPORT SHIELD STRUCTURE FOR REDUCED ON-RESISTANCE AND ASSOCIATED MANUFACTURING METHODS

Abstract

The semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type above the drift region, a gate on the semiconductor layer structure adjacent to the well region, and either a buried shielding structure of the second conductivity type below the well region and separated from the well region by a portion of the drift region, or one or more laterally discontinuous extending contact shielding structures of the second conductivity type extending vertically from the well region to the drift region. [Reference figure] Figure 2A

Description

[Technical Field]

[0001] Priority claims This application claims priority to U.S. Patent Application No. 18 / 472,343, filed September 22, 2023, and U.S. Patent Application No. 18 / 150,432, filed January 5, 2023, the contents of which are incorporated herein by reference in their entireties.

[0002] The present invention relates to semiconductor devices, and more particularly to power semiconductor devices. [Background technology]

[0003] A power semiconductor device refers to a device containing one or more “power” semiconductor dies designed to pass large currents (e.g., tens or hundreds of amperes) and capable of blocking high voltages (e.g., hundreds, thousands, or tens of thousands of volts). A wide variety of power semiconductor devices are known in the art, including, for example, power metal-insulator-semiconductor field-effect transistors (“MISFETs,” including metal-oxide-semiconductor FETs (“MOSFETs”)), bipolar junction transistors (“BJTs”), insulated-gate bipolar transistors (“IGBTs”), junction-barrier Schottky diodes, gate-turn-off transistors (“GTOs”), MOS-controlled thyristors, and various other devices. These power semiconductor devices are typically fabricated from wide-bandgap semiconductor materials, e.g., silicon carbide (“SiC”) or Group III-nitride (e.g., gallium nitride (“GaN”))-based semiconductor materials. As used herein, wide-bandgap semiconductor materials refer to semiconductor materials having a bandgap greater than about 1.40 eV, e.g., greater than about 2 eV.

[0004] A conventional power semiconductor device typically has a semiconductor substrate having a first conductivity type (e.g., an n-type substrate) on which an epitaxial layer structure having the first conductivity type (e.g., n-type) is formed. A portion of this epitaxial layer structure (which may include one or more separate layers) functions as the drift layer or drift region of the power semiconductor device. The device typically includes an "active region" that includes one or more "unit cell" structures having junctions, e.g., p-n junctions. The active region may be formed on and / or within the drift region. The active region serves as a primary junction for blocking voltage in the reverse bias direction and enabling current flow in the forward bias direction. The power semiconductor device may further have an edge termination in a termination region adjacent to the active region. One or more power semiconductor devices may be formed on the substrate, and each power semiconductor device will typically have its own edge termination. After the substrate is fully processed, the resulting structure may be diced to separate the individual edge-terminated power semiconductor devices.

[0005] A power semiconductor device can have a unit cell configuration in which many individual unit cell structures of an active region are electrically connected (e.g., in parallel) to function as a single power semiconductor device. In high-power applications, such a power semiconductor device can include thousands or tens of thousands of unit cells embodied in a single chip or “die.” A die or chip can include a small block of semiconducting material or other substrate in which electronic circuit elements are fabricated. For example, a plurality of individual power semiconductor devices may be formed on a relatively large semiconductor substrate (such as by growing epitaxial layers on the relatively large semiconductor substrate, doping selected regions with dopants, forming insulating and metal layers thereon), and the completed structure may then be cut (e.g., by sawing or dicing operations) into a plurality of individual dies, each of which is a power semiconductor device.

[0006] Power semiconductor devices can have lateral and vertical structures. In a device having a lateral structure, the terminals of the device (e.g., the drain, gate, and source terminals for a power MOSFET device) are on the same major surface (e.g., the top or bottom) of the semiconductor layer structure. In contrast, in a device having a vertical structure, at least one terminal is provided on each major surface of the semiconductor layer structure (e.g., in a vertical MOSFET device, the source may be on the top surface of the semiconductor layer structure and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include an underlying substrate. As used herein, the term "semiconductor layer structure" refers to a structure including one or more semiconductor layers, including a semiconductor substrate and / or a semiconductor epitaxial layer.

[0007] Vertical power semiconductor devices, such as MOSFET or IGBT devices, may have a standard gate electrode design in which the transistor's gate electrode is formed on top of a semiconductor layer structure (referred to herein as a planar gate device), or alternatively, may have the gate electrode buried in a trench inside the semiconductor layer structure (referred to as a gate trench device). With a standard gate electrode design, the channel region of each unit cell transistor is disposed horizontally directly beneath the gate electrode. In contrast, in a gate trench design, the channel is disposed vertically. Gate trench devices can offer enhanced performance but typically require a more complex production process.

[0008] Power semiconductor devices are designed to block (in forward or reverse blocking states) or pass (in forward operating states) large voltages and / or currents. For example, in blocking states, power semiconductor devices may be designed to withstand hundreds or thousands of potential volts. As the applied voltage approaches or passes the voltage level at which the device is designed to block, a significant level of current (called leakage current) may begin to flow through the power semiconductor device. The blocking capability of a device may be a function of, among other things, the doping density / concentration and the thickness of the drift region. Leakage current may also arise for other reasons, such as failure of the edge termination and / or primary junction of the device. If the voltage applied to a device is increased beyond the breakdown voltage to a critical level, the increasing electric field may lead to uncontrolled and unwanted runaway generation of charge carriers within the semiconductor device, leading to a condition known as avalanche breakdown. Summary of the Invention

[0009] In some embodiments, a semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type above the drift region, a gate on the semiconductor layer structure adjacent to the well region, and a buried shielding structure of the second conductivity type below the well region and separated from the well region by a portion of the drift region.

[0010] In some embodiments, at least one contact shield structure of the second conductivity type extends vertically into the drift region and is laterally spaced from the gate, and a buried shield structure extends laterally in the drift region from below the well region to the at least one contact shield structure.

[0011] In some embodiments, the semiconductor layer structure further comprises a gate trench having sidewalls and a bottom surface between the sidewalls and extending into the drift region, the gate being within the gate trench. A bottom shielding structure of the second conductivity type is provided below the bottom surface of the gate trench. The buried shielding structure extends laterally from the bottom shielding structure to the at least one contact shielding structure.

[0012] In some embodiments, at least one of the buried shielding structure and the contact shielding structure comprises a material that is different from the material of the drift region.

[0013] In some embodiments, the drift region comprises a wide bandgap semiconductor material, and at least one of the buried shielding structure and the contact shielding structure comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

[0014] In some embodiments, the buried shielding structure has a different concentration of the second conductivity type dopant than the well region.

[0015] In some embodiments, the semiconductor layer structure further comprises a substrate, with the drift region on the substrate, and a drain contact on the substrate opposite the drift region, and the buried shielding structure extends laterally into the drift region between the well region and the drain contact.

[0016] In some embodiments, the semiconductor layer structure further comprises a current spreading region of the first conductivity type extending between the well region and the drain contact, the current spreading region having a greater dopant concentration than the drift region.

[0017] In some embodiments, the embedded shielding structure comprises a pattern including one or more segments extending in a first lateral direction, and the gate extends in a second lateral direction different from the first lateral direction.

[0018] In some embodiments, the width of each of the one or more segments along the second lateral direction is about 0.1 to 20 μm.

[0019] In some embodiments, one or more segments and / or gates of the embedded shielding structure present a rectilinear, elliptical, or polygonal shape in plan view.

[0020] In some embodiments, the one or more segments are laterally spaced apart such that at least a portion of the conductive path between the well region and the drain contact extends laterally along the second laterally embedded shielding structure.

[0021] In some embodiments, the gate comprises a first gate of a first transistor in the semiconductor layer structure, and the buried shielding structure comprises a second gate of a second transistor in the semiconductor layer structure.

[0022] In some embodiments, the first and second transistors are electrically coupled in a cascode amplifier configuration.

[0023] In some embodiments, the semiconductor layer structure further comprises a source region of the first conductivity type above the well region, and a source contact is provided on a surface of the semiconductor layer structure opposite the drain contact, the source contact being electrically coupled to the source region and the buried shielding structure.

[0024] In some embodiments, a semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type, a buried shield structure of a second conductivity type within the drift region, a well region of the second conductivity type above the drift region, and a source region of the first conductivity type above the well region, wherein the source region, the well region, and a first portion of the drift region between the well region and the buried shield structure provide a p-n junction of a first transistor, and the first portion of the drift region, the buried shield structure, and a second portion of the drift region provide a p-n junction of a second transistor.

[0025] In some embodiments, a gate is provided on the semiconductor layer structure adjacent the well region, the gate comprising a first gate of the first transistor, and the recessed shielding structure comprising a second gate of the second transistor.

[0026] In some embodiments, the first and second transistors are electrically coupled in a cascode amplifier configuration.

[0027] In some embodiments, a source contact is provided on a surface of the semiconductor layer structure opposite the drain contact, the source contact being electrically coupled to the source region and the buried shielding structure.

[0028] In some embodiments, a gate trench having sidewalls and a bottom surface between the sidewalls extends into the drift region, and the gate is within the gate trench. At least one contact shielding structure of the second conductivity type extends vertically from the sidewalls of the gate trench into the laterally spaced drift region and contacts the buried shielding structure, or a metal layer extends from the source contact along at least one of the sidewalls of the gate trench and contacts the buried shielding structure.

[0029] According to some embodiments, a semiconductor device includes a semiconductor layer structure having a first surface and a second surface opposite the first surface, a gate adjacent to the first surface of the semiconductor structure, a drain contact on the second surface of the semiconductor structure, and first and second transistors in the semiconductor layer structure electrically coupled in a cascode amplifier configuration between the first and second surfaces of the semiconductor layer structure.

[0030] In some embodiments, the semiconductor layer structure comprises a drift region of a first conductivity type, a buried shield structure of a second conductivity type in the drift region, a well region of the second conductivity type above the drift region, and a source region of the first conductivity type above the well region, wherein the source region, the well region, and a first portion of the drift region between the well region and the buried shield structure implement a first transistor, and the first portion of the drift region, the buried shield structure, and a second portion of the drift region implement a second transistor.

[0031] In some embodiments, a source contact is provided on the first surface of the semiconductor layer structure, the source contact being electrically coupled to the source region and the buried shielding structure.

[0032] In some embodiments, the semiconductor layer structure further comprises a gate trench having sidewalls and a bottom surface between the sidewalls and extending into the drift region, the gate being within the gate trench. At least one contact shielding structure of the second conductivity type extends vertically from the sidewalls of the gate trench into the laterally spaced drift region and contacts the buried shielding structure, or a metal layer extends from the source contact along at least one of the sidewalls of the gate trench and contacts the buried shielding structure.

[0033] In some embodiments, a method of manufacturing a semiconductor device includes providing a drift region of a first conductivity type; providing a buried shielding structure of a second conductivity type in the drift region; providing a well region of the second conductivity type above the drift region and spaced apart from the buried shielding structure, wherein the drift region, the buried shielding structure, and the well region form a semiconductor layer structure; and providing a gate on the semiconductor layer structure adjacent to the well region.

[0034] In some embodiments, the buried shielding structure comprises a pattern including one or more segments extending laterally into the drift region.

[0035] In some embodiments, providing the buried shielding structure includes forming a first portion of the drift region by a first epitaxy process, forming the buried shielding structure in or on the first portion of the drift region, and forming a second portion of the drift region on the buried shielding structure by a second epitaxy process.

[0036] In some embodiments, forming the buried shielding structure includes implanting a dopant of the second conductivity type into the first portion of the drift region or depositing a material of the second conductivity type on the first portion of the drift region to form the buried shielding structure.

[0037] In some embodiments, the method further includes forming a mask pattern over the first portion of the drift region prior to the implanting or depositing step, wherein the implanting or depositing step is performed in or over areas of the drift region exposed by the mask pattern to form the pattern of the buried shielding structure.

[0038] In some embodiments, the implanting or depositing step is performed as a blanket process without a mask pattern, and the method further includes, after the implanting or depositing step, forming a mask pattern over the first portion of the drift region and performing an etching process on areas of the first portion of the drift region exposed by the mask pattern to form a pattern of the buried shielding structure.

[0039] In some embodiments, the method further includes forming a current spreading region in the first portion of the drift region, the current spreading region including a greater concentration of dopants of the first conductivity type. The buried shielding structure extends adjacent to the current spreading region.

[0040] In some embodiments, providing the buried shielding structure includes forming a mask pattern on the surface of the drift region and implanting dopants of the second conductivity type into areas of the drift region exposed by the mask pattern at an implant energy corresponding to a predetermined depth below the surface of the drift region to form the pattern of the buried shielding structure.

[0041] In some embodiments, the semiconductor layer structure includes a substrate, the drift region is on the substrate, and the method further includes providing a drain contact on the substrate opposite the drift region, the buried shielding structure extending laterally into the drift region between the well region and the drain contact.

[0042] In some embodiments, the gate comprises a first gate of a first transistor in the semiconductor layer structure, and the buried shielding structure comprises a second gate of a second transistor in the semiconductor layer structure.

[0043] In some embodiments, the first and second transistors are electrically coupled in a cascode amplifier configuration.

[0044] In some embodiments, the method further includes providing a source region of the first conductivity type above the well region and providing a source contact on a surface of the semiconductor layer structure opposite the drain contact, the source contact electrically coupled to the source region and the buried shielding structure.

[0045] In some embodiments, providing the gate includes forming a gate trench having sidewalls and a bottom surface between the sidewalls, the gate trench extending through the source region and the well region into the surface of the semiconductor to a depth of about 0.3 to about 10 μm relative to the surface; and forming a gate in the gate trench.

[0046] In some embodiments, the method further includes forming at least one contact shielding structure of the second conductivity type extending vertically from a sidewall of the gate trench to the laterally spaced-apart drift region to contact the buried shielding structure, or forming a metal layer extending from the source contact along at least one of the sidewalls of the gate trench to contact the buried shielding structure.

[0047] In some embodiments, the one or more segments extend in a first lateral direction and the gate extends in a second lateral direction different from the first lateral direction, and the width of each of the one or more segments along the second lateral direction is about 0.1-20 μm.

[0048] In some embodiments, one or more segments and / or gates of the embedded shielding structure present a rectilinear, elliptical, or polygonal shape in plan view.

[0049] In some embodiments, the buried shielding structure has a different concentration of the second conductivity type dopant than the well region.

[0050] In some embodiments, the buried shielding structure comprises a material that is different from the material of the drift region.

[0051] In some embodiments, a method of manufacturing a semiconductor device includes forming a first portion of a drift region, forming a buried shielding structure of a second conductivity type in or on the first portion of the drift region, forming a second portion of the drift region on the buried shielding structure, forming a well region of the second conductivity type above the drift region and spaced from the buried shielding structure, wherein the drift region, the buried shielding structure, and the well region form a semiconductor layer structure, and forming a gate on the layer structure adjacent to the well region.

[0052] In some embodiments, the buried shielding structure comprises a pattern including one or more segments extending laterally into the drift region, and forming the buried shielding structure includes implanting a dopant of the second conductivity type into a first portion of the drift region or depositing a material of the second conductivity type on the first portion of the drift region to form the buried shielding structure.

[0053] In some embodiments, the method further includes forming a mask pattern on the first portion of the drift region prior to the implanting or depositing step, and the implanting or depositing step is performed in or on areas of the first portion of the drift region exposed by the mask pattern to form a pattern of the buried shielding structure in or on areas of the first portion of the drift region.

[0054] In some embodiments, the implanting or depositing step is performed as a blanket process without a mask pattern, and the method further includes, after the implanting or depositing step, forming a mask pattern on the first portion of the drift region and performing an etching process on areas of the first portion of the drift region exposed by the mask pattern to form a pattern of the buried shielding structure.

[0055] In some embodiments, a method for manufacturing a semiconductor device includes forming a drift region of a first conductivity type; forming a buried shielding structure of a second conductivity type in the drift region below a surface of the drift region; forming a well region of the second conductivity type above the drift region and spaced from the buried shielding structure, wherein the drift region, the buried shielding structure, and the well region form a semiconductor layer structure; and forming a gate on the semiconductor layer structure adjacent to the well region.

[0056] In some embodiments, the buried shielding structure comprises a pattern including one or more segments extending laterally into the drift region, and forming the buried shielding structure comprises forming a mask pattern on a surface of the drift region and implanting dopants of the second conductivity type into areas of the drift region exposed by the mask pattern at an implant energy corresponding to a predetermined depth below the surface of the drift region to form the pattern of the buried shielding structure.

[0057] In some embodiments, a semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type above the drift region, a gate on the semiconductor layer structure adjacent the well region, and one or more laterally discontinuous contact shielding structures of the second conductivity type extending vertically into the drift region.

[0058] In some embodiments, the contact shielding structure includes a plurality of separate segments extending longitudinally in one or more lateral directions. For example, the contact shielding structure may include a support shielding structure extending longitudinally in a first lateral direction and spaced apart from the gate. Additionally or alternatively, the contact shielding structure may include a bridge shielding structure extending in a second lateral direction that intersects the first lateral direction to contact a bottom shielding structure of a second conductivity type in the drift region below the gate.

[0059] In some embodiments, at least one of the supporting shielding structure or the bridge shielding structure comprises separate segments.

[0060] In some embodiments, the semiconductor layer structure further includes a gate trench having opposing sidewalls and a bottom surface between the sidewalls and extending into the drift region, the gate being within the gate trench. The bottom shielding structure can extend below the bottom surface of the gate trench.

[0061] In some embodiments, the bridge shielding structure extends along both opposing sidewalls of the gate trench.

[0062] In some embodiments, the bridge shielding structures comprise separate segments, one of the opposing sidewalls of the gate trench having one of the bridge shielding structures thereon and the other of the opposing sidewalls of the gate trench not having one of the bridge shielding structures thereon.

[0063] In some embodiments, the bottom shielding structure extends continuously below the gate.

[0064] In some embodiments, the bottom shielding structure includes one or more separate segments that extend below the gate.

[0065] In some embodiments, the semiconductor device further includes one or more laterally extending recessed shielding structures beneath the well region and separated from the well region by a portion of the drift region.

[0066] In some embodiments, the bottom shielding structure and / or the gate have a rectilinear, elliptical, or polygonal shape in plan view.

[0067] In some embodiments, at least a portion of the conductive path between the well region and the drain contact extends laterally beneath the bridge shielding structure.

[0068] In some embodiments, the respective spacings between the separate segments are aligned along a direction transverse to one or more lateral directions.

[0069] In some embodiments, each spacing between distinct segments is staggered along a direction transverse to one or more lateral directions.

[0070] In some embodiments, the respective spacing between the distinct segments is less than the respective width of the distinct segments.

[0071] In some embodiments, the width of each of the discrete segments is from about 0.1 to about 20 μm.

[0072] In some embodiments, the semiconductor layer structure further comprises a substrate, the drift region on the substrate, and a drain contact on the substrate opposite the drift region, wherein each spacing between the separate segments includes a portion of the semiconductor layer structure that is free of a contact shielding structure.

[0073] In some embodiments, the semiconductor layer structure further comprises a source region of the first conductivity type above the well region, a source contact on a surface of the semiconductor layer structure opposite the drain contact, and the source contact is electrically coupled to the source region and the contact shield structure.

[0074] In some embodiments, the contact shield structure has a different material and / or dopant concentration than that of the drift region.

[0075] In some embodiments, a semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type above the drift region, a gate on the semiconductor layer structure adjacent the well region, a support shielding structure of the second conductivity type extending vertically from the well region into the drift region and spaced apart from the gate, and a bridge shielding structure of the second conductivity type extending laterally from the support shielding structure toward the gate, wherein at least one of the support shielding structure or the bridge shielding structure comprises a plurality of separate segments.

[0076] In some embodiments, the separate segments extend longitudinally in one or more lateral directions, respectively.

[0077] In some embodiments, the semiconductor device further includes a bottom shielding structure of the second conductivity type in the drift region below the gate, and the bridge shielding structure extends laterally from the support shielding structure so as to contact the bottom shielding structure.

[0078] In some embodiments, the semiconductor layer structure further includes a gate trench having opposing sidewalls and a bottom surface between the sidewalls and extending into the drift region, the gate being in the gate trench, and the bottom shielding structure extending below the bottom surface of the gate trench.

[0079] In some embodiments, the bridge shielding structure extends along both opposing sidewalls of the gate trench.

[0080] In some embodiments, the bridge shield structure comprises separate segments, one of the opposing sidewalls of the gate trench having a bridge shield structure thereon and the other of the opposing sidewalls of the gate trench being free of the bridge shield structure.

[0081] In some embodiments, the supporting shielding structure has a different material and / or dopant concentration than that of the bridge shielding structure.

[0082] In some embodiments, the respective spacing between the separate segments is less than the respective width of the separate segments along a direction transverse to one or more lateral directions.

[0083] According to some embodiments, a semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type above the drift region, a gate on the semiconductor layer structure adjacent the well region, and a contact shielding structure of the second conductivity type extending vertically from the well region to the drift region and including a plurality of segments having respective spacings between the segments, each spacing being less than a respective width of the segment.

[0084] In some embodiments, the width of each of the segments is from about 0.1 μm to about 20 μm.

[0085] In some embodiments, the semiconductor device has an about 5% to about 30% increase in avalanche ruggedness and an about 5% to about 30% decrease in on-resistance compared to a semiconductor device having a continuous shielding pattern.

[0086] In some embodiments, the segments extend longitudinally in one or more lateral directions, respectively, with respective spacings between the segments.

[0087] In some embodiments, each spacing between distinct segments is staggered along a direction transverse to one or more lateral directions.

[0088] In some embodiments, the respective spacings between the separate segments are aligned along a direction transverse to one or more lateral directions.

[0089] In some embodiments, the semiconductor layer structure further comprises a substrate, the drift region on the substrate, and a drain contact on the substrate opposite the drift region, each interval including a portion of the semiconductor layer structure that is free of the contact shielding structure.

[0090] In some embodiments, the contact shield structure comprises a support shield structure extending in the first laterally direction and spaced apart from the gate.

[0091] In some embodiments, the semiconductor device further includes a bottom shielding structure of the second conductivity type in the drift region below the gate, and the contact shielding structure further includes a bridge shielding structure extending in a second laterally direction transverse to the first laterally direction to contact the bottom shielding structure.

[0092] In some embodiments, at least one of the supporting shielding structure or the bridge shielding structure comprises a segment.

[0093] In some embodiments, at least a portion of the conductive path between the well region and the drain contact extends laterally beneath the bridge shielding structure.

[0094] Other devices, apparatus, and / or methods according to some embodiments will become apparent to one of ordinary skill in the art upon review of the following drawings and detailed description. Any and all combinations of the above embodiments, as well as all such additional embodiments, are intended to be included within this description, be within the scope of the present invention, and be protected by the accompanying claims. [Brief explanation of the drawings]

[0095] [Figure 1A] FIG. 1 is a schematic cross-sectional view illustrating an exemplary unit cell of a gate trench power semiconductor device including a bottom shielding region disposed below the gate trench. [Figure 1B] FIG. 1 is a schematic cross-sectional view illustrating an exemplary unit cell of a gate trench power semiconductor device including a shielding region below the gate trench and disposed along one sidewall of the gate trench. [Figure 2A] 1 is a schematic cross-sectional view illustrating an exemplary unit cell of a gate trench power semiconductor device including an embedded shielding structure according to some embodiments of the present disclosure. [Figure 2B] 1 is a schematic cross-sectional view illustrating an exemplary unit cell of a planar gate power semiconductor device including an embedded shielding structure according to some embodiments of the present disclosure. [Figure 3A] 1A-1C are plan views illustrating patterns of buried shielding structures and gate electrodes (including gate trenches or planar gate structures) according to some embodiments of the present disclosure. [Figure 3B-3C] 3B is a cross-sectional view of the gate trench structure of FIG. 3A or 3E taken along lines BB, CC, and DD. [Figure 3D] 3B is a cross-sectional view of the gate trench structure of FIG. 3A or 3E taken along lines BB, CC, and DD. [Figure 3E] 1A-1C are plan views illustrating patterns of buried shielding structures and gate electrodes (including gate trenches or planar gate structures) according to some embodiments of the present disclosure. [Figure 4A]1A-1C are plan views illustrating patterns of buried shielding structures and gate electrodes (including gate trenches or planar gate structures) according to some embodiments of the present disclosure. [Figure 4B-4C] 4A or 4D are cross-sectional views taken along lines B'-B' and C'-C' of the gate trench structure. [Figure 4D] 1A-1C are plan views illustrating patterns of recessed shielding structures and gate electrodes (including gate trenches or planar gate structures) according to some embodiments of the disclosure. [Figure 5A] 1A-1C are plan views illustrating patterns of buried shielding structures and gate electrodes (including gate trenches or planar gate structures) according to some embodiments of the present disclosure. [Figure 5B-5C] 5B is a cross-sectional view of the gate trench structure of FIG. 5A taken along lines B"-B" and C"-C". [Figure 6] 1 is a perspective view illustrating a gate trench power semiconductor device including a recessed shielding structure according to some embodiments of the present disclosure. FIG. [Figure 7] 1A-1C are equivalent circuit diagrams illustrating transistor configurations that may be implemented in power semiconductor devices including recessed shielding structures according to some embodiments of the present disclosure. [Figure 8A] 1A and 1B are plan views illustrating patterns of buried shielding structures and gate electrodes according to some embodiments of the present disclosure. [Figure 8B-8C] 8B-8B, 8C-8C, and 8D-8D are cross-sectional views of the gate trench structure of FIG. 8A taken along lines 8B-8B, 8C-8C, and 8D-8D. [Figure 8D] 8B-8B, 8C-8C, and 8D-8D are cross-sectional views of the gate trench structure of FIG. 8A taken along lines 8B-8B, 8C-8C, and 8D-8D. [Figure 9A] 1A and 1B are plan views illustrating patterns of buried shielding structures and gate electrodes according to some embodiments of the present disclosure. [Figure 9B-9C] 9B-9B, 9C-9C, and 9D-9D are cross-sectional views of the gate trench structure of FIG. 9A taken along lines 9B-9B, 9C-9C, and 9D-9D. [Figure 9D]9B-9B, 9C-9C, and 9D-9D are cross-sectional views of the gate trench structure of FIG. 9A taken along lines 9B-9B, 9C-9C, and 9D-9D. [Figure 10A] 1A and 1B are plan views illustrating patterns of buried shielding structures and gate electrodes according to some embodiments of the present disclosure. [Figures 10B-10C] 10B / C-10B / C is a cross-sectional view of an alternative example of the gate trench structure of FIG. 10A taken along line 10B / C-10B / C. [Figures 11A-11C] 3B is a cross-sectional view taken along lines BB and CC of the gate trench structure of FIG. 3A illustrating a method of manufacturing a power semiconductor device including a recessed shielding structure according to some embodiments of the present disclosure. [Figures 11D-11E] 3B is a cross-sectional view taken along lines BB and CC of the gate trench structure of FIG. 3A illustrating a method of manufacturing a power semiconductor device including a recessed shielding structure according to some embodiments of the present disclosure. [Figures 12A-12C] 3B is a cross-sectional view taken along lines BB and CC of the gate trench structure of FIG. 3A illustrating a method of manufacturing a power semiconductor device including a recessed shielding structure according to some embodiments of the present disclosure. [Figures 12D-12F] 3B is a cross-sectional view taken along lines BB and CC of the gate trench structure of FIG. 3A illustrating a method of manufacturing a power semiconductor device including a recessed shielding structure according to some embodiments of the present disclosure. [Figures 13A-13C] 3B is a cross-sectional view taken along lines BB and CC of the gate trench structure of FIG. 3A illustrating a method of manufacturing a power semiconductor device including a recessed shielding structure according to some embodiments of the present disclosure. [Figure 13D-13E] 3B is a cross-sectional view taken along lines BB and CC of the gate trench structure of FIG. 3A illustrating a method of manufacturing a power semiconductor device including a recessed shielding structure according to some embodiments of the present disclosure. [Figures 14A-14D] 3B is a cross-sectional view taken along lines BB and CC of the planar gate structure of FIG. 3A illustrating a method of manufacturing a power semiconductor device including a recessed shielding structure according to some embodiments of the present disclosure. [Figures 15A-15D] 3B is a cross-sectional view taken along lines BB and CC of the gate trench structure of FIG. 3A illustrating a method of manufacturing a power semiconductor device including a recessed shielding structure according to some embodiments of the present disclosure. [Figure 16A] 1A-1C are plan views illustrating patterns of contact shielding structures including segmented support shielding structures and gate electrodes according to some embodiments of the present disclosure. [Figures 16B-16C] 16B-16B and 16C-16C are cross-sectional views of the gate trench structure of FIG. 16A taken along lines 16B-16B and 16C-16C. [Figure 16D] 16D is a cross-sectional view of the gate trench structure of FIG. 16A taken along line 16D-16D. [Figure 17A] 1A-1C are plan views illustrating patterns of contact shielding structures including segmented support shielding structures and gate electrodes according to some embodiments of the present disclosure. [Figures 17B-17C] 17B-17B and 17C-17C are cross-sectional views of the gate trench structure of FIG. 17A. [Figures 17D-17E] 17D-17D and 17E-17E are cross-sectional views of the gate trench structure of FIG. 17A taken along lines 17D-17D and 17E-17E. [Figure 18A] 1A-1C are plan views illustrating patterns of contact shielding structures including segmented support shielding structures and gate electrodes according to some embodiments of the present disclosure. [Figures 18B-18C] 18B is a cross-sectional view taken along lines 18B-18B and 18C-18C of the gate trench structure of FIG. 18A. [Figure 18D] 18D is a cross-sectional view of the gate trench structure of FIG. 18A taken along line 18D-18D. [Figure 19A] 1A-1C are plan views illustrating patterns of contact shielding structures including segmented support shielding structures and gate electrodes according to some embodiments of the present disclosure. [Figures 19B-19C] 19B-19B and 19C-19C are cross-sectional views of the gate trench structure of FIG. 19A taken along lines 19B-19B and 19C-19C. [Figure 19D]19D is a cross-sectional view of the gate trench structure of FIG. 19A taken along line 19D-19D. [Figures 20A-20B] 1A and 1B are plan views illustrating patterns of a contact shielding structure including segmented support shielding structures and square trenched gate electrodes according to some embodiments of the present disclosure. [Figure 20C] 1A and 1B are plan views illustrating patterns of a contact shielding structure including segmented support shielding structures and square trenched gate electrodes according to some embodiments of the present disclosure. [Figures 21A-21B] 1A-1C are plan views illustrating patterns of contact shielding structures including segmented support shielding structures and hexagonal trench gate electrodes according to some embodiments of the present disclosure. [Figure 21C] 1A-1C are plan views illustrating patterns of contact shielding structures including segmented support shielding structures and hexagonal trench gate electrodes according to some embodiments of the present disclosure. [Figures 22A-22B] 1A and 1B are plan views illustrating exemplary segments of a support or bridge shielding structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0096] Some embodiments of the present invention are directed to improvements in power semiconductor devices (e.g., MOSFETs, IGBTs, and other gate-controlled power devices). In devices with gate electrodes and gate insulating layers formed inside trenches in a semiconductor layer structure, high electric fields can degrade the gate insulating layer over time, eventually causing device failure. Deep shielding structures (also referred to herein as bottom shielding structures) may be provided directly below the gate trenches to reduce electric field levels in the gate insulating layer, especially at the corners of the gate trenches where the electric field levels may be more concentrated. The bottom shielding structures may have the same conductivity type as the well regions, which is opposite to the conductivity type of the drift region.

[0097] The bottom shielding structure may typically include a highly doped semiconductor region having the same conductivity type as the channel region. Methods for doping semiconductor materials with n-type and / or p-type dopants include (1) doping the semiconductor material during growth, (2) diffusing the dopants into the semiconductor material, and (3) using ion implantation to selectively implant the dopants into the semiconductor material. When silicon carbide is doped during epitaxial growth, the dopants tend to accumulate non-uniformly; therefore, the dopant concentration can vary, for example, by + / - 15%, which can negatively affect device operation and / or reliability. Furthermore, doping by diffusion is not an option in silicon carbide, gallium nitride, and various wide-bandgap semiconductor devices because n-type and p-type dopants tend not to diffuse well (or at all) in these materials, even at high temperatures.

[0098] In light of the above, ion implantation is often used to dope wide-bandgap semiconductor materials, such as silicon carbide. The depth to which ions are implanted is directly related to the energy of the implant; i.e., ions implanted into a semiconductor layer with higher energies tend to penetrate deeper into the layer. However, when dopant ions are implanted into a semiconductor layer, the ions damage the crystal lattice of the semiconductor layer. This lattice damage can usually only be partially repaired by a thermal annealing process. The amount of lattice damage can also be directly related to the implant energy; higher energy implants tend to cause more lattice damage than lower energy implants. Dopant concentration nonuniformity also tends to decrease as the implant depth increases.

[0099] Various approaches may be used to form trench vertical power semiconductor devices, and Figures 1A and 1B show schematic examples of two such different approaches.

[0100] 1A and 1B are schematic cross-sectional views illustrating exemplary transistor unit cells of trench vertical power devices (designated as power MOSFETs 100a and 100b, respectively) that include P-type shielded regions 140a and 140b. As shown in FIGS. 1A and 1B, power MOSFETs 100a and 100b are each heavily doped (e.g., N + ) a first conductivity type (e.g., n-type) substrate 110. - A first conductivity type drift layer or region 120 is provided on the substrate 110, for example, by epitaxial growth. The drift region 120 can be a wide bandgap semiconductor material (such as silicon carbide (SiC)) in some embodiments. For example, the substrate 110 can be a 4H—SiC substrate, and the drift region 120 can be a 4H—SiC n-type epitaxial layer formed on the substrate 110. A portion of the drift region 120 may include a current spreading layer ("CSL") 185 of the first conductivity type having a higher dopant concentration than a lightly doped portion of the drift region 120. A moderately doped second conductivity type (e.g., p-type) layer is formed on or within the drift region 120 (e.g., by epitaxial growth or implantation) to serve as a well region (e.g., a "P-well") 170 for the devices 100a, 100b. A heavily doped second conductivity type (e.g., p-type) layer is formed on or within the drift region 120 (e.g., by epitaxial growth or implantation) to serve as a well region (e.g., a "P-well") 170 for the devices 100a, 100b. + ) region 174 is formed in well region 170 through, for example, ion implantation. A transistor channel or conductive path 178 may be formed in the moderately doped region P-well 170. The substrate 110, drift region 120 (including current spreading layer 185), and the moderately doped layers defining P-well 170, along with various regions / patterns formed therein, are included in a semiconductor layer structure (designated herein by 106).

[0101] 1A and 1B, trenches 180 having, for example, a "striped" gate trench layout are formed in the semiconductor layer structure 106, with the trenches 180 extending continuously parallel to one another in a first lateral direction. The trenches 180 are spaced apart in a second lateral direction transverse to (e.g., perpendicular to) the first lateral direction and extend vertically toward the substrate 110 into the drift region 120. The lateral directions (e.g., X-, Y-, or other directions in the XY plane) described herein may be substantially perpendicular to the vertical directions (e.g., Z-direction) described herein. The trenches 180 (with gate electrodes 184a formed therein) may be formed to extend through the moderately doped layer 170 to define respective P-wells. The heavily doped (e.g., P + ) Second conductivity type shielding structures 140a, 140b are formed in the drift region 120, for example, by ion implantation. The shielding structures 140a, 140b may be electrically connected to the P-well 170. A gate insulating layer 182a (e.g., gate oxide) is conformally formed on the bottom surface and sidewalls of each trench 180. Corners of the gate trenches 180 and the overlying gate insulating layer 182 may be rounded, even if illustrated otherwise.

[0102] A gate electrode 184a (or "gate") is formed on each gate insulating layer 182a to fill the respective gate trench 180. The portion of the drift region 120 that underlies the well region 170 and / or is adjacent to the bottom of the gate electrode 184a may be referred to as the "JFET" region 175. A vertical transistor channel region including a conductive layer 178 (denoted by the dotted arrow) is defined within the well region 170 adjacent the gate insulating layer 182a and controlled by the gate 184a. A conductive layer of a first conductivity type (e.g., N +) is formed in an upper portion of P-well 170, for example through ion implantation. A heavily doped region 174 of a second conductivity type (e.g., P+) contacts well region 170. Source contacts 190 are formed on source region 160, heavily doped region 174, and deep shield structure 140b (in FIG. 1B ). Source contact 190 may be a resistive metal in some embodiments. Drain contact 192 is formed on the lower surface of substrate 110. A gate contact (not shown) may be electrically connected to each gate electrode 184, for example, by a conductive gate bus (not shown). An inter-metal dielectric layer 186 may be formed on gate 184, and a metal (e.g., aluminum) layer 196 may be formed on inter-metal dielectric layer 186 to contact source contact 190. In some embodiments, the source contact 190 may extend to the inter-metal dielectric 186 layer and may include, for example, a diffusion barrier and / or an adhesion layer.

[0103] As mentioned above, some devices may be susceptible to gate insulation layer degradation due to high electric fields, particularly in gate trench devices where the electric field may be concentrated at the trench corners. To reduce the electric field level in the gate insulation layer, a bottom shielding structure may be provided beneath the gate trench, and the bottom shielding structure must be electrically connected to an ohmic contact region on the top surface of the device (on which source metal may be formed).

[0104] Embodiments of the present disclosure may provide a buried shielding structure extending laterally beneath and spaced apart from a well region and / or gate to provide electrical contact between a contact shielding structure (which may extend vertically in the semiconductor layer structure) and a bottom shielding structure. The buried shielding structure may be implemented without substantial loss of active area, allowing current to flow laterally in the portion of the drift region between the well region and the buried shielding structure and then vertically reach the drain contact. The lateral extension of the buried shielding structure beneath multiple unit cells may enable fewer or segmented source contacts compared to some conventional approaches that may require a source contact in every unit cell. To enhance or maximize the conditions, the buried shielding structure may be implemented in a relatively elaborate pattern, and / or current spreading regions containing a higher concentration of dopant of the first conductivity type may be formed above and / or below the buried shielding structure. The buried shielding structures described herein may further be used to implement cascode configurations (including, for example, JFETs and MOSFETs) between the top and bottom surfaces of a semiconductor layer structure.

[0105] 2A and 2B are schematic cross-sectional views illustrating an exemplary unit cell of a gate trench power semiconductor device 200a including a recessed shielding structure 240 according to some embodiments of the present disclosure, respectively.

[0106] As shown in the gate trench device 200a of FIG. 2A and the planar gate device 200b of FIG. 2B, the semiconductor layer structure 106 includes a drift region 120 of a first conductivity type (e.g., n-type) and a well region 170 of a second conductivity type (e.g., p-type) above the drift region 120. In the gate trench device 200a, the semiconductor layer structure 106 includes a gate trench 180 having sidewalls and a bottom surface between the sidewalls and extending into the drift region 120, with a gate 184a formed in the gate trench. In the planar gate device 200b, a gate 184b is formed on a surface S of the semiconductor layer structure 106. The gates 184a, 184b (collectively 184) extend adjacent to the well region 170 and are separated from the well region 170 by gate insulating layers 182a, 182b (collectively 182), e.g., a gate oxide layer. The source region, well region 170, and portion 175 of drift region 120 below well region 170 can provide the pn junction of first transistor TX1 in semiconductor layer structure 106, and well region 170 can provide the portion of the transistor channel region controlled by gate 184.

[0107] A buried shielding structure 240 of a second conductivity type extends below the well region 170 and is separated from the well region 170 by a portion 175 of the drift region 120 (e.g., JFET region 175). The buried shielding structure 240 may have a different type or concentration of dopants of the second conductivity type than the well region 170 and may extend laterally into the drift region 120 (e.g., to a depth D1) between the well region 170 and the drain contact 192. The depth D1 of the buried shielding structure 240 in the drift region 120 may be equal to or greater than the depth D2 of the well region 170. The buried shielding structure 240 and the well region 170 are separated by a separation distance ΔD along the vertical (e.g., Z) direction. Isolation of the buried shielding structure 240 from the well region 170 (and similarly from the bottom of the gate 184) may provide improved current flow from the channel region to the drain at the bottom of the device. For example, the separation distance ΔD can be about 0 to 4 micrometers (μm), or about 0.2 to 1.5 μm.

[0108] That is, the buried shielding structure 240 may differ from the well region 170 in terms of material, dopant concentration, and / or depth relative to the surface S of the semiconductor layer structure 106. As described in more detail below, the buried shielding structure 240 may be formed as a pattern including one or more segments 245 extending in a first lateral direction (e.g., X-direction), which may be different from a second lateral direction (e.g., Y-direction) in which the gate 184 extends. The buried shielding structure 240 and portions of the drift region 120 above and below the buried shielding structure 240 may provide a p-n junction of the second transistor TX2 in the semiconductor layer structure 106.

[0109] 2A and 2B further show at least one contact-shield structure 140c of a second conductivity type extending vertically from the gate 184 to the laterally spaced drift region 120. In some embodiments, the contact-shield structure(s) 140c are formed by an ion implantation process using a heavily doped (P + ) silicon carbide region. The buried shield structure 240 extends laterally in the drift region 120 from beneath the well region 170 to at least one contact shield structure 140c. The contact shield structure 140c can electrically couple the source contact 190 to the buried shield structure 240 for connection to electrical ground, for example, within the unit cell. The contact shield structure 140c can have a variety of shapes in plan view, including an island shape (e.g., see FIG. 3A ) or a stripe shape (e.g., see FIG. 10A ). The contact shield structure(s) 140c can further act as a supporting shield structure that can reduce the electric field level in the gate oxide layer during device operation and / or provide a low-resistance current path between the source and drain terminals of the MOSFET in the event of avalanche breakdown.

[0110] Portions of drift region 120 above and / or below buried shielding structure 240 (more generally, between well region 170 and drain region 192) may include an optional current spreading layer (CSL) or region 185 of a first conductivity type. Current spreading region 185 has a greater dopant concentration of the first conductivity type than drift region 120. For example, in an n-type drift region 120, current spreading region 185 may be an N+ region separated from drain contact 192 by a lower portion of drift region 120.

[0111] In the gate trench device 200a, the gate trench 180 can extend to a depth D3 that is greater than the depth D2 of the well region 170 but less than the depth D1 of the buried shielding structure 240. For example, the gate trench 180 can have a depth D3 of about 0.3 to about 10 μm relative to the surface S of the semiconductor layer structure 106. In some embodiments, a bottom shielding structure 140a of the second conductivity type is provided below the bottom surface of the gate trench. As described above, the bottom shielding structure 140a can reduce electric field levels in the gate insulating layer 182a, particularly at the corners of the gate trench 180 where the electric field levels may be more concentrated. The buried shielding structure 240 extends laterally from the bottom shielding structure 140a to at least one contact shielding structure 140c, thereby electrically coupling the bottom shielding structure 140a to the source region 160 and the source contact 190 (which may be an ohmic contact region on the surface S).

[0112] The buried shielding structure 240 and / or the contact shielding structure 140c may be formed of a material different from that of the drift region 120. For example, the drift region 120 may include a wide bandgap semiconductor material (such as silicon carbide and / or gallium nitride), while the buried shielding structure 240 and / or the contact shielding structure 140c may include polysilicon, nickel oxide, gallium nitride, or gallium oxide. The buried shielding structure 240 and / or the contact shielding structure 140c may be formed of the same or a different material and / or with a dopant concentration (when present) similar to or different from that of the bottom shielding structure 140a. In some embodiments, the shielding structures 140c and / or 240 may be defined by one or more implantation processes with a substantially uniform concentration or with stepwise or continuous grading. The contact shielding structure 140c may be formed of a material different from that of the buried shielding structure 240 (e.g., about 1×10 17 ~Approx. 5×10 19 cm -3 , or approximately 1 × 10 18 ~Approx. 1×10 19 cm -3 ) compared to a high concentration of dopants of the second conductivity type (e.g., about 1×10 17 ~Approx. 1×10 20 cm -3 ) The dopant concentration of the shielding structures 140c and / or 240 may be higher (e.g., more than about 10 times, e.g., about 100 times higher) than the dopant concentration of the well region 170. The dopant concentration of the shielding structures 140c and / or 240 may vary based on the manufacturing process and / or device design implementation.

[0113] In contrast to some conventional devices that may require a contact shielding structure and / or source contact per unit cell, in some embodiments having less than one contact shielding structure 140c (or source contact) per unit cell, the buried shielding structure 240 may be implemented in various shapes or patterns. Thus, in embodiments of the present disclosure, a larger portion of the semiconductor layer structure 106 may serve as the device active area for electrical conduction, and more sparse or segmented source contacts 190 may be provided on the surface S of the semiconductor layer structure 106 to achieve electrical connection with the source regions 160 and the contact shielding structures 140c (and thus with the buried shielding structure 240). The number of source contacts 190 and / or the distance between the source contacts 190 may be optimized based on electrical performance and / or reliability. For example, providing more source contacts 190 and / or contact shield structures 140c may increase device on-resistance (e.g., due to a reduced available active area), while fewer source contacts 190 and / or contact shield structures 140c may become problematic as device resistance increases, resulting in greater losses during switching operations.

[0114] 3A, 3E, 4A, 4D, and 5A are plan views illustrating semiconductor devices 300, 300′, 400, 400′, and 500 including exemplary patterns 340, 340′, 440, 440′, and 540 of recessed shielding structures 240 (including gate trench or planar gate structures) and gate electrodes 184 according to some embodiments of the present disclosure. As shown in FIGS. 3A, 3E, 4A, 4D, and 5A, the recessed shielding structures 240 can define various patterns extending laterally within the drift 120 in a planar view. The patterns can include segments 245 extending in at least one laterally direction (e.g., in the X and / or Y directions shown in the figures); however, it will be understood that embodiments of the present disclosure are not limited to the specific patterns 340, 340′, 440, 440′, and 540 shown.

[0115] In the exemplary pattern 340 of Figure 3A, the segments 245 of the embedded shielding structure 240 extend linearly in one of a first lateral direction (e.g., the X direction) or a second lateral direction (e.g., the Y direction) (while being laterally spaced apart in the other direction), and the gates 184 (or gate trenches 180) extend in the second lateral direction. In the exemplary pattern 340' of Figure 3E, the segments 245 of the embedded shielding structure 240 extend in the first lateral direction or the second lateral direction, but the gates 184 (or gate trenches 180) extend in a third lateral direction (shown as oblique to the first and second lateral directions). That is, Figures 3A and 3E illustrate exemplary patterns 340, 340', in which the segments 245 of the embedded shielding structure 240 can extend linearly in one or more lateral directions in a plan view.

[0116] 4A and 4D show further example patterns 440, 440′ of the embedded shielding structure 240 according to embodiments of the present disclosure. In the example pattern 440 of FIG. 4A , the segments 245 of the embedded shielding structure 240 extend linearly in both a first lateral direction (e.g., the X direction) and a second lateral direction (e.g., the Y direction), while the gates 184 (or gate trenches 180) extend in multiple lateral directions to define respective polygonal shapes in a plan view. Respective well regions 170 and / or contact shielding regions may be provided within the periphery of the respective polygonal shapes defined by the gates 184 or gate trenches 180. In the exemplary pattern 440′ of FIG. 4D , the gate 184 (or gate trench 180) still defines a polygonal shape, but the segments 245 of the embedded shielding structure 240 extend linearly in first and second lateral directions that are oblique to the X and Y directions in a plan view.

[0117] 5A illustrates a further example in which the gate 184 and the recessed shielding structure 240 are “inverted” from FIG. 4A , such that the gate 184 (or gate trench 180) extends in a second lateral direction (e.g., the Y direction), but the segments 245 of the recessed shielding structure 240 extend in multiple lateral directions to define polygonal shapes in a plan view. While the sides of each polygon are shown as being shared by adjacent segments 245, the polygons defined by the segments 245 may be laterally spaced apart from one another in some embodiments. Respective well regions 170 and / or contact shielding regions may be provided between the gates 184 or between the gate trenches 180. More generally, the recessed shielding structure 240 and / or the gate 184 / gate trench 180 may define a pattern including segments 245 that achieve linear, elliptical, or polygonal shapes in a plan view.

[0118] 3A, 3E, 4A, 4D, and 5A may include segments 245 with relatively precise lateral dimensions and relatively wide spacing between the segments 245 to reduce or minimize disturbances in the active conductive areas of the semiconductor structure. For example, the width of each of the one or more segments 245 along the direction in which the gate 184 (or gate trench 180) extends may be about 0.1 to 20 μm.

[0119] 3B, 3C, and 3D are cross-sectional views taken along lines BB, CC, and DD of the gate trench structure of FIG. 3A or 3E. FIG. 4B and 4C are cross-sectional views taken along lines B'-B' and C'-C' of the gate trench structure of FIG. 4A or 4D. FIG. 5B and 5C are cross-sectional views taken along lines B"-B" and C"-C" of the gate trench structure of FIG. 5A. In particular, FIG. 3C, 4C, and 5C show portions of the active area of ​​the semiconductor layer structure 106 that provide the primary conductive path from source to drain (also referred to herein as vertical conductive areas), while FIG. 3B, 4B, and 5B show portions of the active area of ​​the semiconductor layer structure 106 that provide both the conductive path and the electrical connection to the buried shielding structure 240 (also referred to herein as lateral conductive areas).

[0120] 3B, 4B, and 5B, in a lateral conductive area, the buried shielding structure 240 may extend beneath the well region 170 and / or beneath a bottom surface of the gate 184 (e.g., to at least partially overlap in the vertical or Z direction) and may be spaced apart or separated from the well region 170 and / or gate 184 by a portion 175 of the drift region 120. The buried shielding structure 240 extends laterally in the drift region 120 from beneath the well region 170 and / or gate 184 to at least one contact-shielding structure 140c, which provides electrical connection to the source region 160 and source contact 190 (or a segment thereof) at the top surface S of the semiconductor structure. In the lateral conductive area, the buried shielding structure 240 may extend laterally to fully or partially overlap vertically (in the Z direction) with the gate 184, depending on the direction(s) of the segments 245 of the buried shielding structure 240 and the lateral extension of the gate 184. In contrast, as shown in Figures 3C, 4C, and 5C, in the vertical conductive area, the buried shielding structure 240 may vertically overlap the well region 170 but not fully extend under the gate 184 (i.e., the buried shielding structure 240 may at most partially overlap vertically with the gate 184 in the Z direction), thereby increasing the area of ​​the semiconductor layer structure 106 available for conduction. As shown in Figures 4C and 5C, an additional shallow contact region 174 of a second conductivity type (e.g., a P+ region) may be provided in the vertical conductive area for electrical contact with the well region 170.

[0121] 6 is a perspective view illustrating lateral and vertical conductive areas in a gate trench power semiconductor device 600 including a recessed shielding structure 240 according to some embodiments of the present disclosure. As shown in FIG. 6, in some embodiments, the recessed shielding structure 240 may include segments 245 extending laterally in a first direction, and the contact shielding structures 140c may be spaced laterally in the first direction from the gate trenches 180 and extend continuously in the second direction. A bottom shielding structure 140a of a second conductivity type may extend below the bottom surface of each gate trench. The recessed shielding structure 240 extends laterally in the first direction from the bottom shielding structure 140a to one or more of the contact shielding structures 140c.

[0122] 6 further illustrates that the buried shielding structure 240 can be configured to provide a lateral conductive path within a portion 175 of the drift region 120 between the bottom of the gate trench 180 and the buried shielding structure 240 (e.g., the JFET region 175). In particular, the segments 245 of the buried shielding structure 240 are spaced apart laterally (along the Y direction in this example) such that at least a portion of the conductive path 178 between the well region 170 and the drain contact 192 extends laterally along the buried shielding structure 240 in a second lateral direction (e.g., the Y direction). Thus, the conductive path 178 includes at least a first conductive path 178a in the vertical (Z) direction, a second conductive path 178b in the horizontal (Y) direction, and a third conductive path in the vertical (Z) direction. That is, the buried shielding structure 240 defined by the patterns 340, 340', 440, 540 may have one or more dimensions (horizontal or vertical) that allow lateral conduction from around its relatively narrow segment 245 to the drain contact 192 (into or out of the page in the cross section of Figure 3B, 4B, or 5B).

[0123] In some embodiments, the segments 245 of the embedded shielding structure 240 may have relatively wide spacing between them and relatively narrow widths in one or more horizontal directions such that the vertical conductive area of ​​the semiconductor structure may be increased or maximized. That is, in any of the examples described herein, the horizontal widths of the segments 245 of the embedded shielding structure 240 may be reduced (and / or the horizontal spacing between the segments 245 of the embedded shielding structure 240 may be increased) to increase the area of ​​the semiconductor layer structure 106 available for conduction. For example, the width of each of the segments of the embedded shielding structure 240 along the second horizontal direction (e.g., the Y direction) may be approximately 0.1 to 20 μm. Similarly, the number of contact shielding structures 140 c may be reduced, and / or the horizontal spacing between the contact shielding structures 140 c (or their segments 245) may be increased to achieve desired or optimized performance.

[0124] 7 is an equivalent circuit diagram illustrating a transistor configuration 700 that may be implemented using the recessed shielding structure 240 according to some embodiments of the present disclosure. With reference to the equivalent circuit diagram of FIG. 7 and the cross-sectional views of FIGS. 2A and 2B, the semiconductor layer structure 106 includes a first surface S with the gate 184 adjacent to the surface S (whether on the surface S or in the surface S in the gate trench 180) and an opposing second surface on which the drain contact resides. The semiconductor layer structure 106 includes a first transistor TX1 and a second transistor TX2 electrically coupled between the first and second surfaces (e.g., in a cascode amplifier configuration 700).

[0125] In particular, the source region, the well region 170, and the first portion 120a of the drift region 120 (between the well region 170 and the buried shielding structure 240) provide a first pair of p-n junctions 160 / 170 / 175 that define a first transistor TX1 in the semiconductor layer structure 106. The first portion 120a of the drift region 120, the buried shielding structure 240, and the second portion 120b of the drift region 120 (between the buried shielding structure 240 and the drain contact 192) provide a second pair of p-n junctions 175 / 240 / 120 that define a second transistor TX2 in the semiconductor layer structure 106. Thus, the source region 160 provides a first source S1 of the first transistor TX1, and the first portion 120a of the drift region 120 (i.e., the JFET region 175) provides a second source S2 of the second transistor TX2. The gate 184 provides a first gate G1 of the first transistor TX1, and the recessed shielding structure 240 provides a second gate G2 of the second transistor TX2. The second gate G2 of the second transistor TX2 (provided by the recessed shielding structure 240) is electrically coupled (by the contact shielding region) to the first source S1 of the first transistor TX1 (provided by the source region), thereby resulting in a cascode amplifier configuration 700.

[0126] 8A, 9A, and 10A are plan views illustrating semiconductor devices 800, 900, 1000 including exemplary patterns 840, 940, 1040 of recessed shielding structures 240 and gate electrodes 184 extending into gate trenches 180, according to some embodiments of the present disclosure. As shown in Figures 8A, 9A, and 10A, the gates 184 and contact shielding structures 140c extend continuously and substantially parallel to one another in one lateral direction (e.g., the Y direction), while the recessed shielding structures 240 include patterns 840, 940, 1040 having segments 245 that extend discontinuously in a different lateral direction (e.g., the X direction). However, it will be understood that embodiments of the present disclosure are not limited to the shown configurations or patterns. For example, embodiments may include gate 184, and / or one or more laterally discontinuous or segmented contact shielding structures 140c, one or more laterally continuous embedded shielding structures 240 having linear, elliptical, or polygonal shaped segments 245, or combinations thereof.

[0127] Figures 8B, 8C, and 8D are cross-sectional views taken along lines 8B-8B, 8C-8C, and 8D-8D of the gate trench structure of Figure 8A. Figures 9B, 9C, and 9D are cross-sectional views taken along lines 9B-9B, 9C-9C, and 9D-9D of the gate trench structure of Figure 9A. While Figures 8B and 9B show cross-sections of lateral conductive areas, in particular, Figures 8C and 9C show cross-sections of vertical conductive areas.

[0128] 8B and 9B , in the lateral conductive area, the buried shielding structure 240 extends laterally beneath the well region 170 and beneath the bottom surface of the gate 184, and is separated or spaced from the well region 170 by a portion 175 of the drift region 120. At least one contact-shielding structure 140c of a second conductivity type extends vertically from the sidewall of the gate trench 180 into the laterally spaced-apart drift region 120 to contact the buried shielding structure 240 to provide electrical connection to a source contact 190 (or a segment thereof) electrically coupled to the source region 160 at the top surface S of the semiconductor structure.

[0129] 8B , the bottom shielding structure 140a extends below the bottom surface of the gate trench, and the buried shielding structure 240 extends laterally from the bottom shielding structure 140a at the bottom of the gate trench 180 to at least one contact shielding structure 140c, thereby electrically coupling the buried shielding structure 240 and the bottom shielding structure 140a to the source contact. In some embodiments, the contact shielding structure 140c (shown extending along the Y direction) may further include a segment 245 extending along the X direction on one or both sidewalls of the gate trench 180 (i.e., forming a one- or two-sided "bridge") in the lateral conductive area. However, this structure may prevent conduction on one or both sides of the gate trench.

[0130] 9B , the buried shielding structure 240 is electrically coupled to the source contact 190 by a portion of a metal layer 196 over the source contact 190 (also referred to as source contact metal). In particular, the source contact metal 196 extends laterally (in the X-direction) and vertically (in the Z-direction) along at least one of the sidewalls of the gate trench 180 to contact the buried shielding structure 240 (or the remaining portion of the contact shielding structure 140c that is in contact with the buried shielding structure 240). The source contact metal 196 may be separated from the sidewall(s) of the gate trench 180 by an interlayer dielectric material. This configuration may similarly prevent conduction on one or both sides of the gate trench.

[0131] 8C and 9C , in the vertical conductive area, the buried shielding structure 240 does not extend under the gate 184 to increase the area of ​​the semiconductor layer structure 106 available for conduction. In particular, the segments 245 of the buried shielding structure 240 are laterally spaced apart to define a relatively sparse pattern in which the buried shielding structures 240 are largely absent from the vertical conductive area. The bottom shielding structure 140 a may extend under the gate trench 180 in the vertical conductive area to reduce electric field levels in the gate insulating layer, particularly at the corners of the gate trench.

[0132] 10B and 10C are alternative examples of cross-sectional views taken along line 10B / C-10B / C of the gate trench structure of FIG. 10A. In particular, FIGS. 10B and 10C show alternative examples of vertical conductive areas in which recessed shielding structures 240 extend laterally below well region 170 to at least partially overlap vertically (in the Z direction) with the bottom of the gate trench. In some embodiments, recessed shielding structures 240 may extend below and be spaced apart from well region 170 on one side (in FIG. 10B ) or both sides (in FIG. 10C ) of gate 184, and in some embodiments, overlie a majority of drift region 120 between contact shielding structure 140c and gate 184.

[0133] 10B , more specifically, the recessed shielding structures 240 may extend laterally from the contact shielding structures 140c to below the bottom of the gate trench 180 on one side of the gate trench. The other side of the gate trench 180 (and the associated vertical conductive path 178 along the sidewall of the gate trench) may be free of the recessed shielding structures 240. In the example of FIG. 10C , the recessed shielding structures 240 may extend laterally from their respective contact shielding structures 140c to below the bottom of the gate trench 180 on the opposing side of the gate trench, but include gaps or openings below the gate trench 180 to allow vertical current flow. Lateral conduction (i.e., a lateral conductive path into or out of the page in the cross section of FIG. 8C, 9C, or 10C) may also be provided in portion 175 of drift region 120 between the bottom of gate trench 180 and buried shielding structure 240 (e.g., JFET region 175). That is, buried shielding structure 240 defined by patterns 840, 940, 1040 may have one or more dimensions (lateral or vertical) that enable lateral conduction around relatively narrow segment 245 of buried shielding structure 240 to drain contact 192, as similarly described above in connection with FIG. 3B, 4B, or 5B.

[0134] 11A-11E, 12A-12F, 13A-13E, 14A-14D, and 15A-15D illustrate various examples of methods for fabricating a semiconductor device including a buried shield structure 240 according to some embodiments of the present disclosure. In FIGS. 11A-15D, the method for fabricating the semiconductor device includes providing a drift region 120 of a first conductivity type, providing a buried shield structure 240 of a second conductivity type in the drift region 120, and providing a well region 170 of the second conductivity type above the drift region 120 and spaced apart from the buried shield structure 240. The buried shield structure 240 may be formed using selective epitaxy, ion implantation, etching, and / or a combination thereof. The buried shield structure 240 may be formed in various patterns having one or more segments 245 extending laterally in the drift region 120. Although not shown, a gate 184 is provided on the semiconductor layer structure 106 adjacent to the well region 170 (e.g., in a gate trench 180 in the devices of Figures 11A-13E or 15A-15D, or on the surface S in the planar gate device of Figures 14A-14D).

[0135] 11A-11E are cross-sectional views taken along line BB (showing lateral conductive areas) and line CC (showing vertical conductive areas) of the gate trench structure of FIG. 3A , illustrating a method of fabricating a power semiconductor device including a buried shielding structure according to some embodiments of the present disclosure. As shown in FIG. 11A , a first portion of drift region 120 having a first (e.g., n-) conductivity type is formed, for example, by a first epitaxy process. In FIG. 11B , a buried shielding structure 240 having a second (e.g., p-) conductivity type is formed in or on first portion 120a of drift region 120. In particular, a mask pattern 1101 is formed on first portion 120a of drift region 120. For example, a patterning layer may be formed on the mask layer, and the mask layer may be patterned (photolithographically) using the patterning layer to form a mask pattern 1101 that includes an opening therein that exposes a portion of the drift region 120, the exposed portion of the lateral conductive area (along line BB) being relatively larger than the exposed portion of the vertical conductive area (along line CC).

[0136] Buried shielding structure 240 may be formed in a desired pattern (such as, but not limited to, patterns 340, 440, 540, 840, 940, 1040, as described herein) based on the areas of drift region 120 exposed by mask pattern 1101. In some embodiments, one or more ion implantation processes may be performed to selectively implant dopants of a second conductivity type (e.g., p-type) into the areas of drift region 120 exposed by mask pattern 1101 to form buried shielding structure 240 in the desired pattern using mask pattern 1101 as an implantation mask. The dopant concentration of buried shielding structure 240 may be substantially uniform or gradually transitioned (e.g., stepped or continuous).

[0137] 11C, mask pattern 1101 is removed, and second portion 120b of drift region 120 having a first conductivity type is formed on buried shielding structure 240 (e.g., by a second epitaxy process). In FIG. 11D, JFET region 175 of the first conductivity type, well region 170 of the second conductivity type, and source region 160 of the first conductivity type are formed in or on second portion 120b of drift region 120. For example, JFET region 175, well region 170, and source region 160 may be formed in second portion 120b of drift region 120 by respective masking and / or ion implantation processes. In some embodiments, further shallow contact structures 174 of the second conductivity type (e.g., P+ regions) may be formed adjacent to source region 160 to provide electrical contact to well region 170. This results in a semiconductor layer structure 106 that includes a drift region 120 , a well region 170 , and a source region 160 .

[0138] 11E, contact shielding structures 140c and gate trenches 180 are formed to extend into the surface S of the semiconductor layer structure 106. For example, an etching process may be performed to selectively etch portions of the surface S exposed by the etching mask pattern 1101 (not shown) to form gate trenches 180 that are between the contact shielding structures 140c and extend into the drift region 120 spaced apart from the contact shielding structures 140c.

[0139] 11E , contact shield structure 140c may be formed using various fabrication operations before forming gate trench 180 (pre-trench) or after forming gate trench 180 (post-trench). For example, in some embodiments, an implant mask (not shown) may be formed that includes openings therein exposing portions of surface S of semiconductor layer structure 106, and one or more implantation processes may be performed to implant dopants of the second conductivity type (e.g., p-type) into the exposed portions of the surface to form contact shield structure 140c that extends into drift region 120 and toward the underlying substrate (e.g., 110). The dose and / or implantation energy of the implantation process(es) may be controlled to form contact shield structure 140c with a desired dopant concentration and / or depth (e.g., D1) relative to surface S (e.g., higher implantation energies result in greater depth). The dopant concentration of the contact shield structure 140 c may be substantially uniform or may be gradually graded and may differ from the dopant concentration of the well region 170 .

[0140] In another embodiment, the contact shield structure 140c may be formed by forming an etch mask (not shown) including an opening therein that exposes a portion of the surface S of the semiconductor layer structure 106, and performing one or more etching processes may be performed to form a shield trench extending to the exposed portion of the surface S having a desired depth (e.g., D1). One or more deposition processes may be performed to form a material of a second conductivity type (e.g., p-type) in the shield trench, thereby forming the contact shield structure 140c (also referred to herein as a heterojunction shield structure) that extends into the drift region 120 toward the underlying substrate (e.g., 110) of a material different from the drift region 120. For example, the drift region 120 may be formed of an n-type material (e.g., SiC), and the contact shield structure 140c may be formed of a p-type material (e.g., p-NiO, p-poly-Si, p-GaN, p-Ga2O3).

[0141] In some embodiments, a bottom shielding structure (e.g., 140a) may be formed below and at least partially along the bottom surface of the gate trench before forming the gate trench 180 in some embodiments (e.g., in the same pre-trench process that forms the buried shielding structure 240) or after forming the gate trench 180 (e.g., using a low-energy post-trench implant process). Thus, the bottom shielding structure 140a may be an implanted region of the drift region 120 (and thus may comprise the same material as the drift region 120), but the buried shielding structure 240 may be formed of a different material than the drift region 120, or vice versa. That is, when present, bottom shielding structure 140a and buried shielding structure 240 may be formed using the same or different fabrication operations (e.g., same or different ion implantation or epitaxial processes) and may therefore be the same or different from one another (e.g., in terms of material, depth of extension toward substrate 110, and / or dopant concentration), depending on the fabrication process used. Similarly, contact shielding structure 140c may have a different depth, dopant concentration, and / or material than bottom shielding structure 140a or buried shielding structure 240. For example, contact shielding structure 140c may have a different depth, dopant concentration, and / or material than bottom shielding structure 140a or buried shielding structure 240 (e.g., 1×10 17 cm -3 ~5×10 19 cm -3 ) or higher dopant concentrations (e.g., 1×10 17 cm -3 ~1×10 20 cm -3 ) can be formed.

[0142] 11E, after the gate trench 180 is formed, a gate insulating layer 182a is formed along the sidewalls and bottom surface of the gate trench 180, and a gate electrode 184a is formed in the gate trench. A source contact 190 (or ohmic contact), an inter-metal dielectric 186, and a source metal layer 196 may then be formed. The fabrication operations shown in FIGS. 11A-11E can thereby provide the device 200a of FIG. 2A.

[0143] 12A-12F are cross-sectional views taken along line BB (indicating a lateral conductive area) and line CC (indicating a vertical conductive area) of the gate trench structure of FIG. 3A illustrating a method of fabricating a power semiconductor device including a buried shielding structure according to some embodiments of the present disclosure. The operations of FIG. 12A-12F may be similar to those of FIG. 11A-11E, except that the implantation or deposition process of FIG. 11B is performed as a blanket implantation or epitaxy process without mask pattern 1101, followed by a subsequent etching process using mask pattern 1101 to form buried shielding structure 240 in a desired pattern based on the area of ​​drift region 120 exposed by mask pattern 1101.

[0144] 12A, a first portion of drift region 120 having a first (e.g., n-) conductivity type is formed, for example, by a first epitaxy process. In FIG. 12B, a buried shielding structure 240 having a second (e.g., p-) conductivity type is formed on first portion 120a of drift region 120. To form buried shielding structure 240, in particular, a blanket implantation or epitaxy process is performed to implant or deposit material of the second conductivity type on first portion 120a of drift region 120. The blanket process may be performed on most or all of the top surface of first portion 120a of drift region 120.

[0145] 12C, after an implantation or epitaxy process, a mask pattern 1101 having openings is formed over first portion 120a of drift region 120, the openings exposing relatively larger portions of lateral conductive areas (along line BB) than of vertical conductive areas (along line CC). Using mask pattern 1101, an etching process is selectively performed on areas of first portion 120a of drift region 120 to form buried shielding structures 240 in a desired pattern based on the areas of drift region 120 exposed by mask pattern 1101.

[0146] 12D, mask pattern 1101 is removed, and second portion 120b of drift region 120 having the first conductivity type is formed (e.g., by a second epitaxy process) on buried shielding structure 240. In FIG. 12E, JFET region 175 of the first conductivity type, well region 170 of the second conductivity type, and source region 160 of the first conductivity type are formed in or on second portion 120b of drift region 120, and in FIG. 12F, contact shielding structure 140c and gate trench 180 are formed to extend to surface S of semiconductor layer structure 106, similar to that described above in connection with FIGS. 11A-11E. In some embodiments, a bottom shielding structure (e.g., 140a) may be formed below and at least partially along the bottom surface of the gate trench. A gate insulating layer 182a, a gate electrode 184a, a source contact 190, an intermetal dielectric 186, and a metal layer 196 may be subsequently formed to provide the device 200a of Figure 2A.

[0147] 13A-13E are cross-sectional views taken along lines BB and CC of the gate trench structure of FIG. 3A illustrating a method of fabricating a power semiconductor device including a recessed shielding structure according to some embodiments of the present disclosure. The operations of FIGS. 13A-13E may be similar to those of FIGS. 11A-11E except that current spreading layers or regions may be formed above and / or below the recessed shielding structure 240.

[0148] 13A, a first portion of drift region 120 having a first (e.g., n-) conductivity type is formed (e.g., by a first epitaxy process), and a current spreading region 185 having a greater concentration of dopants of the first conductivity type is formed in first portion 120a of drift region 120. For example, current spreading region 185 may be an N+ region implanted in or otherwise formed on first portion 120a of drift region 120 using a selective or blanket process.

[0149] 13B , buried shielding structures 240 having a second (e.g., p-) conductivity type are formed in or on first portion 120a of drift region 120. In particular, mask pattern 1101 is formed on first portion 120a of drift region 120 (e.g., on current spreading region 185), and buried shielding structures 240 are formed in a desired pattern based on the areas of drift region 120 exposed by mask pattern 1101. For example, buried shielding structures 240 may be formed in or on current spreading region 185 using one or more ion implantation processes or selective epitaxy processes to implant or deposit material of the second conductivity type (e.g., p-type) into or on the areas exposed by mask pattern 1101. Thus, current spreading region 185 may extend above and / or below buried shielding structures 240 relative to the underlying substrate (e.g., 110).

[0150] In Figure 13C, mask pattern 1101 is removed, and second portion 120b of drift region 120 having the first conductivity type is formed (e.g., by a second epitaxy process) on buried shielding structure 240 and / or on current spreading region 185. In Figure 13D, JFET region 175 of the first conductivity type, well region 170 of the second conductivity type, and source region 160 of the first conductivity type are formed in or on second portion 120b of drift region 120, and in Figure 13E, contact shielding structure 140c and gate trench 180 are formed extending to surface S of semiconductor layer structure 106, in a manner similar to that described above in connection with Figures 11A-11E.

[0151] The gate trench 180, in some embodiments, may be limited above a current spreading region 185. In some embodiments, a bottom shielding structure (e.g., 140a) may be formed below and at least partially along a bottom surface of the gate trench. A gate insulation layer 182a, a gate electrode 184a, a source contact 190, an inter-metal dielectric 186, and a metal layer 196 may subsequently be formed to provide the device 200a of FIG. 2A.

[0152] 14A-14D are cross-sectional views taken along lines BB and CC of the planar gate structure of FIG. 3A illustrating a method of fabricating a power semiconductor device including a recessed shielding structure according to some embodiments of the present disclosure. The operations of FIGS. 14A-14D are similar to those of FIGS. 11A-11E, except that the device is formed with a planar gate structure.

[0153] As shown in Figure 14A, a first portion of drift region 120 having a first (e.g., n-) conductivity type is formed (e.g., by a first epitaxy process). In Figure 14B, buried shielding structures 240 having a second (e.g., p-) conductivity type are formed in or on first portion 120a of drift region 120. In particular, mask pattern 1101 is formed on first portion 120a of drift region 120, and buried shielding structures 240 are formed in a desired pattern using, for example, one or more ion implantation processes or selective epitaxy processes to implant or deposit material of the second conductivity type into or on areas exposed by mask pattern 1101.

[0154] 14C, mask pattern 1101 is removed, and second portion 120b of drift region 120 having the first conductivity type is formed (e.g., by a second epitaxy process) on buried shielding structure 240. In FIG. 14D, JFET region 175 of the first conductivity type, well region 170 of the second conductivity type, and source region 160 of the first conductivity type are formed in or on second portion 120b of drift region 120, and contact shielding structure 140c is formed to extend to surface S of semiconductor layer structure 106. Gate insulation layer 182b, gate electrode 184b, source contact 190, inter-metal dielectric 186, and metal layer 196 may subsequently be formed to provide device 200b of FIG. 2B.

[0155] 15A, 15B, 15C, and 15D are cross-sectional views taken along lines BB and CC of the gate trench structure of FIG. 3A illustrating a method of fabricating a power semiconductor device including a recessed shielding structure according to some embodiments of the present disclosure. The operations of FIGS. 15A-15D may be similar to those of FIGS. 11A-11E, except that the recessed shielding structure 240 is formed by one or more deep ion implantation processes.

[0156] 15A, a drift region 120 having a first (e.g., n-) conductivity type is formed (e.g., by an epitaxy process). In contrast to the embodiments discussed above, the drift region 120 may be formed to a desired thickness (e.g., the thickness of the semiconductor layer structure 106 in the completed device) before forming the buried shielding structure 240.

[0157] 15B , buried shielding structures 240 having a second (e.g., p-) conductivity type are formed in drift region 120 at a desired depth (e.g., D1) relative to its surface S. In particular, mask pattern 1101 is formed on surface S of drift region 120, and buried shielding structures 240 are formed in the desired pattern using one or more deep ion implantation processes to implant dopant material of the second conductivity type into areas exposed by mask pattern 1101. The dose and / or implantation energy of the implantation process(es) may be controlled to form buried shielding structures 240 at a predetermined dopant concentration and / or depth (e.g., D1) below surface S (e.g., higher implantation energies result in greater depths).

[0158] In Figure 15C, mask pattern 1101 is removed, and JFET region 175 of the first conductivity type, well region 170 of the second conductivity type, and source region 160 of the first conductivity type are formed in or on second portion 120b of drift region 120. In Figure 15D, contact shielding structure 140c and gate trench 180 are formed extending to surface S of semiconductor layer structure 106, similar to that described above in connection with Figures 11A-11E. Gate insulation layer 182b, gate electrode 184b, source contact 190, inter-metal dielectric 186, and metal layer 196 may subsequently be formed to provide device 200b of Figure 2B.

[0159] 2A and 2B , after the operations shown in FIGS. 11E, 12F, 13E, 14D, and 15D, a drain contact 192 is provided on the substrate 110 opposite the drift region 120. Thus, the buried shielding structure 240 extends laterally into the drift region 120 between the well region 170 and the drain contact 192. In some embodiments, the gate 184 can provide a first gate G1 of the first transistor TX1 within the semiconductor layer structure 106, and the buried shielding structure 240 can provide a second gate G2 of the second transistor TX2 within the semiconductor layer structure 106, such that the first and second transistors TX1, TX2 are electrically coupled in the cascode amplifier configuration 700.

[0160] It will be understood that any of the operations shown in Figures 11A-15D can be combined in various embodiments herein. For example, one or more of the pre-trench implant operations can be performed between one or more of the pre-trench heterojunction operations, or vice versa. Similarly, one or more of the post-trench implant operations can be performed between one or more of the post-trench heterojunction operations, or vice versa. More generally, although the fabrication operations shown in Figures 11A-15D are illustrated by way of example in connection with forming shielding regions 140a, 140c, 240 by implantation, or epitaxial growth, or deposition, it will be understood that any of the illustrated operations can be utilized in combination to provide any desired combination of implanted heterojunction shielding regions 140a, 140c, 240 with similar or different depths and / or materials.

[0161] As mentioned above, the contact shielding structure 140c can have various shapes in plan view, including an island shape (e.g., see FIG. 3A) or a stripe shape (e.g., see FIG. 10A). As described further herein, the contact shielding structure(s) 140c may include or refer to both (i) a support shielding structure and (ii) a bridge shielding structure. The support shielding structure can reduce the electric field level in the gate oxide layer during device operation and / or can provide a low-resistance current path between the source and drain terminals of the MOSFET in the event of avalanche breakdown. The bridge shielding structure can electrically connect the bottom shielding structure 140a to the support shielding structure. In some embodiments, the contact shielding structure 140c (including the support shielding structure and / or the bridge shielding structure) can be discontinuous or segmented, providing additional area within the semiconductor structure for current flow.

[0162] In particular, the contact shield structure 140c may include multiple separate segments extending longitudinally (e.g., lengthwise) in one or more laterally (e.g., X, Y, or other directions in the XY plane), with respective segment widths along a direction transverse to the respective longitudinal extensions. The spacing between the segments of the contact shield structure 140c (e.g., along the respective longitudinal extensions of the segments) may be sufficient to avoid punch-through (e.g., in well regions) or, in other circumstances, premature failure of the device. Thus, a segmented contact shield structure as described further herein may provide similar blocking capabilities compared to a continuously extending contact shield structure, while reducing the on-resistance (Rds,on) for a given area of ​​the device.

[0163] The spacing between segments of the contact shield structure 140c may vary in various embodiments to improve or optimize performance. For example, providing more segments of the contact shield structure 140c may improve avalanche robustness (by providing a shielding pattern with a wider perimeter area to distribute the avalanche current), but increasing the number of contact shield structures 140c may increase device on-resistance (due to a reduction in available active area within the semiconductor structure). The embodiments of the contact shield structure 140c described below in connection with Figures 16-22 may be used alone or in combination with any of the embedded shield structures (e.g., 240) or related patterns (e.g., 340, 440, etc.) described herein in connection with Figures 1-15.

[0164] 16A, 17A, 18A, and 19A are plan views illustrating semiconductor devices 1600, 1700, 1800, and 1900, respectively, including an exemplary contact shielding structure 140c and a gate electrode 184 extending into a gate trench 180, according to some embodiments of the present disclosure. As shown in FIGS. 16A, 17A, 18A, and 19A, the gate 184 extends continuously in one lateral direction (shown as the Y direction in this example), while the contact shielding structure 140c extends discontinuously in one or more lateral directions (e.g., one or more directions in the XY plane). More specifically, the contact shielding structure 140c includes a support shielding structure 140c1 and a bridge shielding structure 140c2, at least one of which extends discontinuously in one or more lateral directions (shown as the Y direction for the support shielding structure 140c1 and the X direction for the bridge shielding structure 140c2 in these examples). The support shielding structure 140c1 extends longitudinally in a first lateral direction (denoted as the Y direction) parallel to and spaced from the gate 184. The bridge shielding structure 140c2 extends in a second lateral direction transverse to the first lateral direction toward the gate 184 (e.g., to contact the bottom shielding structure 140a below the gate 184).

[0165] The contact shielding structure 140c (including the supporting shielding structure 140c1 and / or the bridge shielding structure 140c2) can include a plurality of separate segments 145 extending longitudinally in one or more laterally. For example, as shown in Figures 16A and 17A, the supporting shielding structure 140c1 includes segments 145 having a spacing S1 between the segments 145 along the Y direction, while the bridge shielding structure 140c2 extends continuously in the X direction. While the spacing S1 between the segments 145 of the supporting shielding structure 140c1 is aligned along the X direction in the exemplary device 1600 of Figure 16A, the spacing S1 between the segments 145 of the supporting shielding structure 140c1 is staggered along the X direction in the exemplary device 1700 of Figure 17A. In the example device 1800 of Figure 18A, spacing S1 is provided between segments 145 of supporting shielding structure 140c1 along the Y direction, and spacing S1' is provided between segments 145 of bridge shielding structure 140c2 along the X direction. In the example device 1900 of Figure 19A, spacing S1' is provided between segments 145 of bridge shielding structure 140c2 along the X direction, while supporting shielding structure 140c1 extends continuously along the Y direction.

[0166] 20A, 20B, and 20C are plan views illustrating semiconductor devices 2000a, 2000b, and 2000c including an alternative configuration of contact shielding structure 140c in combination with square trench gate electrode 184. As shown in example device 2000a of FIG. 20A, support shielding structure 140c1 extends laterally in both the X and Y directions parallel to and spaced from each sidewall of square gate trench 180. Bridge shielding structure 140c2 extends laterally in the Y direction, intersecting and extending along opposing sidewalls of each gate trench 180. In example device 2000b of FIG. 20B, support shielding structure 140c1 includes segments 145 with spacing S1 between segments 145 along the Y direction and / or along the X direction (as shown), while bridge shielding structure 140c2 extends continuously along the Y direction. In the example device 2000c of FIG. 20C, a spacing S1' is provided between segments 145 of the bridge shielding structure 140c2 along the Y direction, while the supporting shielding structure 140c1 extends continuously along both the X and Y directions.

[0167] 21A, 21B, and 21C are plan views illustrating semiconductor devices 2100a, 2100b, and 2100c, each including a further alternative configuration of a contact shielding structure 140c in combination with a hexagonal trench gate electrode 184. As shown particularly in the exemplary device 2100a of FIG. 21A, the support shielding structure 140c1 extends laterally in multiple directions in the XY plane, parallel to and spaced from each sidewall of the hexagonal gate trench 180. The bridge shielding structure 140c2 extends laterally in one direction in the XY plane, intersecting and extending along opposing sidewalls of each gate trench 180. In the exemplary device 2100b of FIG. 21B, the support shielding structure 140c1 includes segments 145 with a spacing S1 between them, while the bridge shielding structure 140c2 extends continuously in the illustrated lateral direction. In the exemplary device 2100c of FIG. 21C, a spacing S1′ is provided between the segments 145 of the bridge shielding structure 140c2 in the orientation shown, while the support shielding structure 140c1 extends continuously in multiple directions in the XY plane around the sidewalls of the hexagonal gate trench 180.

[0168] 16A, 17A, 18A, 19A, 20A-20C, and 21A-21C are provided by way of example only, and it will be understood that embodiments of the present disclosure are in no way limited to the configurations or patterns shown in the examples described herein. That is, embodiments of the present disclosure can include any contact shielding structure 140c that has not only one or more discontinuous or segmented support shielding structures 140c1 and one or more laterally continuous (or vice versa) bridge shielding structures 140c2, but also combinations thereof, and that is rectilinear, elliptical, or polygonal in plan view.

[0169] 16B-16D, 17B-17E, 18B-18D, and 19B-19D show various cross sections of semiconductor devices 1600, 1700, 1800, and 1900, respectively. As shown in these cross sections, semiconductor layer structure 106 includes drift region 120 of a first conductivity type and well region 170 of a second conductivity type within or above drift region 120. Drift region 120 may, in some embodiments, include an (optional) current spreading layer of the first conductivity type below well region 170. A gate trench 180 having opposing sidewalls and a bottom surface therebetween extends vertically through the well region into drift region 120, with a gate insulating layer 182 and a gate 184 extending between the sidewalls of gate trench 180. The portion 175 of the drift region below the well region 170 and the bottom of the gate trench 180 may be referred to as the JFET region 175. The second conductivity type contact shield structure 140c extends vertically from the well region 170 to the drift region 120 and further includes one or more laterally discontinuous supporting and bridging shielding structures 140c1 and 140c2.

[0170] In particular, Figures 16C, 17C, 17E, 18C, 19C, and 19D show cross sections of exemplary supporting shielding structures 140c1. The supporting shielding structures 140c1 extend longitudinally in a first lateral direction (denoted as the Y direction) and are spaced apart from respective gates 184 in a second lateral direction (denoted as the X direction). In the cross-sectional views shown in Figures 16C, 17C, 18C, 19C, and 19D, the supporting shielding structures 140c1 are spaced apart from both opposing sidewalls of each gate trench 180. In the cross-section shown in Figure 17E, the supporting shielding structures 140c1 are segmented such that they are spaced apart from only one of the sidewalls of the gate trench 180 (there is no supporting shielding structure 140c1 adjacent to the opposite sidewall of the gate trench 180). As described above, the support shielding structure 140c1 may be configured to reduce the electric field concentration in the gate insulating layer 182 during device operation. The support shielding structure 140c1 may further provide a low resistance current path between the source and drain terminals of the devices 1600, 1700, 1800, 1900 in the event of avalanche breakdown.

[0171] 16B, 17B, 18B, and 19B show cross sections of an exemplary bridge shielding structure 140c2. The bridge shielding structure 140c2 extends longitudinally toward the gate 184 in a lateral direction (denoted as the X-direction) transverse to the direction of extension of the support shielding structure 140c1 (denoted as the Y-direction). As described above, the bridge shielding structure 140c2 may be configured to electrically connect the support shielding structure 140c1 to the bottom shielding structure 140a, which extends (continuously or discontinuously) below the bottom surface of the gate trench 180 to reduce or prevent field breakdown in the gate insulation layer 182, particularly at the corners of the gate trench 180. The bridge shielding structure 140c2 may extend on one or both sidewalls of the respective gate trench 180 (i.e., form a one-sided or two-sided "bridge" that contacts the bottom shielding structure 140a). The cross sections shown in Figures 16B and 17B show two-sided bridge shielding structures 140c2 extending along both opposing sidewalls of the gate trench 180 to contact the bottom shielding structure 140a. The cross sections shown in Figures 18B and 19B show a one-sided bridge shielding structure 140c2 that is segmented to extend along only one of the sidewalls of the gate trench 180 to contact the bottom shielding structure 140a, thereby enabling conduction along the opposing sidewalls of the gate trench 180 (which are absent the bridge shielding structure 140c2).

[0172] In either a one-sided or two-sided bridge configuration, the bridge shielding structure 140c2 electrically couples the bottom shielding structure 140a to a heavily doped region 174 and a source contact 190 on the surface of the semiconductor layer structure 106. In particular, a source region 160 of a first conductivity type and a heavily doped region 174 of a second conductivity type are provided above the well region 170, and the source contact 190 is electrically coupled to the source region 160 and the heavily doped region 174 at the surface of the semiconductor layer structure 106. An inter-metal dielectric layer 186 separates the gate 184 from metal layer(s) 196 formed to contact the source contact 190. The bridge shielding structure 140c2 (or a segment 145 thereof) extends vertically from the source contact 190 to the bottom shielding structure 140a and extends laterally from the bottom shielding structure 140a to contact the supporting shielding structure 140c1 (or a segment 145 thereof) and provide an electrical connection to the source contact 190, which is electrically coupled to the source region 160 at the top surface of the semiconductor structure 106 (e.g., opposite the drain contact 192 in FIG. 2A).

[0173] 16D, 17D, 18D, and 19D, segments 145 of support shielding structures 140c1 and / or bridge shielding structures 140c2 according to embodiments described herein are configured to provide the above-described advantages with respect to electric field concentration and avalanche performance, while also increasing or maximizing the area of ​​semiconductor layer structure 106 available for electrical conduction. In particular, segments 145 of support shielding structures 140c1 and / or bridge shielding structures 140c2 are laterally spaced apart (by spacings S1, S1′) to define a relatively sparse pattern such that contact shielding structures 140c are absent from portions of semiconductor structure 106. That is, each spacing S1, S1′ between separate segments 145 may include portions of drift region 120 between well region 170 and drain contact (not shown) that are free of contact shielding structures 140c. In some embodiments, the spacing S1, S1′ between the segments 145 (and / or the spacing S2, S2′ between adjacent bridge shielding structures 140c2) may be provided such that each transistor unit cell includes less than one bridge shielding structure 140c2, thereby increasing the available conductive area in the semiconductor layer structure 106.

[0174] 22A and 22B are plan views illustrating example segments 145a, 145b and spacings S1, S1′ of a contact shield structure 140c according to some embodiments of the present disclosure. The segments 145a, 145b (collectively 145) shown in FIGS. 22A and 22B may represent segments of either the support shield structure 140c1 or the bridge shield structure 140c2 (collectively 140c) described herein. The dimensions L, W of the segments 145 and / or the spacing S between the segments 145 may be configured to increase avalanche breakdown performance.

[0175] As shown in FIG. 22A , segment 145a of contact shielding structure 140c extends longitudinally along length L and has width W along a direction transverse to or perpendicular to length L. Thus, the total perimeter area of ​​segment 145a is 2L + 2W. As noted above, avalanche performance can be improved by configuring contact shielding structure 140c to provide a larger perimeter area for avalanche current distribution. Thus, the perimeter area of ​​contact shielding structure 140c can be increased by increasing the number of segments 145. In particular, as shown in FIG. 22B , two segments 145b of contact shielding structure 140c extend longitudinally along the same length L and width W as segment 145a in FIG. 22A , with a spacing S between segments 145b. Thus, the total perimeter area of ​​segment 145b is 4(LS) / 2+4W=2L-2S+4W, which is greater than the perimeter area of ​​segment 145a (and thus provides improved avalanche performance relative to segment 145a). By making the width W of each of segments 145b greater than the spacing S between segments 145b, the perimeter area (particularly the corner area or number of corners) for avalanche current distribution can be increased. In other words, improved avalanche performance can be achieved when the spacing S between individual segments 145b is less than the width W of each of the individual segments 145b. In some embodiments, the width of each of the individual segments can be approximately 0.1-20 μm, e.g., approximately 0.1-10 μm. However, as also described above, providing more segments 145 of contact shield structure 140c can improve avalanche robustness at the expense of on-resistance Rds,on.In some embodiments, semiconductor devices including the segmented contact shielding structures 140c (i.e., including spacing between support shielding structures 140c1 and / or bridge shielding structures 140c2) described herein can be configured to achieve greater than a 5% (e.g., about 5% to about 30%) reduction in on-resistance compared to devices having continuously extending shielding structures, and greater than about a 5% (e.g., about 5% to about 30%) increase in avalanche ruggedness compared to devices having continuously extending (i.e., non-segmented) shielding structures.

[0176] 16-22 are described in the context of a trench gate configuration in which gates 184 are provided within respective gate trenches 180 that include opposing sidewalls and a bottom surface between the sidewalls and extend into drift region 120. However, embodiments of the present disclosure are not limited to such gate configurations and may include planar gate configurations (e.g., as shown in FIG. 2B) as well. Bottom shielding structure 140a may extend continuously beneath gate 184 or may include one or more separate segments extending beneath gate 184. Bottom shielding structure 140a and / or gate 184 / trench 180 may have a rectilinear, elliptical, or polygonal shape in a plan view.

[0177] As such, the embodiments described herein illustrate various examples of different combinations of shielding structures according to the present disclosure. However, it will be understood that embodiments of the present disclosure can include any and all combinations of the features described herein and are not limited to the exemplary patterns shown. Embodiments of the present invention may be used in trench or planar gate vertical semiconductor power transistors, including, but not limited to, MOSFETs, IGBTs, or other power devices where contact to a shielding region below and / or spaced from a well or gate is desired.

[0178] In the above description, each exemplary embodiment is described in terms of regions of a particular conductivity type. It will be understood that devices of the opposite conductivity type can be formed by simply reversing the conductivity of the n-type and p-type layers in each of the above embodiments. Thus, it will be understood that the present invention covers both n-channel and p-channel devices for each different device structure (e.g., MOSFET, IGBT, etc.).

[0179] The present invention has been discussed above primarily with respect to silicon carbide-based power semiconductor devices. However, it will be understood that silicon carbide is used herein as an example and that the devices discussed herein may be formed in any suitable wide bandgap semiconductor material system. By way of example, a gallium nitride-based semiconductor material (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used in place of silicon carbide in any of the above embodiments. More generally, although discussed in connection with silicon carbide devices, embodiments of the present invention are not so limited and may have applicability to devices formed using other wide bandgap semiconductor materials, such as gallium nitride, zinc selenide, or any other II-VI or III-V wide bandgap compound semiconductor material.

[0180] Embodiments of the present invention have been described above with reference to the accompanying drawings, in which embodiments of the invention are shown. It will be understood, however, that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth above. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numerals refer to like elements throughout.

[0181] While terms such as first, second, etc. are used throughout this specification to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present invention. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0182] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0183] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that it can be directly on or extending directly onto the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it will be further understood that it can be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0184] Comparative terms such as "lower," "upper," "upper," "lower," "top," or "bottom" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0185] Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. In the drawings, layer thicknesses and areas may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations are to be expected as a result, for example, of production techniques and / or tolerances. Embodiments of the present invention will be further described with reference to manufacturing operations. It will be understood that the steps shown in a manufacturing operation do not have to be performed in the order shown.

[0186] Some embodiments of the present invention are described in terms of semiconductor layers and / or regions characterized as having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration within the layer and / or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, while p-type material has a majority equilibrium concentration of positively charged holes. Some materials may be designated using a "+" or "-" (as in n+, n-, p+, p-, n++, n--, p++, or p--) to denote a relatively larger ("+") or smaller ("-") concentration of majority carriers compared to another layer or region. However, such designations do not imply the presence of a particular concentration of majority or minority carriers within the layer or region.

[0187] In the drawings and specification, exemplary embodiments of the invention have been disclosed and, although specific terms have been employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

1. A semiconductor device comprising: a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type above the drift region; a gate on the semiconductor layer structure adjacent to the well region; a buried shielding structure of the second conductivity type below the well region and separated from the well region by a portion of the drift region; A semiconductor device comprising:

2. further comprising at least one contact shielding structure of the second conductivity type extending vertically into the drift region and laterally spaced from the gate; the buried shield structure extends laterally in the drift region from beneath the well region to the at least one contact shield structure; The semiconductor device of claim 1 .

3. the semiconductor layer structure further comprises a gate trench having sidewalls and a bottom surface between the sidewalls and extending into the drift region, the gate being in the gate trench; the semiconductor device further comprising a bottom shielding structure of the second conductivity type below the bottom surface of the gate trench, the buried shielding structure extending laterally from the bottom shielding structure to the at least one contact shielding structure. The semiconductor device of claim 2 .

4. The semiconductor device of claim 2 , wherein at least one of the buried shielding structure and the contact shielding structure comprises a material different from a material of the drift region.

5. 5. The semiconductor device of claim 4, wherein the drift region comprises a wide bandgap semiconductor material, and the at least one of the buried shielding structure and the contact shielding structure comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

6. 2. The semiconductor device of claim 1, wherein the buried shielding structure has a different concentration of dopants of the second conductivity type than the well region.

7. the semiconductor layer structure a substrate, the drift region being on the substrate; and a drain contact on the substrate opposite the drift region; Furthermore, the buried shielding structure extends laterally into the drift region between the well region and the drain contact; The semiconductor device of claim 1 .

8. 8. The semiconductor device of claim 7, wherein the semiconductor layer structure further comprises a current spreading region of the first conductivity type extending between the well region and the drain contact, the current spreading region having a greater dopant concentration than the drift region.

9. 8. The semiconductor device of claim 7, wherein the embedded shielding structure comprises a pattern including one or more segments extending in a first lateral direction, and the gate extends in a second lateral direction different from the first lateral direction.

10. 10. The semiconductor device of claim 9, wherein a width of each of the one or more segments along the second lateral direction is about 0.1 to 20 μm.

11. The semiconductor device of claim 9 , wherein the one or more segments of the embedded shielding structure and / or the gate present a rectilinear, elliptical, or polygonal shape in plan view.

12. 10. The semiconductor device of claim 9, wherein the one or more segments are laterally spaced apart such that at least a portion of a conductive path between the well region and the drain contact extends laterally along the buried shielding structure in the second lateral direction.

13. 8. The semiconductor device of claim 7, wherein the gate comprises a first gate of a first transistor in the semiconductor layer structure, and the buried shielding structure comprises a second gate of a second transistor in the semiconductor layer structure.

14. 14. The semiconductor device of claim 13, wherein the first transistor and the second transistor are electrically coupled in a cascode amplifier configuration.

15. the semiconductor layer structure further comprises a source region of the first conductivity type above the well region; the semiconductor device further comprising a source contact on a surface of the semiconductor layer structure opposite the drain contact, the source contact being electrically coupled to the source region and the buried shielding structure.

15. The semiconductor device of claim 14.

16. A semiconductor device comprising: A semiconductor layer structure comprising: a drift region of a first conductivity type; a buried shielding structure of a second conductivity type in the drift region; a well region of the second conductivity type above the drift region; a source region of the first conductivity type above the well region; a semiconductor layer structure comprising: the source region, the well region, and a first portion of the drift region between the well region and the buried shield structure provide a pn junction of a first transistor; the first portion of the drift region, the buried shielding structure, and the second portion of the drift region provide a pn junction of a second transistor; Semiconductor devices.

17. a gate on the semiconductor layer structure adjacent to the well region; the gate comprises a first gate of the first transistor, and the recessed shielding structure comprises a second gate of the second transistor.

17. The semiconductor device of claim 16.

18. 20. The semiconductor device of claim 17, wherein the first transistor and the second transistor are electrically coupled in a cascode amplifier configuration.

19. 20. The semiconductor device of claim 18, further comprising a source contact on a surface of the semiconductor layer structure opposite the drain contact, the source contact electrically coupled to the source region and the buried shielding structure.

20. the semiconductor layer structure further comprising a gate trench having sidewalls and a bottom surface between the sidewalls and extending into the drift region, the gate being within the gate trench; at least one contact shielding structure of the second conductivity type extends vertically from the sidewall of the gate trench into the laterally spaced drift region and contacts the buried shielding structure; or a metal layer extending from the source contact along at least one of the sidewalls of the gate trench and contacting the recessed shielding structure; 20. The semiconductor device of claim 19.

21. A semiconductor device comprising: a semiconductor layer structure having a first surface and a second surface opposite the first surface; a gate adjacent to the first surface of the semiconductor structure; a drain contact on the second surface of the semiconductor structure; and a first transistor and a second transistor in the semiconductor layer structure electrically coupled in a cascode amplifier configuration between the first surface and the second surface of the semiconductor layer structure; A semiconductor device comprising:

22. the semiconductor layer structure a drift region of a first conductivity type; a buried shielding structure of a second conductivity type in the drift region; a well region of the second conductivity type above the drift region; a source region of the first conductivity type above the well region; Equipped with the source region, the well region, and a first portion of the drift region between the well region and the buried shield structure implement the first transistor; the first portion of the drift region, the buried shielding structure, and the second portion of the drift region realizing the second transistor.

22. The semiconductor device of claim 21.

23. 23. The semiconductor device of claim 22, further comprising a source contact on the first surface of the semiconductor layer structure, the source contact electrically coupled to the source region and the buried shielding structure.

24. the semiconductor layer structure a gate trench having sidewalls and a bottom surface between the sidewalls and extending into the drift region, the gate being in the gate trench; at least one contact shielding structure of the second conductivity type extends vertically from the sidewall of the gate trench into the laterally spaced drift region and contacts the buried shielding structure; or a metal layer extending from the source contact along at least one of the sidewalls of the gate trench and contacting the recessed shielding structure; 24. The semiconductor device of claim 23.

25. 1. A method for manufacturing a semiconductor device, comprising: providing a drift region of a first conductivity type; providing a buried shielding structure of a second conductivity type within the drift region; providing a well region of the second conductivity type above the drift region and spaced from the buried shield structure, the drift region, the buried shield structure, and the well region forming a semiconductor layer structure; providing a gate on the semiconductor layer structure adjacent the well region; A method comprising:

26. 26. The method of claim 25, wherein the buried shielding structure comprises a pattern including one or more segments extending laterally into the drift region.

27. providing the recessed shielding structure includes: forming a first portion of the drift region by a first epitaxy process; forming the buried shielding structure in or over the first portion of the drift region; forming a second portion of the drift region on the buried shield structure by a second epitaxy process; 27. The method of claim 26, comprising:

28. 28. The method of claim 27, wherein forming the buried shielding structure comprises implanting dopants of the second conductivity type into the first portion of the drift region or depositing material of the second conductivity type on the first portion of the drift region to form the buried shielding structure.

29. further comprising forming a mask pattern on the first portion of the drift region prior to the implanting step or the depositing step; the implanting or depositing step is performed in or on areas of the drift region exposed by the mask pattern to form the pattern of the buried shielding structure; 29. The method of claim 28.

30. the implanting step or the depositing step is performed as a blanket process without a mask pattern; The method comprises: forming a mask pattern over the first portion of the drift region after the implanting step or the depositing step; performing an etching process on areas of the first portion of the drift region exposed by the mask pattern to form the pattern of the buried shielding structure; 30. The method of claim 28, further comprising:

31. forming a current spreading region in the first portion of the drift region, the current spreading region including a greater concentration of dopants of the first conductivity type; the buried shielding structure extends adjacent to the current spreading region; 28. The method of claim 27.

32. providing the recessed shielding structure includes: forming a mask pattern on a surface of the drift region; implanting dopants of the second conductivity type into areas of the drift region exposed by the mask pattern at an implant energy corresponding to a predetermined depth below the surface of the drift region to form the pattern of the buried shielding structure; 27. The method of claim 26, comprising:

33. the semiconductor layer structure includes a substrate, the drift region is on the substrate, the method further comprising providing a drain contact on the substrate opposite the drift region, the buried shielding structure extending laterally into the drift region between the well region and the drain contact.

27. The method of claim 26.

34. 34. The method of claim 33, wherein the gate comprises a first gate of a first transistor in the semiconductor layer structure, and the buried shielding structure comprises a second gate of a second transistor in the semiconductor layer structure.

35. 35. The method of claim 34, wherein the first transistor and the second transistor are electrically coupled in a cascode amplifier configuration.

36. providing a source region of the first conductivity type above the well region; providing a source contact on a surface of the semiconductor layer structure opposite the drain contact; further comprising the source contact is electrically coupled to the source region and the buried shield structure; 36. The method of claim 35.

37. the step of providing a gate comprises: forming a gate trench having sidewalls and a bottom surface between said sidewalls, said gate trench extending through said source region and said well region into said semiconductor surface to a depth of about 0.3 to about 10 μm relative to said surface; forming the gate in the gate trench; 37. The method of claim 36, comprising:

38. forming at least one contact shielding structure of the second conductivity type extending vertically from the sidewall of the gate trench into the laterally spaced drift region so as to contact the buried shielding structure; or forming a metal layer extending from the source contact along at least one of the sidewalls of the gate trench so as to contact the buried shielding structure; 38. The method of claim 37, further comprising:

39. 27. The method of claim 26, wherein the one or more segments extend in a first lateral direction, the gate extends in a second lateral direction different from the first lateral direction, and a width of each of the one or more segments along the second lateral direction is about 0.1 to 20 μm.

40. 27. The method of claim 26, wherein the one or more segments of the embedded shielding structure and / or the gate present a rectilinear, elliptical, or polygonal shape in plan view.

41. 26. The method of claim 25, wherein the buried shielding structure has a different concentration of dopants of the second conductivity type than the well region.

42. The method of claim 25 , wherein the buried shielding structure comprises a material different from a material of the drift region.

43. 1. A method for manufacturing a semiconductor device, comprising: forming a first portion of a drift region; forming a buried shielding structure of a second conductivity type within or over the first portion of the drift region; forming a second portion of the drift region over the buried shield structure; forming a well region of the second conductivity type above the drift region and spaced from the buried shield structure, the drift region, the buried shield structure, and the well region forming a semiconductor layer structure; forming a gate on the semiconductor layer structure adjacent the well region; A method comprising:

44. the buried shielding structure comprises a pattern including one or more segments extending laterally within the drift region; forming the buried shielding structure includes implanting dopants of the second conductivity type into the first portion of the drift region or depositing material of the second conductivity type on the first portion of the drift region to form the buried shielding structure; 44. The method of claim 43.

45. further comprising forming a mask pattern on the first portion of the drift region prior to the implanting step or the depositing step; the implanting or depositing step is performed in or on areas of the first portion of the drift region exposed by the mask pattern to form the pattern of the buried shielding structure in or on areas of the first portion of the drift region.

45. The method of claim 44.

46. the implanting step or the depositing step is performed as a blanket process without a mask pattern; The method comprises: forming a mask pattern over the first portion of the drift region after the implanting step or the depositing step; performing an etching process on areas of the first portion of the drift region exposed by the mask pattern to form the pattern of the buried shielding structure; 45. The method of claim 44, further comprising:

47. 1. A method for manufacturing a semiconductor device, comprising: forming a drift region of a first conductivity type; forming a buried shielding structure of a second conductivity type within the drift region below a surface of the drift region; forming a well region of the second conductivity type above the drift region and spaced from the buried shield structure, the drift region, the buried shield structure, and the well region forming a semiconductor layer structure; forming a gate on the semiconductor layer structure adjacent the well region; A method comprising:

48. the buried shielding structure comprises a pattern including one or more segments extending laterally within the drift region, and forming the buried shielding structure comprises: forming a mask pattern on the surface of the drift region; implanting dopants of a second conductivity type into areas of the drift region exposed by the mask pattern at an implant energy corresponding to a predetermined depth below the surface of the drift region to form the pattern of the buried shielding structure; 48. The method of claim 47, comprising:

49. A semiconductor device comprising: a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type above the drift region; a gate on the semiconductor layer structure adjacent to the well region; one or more laterally discontinuous contact shield structures of the second conductivity type extending vertically from the well region to the drift region; A semiconductor device comprising:

50. 50. The semiconductor device of claim 49, wherein the contact shielding structure includes a plurality of separate segments each extending in the one or more laterally directions.

51. 51. The semiconductor device of claim 50, wherein the contact shield structure comprises a support shield structure extending in a first laterally direction and spaced apart from the gate.

52. a bottom shielding structure of the second conductivity type in the drift region below the gate; the contact shielding structure further comprises a bridge shielding structure extending in a second laterally direction transverse to the first laterally direction so as to contact the bottom shielding structure; 52. The semiconductor device of claim 51.

53. 53. The semiconductor device of claim 52, wherein at least one of the support shielding structure or the bridge shielding structure comprises the separate segments.

54. the semiconductor layer structure further comprising a gate trench having opposing sidewalls and a bottom surface between the sidewalls and extending into the drift region, the gate being in the gate trench; the bottom shielding structure extends below the bottom surface of the gate trench.

54. The semiconductor device of claim 53.

55. 55. The semiconductor device of claim 54, wherein the bridge shielding structure extends along both of the opposing sidewalls of the gate trench.

56. 46. ​​The semiconductor device of claim 45, wherein the bridge shielding structure comprises the separate segments, one of the opposing sidewalls of the gate trench having one of the bridge shielding structures thereon, and the other of the opposing sidewalls of the gate trench being free of the one of the bridge shielding structures.

57. 53. The semiconductor device of claim 52, wherein the bottom shielding structure extends continuously beneath the gate.

58. 53. The semiconductor device of claim 52, wherein the bottom shielding structure includes one or more separate segments extending below the gate.

59. 53. The semiconductor device of claim 52, further comprising one or more laterally extending recessed shielding structures beneath the well region and separated from the well region by a portion of the drift region.

60. 53. The semiconductor device of claim 52, wherein the bottom shielding structure and / or the gate have a rectilinear, elliptical, or polygonal shape in plan view.

61. 53. The semiconductor device of claim 52, wherein at least a portion of the conductive path between the well region and the drain contact extends laterally below the bridge shielding structure.

62. 51. The semiconductor device of claim 50, wherein respective spacings between the separate segments are aligned along a direction transverse to the one or more lateral directions.

63. 51. The semiconductor device of claim 50, wherein each spacing between the distinct segments is staggered along a direction transverse to the one or more lateral directions.

64. 51. The semiconductor device of claim 50, wherein each spacing between the separate segments is less than each width of the separate segments.

65. 65. The semiconductor device of claim 64, wherein the width of each of the separate segments is from about 0.1 to about 20 μm.

66. the semiconductor layer structure a substrate, the drift region being on the substrate; and a drain contact on the substrate opposite the drift region; Furthermore, each spacing between the distinct segments includes a portion of the semiconductor layer structure that is free of the contact shielding structure; 51. The semiconductor device of claim 50.

67. the semiconductor layer structure further comprises a source region of the first conductivity type above the well region; the semiconductor device further comprising a source contact on a surface of the semiconductor layer structure opposite the drain contact, the source contact being electrically coupled to the source region and the contact shield structure.

67. The semiconductor device of claim 66.

68. 50. The semiconductor device of claim 49, wherein the contact shield structure has a different material and / or dopant concentration than that of the drift region.

69. A semiconductor device comprising: a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type above the drift region; a gate on the semiconductor layer structure adjacent to the well region; a support and shield structure of the second conductivity type extending vertically from the well region into the drift region and spaced apart from the gate; a bridge shield structure of the second conductivity type extending laterally from the support shield structure toward the gate; Equipped with at least one of the support shielding structure or the bridge shielding structure comprises a plurality of separate segments; Semiconductor devices.

70. 70. The semiconductor device of claim 69, wherein the separate segments each extend longitudinally in one or more lateral directions.

71. a bottom shielding structure of the second conductivity type in the drift region below the gate; the bridge shield structure extends laterally from the support shield structure so as to contact the bottom shield structure; 71. The semiconductor device of claim 70.

72. the semiconductor layer structure a gate trench having opposing sidewalls and a bottom surface between the sidewalls and extending into the drift region, the gate being in the gate trench; the bottom shielding structure extends below the bottom surface of the gate trench.

72. The semiconductor device of claim 71.

73. 73. The semiconductor device of claim 72, wherein the bridge shielding structure extends along both of the opposing sidewalls of the gate trench.

74. 73. The semiconductor device of claim 72, wherein the bridge shield structure comprises separate segments, one of the opposing sidewalls of the gate trench having the bridge shield structure thereon and the other of the opposing sidewalls of the gate trench being free of the bridge shield structure.

75. 71. The semiconductor device of claim 70, wherein the supporting shielding structure has a different material and / or dopant concentration than that of the bridge shielding structure.

76. 71. The semiconductor device of claim 70, wherein each spacing between the separate segments is less than a respective width of the separate segments along a direction transverse to the one or more lateral directions.

77. A semiconductor device comprising: a semiconductor layer structure including a drift region of a first conductivity type and a well region of a second conductivity type above the drift region; a gate on the semiconductor layer structure adjacent to the well region; a contact shield structure of the second conductivity type extending vertically from the well region to the drift region and including a plurality of segments having respective spacings between the segments; Equipped with the respective spacings being smaller than the respective widths of the segments; Semiconductor devices.

78. 78. The semiconductor device of claim 77, wherein said each width of said segments is between about 0.1 μm and about 20 μm.

79. 78. The semiconductor device of claim 77, wherein the semiconductor device has about 5% to about 30% increased avalanche resistance and about 5% to about 30% reduced on-resistance compared to a semiconductor device having a continuous shielding pattern.

80. 78. The semiconductor device of claim 77, wherein the segments extend longitudinally in one or more respective lateral directions with the respective spacings between the segments.

81. 81. The semiconductor device of claim 80, wherein the respective spacings between distinct segments are staggered along a direction transverse to the one or more lateral directions.

82. 81. The semiconductor device of claim 80, wherein the respective spacings between separate segments are aligned along a direction transverse to the one or more lateral directions.

83. the semiconductor layer structure a substrate, the drift region being on the substrate; and a drain contact on the substrate opposite the drift region; Furthermore, each of the gaps includes a portion of the semiconductor layer structure that is free of the contact shielding structure; 78. The semiconductor device of claim 77.

84. 78. The semiconductor device of claim 77, wherein the contact shield structure comprises a support shield structure extending in a first laterally direction and spaced apart from the gate.

85. a bottom shielding structure of the second conductivity type in the drift region below the gate; the contact shielding structure further comprises a bridge shielding structure extending in a second laterally direction transverse to the first laterally direction so as to contact the bottom shielding structure; 85. The semiconductor device of claim 84.

86. 86. The semiconductor device of claim 85, wherein at least one of the supporting shielding structure or the bridge shielding structure comprises the segment.

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