Isolation structures and integrated circuits

Abstract

The present invention relates to an isolation structure including a junction termination and a lateral double-diffused metal oxide semiconductor field effect transistor, the junction termination including a plurality of junction termination floating field plates, the lateral double-diffused metal oxide semiconductor field effect transistor including a plurality of LDMOS floating field plates, each LDMOS floating field plate electrically connected to at least one junction termination floating field plate, and a length of each junction termination floating field plate greater than a length of the LDMOS floating field plate electrically connected to the junction termination floating field plate.

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductor manufacturing, particularly isolation structures, and more particularly to integrated circuits. [Background technology]

[0002] This application claims priority to a Chinese patent application filed on June 15, 2023, application number 2023107143293, entitled "Isolation Structure and Integrated Circuit," the entire contents of which are incorporated herein by reference.

[0003] High-voltage integrated circuits contain high-voltage semiconductor devices and low-voltage semiconductor devices, i.e., high-voltage and low-voltage regions. Therefore, high-voltage and low-voltage regions must be isolated from each other by high- and low-voltage isolation structures. These isolation structures include junction terminations, isolation rings, and lateral double-diffused metal-oxide-semiconductor field-effect transistors (LDMOSs). LDMOSs are gates that transmit electrical signals between the high-voltage and low-voltage regions, making them vulnerable to breakdown when subjected to high voltages. Technical measures can be used to uniformize the potential distribution within the LDMOS, avoid potential line concentration, and increase the breakdown voltage of the LDMOS. Summary of the Invention [Problem to be solved by the invention]

[0004] According to some embodiments, an isolation structure is provided. [Means for solving the problem]

[0005] The isolation structure includes a junction termination and a lateral double-diffused metal oxide semiconductor field effect transistor, the junction termination including a plurality of junction termination floating field plates, the lateral double-diffused metal oxide semiconductor field effect transistor including a plurality of LDMOS floating field plates, each LDMOS floating field plate electrically connected to at least one junction termination floating field plate, and a length of each junction termination floating field plate greater than a length of the LDMOS floating field plate electrically connected to each junction termination floating field plate, the junction termination floating field plates and the LDMOS floating field plates being composed of a conductive material.

[0006] The isolation structure can be applied to an integrated circuit, and when a device in the integrated circuit operates, the junction termination floating field plate in the junction termination can generate an induced potential, which affects the potential of the lateral double-diffused metal-oxide-semiconductor field-effect transistor through the LDMOS floating field plate because the LDMOS floating field plate is electrically connected to the junction termination floating field plate. Each junction termination floating field plate induces a predetermined potential at the junction termination and transmits it to the lateral double-diffused metal-oxide-semiconductor field effect transistor via the LDMOS floating field plate. After that, each junction termination floating field plate corresponds to an external "voltage source" for the lateral double-diffused metal-oxide-semiconductor field effect transistor, and the potential within the lateral double-diffused metal-oxide-semiconductor field effect transistor is controlled by the junction termination floating field plate and the LDMOS floating field plate. Therefore, by simply controlling the spacing between the LDMOS floating field plates, the internal potential distribution within the lateral double-diffused metal-oxide-semiconductor field effect transistor can be indirectly controlled, and the spacing between the LDMOS floating field plates can be flexibly adjusted according to design needs. This allows for free control of the internal potential of the lateral double-diffused metal-oxide-semiconductor field effect transistor, uniforming the internal potential distribution within the LDMOS, and increasing the breakdown voltage of the LDMOS.

[0007] In one embodiment, the isolation structure further includes an isolation ring surrounding the lateral double-diffused metal oxide semiconductor field effect transistor, the isolation ring being used to isolate the lateral double-diffused metal oxide semiconductor field effect transistor from the junction termination.

[0008] In one embodiment, the isolation ring further includes a plurality of isolation ring floating field plates, each of which is electrically connected to a corresponding junction termination floating field plate via one of the isolation ring floating field plates, one end of each isolation ring floating field plate extending to the corresponding junction termination floating field plate, and the other end of each isolation ring floating field plate extending to the corresponding LDMOS floating field plate.

[0009] In one embodiment, the lateral double-diffused metal oxide semiconductor field effect transistor further includes a source region, a drain region, a gate, a drift region, and a field region insulating layer. At least a part of the drift region is located between the source region and the drain region. The field region insulating layer is located on the drift region. One side of the gate is close to the source region, and the other side is close to the drain region. The number of the LDMOS floating field plates is the same as the number of the junction termination floating field plates. The plurality of LDMOS floating field plates are electrically connected to the plurality of junction termination floating field plates in a one-to-one correspondence. The LDMOS floating field plate includes a first field plate provided close to the source region, a second field plate provided close to the drain region, and a third field plate located between the first field plate and the second field plate. The distance between adjacent third field plates is smaller than a2. The distance between the second field plate farthest from the drain region among the second field plates and an adjacent third field plate is larger than a3, and the distance between adjacent second field plates is larger than a3. The distance between the first field plate farthest from the source region among the first field plates and an adjacent third field plate is larger than a4, and the distance between adjacent first field plates is larger than a4, satisfying a2 < a3 and a2 < a4.

[0010] In one embodiment, the lateral double-diffused metal oxide semiconductor field effect transistor includes NLDMOS and PLDMOS. The isolation ring includes a first isolation ring surrounding the NLDMOS and a second isolation ring surrounding the PLDMOS. The length of each of the junction termination floating field plates is the sum of the length of the LDMOS floating field plate of the corresponding NLDMOS and the length of the LDMOS floating field plate of the corresponding PLDMOS.

[0011] In one embodiment, the junction termination further comprises a first insulating layer, and the plurality of junction termination floating field plates are located on the first insulating layer.

[0012] In one embodiment, the junction termination further includes a cathode region and an anode region, the conductivity types of the cathode region and the anode region being the same as the conductivity type of the drain region of the NLDMOS, the cathode region being electrically connected to the potential of the source region of the NLDMOS via a metal connection line, and the anode region being electrically connected to the potential of the drain region of the NLDMOS via a metal connection line.

[0013] In one embodiment, each junction-terminated floating field plate is connected in a closed loop with a corresponding isolation ring floating field plate and a corresponding LDMOS floating field plate.

[0014] In one embodiment, the isolation ring further includes an isolation junction, a protective well, and a second insulating layer, the plurality of isolation ring floating field plates are located on the second insulating layer, the second insulating layer is located on the isolation junction and the protective well, the conductivity type of the isolation junction and the protective well is opposite to the conductivity type of the drain region of the NLDMOS, and the doping concentration of the protective well is greater than the doping concentration of the isolation junction.

[0015] In one embodiment, each isolation ring floating field plate includes a junction termination connection portion, an LDMOS connection portion, and an intermediate portion, one end of the intermediate portion is connected to the junction termination connection portion, and an angle formed between the intermediate portion and an extension line of the junction termination connection portion in a plane is greater than 0 degrees and less than 80 degrees, the other end of the intermediate portion is connected to the LDMOS connection portion, and an angle formed between the intermediate portion and an extension line of the LDMOS connection portion in a plane is greater than 0 degrees and less than 80 degrees, the protective well is provided directly below a connection position between at least some of the junction termination connection portions and the intermediate portion, and the protective well is provided directly below a connection position between at least some of the LDMOS connection portions and the intermediate portion.

[0016] The protective well includes strip-shaped doped regions provided at connection positions between the plurality of junction termination connection portions and the intermediate portion, and strip-shaped doped regions at connection positions between the plurality of LDMOS connection portions and the intermediate portion, and / or the protective well includes point-shaped doped regions provided at connection positions between the plurality of junction termination connection portions and the intermediate portion and arranged in a row, and point-shaped doped regions provided at connection positions between the plurality of LDMOS connection portions and the intermediate portion and arranged in a row.

[0017] In one embodiment, the distance from the connection position between the junction termination connection portion and the intermediate portion to the edge of the isolation ring is b1, and the distance from the connection position between the LDMOS connection portion and the intermediate portion to the edge of the isolation ring is b2, where b1 is 10% to 30% of the width of the isolation ring and b2 is 10% to 30% of the width of the isolation ring.

[0018] In one embodiment, the junction termination floating field plate, the isolation ring floating field plate, and the LDMOS floating field plate are made of the same material and are fabricated in the same fabrication steps.

[0019] In one embodiment, the material of the gate is the same as the materials of the junction termination floating field plate, the isolation ring floating field plate, and the LDMOS floating field plate, and is formed by manufacturing in the same manufacturing step.

[0020] In one embodiment, the junction termination floating field plate, the isolation ring floating field plate, and the LDMOS floating field plate are made of doped polysilicon.

[0021] In one embodiment, the intervals between adjacent junction termination floating field plates are equal.

[0022] In one embodiment, the interval between adjacent junction termination floating field plates is a1, and satisfies a2 < a1 < a3 and a2 < a1 < a4.

[0023] In one embodiment, the interval between adjacent junction termination floating field plates is 1.0 - 3.2 μm, the interval between adjacent third field plates is 0.5 - 3.0 μm, the interval between adjacent first field plates, and the interval between one of the first field plates farthest from the source region and one adjacent third field plate is 1.2 - 4.0 μm, the interval between adjacent second field plates, and the interval between one of the second field plates farthest from the drain region and one adjacent third field plate is 1.2 - 4.0 μm.

[0024] Furthermore, an integrated circuit needs to be provided.

[0025] This integrated circuit includes a first voltage region, a second voltage region, and an isolation structure located between the first voltage region and the second voltage region, and the isolation structure is the isolation structure described in any of the above embodiments.

[0026] The operating voltage of the device in the second voltage domain is greater than the operating voltage of the device in the first voltage domain.

[0027] In the integrated circuit, when the devices in the first and second voltage domains operate, the junction termination floating field plate in the junction termination can generate an induced potential. Because the LDMOS floating field plate is electrically connected to the junction termination floating field plate, the induced potential affects the potential of the lateral double-diffused metal-oxide-semiconductor field-effect transistor through the LDMOS floating field plate. Because potential lines converge at the source and drain of the lateral double-diffused metal-oxide-semiconductor field-effect transistor, increasing the spacing between the first and second field plates located near the source and drain regions and narrowing the spacing between the third field plates located at the middle of the drift region reduces the potential gradient near the source and drain regions of the lateral double-diffused metal-oxide-semiconductor field-effect transistor and increases the potential gradient near the middle of the drift region, thereby making the potential distribution in the lateral double-diffused metal-oxide-semiconductor field-effect transistor more uniform and increasing the breakdown voltage of the LDMOS.

[0028] In one embodiment, the drain of the NLDMOS is connected to the potential of the second voltage domain, and the source of the NLDMOS is grounded. [Brief explanation of the drawings]

[0029] To better describe and illustrate the embodiments and / or examples of the invention disclosed herein, reference may be made to one or more drawings. Any additional details or examples used to illustrate the drawings should not be deemed to limit the scope of the disclosed invention, either of the presently described embodiments and / or examples, or of the best mode of such invention as currently understood. [Figure 1] FIG. 1 is a front view of an integrated circuit according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along the line AA' shown in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along the line BB′ shown in FIG. [Figure 4] FIG. 2 is a cross-sectional view taken along the line CC' shown in FIG. [Figure 5] FIG. 2 is a cross-sectional view taken along the line DD′ shown in FIG. [Figure 6] FIG. 2 is a cross-sectional view taken along the line EE' shown in FIG. [Figure 7] 2 is a local enlarged view of the first isolation ring shown in FIG. 1. [Figure 8] FIG. 10 is a local enlarged view of the vicinity of a first isolation ring in one embodiment. [Figure 9] FIG. 2 is a cross-sectional view taken along line DD' shown in FIG. 1 in an embodiment having a protective well. [Figure 10] FIG. 2 is a cross-sectional view taken along line EE' shown in FIG. 1 in an embodiment having a protective well. [Figure 11] 1. FIG. 4 is a cross-sectional view taken along line DD' shown in FIG. 1 in yet another embodiment having a protective well. [Figure 12] 1. FIG. 5 is a cross-sectional view taken along line EE' shown in FIG. 1 in yet another embodiment having a protective well. [Figure 13] FIG. 10 is a local enlarged view of the vicinity of a first isolation ring in another embodiment. [Figure 14] FIG. 10 is a local enlarged view of the vicinity of a first isolation ring in yet another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0030] To facilitate an understanding of the present invention, the present invention will now be described more fully hereinafter with reference to the associated drawings. Preferred embodiments of the present invention are illustrated in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more complete disclosure of the present invention.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terms used herein are for the purpose of describing particular examples only and are not intended to limit the invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] When an element or layer is referred to as being "located on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly located on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. When an element or layer is referred to as being "directly located on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. In this specification, "connection" should be understood as "electrical connection," "communication connection," etc., when it involves the transmission of electrical signals or data between connected circuits, modules, units, etc. Note that terms such as first, second, and third may be used to describe various elements, components, regions, layers, and / or sections, but these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0033] Spatially relative terms such as "below," "below," "below," "below," "above," and the like may be used herein to readily describe the relationship of one element or feature to another element or feature shown in a figure. Note that spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if a device in a figure were inverted, an element or feature described as "below" or "beneath" or "beneath" another element or feature would be oriented as "above" the other element or feature. Thus, the exemplary terms "below" and "below" can encompass both an orientation of above and below. A device may be oriented differently (rotated 90 degrees or at another orientation), and the spatial terms used herein may be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms "a," "an," and "said" are intended to include the plural forms unless the context clearly dictates otherwise. It should be understood that "at least one" means one or more and "plurality" means two or more. "At least some of the elements" means some or all of the elements. It will be further understood that the terms "consisting of" and / or "including," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0035] Embodiments of the present invention are described herein with reference to cross sections that are schematic illustrations of idealized embodiments of the present invention (and intervening structures). As such, variations from the shapes depicted due, for example, to manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein but should include deviations in shape that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle typically has rounded or curved features at its edges and / or an implant concentration gradient, rather than a binary transition from implanted to non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the implanted region and the plane where the implantation occurs. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to represent the actual shape of a region of a device, nor are they intended to limit the scope of the present invention.

[0036] The terms in the semiconductor field used in this specification are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type indicates a P-type with a high doping concentration, P-type indicates a P-type with a medium doping concentration, P-type indicates a P-type with a low doping concentration, N+ type indicates an N-type with a high doping concentration, N-type indicates an N-type with a medium doping concentration, and N-type indicates an N-type with a low doping concentration.

[0037] According to some embodiments, a semiconductor high- and low-voltage isolation structure is proposed, in which a variable-pitch field plate is used to control the potential of the LDMOS in the isolation structure, thereby adjusting and controlling the potential distribution and surface electric field distribution in the LDMOS drift region, thereby preventing the LDMOS from becoming a weak point for breakdown in the isolation structure and achieving a high- and low-voltage isolation structure with better isolation capabilities. Figure 1 is a schematic diagram of an integrated circuit according to one embodiment, which includes a low-voltage region 100, a high-voltage region 300, and an isolation structure located between the low-voltage region 100 and the high-voltage region 300. The operating voltage of devices in the high-voltage region 300 is higher than the operating voltage of devices in the low-voltage region 100, and the isolation structure is used to isolate the potential between the high-voltage region 300 and the low-voltage region 100.

[0038] In one embodiment, the isolation structure includes a junction termination 210 and a lateral double-diffused metal oxide semiconductor field effect transistor.

[0039] The junction termination 210 includes a plurality of junction termination floating field plates 211. The lateral double-diffused metal oxide semiconductor field effect transistor includes a plurality of LDMOS floating field plates 251. Each LDMOS floating field plate 251 is electrically connected to at least one junction termination floating field plate 211. The length of each junction termination floating field plate 211 is greater than the length of the LDMOS floating field plate 251 electrically connected to it. Each junction termination floating field plate 211 and LDMOS floating field plate 251 is composed of a conductive material.

[0040] In this embodiment, the multiple LDMOS floating field plates 251 are electrically connected to the multiple junction termination floating field plates 211 in a one-to-one correspondence, i.e., one LDMOS floating field plate 251 is electrically connected to one junction termination floating field plate 211. In other embodiments, one junction termination floating field plate 211 may be connected to multiple LDMOS floating field plates 251, i.e., an LDMOS floating field plate 251 electrically connected to a certain junction termination floating field plate 211 is branched into multiple branches in the LDMOS region. Alternatively, one LDMOS floating field plate 251 is connected to multiple junction termination floating field plates 211, i.e., a junction termination floating field plate 211 electrically connected to a certain LDMOS floating field plate 251 is branched into multiple branches in the junction termination region.

[0041] When devices in the integrated circuit (i.e., low-voltage devices in the low-voltage region 100 and high-voltage devices in the high-voltage region 300) are operating, the junction termination floating field plate 211 in the junction termination 210 can generate an induced potential. Because the LDMOS floating field plate 251 is electrically connected to the junction termination floating field plate 211, the induced potential affects the potential of the lateral double-diffused metal-oxide-semiconductor field effect transistor through the LDMOS floating field plate 251. Each junction termination floating field plate 211 induces a predetermined potential in the junction termination 210 and transmits it to the lateral double-diffused metal-oxide-semiconductor field effect transistor through the junction termination floating field plate 211 and the LDMOS floating field plate 251. After that, each junction termination floating field plate 211 corresponds to an external "voltage source" for the lateral double-diffused metal-oxide-semiconductor field effect transistor, and the potential in the lateral double-diffused metal-oxide-semiconductor field effect transistor is controlled by the junction termination floating field plate 211 and the LDMOS floating field plate 251. Therefore, by simply controlling the spacing between the LDMOS floating field plates 251, the potential distribution inside the lateral double-diffused metal-oxide-semiconductor field-effect transistor can be indirectly controlled, and the spacing between the LDMOS floating field plates 251 can be flexibly adjusted according to design needs, thereby realizing free control of the potential inside the lateral double-diffused metal-oxide-semiconductor field-effect transistor.

[0042] The isolation structure shown in FIG. 1 further includes an isolation ring surrounding the lateral double-diffused metal oxide semiconductor field effect transistor, which is used to isolate the lateral double-diffused metal oxide semiconductor field effect transistor from the junction termination 210. The isolation ring is connected to the lateral double-diffused metal oxide semiconductor field effect transistor and the junction termination 210. In the embodiment shown in FIG. 1, the isolation ring includes a first isolation ring 230 and a second isolation ring 250, and the lateral double-diffused metal oxide semiconductor field effect transistor includes an NLDMOS 220 and a PLDMOS 240. The first isolation ring 230 surrounds the NLDMOS 220, and the second isolation ring 250 surrounds the PLDMOS 240. A floating field plate refers to a field plate that is not connected to a potential. The main structure of the first isolation ring 230 and the second isolation ring 250 is an isolation junction 233 (see FIG. 5), and in one embodiment of the present application, the isolation junction is a P-type doped region.

[0043] 2 is a cross-sectional view taken along line A-A' in FIG. 1. Referring to FIGS. 1 and 2 together, in one embodiment, NLDMOS 220 includes source region 222, drain region 224, gate 226, drift region 223, field region insulating layer 32, and LDMOS floating field plate 251. At least a portion of drift region 223 is located between source region 222 and drain region 224, and field region insulating layer 32 is located on drift region 223. Gate 226 is adjacent to source region 222 on one side and adjacent to drain region 224 on the other side. Source region 222 and gate 226 are located adjacent to low-voltage region 100, and drain region 224 is located adjacent to high-voltage region 300. The number of LDMOS floating field plates 251 is the same as the number of junction-terminated floating field plates 211, and the multiple LDMOS floating field plates 251 are electrically connected to the multiple junction-terminated floating field plates 211 in a one-to-one correspondence. Each LDMOS floating field plate 251 includes a first field plate adjacent to the source region 222, a second field plate adjacent to the drain region 224, and a third field plate located between the first and second field plates. In the embodiment shown in FIGS. 1 and 2 , the number of LDMOS floating field plates 251 is N. Starting from the LDMOS floating field plate 251 closest to the drain region 224, the 1st to p-1th are second field plates, the pth to N-mth are third field plates, and the N-m+1th to Nth are first field plates. The spacing between adjacent third field plates is smaller than a2. The distance between one of the multiple second field plates that is farthest from the drain region 224 (i.e., p-1) and the adjacent third field plate (i.e., p) is greater than a3, and the distance between adjacent second field plates is also greater than a3.Among the plurality of first field plates, the distance between the one farthest from the source region 222 (i.e., N−m + 1) and the adjacent third field plate (i.e., N−m) is greater than a4, and the distance between adjacent first field plates is greater than a4. The relationship among a2, a3, and a4 satisfies a2 < a3 and a2 < a4. That is, the distance between the first field plate provided close to the source region 222 and the second field plate provided close to the drain region 224 is widely installed, and the distance between the third field plates located at the intermediate position of the drift region 223 is narrowly installed.

[0044] 3 is a cross-sectional view taken along line BB' in FIG. 1. Referring to FIGS. 1 and 3 together, in one embodiment, PLDMOS 240 includes source region 242, drain region 244, gate 246, drift region 243, field region insulating layer 34, and LDMOS floating field plate 251. At least a portion of drift region 243 is located between source region 242 and drain region 244, and field region insulating layer 34 is located on drift region 243. Gate 246 is adjacent to source region 242 on one side and adjacent to drain region 244 on the other side. Source region 242 and gate 246 are located adjacent to high-voltage region 300, and drain region 244 is located adjacent to low-voltage region 100. The number of LDMOS floating field plates 251 is the same as the number of junction termination floating field plates 211, and the multiple LDMOS floating field plates 251 are electrically connected to the multiple junction termination floating field plates 211 in a one-to-one correspondence. Each LDMOS floating field plate 251 includes a first field plate provided adjacent to the source region 242, a second field plate provided adjacent to the drain region 244, and a third field plate located between the first and second field plates. In the embodiment shown in FIGS. 1 and 3 , the number of LDMOS floating field plates 251 is N, and starting from the LDMOS floating field plate 251 closest to the source region 242, the 1st to p-1th LDMOS floating field plates are first field plates, the pth to N-mth LDMOS floating field plates are third field plates, and the N-m+1th to Nth LDMOS floating field plates are second field plates.The distance between adjacent third field plates is smaller than a2. Among the plurality of second field plates, the distance between the one second field plate (i.e., the (N−m + 1)-th one) that is farthest from the drain region 244 and the adjacent third field plate (i.e., the (N−m)-th one) is larger than a3, and the distance between adjacent second field plates is larger than a3. Among the plurality of first field plates, the distance between the one first field plate (i.e., the (p−1)-th one) that is farthest from the source region 242 and the adjacent third field plate (i.e., the p-th one) is larger than a4, and the distance between adjacent first field plates is larger than a4. Then, the relationship among a2, a3, and a4 satisfies a2 < a3 and a2 < a4. That is, the distance between the first field plate provided close to the source region 242 and the second field plate provided close to the drain region 244 is widely installed, and the distance between the third field plates located at the intermediate position of the drift region 243 is narrowly installed.

[0045] The length of each junction terminal floating field plate 211 is larger than the length of the corresponding LDMOS floating field plate, whereby the potential of the junction terminal floating field plate 211 is dominant. Taking FIG. 1 as an example, that is, the length of each junction terminal floating field plate 211 is larger than the sum of the lengths of the LDMOS floating field plates 251 in the corresponding NLDMOS 220 and the LDMOS floating field plates 251 in the PLDMOS 240.

[0046] Because potential lines are concentrated at the source and drain of a lateral double-diffused metal-oxide-semiconductor field-effect transistor, by widely spacing the first and second field plates located close to the source and drain regions and narrowly spacing the third field plate located at the middle of the drift region, the potential gradient near the source and drain regions of the lateral double-diffused metal-oxide-semiconductor field-effect transistor can be reduced and the potential gradient near the middle of the drift region can be increased, thereby making the potential distribution of the lateral double-diffused metal-oxide-semiconductor field-effect transistor more uniform and improving the breakdown voltage of the LDMOS in an isolation structure.

[0047] 1 , the isolation ring further includes a plurality of isolation ring floating field plates 231, the number of which is the same as the number of junction termination floating field plates 211. Each junction termination floating field plate 211 is electrically connected in one-to-one correspondence to a corresponding LDMOS floating field plate 251 via a corresponding isolation ring floating field plate 231. One end of each isolation ring floating field plate 231 extends to the corresponding junction termination floating field plate 211, and the other end extends to the corresponding LDMOS floating field plate 251.

[0048] In one embodiment, the distance between adjacent junction termination floating field plates is a1, and a2 < a1 < a3 and a2 < a1 < a4 are satisfied. In addition to satisfying the above conditions a2 < a1 < a3 and a2 < a1 < a4, the distance between adjacent junction termination floating field plates 211 is 1.0 to 3.2 μm, the distance between adjacent third field plates is 0.5 to 3.0 μm, the distance between adjacent first field plates, and the distance between one first field plate farthest from the source region and the adjacent third field plate is 1.2 to 4.0 μm, the distance between adjacent second field plates, and the distance between one second field plate farthest from the drain region and the adjacent third field plate is 1.2 to 4.0 μm.

[0049] In one embodiment of the present application, adjacent junction termination floating field plates 211 are evenly distributed at an interval L1. In NLDMOS220, the first to p-th LDMOS floating field plates 251 close to the drain region 224 are evenly distributed at an interval L3, the N-m-th to N-th LDMOS floating field plates 251 close to the source region 222 are evenly distributed at an interval L4, and the remaining p-th to N-m-th LDMOS floating field plates 251 are evenly distributed at an interval L2. In PLDMOS240, the first to p-th LDMOS floating field plates 251 close to the source region 242 are evenly distributed at an interval L6, the N-m-th to N-th LDMOS floating field plates 251 close to the drain region 244 are evenly distributed at an interval L7, and the remaining p-th to N-m-th LDMOS floating field plates 251 are evenly distributed at an interval L5. Further, the relationships L1 > L2, L1 > L5, L3 > L, L4 > L1, L6 > L1, and L7 > L1 are satisfied.

[0050] In one embodiment, the total number N of the floating field plates ranges from 10 to 100, the values ​​of p and m range from 2 to 15, and the value of N-p-m ranges from 1 to 96.

[0051] In one embodiment, source region 222 and drain region 224 of NLDMOS 220 are N+ regions, and drift region 223 is an N-type drift region. Source region 242 and drain region 244 of PLDMOS 240 are P+ regions, and drift region 243 is a P-type drift region.

[0052] 2, the NLDMOS 220 further includes a body region 221, a P-well 225, an N-well 227, a deep N-well 229, and a P-type buried layer 228. The body region 221 and the source region 222 are shorted after being drawn out through contact holes. The body region 221 and the source region 222 are located in the P-well 225. The drain region 224 is located in the N-well 227. The field region insulating layer 32 of the NLDMOS 220 is located between the source region 222 and the drain region 224. The P-type buried layer 228 is located below the drift region 223 and the P-well 225. The deep N-well 229 is located below the drift region 223 and the N-well 227.

[0053] 3, PLDMOS 240 further includes a body region 241, a P-well 245, an N-well 247, a deep N-well 249, and a P-type buried layer 248. The body region 241 and the source region 242 are shorted after being drawn out through contact holes. The body region 241 and the source region 242 are located in the N-well 247. The drain region 244 is located in the P-well 245. The field region insulating layer 34 of PLDMOS 240 is located between the source region 242 and the drain region 244. The deep N-well 249 is located below the drift region 243 and the N-well 247. The P-type buried layer 248 is located in the deep N-well 249 and below the drift region 243 and the P-well 245.

[0054] In one embodiment, the drain of NLDMOS 220 is connected to the potential of high voltage region 300 and the source of NLDMOS 220 is grounded. In one embodiment, the source of PLDMOS 240 is connected to the potential of high voltage region 300 and the drain of PLDMOS 240 is grounded.

[0055] In one embodiment, the isolation structure (including the junction termination 210, isolation ring, and lateral double-diffused metal oxide semiconductor field effect transistor) further includes a substrate 10 located at the bottom and a passivation layer 20 located on the top surface of the device. In the embodiment shown in Figure 1, the substrate 10 is made of P-doped single crystal silicon.

[0056] In one embodiment, junction termination floating field plate 211, isolation ring floating field plate 231, and LDMOS floating field plate 251 are made of the same material and are fabricated in the same process. In one embodiment, junction termination floating field plate 211, isolation ring floating field plate 231, and LDMOS floating field plate 251 are made of doped polysilicon. In one embodiment, the material of the gate in a lateral double-diffused metal oxide semiconductor field effect transistor (including NLDMOS 220 and PLDMOS 240) is doped polysilicon. In one embodiment, junction termination floating field plate 211, isolation ring floating field plate 231, LDMOS floating field plate 251, gate 226, and gate 246 may be fabricated in the same process.

[0057] Figure 4 is a cross-sectional view taken along line CC' in Figure 1. Referring to Figures 1 and 4 together, in one embodiment, the junction termination 210 further includes a first insulating layer 31, and each junction termination floating field plate 211 is located on the first insulating layer 31.

[0058] In one embodiment, first insulating layer 31, field region insulating layer 32 and field region insulating layer 34 may be made of silicon oxide, for example silicon dioxide.

[0059] 4, the junction termination 210 further includes a cathode region 212 and an anode region 214. The conductivity types of the cathode region 212 and the anode region 214 are the same as the conductivity type of the drain region 224 of the NLDMOS 220, i.e., both are N+ regions. The cathode region 212 is electrically connected to the potential of the source region 222 of the NLDMOS 220 by a metal connection line (not shown) that is brought out through a contact hole, and the anode region 214 is electrically connected to the potential of the drain region 224 of the NLDMOS 220 by a metal connection line (not shown) that is brought out through a contact hole. Providing a structure similar to a gateless NLDMOS structure in the junction termination 210 is advantageous for isolation between the high-voltage region 300 and the low-voltage region 100.

[0060] 4, the junction termination 210 further includes an N-type region 213. At least a portion of the N-type region 213 is located between the cathode region 212 and the anode region 214, and the first insulating layer 31 is located on the N-type region 213. The function of the N-type region 213 is similar to that of a drift region.

[0061] 4, junction termination 210 further includes termination isolation junction 271. Termination isolation junction 271 is located between N-type region 213 and low voltage region 100, and between N-type region 213 and high voltage region 300. Termination isolation junction 271 has the same conductivity type as that of substrate 10. In an embodiment where substrate 10 is a P-type substrate, termination isolation junction 271 is a P-type doped region.

[0062] In one embodiment, the junction termination 210 further includes a body region 216, a P-well 215, an N-well 217, a deep N-well 219, and a P-type buried layer 218. The body region 216 and the cathode region 212 are shorted after being drawn out through a contact hole. The body region 216 and the cathode region 212 are located in the P-well 215. The anode region 214 is located in the N-well 217. The first insulating layer 31 is located between the P-well 215 and the N-well 217. The P-type buried layer 218 is located below the N-type region 213 and the P-well 215. The deep N-well 219 is located below the N-type region 213 and the N-well 217.

[0063] 1 , in one embodiment, each junction termination floating field plate 211 is connected to a corresponding isolation ring floating field plate 231 and LDMOS floating field plate 251 in a planar closed loop, i.e., closed floating field plate. It can be understood that the junction termination 210 passes over the isolation ring and is connected end-to-end to the NLDMOS 220 and PLDMOS 240. The N floating field plates in the junction termination 210 are equally spaced apart with an interval L1. When the devices in the high-voltage region 300 and the low-voltage region 100 begin to operate, the potential between the high-voltage region 300 and the low-voltage region 100 is separated by the isolation structure. At this time, the drain end (i.e., anode region 214) and source end (i.e., cathode region 212) of the junction termination 210, the source end and drain end of the PLDMOS 240, and the drain end and source end of the NLDMOS 220 receive the voltage between the high-voltage region 300 and the low-voltage region 100, and the potential drops from the high-voltage potential to the ground potential inside the junction termination 210, the NLDMOS 220, and the PLDMOS 240. The floating field plate is a heavily doped polycrystalline silicon field plate with a large number of free electrons inside, so that the floating field plate has a certain induced potential in an electric field. The N junction termination floating field plates 211 in the junction termination 210 are affected by the potential distribution inside the junction termination 210 and are respectively at potentials V1, V2, ..., V NThe value of the induced potential of each floating field plate is determined by its location and is approximately equal to the potential of the junction termination region below it, so the potential distribution within junction termination 210 controls the induced potential of each junction termination floating field plate 211. After the floating field plates are transferred to NLDMOS 220 and PLDMOS 240, the potential distribution within NLDMOS 220 and PLDMOS 240 also has a corresponding impact on the induced potential of the floating field plates. In the isolation structure, the area occupied by junction termination 210 is much larger than the area occupied by the LDMOS, and correspondingly, the junction termination area through which each closed floating field plate passes is also much larger than the area of ​​the LDMOS it passes through (see FIG. 1 ), and each closed floating field plate has only one predetermined induced potential, i.e., each closed floating field plate is an equipotential body in the electric field, so the potential distribution within junction termination 210 has absolute dominance over the induced potential generated by the closed floating field plate, and the induced potential of each closed floating field plate can be considered to be determined by junction termination 210. Because the LDMOS cannot change the induced potential of each closed floating field plate, each field plate extending from junction termination 210 corresponds to an external “voltage source” for the LDMOS, and the floating field plate brings the area of ​​the LDMOS portion below it close to the potential of the floating field plate.

[0064] As described above, the proposed semiconductor high and low voltage isolation structure of the above embodiment forms a potential control system with a floating field plate. The potential distribution in the junction termination 210 controls the induced potential of the closed floating field plate, and the induced potential of the closed floating field plate controls the potential distribution in the LDMOS.

[0065] Based on the above principle, the above embodiment realizes potential control of the LDMOS in an isolation structure using variable-pitch floating field plates. First, the potential distribution in the NLDMOS 220 and PLDMOS 240 is made closer to the junction termination 210. When two adjacent field plates among the N floating field plates are transferred to the LDMOS region at the same interval L1, the potential distribution in the LDMOS is restricted to the floating field plates and therefore approaches the potential distribution in the junction termination 210. Then, by changing the interval between the LDMOS floating field plates 251 in the LDMOS, the potential distribution in the LDMOS can be further controlled according to needs, and the magnitude of the electric field strength in different regions in the LDMOS can be changed. In this application, the N junction termination floating field plates 211, which are originally distributed at equal intervals L1 in the junction termination 210, are "reoriented" in the form of sloped field plates in the isolation ring using variable-pitch field plates. Then, these N floating field plates are distributed at intervals different from L1 in the LDMOS. Because each floating field plate already has a predetermined potential before being transferred to the LDMOS region, the potential difference between them is also predetermined, and changing the spacing between the field plates changes the gradient of the potential between them, correspondingly changing the gradient of the potential in the LDMOS region covered by the variable-pitch LDMOS floating field plate 251. Because the strength of the electric field is the gradient of the potential, changing the spacing of the LDMOS floating field plate 251 in a certain region changes the magnitude of the electric field strength in the corresponding region, thereby realizing control over the internal potential and surface electric field strength of the LDMOS.

[0066] In other words, the purpose of the variable pitch field plate is to control the potential distribution in the LDMOS through the potential distribution in the junction termination 210, thereby improving the performance of the LDMOS and improving the isolation capability of the entire isolation structure. The closed floating field plate provides external control for the LDMOS device, which has beneficial effects. Its advantages over conventional field plate technology are as follows: The present invention can eliminate potential line concentrations, and the variable pitch field plate can control the potential gradient in each part of the LDMOS drift region to be approximately equal, meaning that the potential change is uniform and does not change abruptly in some areas, and therefore the LDMOS does not become a vulnerable point for breakdown of the isolation structure. The present invention provides comprehensive control over the potential inside the LDMOS, and the variable pitch field plate can achieve control over the potential of the entire LDMOS drift region, not just a few areas. Meanwhile, the present technical solution does not complicate the process or structure, which means that increased manufacturing costs are avoided. The closed floating field plate in the above embodiment may be a polysilicon field plate. Because the polysilicon process is a common process for forming various types of device gates in the manufacturing process of high and low voltage isolation structures, the closed floating field plate can be formed using the same process as the polysilicon gate, thereby not increasing the manufacturing process. In addition, the closed floating field plate does not require changes to the internal structure when performing potential control on the LDMOS, thereby avoiding complications in the design and manufacturing of the LDMOS.

[0067] FIG. 5 is a cross-sectional view taken along line DD' in FIG. 1 , FIG. 6 is a cross-sectional view taken along line EE' in FIG. 1 , and FIG. 7 is a locally enlarged view of the first isolation ring 230 shown in FIG. 1 . In one embodiment, the isolation ring further includes a second insulating layer 33, and each isolation ring floating field plate 231 is located on the second insulating layer 33, which is located on the isolation junction 233. In one embodiment, the material of the second insulating layer 33 may be silicon oxide, for example, silicon dioxide. The isolation junction 233 has the same conductivity type as that of the substrate 10. In an embodiment in which the substrate 10 is a P-type substrate, the isolation junction 233 is a P-type doped region.

[0068] 7, each isolation ring floating field plate 231 includes a junction termination connection portion 231a, an LDMOS connection portion 231c, and a middle portion 231b. One end of the middle portion 231b is connected to the junction termination connection portion 231a, and the angle β between the middle portion 231b and an extension of the junction termination connection portion 231a in a plane is greater than 0 degrees and less than 80 degrees. The other end of the middle portion 231b is connected to the LDMOS connection portion 231c, and the angle θ between the middle portion 231b and an extension of the LDMOS connection portion 231c in a plane is greater than 0 degrees and less than 80 degrees. For the closed floating field plate, the spacing between adjacent LDMOS floating field plates 251 does not match the spacing between adjacent junction termination floating field plates 211 to uniformly distribute the potential across the lateral double-diffused metal-oxide-semiconductor field effect transistor in the isolation structure. By "changing the orbit" by adopting the above-described graded field plate format for the isolation ring, the spacing of the floating field plates is changed from the spacing distribution of junction-terminated floating field plates 211 to that of LDMOS floating field plates 251.

[0069] In one embodiment, the distance from the connection point between the junction termination connection portion 231a and the middle portion 231b to the edge of the isolation ring is b1, and the distance from the connection point between the LDMOS connection portion 231c and the middle portion 231b to the edge of the isolation ring is b2, where b1 is 10% to 30% of the width of the isolation ring, and b2 is 10% to 30% of the width of the isolation ring. That is, the connection point between the middle portion 231b and the junction termination connection portion 231a / LDMOS connection portion 231c should be kept a certain distance from the boundary of the isolation ring. This is because the corners of the graded field plate (i.e., the positions of the included angles β and θ) cause power lines to concentrate and generate a strong electric field. By positioning the corners at a certain distance from the boundary of the isolation ring, the withstand voltage of the isolation ring can be improved (i.e., the breakdown voltage can be increased) compared to positioning the corners at the boundary of the isolation ring, and breakdown between the lateral double-diffused metal-oxide-semiconductor field-effect transistor and the junction termination 210 can be prevented. In the embodiment shown in FIG. 7, the corners of the tilted field plate are located at lines DD' and EE'.

[0070] In one embodiment, the isolation ring further includes a protective well 235, and the second insulating layer 33 is located at the isolation junction 233 and the protective well 235. The conductivity type of the protective well 235 is opposite to that of the NLDMOS drain region 224, and the doping concentration of the protective well 235 is greater than that of the isolation junction 233. In one embodiment, the protective well 235 is a P+ doped region. The provision of the protective well 235 further improves the isolation ring's withstand voltage and prevents breakdown of the isolation ring due to potential line concentration. In one embodiment, the protective well 235 is provided directly below the connection position between at least a portion of the junction termination connection portion 231a and the middle portion 231b, and the protective well 235 is provided directly below the connection position between at least a portion of the LDMOS connection portion 231c and the middle portion 231b. This is because the corners of the graded field plate cause power line concentration. Therefore, by placing the protective well 235 directly under the corner of the gradient field plate, the effect of improving the withstand voltage of the isolation ring can be better achieved.

[0071] FIG. 8 is a locally enlarged view of the first isolation ring 230 of an isolation structure according to one embodiment, with the protective well 235 shown as semi-transparent. In this embodiment, the protective well 235 is an integrated P+ structure. Regarding a technical proposal for forming the protective well 235 using an ion implantation process, in one embodiment, the width of the implantation window of the protective well 235 should be 100% to 110% of the distance between both ends of the graded field plates, and the length should be 100% to 110% of the maximum distance between the first field plate and the Nth field plate, thereby underlying the corners of all the graded field plates. Region 100a in FIG. 8 has the same structure as a portion of the low-voltage region 100, and region 300a has the same structure as a portion of the high-voltage region 300. FIG. 9 is a cross-sectional view taken along line D-D' in FIG. 1 of an embodiment having the protective well 235, and FIG. 10 is a cross-sectional view taken along line E-E' in FIG. 1 of an embodiment having the protective well 235. 9 and 10 show the embodiment shown in FIG. 5 and the embodiment shown in FIG. 6, respectively, to which a protective well 235 is added.

[0072] 11 and 12, in some embodiments, the protective well 235 may affect only some of the isolated ring floating field plates 231, for example, only the field plates on the high-voltage side. In the embodiments shown in FIGS. 11 and 12, the protective well 235 is provided below some of the isolated ring floating field plates 231 that are close to the high-voltage region 300, and no protective well 235 is provided below the remaining isolated ring floating field plates 231. In the embodiment shown in FIG. 12, the protective well 235 is provided below a plurality of isolated ring floating field plates 231 (i.e., the first through pth isolated ring floating field plates 231 that are close to the high-voltage region 300) spaced apart by L3. In some embodiments, the length of the protective well 235 is 100% to 110% of the maximum distance between the first through pth field plates. In an embodiment in which the protective well 235 is provided only below some of the isolation ring floating field plates 231, the isolation ring floating field plates 231 that are affected by the protective well 235 can be selected as some of the isolation ring floating field plates 231 that are close to the high voltage region 300, thereby achieving a positive effect of improving the isolation ring withstand voltage. In other embodiments, the isolation ring floating field plates 231 may be provided below other isolation ring floating field plates 231.

[0073] 13 is a locally enlarged view of the vicinity of the first isolation ring 230 in another embodiment, in which the protective well 235 is semi-transparent. Its main difference from the embodiment shown in FIG. 8 is that the protective well 235 is a strip-shaped P+ doped region provided at the corner. Regarding the technical proposal for forming the protective well 235 using an ion implantation process, in one embodiment, the width of the implantation window of the protective well 235 should be 2% to 5% of the isolation ring width C, and its length should be 100% to 110% of the maximum distance between the first field plate and the Nth field plate, thereby laying below the corners of all the graded field plates.

[0074] 14 is a locally enlarged view of the vicinity of the first isolation ring 230 in yet another embodiment, in which the protective well 235 is semi-transparent. Its main difference from the embodiment shown in FIG. 8 is that the protective well 235 has P+ doped regions at the corners, and these P+ dotted regions are arranged in rows. Regarding the technical solution for forming the protective well 235 using an ion implantation process, in one embodiment, the width of the implantation window of the protective well 235 is 2% to 5% of the width of the isolation ring.

[0075] In one embodiment, the P+ implantation of the protection well 235, the junction termination 210, and the lateral double-diffused metal oxide semiconductor field effect transistor is performed in the same step, i.e., the implantation photolithography before the ion implantation of the protection well 235 uses the same photomask and completes the photolithography of the implantation window in the same photolithography step as the body region 221 of the NLDMOS 220, the source region 242 and the drain region 244 of the PLDMOS 240, and the body region 216 of the junction termination 210. Therefore, the formation of the protection well 235 does not add an additional manufacturing process, which is advantageous for cost savings.

[0076] In the description herein, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In the description herein, exemplary references to the above terms do not necessarily refer to the same embodiment or example.

[0077] The technical features of the above embodiments can be combined in any way, and for the sake of brevity, not all possible combinations of the technical features in the above embodiments are described, but as long as there is no contradiction in the combination of these technical features, they should be considered within the scope described in this specification.

[0078] The above examples only show some embodiments of the present invention, and although the descriptions are specific and detailed, they should not be understood as limiting the scope of the present invention. It should be noted that a person skilled in the art can make many modifications and improvements without departing from the concept of the present invention, and all of these fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent of the present invention should be determined based on the scope of the appended claims.

Claims

1. a junction termination and a lateral double-diffused metal oxide semiconductor field effect transistor; the junction termination includes a plurality of junction termination floating field plates; the lateral double-diffused metal oxide semiconductor field effect transistor includes a plurality of LDMOS floating field plates, each LDMOS floating field plate electrically connected to at least one junction termination floating field plate, and a length of each junction termination floating field plate is greater than a length of the LDMOS floating field plate electrically connected to each of the junction termination floating field plates.

2. 2. The isolation structure of claim 1, further comprising an isolation ring surrounding the lateral double-diffused metal oxide semiconductor field effect transistor, the isolation ring being used to isolate the lateral double-diffused metal oxide semiconductor field effect transistor from the junction termination.

3. 3. The isolation structure of claim 2, wherein the isolation ring further includes a plurality of isolation ring floating field plates, each LDMOS floating field plate being electrically connected to a corresponding junction termination floating field plate through one of the isolation ring floating field plates, one end of each isolation ring floating field plate extending to the corresponding junction termination floating field plate, and the other end of each isolation ring floating field plate extending to the corresponding LDMOS floating field plate.

4. The lateral double-diffused metal oxide semiconductor field effect transistor further includes a source region, a drain region, a gate, a drift region, and a field region insulating layer, at least a portion of the drift region is located between the source region and the drain region, the field region insulating layer is located on the drift region, one side of the gate is adjacent to the source region and the other side is adjacent to the drain region, the number of the LDMOS floating field plates is the same as the number of the junction termination floating field plates, the plurality of LDMOS floating field plates are electrically connected in one-to-one correspondence with the plurality of junction termination floating field plates, and the LDMOS floating field plate includes a first field plate provided adjacent to the source region, a second field plate provided adjacent to the drain region, and a third field plate provided adjacent to the drain region.

4. The isolation structure of claim 3, further comprising: a second field plate disposed adjacent to the drain region; and a third field plate located between the first and second field plates, wherein the spacing between adjacent third field plates is smaller than a2; the spacing between one second field plate among the plurality of second field plates that is farthest from the drain region and an adjacent third field plate is greater than a3 and the spacing between adjacent second field plates is also greater than a3; the spacing between one first field plate among the plurality of first field plates that is farthest from the source region and an adjacent third field plate is greater than a4 and the spacing between adjacent first field plates is also greater than a4, satisfying a2<a3 and a2<a4.

5. 5. The isolation structure of claim 4, wherein the lateral double-diffused metal oxide semiconductor field effect transistor includes an NLDMOS and a PLDMOS, the isolation rings include a first isolation ring surrounding the NLDMOS and a second isolation ring surrounding the PLDMOS, and a length of each junction termination floating field plate is the sum of a length of an LDMOS floating field plate of a corresponding NLDMOS and a length of an LDMOS floating field plate of a corresponding PLDMOS.

6. 6. The isolation structure of claim 5, wherein the junction termination further comprises a first insulating layer, and the plurality of junction termination floating field plates are located on the first insulating layer.

7. 7. The isolation structure of claim 6, wherein the junction termination further includes a cathode region and an anode region, the cathode region and the anode region being N-type regions, the cathode region being electrically connected to a potential of a source region of the NLDMOS through a metal connection line, and the anode region being electrically connected to a potential of a drain region of the NLDMOS through a metal connection line.

8. 4. The isolation structure of claim 3, wherein each of the junction-terminated floating field plates is connected in a closed loop with a corresponding isolation ring floating field plate and a corresponding LDMOS floating field plate.

9. the isolation ring further includes an isolation junction, a protective well, and a second insulating layer, the plurality of isolation ring floating field plates are located on the second insulating layer, the second insulating layer is located on the isolation junction and the protective well, the isolation junction and the protective well are P-type regions, and a doping concentration of the protective well is greater than a doping concentration of the isolation junction; 8. The isolation structure of claim 7, wherein each of the isolation ring floating field plates includes a junction termination connection portion, an LDMOS connection portion, and an intermediate portion, one end of the intermediate portion is connected to the junction termination connection portion, and an angle formed between the intermediate portion and an extension of the junction termination connection portion in a plane is greater than 0 degrees and less than 80 degrees, the other end of the intermediate portion is connected to the LDMOS connection portion, and an angle formed between the intermediate portion and an extension of the LDMOS connection portion in a plane is greater than 0 degrees and less than 80 degrees, and the protective well is provided directly below a connection position between at least some of the junction termination connection portions and the intermediate portion, and the protective well is provided directly below a connection position between at least some of the LDMOS connection portions and the intermediate portion.

10. 10. The isolation structure of claim 9, wherein the protection well includes: strip-shaped doped regions provided at connection positions between a plurality of the junction termination connection portions and the intermediate portion; and strip-shaped doped regions provided at connection positions between a plurality of the LDMOS connection portions and the intermediate portion.

11. 10. The isolation structure of claim 9, wherein the protection well includes: doped doping regions arranged in a row at connection positions between a plurality of the junction termination connection portions and the intermediate portion; and doped doping regions arranged in a row at connection positions between a plurality of the LDMOS connection portions and the intermediate portion.

12. 10. The isolation structure of claim 9, wherein a distance from a connection position between the junction termination connection and the intermediate portion to an edge of the isolation ring is b1, and a distance from a connection position between the LDMOS connection and the intermediate portion to an edge of the isolation ring is b2, wherein b1 is 10% to 30% of a width of the isolation ring, and b2 is 10% to 30% of a width of the isolation ring.

13. 4. The isolation structure of claim 3, wherein the junction termination floating field plate, the isolation ring floating field plate, and the LDMOS floating field plate are made of the same material.

14. 14. The isolation structure of claim 13, wherein the junction termination floating field plate, the isolation ring floating field plate, and the LDMOS floating field plate are made of doped polysilicon.

15. 5. The isolation structure of claim 4, wherein the material of the gate is the same as the material of the junction termination floating field plate, the isolation ring floating field plate, and the LDMOS floating field plate.

16. 5. The isolation structure of claim 4, wherein the spacing between adjacent junction-terminated floating field plates is a1, and satisfies a2<a1<a3 and a2<a1<a4.

17. 5. The isolation structure of claim 4, wherein the spacing between adjacent junction-terminated floating field plates is equal.

18. 5. The isolation structure of claim 4, wherein the spacing between adjacent junction termination floating field plates is 1.0 to 3.2 μm, the spacing between adjacent third field plates is 0.5 to 3.0 μm, the spacing between adjacent first field plates and the spacing between one of the first field plates farthest from the source region and one of the adjacent third field plates is 1.2 to 4.0 μm, and the spacing between adjacent second field plates and the spacing between one of the second field plates farthest from the drain region and one of the adjacent third field plates is 1.2 to 4.0 μm.

19. 19. An integrated circuit comprising: a first voltage region; a second voltage region; and an isolation structure according to any one of claims 1 to 18 located between the first and second voltage regions.

20. 20. The integrated circuit of claim 19, wherein an operating voltage of a device in the second voltage domain is greater than an operating voltage of a device in the first voltage domain.

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