Power semiconductor device and its manufacturing method

Abstract

A power semiconductor device (20) is identified, comprising: a drift layer (1) of a first conductivity type; at least one well region (2) of a second conductivity type different from the first conductivity type; at least one first doped region (3) of the first conductivity type and at least one second doped region (4) of the second conductivity type, wherein the at least one well region (2), the at least one first doped region (3), and the at least one second doped region (4) are provided on a first side of the power semiconductor device (20), the at least one first doped region (3) and the at least one second doped region (4) are spaced from the drift layer (1) by the at least one well region (2), and an interface between the at least one first doped region (3) and the at least one second doped region (4) is structured. Furthermore, a method for manufacturing such a power semiconductor device (20) is identified.

Description

[Technical Field]

[0001] The present disclosure relates to a power semiconductor device and a method for manufacturing the same. [Background technology]

[0002] Some power semiconductor devices are realized, for example, as metal-oxide-semiconductor field-effect transistors (MOSFETs). MOSFETs may be based on wide-bandgap materials, such as silicon carbide (SiC). SiC MOSFETs rated at 650 V and 1200 V are currently commercially available. Implemented using either planar or trench cell designs, SiC MOSFETs offer competitive static losses, high-speed dynamic performance, and sufficient reliability. With regard to fault handling capabilities, SiC MOSFETs still fall short of the typical industry standards exhibited by their Si counterparts. This is typically associated with a strong trade-off between conduction losses and short-circuit withstand capability (SCWT). Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to power semiconductor devices with improved efficiency. Further embodiments relate to methods for manufacturing such power semiconductor devices. [Means for solving the problem]

[0004] This is achieved by the subject matter of the independent claims. Further embodiments are evident from the dependent claims and the following description.

[0005] The term "power" in this specification and below refers to power semiconductor devices adapted to handle voltages above 100V, for example 650V or 1200V, and / or currents above 1A.

[0006] The power semiconductor device is, for example, a power metal insulating semiconductor field-effect transistor (abbreviated as power MISFET). The term MISFET also includes MOSFETs having oxide as an insulating material in the gate. The power semiconductor device may also be an insulated gate bipolar transistor (IGBT).

[0007] Exemplarily, the power MISFET includes a wide bandgap material, which may be silicon carbide (SiC), and thus the power semiconductor device is exemplarily embodied as a power SiC MISFET, particularly a power SiC MOSFET.

[0008] According to an embodiment, a power semiconductor device includes a drift layer of a first conductivity type. For example, the drift layer includes or is made of a semiconductor material. Illustratively, the semiconductor material is SiC. For example, the drift layer includes a first dopant that defines the first conductivity type.

[0009] The drift layer has, for example, a main extension plane, with the lateral direction aligned parallel to the main extension plane and the longitudinal direction aligned perpendicular to the main extension plane.

[0010] According to an embodiment, a power semiconductor device includes at least one well region of a second conductivity type different from the first conductivity type.

[0011] Exemplarily, the power semiconductor device includes a plurality of well regions, in particular at least two well regions, which are exemplarily separated from each other in the lateral direction.

[0012] For example, the well regions, in particular all the well regions, extend laterally along a main extension direction. The main extension directions of the well regions can be aligned parallel to one another.

[0013] The well region includes or consists of a semiconductor material, for example, the same material as the semiconductor material of the drift layer. Illustratively, the well region includes a second dopant that defines a second conductivity type.

[0014] Illustratively, the first dopant is an n-type dopant such that the first conductivity type is n-type conductivity, and the second dopant is a p-type dopant such that the second conductivity type is p-type conductivity, or vice versa. For example, n-type conductivity is achieved by using phosphorus (P) and / or nitrogen (N) as the first dopant. P-type conductivity is achieved by using aluminum (Al) and / or boron (B) as the second dopant.

[0015] According to an embodiment, a power semiconductor device comprises at least one first doped region of a first conductivity type and at least one second doped region of a second conductivity type.

[0016] The first doped region and the second doped region may include or consist of a semiconductor material that is the same as the semiconductor material of the drift layer. Illustratively, the first doped region includes an additional first dopant. Illustratively, the second doped region includes an additional second dopant. For example, the additional first dopant may be an n-type dopant and the additional second dopant may be a p-type dopant, or vice versa.

[0017] Illustratively, the additional first dopant is the same dopant as the first dopant. Furthermore, the additional second dopant is illustratively the same dopant as the second dopant.

[0018] Illustratively, the drift layer has a uniform doping concentration such that the maximum doping concentration corresponds to the average doping concentration. For example, the maximum doping concentration of the first doped region is higher than the maximum doping concentration of the drift layer. Illustratively, the maximum doping concentration of the first doped region is at least one order of magnitude or at least two orders of magnitude higher than the maximum doping concentration of the drift layer. For example, the maximum doping concentration of the drift layer is at least 1×10 14 cm -3 and up to 1 × 10 17 cm -3 is.

[0019] For example, the maximum doping concentration of the second doped region is higher than the maximum doping concentration of the well region, and typically is at least one or two orders of magnitude higher than the maximum doping concentration of the well region.

[0020] For example, the maximum doping concentration of the first doped region is at least 1×10 16 cm -3 and up to 1 × 10 21 cm -3 For example, the maximum doping concentration of the second doped region is at least 1×10 17 cm -3 and up to 1 × 10 21 cm -3 is.

[0021] In particular, at least a portion of the first doped region forms a source region of the power semiconductor device, the source region being a region into which charge carriers, e.g., electrons or holes, are injected into the well region.

[0022] According to an embodiment of the power semiconductor device, at least one well region, at least one first doped region, and at least one second doped region are provided on a first side of the power semiconductor device.

[0023] The at least one well region, the at least one first doped region, and the at least one second doped region each extend vertically from the first side to a predetermined depth, where the well region can have a first depth, the first doped region can have a second depth, and the second doped region can have a third depth.

[0024] Illustratively, the first depth is greater than the second depth and the third depth. For example, the third depth is greater than the second depth, or the second depth and the third depth are equal. For example, the second depth is at least 0.1 μm and at most 0.5 μm. For example, the third depth is at least 0.3 μm and at most 3 μm.

[0025] For example, the first main surface of the power semiconductor device on the first side is formed flat and extends parallel to the lateral direction. That is, the top surface of the well region, the top surface of the first doped region, and the top surface of the second doped region are part of the first main surface.

[0026] According to an embodiment of the power semiconductor device, the at least one first doped region and the at least one second doped region are separated from the drift layer by at least one well region.

[0027] The first doped region and the second doped region are illustratively embedded in a well region. That is, the outer surfaces of the first doped region and the second doped region are covered by the well region, except for the upper surfaces of the first doped region and the second doped region. Illustratively, the upper surfaces of the first doped region, the second doped region, and the well region are flush with each other.

[0028] For example, the top surface of the first doped region and the top surface of the second doped region are at least in a region that can be contacted from the outside in a conductive manner.

[0029] Each well region is illustratively provided with two first doped regions and one second doped region, the second doped region being laterally disposed between the two first doped regions.

[0030] According to an embodiment of the power semiconductor device, the interface between the at least one first doped region and the at least one second doped region is structured to be non-uniform in the main extension direction of the at least one well region. For example, the first doped region and the second doped region are directly adjacent to each other in the lateral direction. This means that the first doped region and the second doped region form an interface.

[0031] Exemplarily, the unstructured interface extends uniformly along the main extension direction of the well region. A structured interface is not, in particular, a flat interface. In fact, an unstructured interface is characteristic of a flat interface. Exemplarily, a structured interface includes a structure formed by a lateral extent of a first doped region and therefore by a lateral extent of a second doped region. In this context, the structure has an extension that is greater than the unevenness resulting from manufacturing tolerances. For example, a non-uniform structure includes a step structure. This means that the non-uniform structure is not, in particular, a continuous linear structure.

[0032] At such a structured interface between the first and second doped regions, the on-resistance R on experiences only a small increase of about 7% to 8% compared to regions without structured interfaces. Furthermore, at such structured interfaces, the maximum saturation current of the drain, I Dat_max is reduced by at least 40% compared to the conventional MOSFET value. Dat_max Since is directly related to SCWT, this means that MOSFETs with structured interfaces advantageously offer significantly improved conduction loss to SCWT tradeoff.

[0033] That is, a power semiconductor device with structured interfaces advantageously provides a longer SCWT value and therefore an improved device durability.

[0034] According to a further embodiment of the power semiconductor device, the at least one second doped region comprises a plurality of portions, each of which may have the same maximum doping concentration and / or distribution of the second dopant as the first dopant. Alternatively, at least some of the portions may have different maximum doping concentrations and / or distributions of the second dopant.

[0035] According to a further embodiment of the power semiconductor component, the portions are arranged successively next to one another along a main extension direction, which in particular extends along a main extension direction of the respective well region.

[0036] According to a further embodiment of the power semiconductor device, each of the plurality of portions has a length perpendicular to the main extension direction. Exemplarily, the lengths of all the portions may be equal to each other. Alternatively, the lengths of at least some of the portions may be different from each other.

[0037] According to a further embodiment of the power semiconductor component, adjacent portions are in direct contact with each other along the main direction of extension.

[0038] According to a further embodiment of the power semiconductor component, the adjacent portions are spaced apart from one another along the main direction of extension. In this embodiment, the first doped regions are arranged laterally between the adjacent portions, that is, the portions are spaced apart in the laterally direction by the first doped regions.

[0039] According to a further embodiment of the power semiconductor device, the plurality of portions includes first portions and second portions arranged alternately and consecutively along the main extension direction.

[0040] According to a further embodiment of the power semiconductor device, each first portion has a first length perpendicular to the main extension direction and each second portion has a second length perpendicular to the main extension direction.

[0041] According to a further embodiment of the power semiconductor device, the first length is greater than the second length. Illustratively, all of the first portions have the same length, i.e., the first length, and all of the second portions have the same length, i.e., the second length.

[0042] According to a further embodiment of the power semiconductor device, the maximum doping concentration of the first portions is higher than the maximum doping concentration of the second portions, and illustratively, all of the first portions have the same maximum doping concentration, and all of the second portions have the same maximum doping concentration.

[0043] According to a further embodiment of the power semiconductor component, the at least one first doped region is arranged along the main extension direction between portions of the at least one second doped region.

[0044] Exemplarily, the first doped regions are disposed between the mutually facing side surfaces of the adjacent portions. For example, the first doped regions can completely cover the side surfaces of the adjacent portions in a lateral direction perpendicular to the main extension direction. Alternatively, the first doped regions can cover the side surfaces of the adjacent first portions in a region in the lateral direction perpendicular to the main extension direction. This means that the first doped regions are disposed between the end regions of the adjacent first portions, but are not disposed in the central regions of the adjacent first portions where the second portions are disposed.

[0045] According to a further embodiment of the power semiconductor device, the distance between adjacent portions is at least 0.1 μm and at most 1 μm. Exemplarily, the distance is defined between facing side surfaces of adjacent portions. In particular, the distance is defined between facing side surfaces of adjacent first portions. Alternatively, or additionally, the distance is defined between facing side surfaces of adjacent second portions.

[0046] According to a further embodiment of the power semiconductor component, when the adjacent portions are spaced apart from each other along the main extension direction, the at least one first doped region comprises a first doped zone and a second doped zone, the first doped zone being arranged between adjacent portions of the at least one second doped region along the main extension direction. Exemplarily, the first doped zone is arranged between facing side surfaces of the adjacent portions, in particular between side surfaces of the end regions of the portions.

[0047] According to a further embodiment of the power semiconductor device, the maximum doping concentration of the first doped zone is lower than the maximum doping concentration of the second doped zone, typically by at least one or at least two orders of magnitude lower than the maximum doping concentration of the second doped zone.

[0048] According to a further embodiment of the power semiconductor component, additional extensions extending perpendicular to the length of the portion are arranged in the end regions of the portion, in particular each portion has two end regions opposite each other, the end regions being located at the ends of the portion along the length.

[0049] In particular, the portion and the additional extension form a second doped region, for example, the portion and the additional extension have a T-shape in the transverse direction when viewed from above along the vertical direction.

[0050] According to a further embodiment of the power semiconductor component, the distance between adjacent additional extensions is at least 0.1 μm and at most 1 μm, in particular the mutually facing side surfaces of adjacent additional extensions are spaced apart in the lateral direction by said distance.

[0051] For example, the first doped zone may be arranged between adjacent additional extensions, in particular between the mutually facing side surfaces of the adjacent additional extensions, and in this case the second zone may be arranged between the mutually facing side surfaces of the adjacent parts.

[0052] For example, the maximum doping concentration of the portion is the same as the maximum doping concentration of the additional extension, or the maximum doping concentration of the portion is higher than the maximum doping concentration of the additional extension.

[0053] According to a further embodiment, the power semiconductor device comprises at least two well regions, each well region including, for example, two first doped regions with a second doped region laterally disposed therebetween.

[0054] According to a further embodiment, the power semiconductor device includes at least one intermediate region. Illustratively, the intermediate region includes a further first dopant, for example an n-type dopant. For example, the maximum doping concentration of the intermediate region is higher than the maximum doping concentration of the drift layer.

[0055] According to a further embodiment of the power semiconductor device, at least two well regions and at least one intermediate region are provided on a first side of the power semiconductor device.

[0056] According to a further embodiment of the power semiconductor component, the at least one intermediate region is provided between two of the at least two well regions, in particular in the lateral direction.

[0057] The intermediate region is illustratively a junction field effect transistor (JFET) region or an electron barrier region, which is advantageously introduced into the drift layer to locally increase the resistance of the source region.

[0058] According to a further embodiment, a power semiconductor device comprises a semiconductor body having a first main surface on a first side and a second main surface on a second side, the semiconductor body comprising a drift layer, at least one well region, at least one first doped region, and at least one second doped region. The second side is opposite the first side in the longitudinal direction. The semiconductor body may additionally comprise an intermediate region and / or a substrate layer.

[0059] According to a further embodiment, the power semiconductor device includes an upper metal layer disposed on the first main surface. For example, the upper metal layer is provided on the source region, i.e., on the first side, on the first doped region and the second doped region. For example, the upper metal layer is provided on the first main surface.

[0060] According to a further embodiment of the power semiconductor device, the upper metal layer at least partially overlaps the at least one first doped region and the at least one second doped region, and illustratively is in direct contact with the first doped region and the second doped region on their upper surfaces.

[0061] For example, the end region of the portion of the first doped region is free of the top metal layer. Illustratively, the additional extension is free of the top metal layer, i.e., the end region of the portion does not laterally overlap with the top metal layer.

[0062] According to a further embodiment, the power semiconductor device includes a substrate layer. Illustratively, the substrate layer of the first conductivity type is disposed on the drift layer at a second side opposite the first side. For example, the maximum doping concentration of the drift layer is at least two orders of magnitude higher, e.g., five times higher, than the maximum doping concentration of the drift layer.

[0063] According to a further embodiment, the power semiconductor device includes a backside metal layer disposed on the second main surface. For example, the backside metal layer is provided on the second main surface of the drift layer on the second side. For example, the backside metal layer completely covers the second main surface.

[0064] The top metal layer and / or the back metal layer may, for example, comprise or consist of a metal, e.g., the top metal layer and / or the back metal layer may be an electrode that can be contacted externally in an electrically conductive manner.

[0065] According to a further embodiment of the power semiconductor device, the substrate layer is disposed between the second electrode and the drift layer.

[0066] According to a further embodiment, the power semiconductor device comprises a gate disposed on the first main surface. In particular, the gate does not laterally overlap the source region. Illustratively, the gate is disposed on at least one intermediate region.

[0067] The gate illustratively includes a gate contact and a gate insulator. The gate contact includes or consists of a metal. The gate insulator includes an electrically insulating material, such as an electrically insulating oxide or a high-k dielectric. SiO2 has a dielectric constant of 3.9, and "high-k" dielectric materials are said to have a dielectric constant k>3.9.

[0068] For example, the gate contact is at least in an area that can be electrically conductively contacted from the outside, and is exemplarily embedded in the gate insulator, i.e., the gate insulator covers all of the outer surface of the gate contact except for the area intended for external contact.

[0069] Further embodiments relate to a method for manufacturing a power semiconductor device, in particular a power semiconductor device as described herein above. Accordingly, features described in relation to the method are also applicable to the power semiconductor device, and vice versa.

[0070] According to one embodiment of the method, a drift layer of a first conductivity type is provided. In particular, the drift layer is an epitaxial semiconductor layer. For example, a substrate of the drift layer is epitaxially grown. The substrate is further doped with a first dopant.

[0071] According to an embodiment of the method, at least one well region of a second conductivity type different from the first conductivity type is formed on the first side. Exemplarily, the well region is formed in the drift layer, i.e., the substrate, by a doping process. For example, a second dopant is introduced into the drift layer. Exemplarily, the well region is formed by introducing the second dopant into the drift layer.

[0072] According to an embodiment of the method, at least one first doped region of a first conductivity type and at least one second doped region of a second conductivity type are formed on the first side. Illustratively, a source region including the first doped region and the second doped region is formed in the drift layer by a further doping process.

[0073] For example, the source region is formed by introducing at least one of an additional first dopant or an additional second dopant into the drift layer. The phrase "at least one of an additional first dopant or an additional second dopant is introduced" is intended to encompass the cases where an additional first dopant is introduced, an additional second dopant is introduced, or an additional first dopant and an additional second dopant are introduced.

[0074] The first dopant, the further first dopant, the second dopant, and / or the further second dopant are incorporated, for example, into the drift layer, for example, by an ion implantation process.

[0075] According to an embodiment of the method, a mask is used to form the at least one first doped region such that the interface between the at least one first doped region and the at least one second doped region is structured, in particular the mask is an implantation mask configured to confine an implanted region of the further first dopant.

[0076] According to a further embodiment of the method, a further mask is used to form the at least one second doped region, in particular a further implantation mask configured to confine the implantation region of the second further dopant.

[0077] Using such a method, compared to conventional SiC MISFET fabrication, no process modifications are required and, advantageously, no extra masks are required to fabricate the structured interface between the first and second doped regions, since only the implant masks for the first and second dopants need to be redrawn to form such a structured interface.

[0078] According to a further embodiment of the method, a self-aligned process is used to form the at least one second doped region, which allows for a particularly simple and accurate definition of the structured interface.

[0079] The accompanying drawings are included for a further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. [Brief explanation of the drawings]

[0080] [Figure 1] 1 shows an exemplary schematic diagram of a power semiconductor device according to the prior art; [Figure 2] 1A and 1B schematically illustrate a top view of a power semiconductor device according to an exemplary embodiment. [Figure 3] 1A and 1B schematically illustrate a top view of a power semiconductor device according to an exemplary embodiment. [Figure 4] 1A and 1B schematically illustrate a top view of a power semiconductor device according to an exemplary embodiment. [Figure 5] 3 illustrates, among other things, an exemplary diagram of simulated performance data for a power semiconductor device according to an exemplary embodiment. [Figure 6] 3 illustrates, among other things, an exemplary diagram of simulated performance data for a power semiconductor device according to an exemplary embodiment. [Figure 7] 3 illustrates, among other things, an exemplary diagram of simulated performance data for a power semiconductor device according to an exemplary embodiment. [Figure 8] 3 illustrates, among other things, an exemplary diagram of simulated performance data for a power semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0081] The power semiconductor device according to FIG. 1 includes a backside metal layer 7, a substrate layer 6, and a drift layer 1 stacked on top of each other in the order shown. Adjacent layers are in direct contact with each other. Illustratively, the drift layer 1 is an epitaxial drift layer 1. That is, the drift layer 1 is formed, for example, by an epitaxial process. The drift layer 1 is of a first conductivity type.

[0082] The maximum doping concentration of the substrate layer 6 is higher than the maximum doping concentration of the drift layer 1. That is, the drift layer 1 is a lightly doped layer, and the substrate layer 6 is a highly doped layer.

[0083] The drift layer 1, and in particular the substrate layer 6, comprises a semiconductor material formed from SiC. For example, a highly doped collector layer of the second conductivity type can replace the substrate layer 6 of the first conductivity type. In this case, the power semiconductor device 20 is an IGBT.

[0084] The power semiconductor device 20 further includes two well regions 2 of a second conductivity type different from the first conductivity type on a first side of the drift layer 1. The first side faces away from the back surface metal layer 7.

[0085] For example, the first conductivity type is n-type conductivity, and the second conductivity type is p-type conductivity.

[0086] The well region 2 is formed, for example, by a doping process in the drift layer 1. For example, the well region 2 is formed to a first depth by introducing a second dopant into the drift layer 1.

[0087] The two well regions 2 are separated from each other in the lateral direction. In other words, the two well regions 2 are arranged in the drift layer 1 at a distance from each other in the lateral direction. Each of the two well regions 2 extends along a main extension direction. Furthermore, the two main extension directions of the two well regions 2 are aligned parallel to each other.

[0088] Between the two well regions 2 on the first side, an intermediate region 5 is arranged, which also extends along the main extension direction.

[0089] Each well region 2 comprises two first doped regions 3 of a first conductivity type and one second doped region 4 of a second conductivity type.

[0090] The two first doped regions 3 are separated from each other in the lateral direction. In other words, the two first doped regions 3 are arranged in each well region 2 at a distance from each other in the lateral direction and extend along the main extension direction of the respective well region 2. The second doped region 4 is arranged between the two first doped regions 3 and also extends along the main extension direction of the respective well region 2. The first region and the second region extend to a second depth and a third depth, respectively, in a vertical direction perpendicular to the main extension plane of the power semiconductor device 20.

[0091] The top surfaces of the well region 2, the first doped region 3, the second doped region 4 and the intermediate region 5 are arranged in a common plane, ie the first main surface.

[0092] In addition, a gate 8 is disposed on the first side on the intermediate region 5. The gate 8 covers the intermediate region 5 and the well region 2, and only partially covers the first doped regions 3, in particular their upper surfaces. That is, the gate 8 overlaps the intermediate region 5, the two well regions 2, and the two first doped regions 3 in the different well regions 2 in a top view. The gate 8 includes a gate contact and a gate insulator.

[0093] 2 includes a structured interface between the first doped region 3 and the second doped region 4, as compared to the power semiconductor device of FIG. 1. The second doped region 4 includes a plurality of portions 10, which include a first portion 11 and a second portion 12.

[0094] The portions 10, in particular the first portion 11 and the second portion 12, are arranged next to each other in succession along the main extension direction. The first portions 11 and the second portions 12 are arranged alternately along the main extension direction. Adjacent portions 10 are in direct contact with each other along the main extension direction.

[0095] Each first portion 11 has a first length perpendicular to the main extension direction, and each second portion 12 has a second length perpendicular to the main extension direction. The first length is greater than the second length. In particular, the first portions 11 protrude beyond the second portions 12 in the direction perpendicular to the main extension direction. This means that the end regions of the first portions 11 protrude beyond the second portions 12 in the direction perpendicular to the main extension direction.

[0096] The first doped regions 3 are arranged laterally along the main extension direction between the end regions of adjacent first portions 11 of the second doped regions 4 .

[0097] The upper metal layer 9 is disposed on a portion 10 of the second doped region 4 and on the first doped region 3, particularly on the first main surface. The upper metal layer 9 completely overlaps the second portion 12 in the lateral direction and partially overlaps the first portion 11. The upper metal layer 9 is absent at the end of the end region of the first portion 11.

[0098] The upper metal layer 9 laterally overlaps the first doped region 3. In particular, the upper metal layer 9 is arranged on the first doped region 3 and between the first portions 11 of the second doped region 4.

[0099] 3 includes portions 10 of the second doped region 4 having the same length, as compared to FIG. 2. Adjacent portions 10 are spaced apart from each other along the main extension direction. The first doped region 3 is laterally disposed between the adjacent portions 10.

[0100] 4 comprises, in comparison with FIG. 3, a portion 10 in which an additional extension 13 is arranged in an end region. The additional extension 13 extends in particular along the main extension direction and perpendicular to the portion 10.

[0101] The first doped regions 3 are arranged laterally between adjacent portions 10 , in particular also between adjacent additional extensions 13 .

[0102] In top view, the second doped region 4 with the portion 10 and the additional extension 13 is T-shaped in the lateral direction.

[0103] Adjacent additional extensions 13, in particular the side surfaces of adjacent additional extensions 13 facing each other, exemplarily have a distance of at least 0.1 μm and at most 1 μm.

[0104] The first doped region 3 comprises a first doped zone 14 and a second doped zone 15, the first doped zone 14 being arranged along the main extension direction between adjacent parts 10 of one second doped region 4. This means that the first doped zone 14 is arranged between the mutually facing side surfaces of adjacent additional extensions 13 which are laterally opposite each other.

[0105] The maximum doping concentration of the first doped zone 14 is lower than the maximum doping concentration of the second doped zone 15 .

[0106] The second doped zone 15 extends laterally from the side facing the intermediate region 5 to the intermediate region 5 .

[0107] current I DSis expressed in amperes (A / cm 2 ) and is shown on the y-axis of the diagram according to FIG. 5. Furthermore, the drain-source voltage V DS is shown on the x-axis in volts (V). The top IV curve corresponds to a prior art SiC MOSFET that does not have a structured interface between the first and second doped regions 4.

[0108] Illustratively, the top IV curve is calculated depending on the structure of FIG. The middle IV curve corresponds to the power semiconductor device 20 which is a SiC MISFET according to the exemplary embodiment of Figure 4, and the distance between adjacent additional extension portions 13 is 0.3 μm. The bottom IV curve corresponds to the power semiconductor device 20 which is a SiC MISFET according to the exemplary embodiment of Figure 4, and the distance between adjacent additional extension portions 13 is 0.6 μm.

[0109] Illustratively, the middle and bottom IV curves are calculated depending on the structure of FIG. The values ​​in Figure 5 are for a gate-source voltage of 15 V. GS and simulated at a temperature of 300K.

[0110] In Figure 6, the current I DS (Ampere, A / cm 2 ) is shown on the y-axis of the diagram. Additionally, time t in seconds (s) is shown on the x-axis. Similar to the curves shown in FIG. 5, the top I t curve corresponds to a SiC MOSFET according to the prior art, and the middle and bottom I t curves correspond to SiC MISFETs according to the exemplary embodiment of FIG.

[0111] The values ​​in the diagram in Figure 6 are for a gate-source voltage V of 15V. GS and a drain-source voltage V of 600 V DS It is simulated using

[0112] Figure 7 shows a summary of the results shown in Figures 5 and 6. The B1 design corresponds to the power semiconductor device 20 of Figure 4 with a distance of 0.3 μm. B1 is expressed in A / cm 2 In I Dat_max Although this results in a significant 42% reduction in mΩcm 2 Specific R on The values ​​show only a modest increase of 7%, which in turn leads to longer SCWT values ​​and thus improved device durability.

[0113] The B2 design corresponds to the power semiconductor element 20 of Figure 4 with a distance of 0.6 μm. The Ref design corresponds to the reference power semiconductor element 20 according to Figure 1, i.e., prior art.

[0114] The transfer characteristics of the reference SiC MOSFET Ref and one using the B1 design are shown in the diagram of Figure 8. The values ​​in the diagram of Figure 8 are for a drain-source voltage V of 1 V. DS and a temperature of 300 K. Virtually no change is observed. [Explanation of symbols]

[0115] 1 Drift layer 2 well area 3 First doped region 4 Second doped region 5 Intermediate area 6 substrate layers 7 Back metal layer 8 Gates 9 Upper metal layer 10 parts 11 First Part 12 Second Part 13 Additional extensions 14 First Dope Zone 15 Second Dope Zone 20 Power semiconductor devices

Claims

1. A power semiconductor device (20), a drift layer (1) of the first conductivity type, at least one well region (2) of a second conductivity type different from said first conductivity type; - comprising at least one first doped region (3) of said first conductivity type and at least one second doped region (4) of said second conductivity type, the at least one well region (2), the at least one first doped region (3), and the at least one second doped region (4) are provided on a first side of the power semiconductor device (20); - said at least one first doped region (3) and said at least one second doped region (4) are spaced from said drift layer (1) by said at least one well region (2); A power semiconductor component (20), wherein the interface between the at least one first doped region (3) and the at least one second doped region (4) is structured to be non-uniform in the main direction of extension of the at least one well region (2).

2. said at least one second doped region (4) comprises a plurality of portions (10); - said portions (10) are arranged successively next to each other along the main direction of extension; The power semiconductor device (20) according to claim 1, wherein each of said plurality of portions (10) has a length perpendicular to said main extension direction.

3. adjacent portions (10) are in direct contact with each other along said main direction of extension, or A power semiconductor component (20) according to claim 2, wherein adjacent portions (10) are spaced apart from each other along said main direction of extension.

4. - said plurality of portions (10) comprises first portions (11) and second portions (12) arranged successively and alternately along said main direction of extension; each first portion (11) has a first length perpendicular to said main direction of extension and each second portion (12) has a second length perpendicular to said main direction of extension; The power semiconductor device (20) according to claim 2 or 3, wherein the first length is greater than the second length.

5. 5. The power semiconductor device (20) according to claim 4, wherein the maximum doping concentration of the first portion (11) is higher than the maximum doping concentration of the second portion (12).

6. Adjacent portions (10) are spaced apart from each other along the main direction of extension; - said at least one first doped region (3) is arranged along said main direction of extension between said portions (10) of said at least one second doped region (4); The power semiconductor component (20) according to any one of claims 3 to 5, wherein the distance between adjacent portions (10) is at least 0.1 μm and at most 1 μm.

7. Adjacent portions (10) are spaced apart from each other along the main direction of extension; said at least one first doped region (3) comprises a first doped zone (14) and a second doped zone (15); - said first doped zones (14) are arranged along said main direction of extension between adjacent portions (10) of said at least one second doped region (4); The power semiconductor component (20) according to any one of claims 3 to 6, wherein the maximum doping concentration of the first doped zone (14) is lower than the maximum doping concentration of the second doped zone (15).

8. - additional extensions (13) extending perpendicularly to the length of said part (10) are arranged in the end regions of said part (10), The power semiconductor component (20) according to any one of claims 2 to 7, wherein the distance between adjacent additional extensions (13) is at least 0.1 μm and at most 1 μm.

9. The power semiconductor device (20) further comprises: - at least two well regions (2), - at least one intermediate region (5), - the at least two well regions (2) and the at least one intermediate region (5) are provided on the first side of the power semiconductor device (20); The power semiconductor device (20) according to any one of claims 1 to 8, wherein said at least one intermediate region (5) is provided between two of said at least two well regions (2).

10. The power semiconductor device (20) further comprises: - a semiconductor body having a first main surface on said first side and a second main surface on a second side, The power semiconductor device (20) according to any one of claims 1 to 9, wherein the semiconductor body comprises the drift layer (1), the at least one well region (2), the at least one first doped region (3), and the at least one second doped region (4).

11. The power semiconductor device (20) further comprises: - a top metal layer (9) arranged on said first main surface, The power semiconductor component (20) according to claim 10, wherein the upper metal layer (9) at least partially overlaps the at least one first doped region (3) and the at least one second doped region (4).

12. The power semiconductor device (20) further comprises: a substrate layer (6), a back metal layer (7) arranged on said second main face, The power semiconductor device (20) according to claim 10 or 11, wherein the substrate layer (6) is arranged between the arranged back metal layer (7) and the drift layer (1).

13. The power semiconductor device (20) according to any one of claims 10 to 12, further comprising a gate (8) disposed on the first main surface.

14. A method for manufacturing a power semiconductor device (20), comprising: - providing a drift layer (1) of a first conductivity type; - forming at least one well region (2) on the first side of a second conductivity type different from said first conductivity type; forming at least one first doped region (3) of said first conductivity type and at least one second doped region (4) of said second conductivity type on said first side, - a method for manufacturing a power semiconductor component (20), in which a mask is used to form the at least one first doped region (3) such that the interface between the at least one first doped region (3) and the at least one second doped region (4) is structured.

15. a further mask is used to form said at least one second doped region (4), or The method for manufacturing a power semiconductor component (20) according to claim 14, wherein a self-aligned process is used to form said at least one second doped region (4).

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