FPGA 3D Chiplet Packaging Structure

Abstract

This application relates to the technical field of chip packaging, and more particularly to a three-dimensional FPGA chiplet packaging structure. This application provides a three-dimensional FPGA chiplet packaging structure, including a plurality of stacked FPGA packaging modules and a connection substrate. The FPGA packaging modules are provided with microbump structures for interconnection with FPGA chips, and the topological layout of the elements and microbump structures in each FPGA packaging module is the same. In adjacent FPGA packaging modules, at least some of the microbump structures overlap, and the FPGA chips in adjacent FPGA packaging modules are interconnected through the microbump structures at the overlapping positions. The connection substrate is used to mount the stacked FPGA packaging modules and enable signal transmission from each FPGA packaging module to the outside. This application provides a three-dimensional FPGA chiplet packaging structure that increases the capacity of FPGA chiplets per unit area and improves the performance of the FPGA chiplets.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to a Chinese patent application filed with the China Patent Office on December 1, 2023, bearing application number 202311639166.3 and entitled "FPGA Three-Dimensional Chiplet Packaging Structure," the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the technical field of chip packaging, and in particular to FPGA three-dimensional chiplet packaging structures. [Background technology]

[0003] The capacity of an FPGA (Field Programmable Gate Array) chiplet is limited by the number of CLBs (Configurable Logic Blocks), while the number of CLBs in an FPGA chiplet with the same area is further limited by power consumption, area, pins, and packaging process. Future high-performance applications require higher FPGA capacity to process more data. However, traditional FPGA packaging structures limit the number of CLBs per unit area, making it impossible to exceed the capacity limit and further improving performance.

[0004] Therefore, what is needed is a means to overcome capacity limitations and increase performance by allowing more CLBs to be packed into an FPGA chiplet per unit area. Summary of the Invention [Problem to be solved by the invention]

[0005] To solve the above problem, the present application provides an FPGA three-dimensional chiplet packaging structure to solve the problem that the capacity of an FPGA chiplet is limited by the number of CLBs, making it difficult to exceed the capacity limit and making it difficult to improve performance. [Means for solving the problem]

[0006] The present application provides an FPGA three-dimensional chiplet packaging structure, which includes a plurality of stacked FPGA packaging modules and a connection substrate, wherein the FPGA packaging modules are provided with microbump structures for interconnection with FPGA chips, the topological layout of the elements and microbump structures in each of the FPGA packaging modules is the same, and the FPGA packaging modules in adjacent layers are laid out so that at least some of the microbump structures overlap, and the FPGA chips in adjacent FPGA packaging modules are interconnected by the microbump structures at the overlapping positions, and the connection substrate is used to mount the stacked FPGA packaging modules and realize signal transmission of each of the FPGA packaging modules to the outside.

[0007] Optionally, the stacking manner of the FPGA packaging modules is such that the FPGA packaging modules are completely overlapped, and the projection patterns of the FPGA packaging modules on different layers onto the connecting substrates are completely overlapped.

[0008] Optionally, the stacking method of the FPGA packaging modules is such that the FPGA packaging modules of adjacent layers are rotated horizontally by 180°, and then some of them are shifted and some of them overlap, and the interconnection of the FPGA packaging modules of adjacent layers is realized by a micro-bump structure at the overlapping position.

[0009] Optionally, the connection substrate includes a main substrate and a height-increasing substrate, the height-increasing substrate is stacked on a portion of the main substrate, the FPGA packaging module not directly connected to the main substrate has a non-overlapping region, and the height-increasing substrate at least partially corresponds to the non-overlapping region in the FPGA packaging module not directly connected to the main substrate and is electrically connected to the FPGA packaging module at the corresponding position.

[0010] Optionally, the distance between the main board and the FPGA packaging module directly connected thereto is a first distance, and the distance between the height increasing board and the FPGA packaging module not directly connected thereto is a second distance, and the first distance and the second distance are the same.

[0011] Optionally, an I / O interface is provided on the height increasing board, and the I / O interface is electrically connected to the non-overlapping region.

[0012] Optionally, the FPGA packaging module includes a packaging substrate having an overlapping region for providing the overlapping and interconnected micro-bump structures, and directly opposite the micro-bump structures located in the overlapping region, the packaging substrate has a front connection opening facing the micro-bump structures and a back connection opening on the surface opposite to the micro-bump structures, the front connection opening is electrically connected to the corresponding back connection opening, the front connection opening is connected to the micro-bump structures, and the back connection opening is suitable for connection to the micro-bump structures at corresponding positions in the underlying FPGA packaging module.

[0013] Optionally, the connection substrate is provided with connection wiring and a docking interface, and the docking interface is used to connect to the stacked FPGA packaging modules and realize signal transmission of each of the FPGA packaging modules to the outside via the connection wiring, the FPGA packaging modules include a first FPGA packaging module and a second FPGA packaging module, the second FPGA packaging module is stacked above the first FPGA packaging module, and in the first FPGA packaging module, a back connection opening located in the overlapping area is electrically connected to a docking interface at a corresponding position on the connection substrate.

[0014] Optionally, the connecting substrate is provided with a substrate micro-bump structure, which is provided corresponding to the docking interface, is connected to the docking interface in a one-to-one correspondence, and is suitable for electrically connecting to the rear connection opening of the FPGA packaging module above.

[0015] Optionally, the FPGA packaging module includes an Xbar interconnect switch, and Xbar interconnect switches in the FPGA packaging modules of adjacent layers are interconnected by the micro-bump structures in overlapping regions.

[0016] The present invention relates to a three-dimensional FPGA chiplet packaging structure that includes a plurality of stacked FPGA packaging modules, with the FPGA chips in adjacent FPGA packaging modules interconnected by microbump structures at overlapping positions. This allows for interconnections between the stacked FPGA chips, enabling three-dimensional stacked packaging of FPGA chips, thereby increasing the number of CLBs per unit area of ​​the FPGA chiplet, increasing the capacity per unit area of ​​the FPGA chiplet, and improving the performance of the FPGA chiplet. Compared to a method of stacking FPGA chips after packaging, where different FPGA chips are stacked using wire bonding and TSV through-vias, this method has fewer process steps. Furthermore, while wire bonding methods are prone to problems such as wire breakage and solder misalignment, resulting in relatively low yields, the microbump structure is more stable and results in higher yields. When a transmission problem occurs, the wire bonding method requires many wires in the wire bonding-TSV process product, making testing difficult. However, the microbump array connection method makes it easier to determine which specific chip layer has the problem.

[0017] In order to more clearly describe the specific embodiments of the present application or the technical solutions of the prior art, the following will briefly describe the drawings that need to be used in the description of the specific embodiments or the prior art. It is obvious that the drawings in the following description are some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without any creative work. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a structural schematic diagram of an FPGA three-dimensional chiplet packaging structure according to one embodiment of the present application; [Figure 2] 2 is a schematic diagram of a first FPGA packaging module and a second FPGA packaging module of the FPGA three-dimensional chiplet packaging structure in FIG. 1; [Figure 3] FIG. 2 is a structural schematic diagram of an FPGA three-dimensional chiplet packaging structure according to another embodiment of the present application; [Figure 4] 2 is a schematic diagram of a first FPGA packaging module and a second FPGA packaging module of the FPGA three-dimensional chiplet packaging structure in FIG. 1; [Figure 5] 1 is a schematic diagram of the connection relationship between an Xbar interconnection switch in a first FPGA packaging module and an Xbar interconnection switch in a second FPGA packaging module of an FPGA three-dimensional chiplet packaging structure according to one embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0019] To solve the problem that the capacity of an FPGA chiplet is limited by the number of CLBs, making it difficult to exceed the capacity limit and making it difficult to improve performance, this application provides an FPGA three-dimensional chiplet packaging structure.

[0020] This application provides an FPGA three-dimensional chiplet packaging structure, including a plurality of stacked FPGA packaging modules and a connection substrate. The FPGA packaging modules are provided with microbump structures for interconnection with FPGA chips. The topological layout of the elements and microbump structures in each FPGA packaging module is the same. In the FPGA packaging modules of adjacent layers, at least some of the microbump structures are laid out to overlap, and the FPGA chips in adjacent FPGA packaging modules are interconnected by the microbump structures at the overlapping positions. The connection substrate is used to mount the stacked FPGA packaging modules and enable signal transmission from each FPGA packaging module to the outside.

[0021] The FPGA three-dimensional chiplet packaging structure of the present application can effectively increase the number of CLBs in an FPGA chiplet per unit area, thereby increasing the capacity of the FPGA and improving the performance of the FPGA.

[0022] The technical solutions of the present application will be described below clearly and completely with reference to the drawings, and it is obvious that the described embodiments are only some of the embodiments of the present application, but not all of the embodiments. Based on the embodiments of the present application, all other embodiments that a person skilled in the art can obtain without creative work fall within the scope of protection of the present application.

[0023] In the description of this application, orientations or positional relationships indicated by terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are orientations or positional relationships based on the drawings, and are used merely for the convenience and simplification of the description of this application, and do not indicate or imply that such devices or elements necessarily have a specific orientation or are constructed and operated in a specific orientation, and should not be understood as limiting this application. Furthermore, terms such as "first," "second," and "third" are used for the purpose of explanation only, and should be understood as not indicating or implying relative importance.

[0024] In the description of this application, unless otherwise clearly specified or limited, the terms "attached," "coupled," and "connected" should be understood in a broad sense, and may refer to, for example, a fixed connection, a detachable connection, or an integral connection, a mechanical connection, an electrical connection, a direct connection, an indirect connection via an intermediate medium, or internal communication between two elements. Those skilled in the art can understand the specific meanings of the above terms in this application according to specific circumstances.

[0025] Furthermore, the technical features according to the various embodiments of the present application described below can be combined with each other unless they are inconsistent with each other.

[0026] Example Referring to Figures 1 to 5, the present application provides an FPGA three-dimensional chiplet packaging structure, which includes a plurality of stacked FPGA packaging modules and a connection substrate, wherein the FPGA packaging modules are provided with micro-bump structures for interconnection with FPGA chips, and the topology layout of the elements and micro-bump structures in each of the FPGA packaging modules is the same.

[0027] The FPGA packaging modules of adjacent layers are laid out so that at least some of the microbump structures overlap, and the FPGA chips in the adjacent FPGA packaging modules are interconnected by the microbump structures at the overlapping positions. A connection substrate is used to mount the stacked FPGA packaging modules and realize signal transmission from each of the FPGA packaging modules to the outside. One FPGA packaging module can be regarded as one CLB.

[0028] The FPGA 3D chiplet packaging structure according to this embodiment includes a plurality of stacked FPGA packaging modules, with the FPGA chips in adjacent layers of the FPGA packaging modules interconnected by microbump structures at overlapping positions. This allows for interconnections between the stacked FPGA chips, enabling 3D stacked packaging of FPGA chips, thereby increasing the number of CLBs per unit area of ​​the FPGA chiplet, increasing the capacity per unit area of ​​the FPGA chiplet, and improving the performance of the FPGA chiplet. Compared to a method of stacking FPGA chips after packaging, where different FPGA chips are stacked using wire bonding and TSV through vias, this method has fewer process steps. Furthermore, while wire bonding methods are prone to problems such as wire breakage and solder misalignment, resulting in relatively low yields, the microbump structure is more stable and results in higher yields. If a transmission problem occurs, the wire bonding method has many wires in the wire bonding-TSV process product, making testing difficult, whereas the microbump array connection method makes it easier to determine which specific chip layer has the problem.

[0029] 1-2 or 3-4, the FPGA packaging module includes a packaging substrate (e.g., 211, 221 in FIG. 1), and microbump structures (e.g., 213, 223 in FIG. 1) and an FPGA chip are connected by connection wiring within the packaging substrate (not shown). The packaging substrate has an overlapping region for providing the overlapping and interconnected microbump structures (black blocks in FIG. 1 and circles in FIG. 2). Directly opposite the microbump structure located in the overlapping region, the packaging substrate has front connection openings (e.g., 2111, 2211 in Figure 1) facing the microbump structure and back connection openings (e.g., 2112, 2212 in Figure 1) on the surface opposite the microbump structure, and the front connection openings are electrically connected to the corresponding back connection openings, the front connection openings are connected to the microbump structure, and the back connection openings are suitable for connection to microbump structures at corresponding positions in the underlying FPGA packaging module.

[0030] Furthermore, the connection board 100 is provided with connection wiring and a docking interface (not shown), and the docking interface is used to connect to the stacked FPGA packaging modules and realize signal transmission of each of the FPGA packaging modules to the outside via the connection wiring.

[0031] Here, the electrical connection between the front connection opening and the corresponding back connection opening may be directly connected by a TSV through via, or may be indirectly connected by wiring inside the packaging substrate.

[0032] Furthermore, the connecting substrate is provided with a substrate micro-bump structure, which is provided corresponding to the docking interface, is connected to the docking interface in a one-to-one correspondence, and is suitable for electrically connecting to the rear connection opening of the FPGA packaging module above.

[0033] 1-2 or 3-4, the FPGA packaging module includes a first FPGA packaging module 210 and a second FPGA packaging module 220. The second FPGA packaging module 220 is stacked above the first FPGA packaging module 210, and a back connection opening 2112 located in the overlapping region of the first FPGA packaging module 210 is electrically connected to a docking interface at a corresponding position on the connection substrate. In the embodiment of FIGS. 1-2 or 3-4, the stacked FPGA packaging modules include only the first FPGA packaging module 210 and the second FPGA packaging module 220. In some other embodiments, more FPGA packaging modules may be stacked in this manner.

[0034] Furthermore, the connecting substrate is provided with a substrate micro-bump structure, which is provided corresponding to the docking interface, is connected to the docking interface in a one-to-one correspondence, and is suitable for electrically connecting to the rear connection opening of the FPGA packaging module above.

[0035] In different embodiments, there are several options for stacking FPGA packaging modules.

[0036] 1 and 2, in some embodiments, the stacking manner of the FPGA packaging modules is such that the FPGA packaging modules are completely overlapped, and the projection patterns of the FPGA packaging modules of different layers onto the connection substrate are completely overlapped. That is, the first FPGA packaging module 210 and the second FPGA packaging module 220 are completely overlapped, and the projection patterns of the first FPGA packaging module 210 and the second FPGA packaging module 220 onto the connection substrate 100 are completely overlapped. A in FIG. 2 is used only to indicate the orientation of the packaging modules and is not intended to indicate any specific technical features.

[0037] In this method, the first FPGA packaging module 210 includes a first packaging substrate 211, which is provided with a first FPGA chip 212 and first micro-bump structures 213 arranged in an array for interconnection. At the same time, the first packaging substrate 211 has a front connection opening 2111 facing the first micro-bump structures 213 below the first micro-bump structures 213, and a back connection opening 2112 on the surface opposite to the first micro-bump structures 213. The second FPGA packaging module 220 includes a second packaging substrate 221, which is provided with a second FPGA chip 222 and second micro-bump structures 223 for interconnection. At the same time, the second packaging substrate 221 has a front connection opening 2211 facing the second micro-bump structure 223 below the second micro-bump structure 223 on its surface directly opposite the second packaging substrate 221, and a back connection opening 2212 on its surface opposite the second micro-bump structure 223. The front connection openings 2111, 2211 are electrically connected to the corresponding back connection openings 2112, 2212, and the front connection openings 2111, 2211 are connected to the corresponding micro-bump structures 213, 223, so that the back connection opening 2212 of the second packaging substrate 221 is suitable for connection to the first micro-bump structure 213 at the corresponding position in the first FPGA packaging module below.

[0038] The connecting substrate 100 is provided with a substrate microbump structure (the structural form of which is the same as the above-mentioned first microbump structure 213 and second microbump structure 223), which is provided corresponding to the docking interface, connected to the docking interface in a one-to-one correspondence, and suitable for electrically connecting to the rear connection opening of the FPGA packaging module above, i.e., the first FPGA packaging module 210.

[0039] Alternatively to the above stacking method, an incompletely overlapping stacking method may be selected.

[0040] 3 and 4, in some other embodiments, the stacking method of the FPGA packaging modules is such that the FPGA packaging modules of adjacent layers are rotated horizontally by 180°, and then partially offset and partially overlap, and the FPGA packaging modules of adjacent layers are interconnected by micro-bump structures at the overlapping positions. Referring to FIG. 4, the first FPGA packaging module 210 and the second FPGA packaging module 220 are rotated horizontally by 180°, and then partially offset and partially overlap. A in FIG. 4 is only used to indicate the orientation of the packaging modules and is not used to indicate specific technical features.

[0041] 4, in this stacking method, the connection substrate 100 includes a main substrate 110 and a height-increasing substrate 120. The height-increasing substrate 120 is stacked on a portion of the main substrate 110. The FPGA packaging module not directly connected to the main substrate, i.e., the second FPGA packaging module 220, has a non-overlapping region. The height-increasing substrate 120 at least partially corresponds to the non-overlapping region of the FPGA packaging module not directly connected to the main substrate, i.e., the second FPGA packaging module 220, and is electrically connected to the FPGA packaging module, i.e., the second FPGA packaging module 220, at the corresponding position.

[0042] In this stacking method, on the one hand, the overlapping areas allow interconnection between the first FPGA chip 212 and the second FPGA chip 222 in the adjacent first FPGA packaging module 210 and second FPGA packaging module 220, realizing stacked connections of multiple chips per unit area, and these are all connected to the main substrate 110 to enable external signal connection. At the same time, when rotated symmetrically 180°, the second FPGA packaging module 220 can free up a significant portion of the non-overlapping microbumps—the non-overlapping area, so to speak, the interconnection area. This area is not shielded by the underlying first FPGA packaging module 210, so it can be connected to the connection substrate, realizing more interface connections and more signal transmission. Not only does this increase the chip capacity, but it also increases the signal transmission wiring, thereby ensuring improved capacity and performance. Furthermore, the provision of the height-increasing substrate 120 not only reduces the distance between the connection substrate and the packaging module, but also ensures structural stability and signal transmission stability.

[0043] Regarding the selection of the connection method, the main substrate 110 may be provided with a docking interface and a substrate micro-bump structure, which is connected to the docking interface in a one-to-one correspondence and is connected to the backside connection opening on the backside of the first packaging substrate 211 of the first FPGA packaging module 210. The height-increasing substrate 120 may also be provided with a docking interface and a micro-bump structure, which is connected to the docking interface in a one-to-one correspondence and is connected to the backside connection opening on the backside of the second packaging substrate 221 of the second FPGA packaging module 220. Alternatively, other connection methods such as copper pillars or solder balls may be used.

[0044] An I / O interface is provided on the height increasing substrate 120, and the I / O interface is electrically connected to the non-overlapping region. In this embodiment, for example, the docking interface of the height increasing substrate 120 is set as the I / O interface. That is, since the overlapping region has already realized the connection between the second FPGA packaging module 220 and the outside, the non-overlapping region is an empty interconnection region, which can be used to realize the docking of more transmission wiring, and can be set as, for example, a DDR I / O connection interface.

[0045] Furthermore, the distance between the main board 110 and the FPGA packaging module directly connected thereto is a first distance, and the distance between the height-increasing board 120 and the FPGA packaging module not directly connected thereto is a second distance, and the first distance and the second distance are the same.

[0046] 3 and 4, the distance between the main substrate 110 and the first FPGA packaging module 210 that is directly connected thereto is a first distance, and the distance between the height-increasing substrate 120 and the second FPGA packaging module 220 that is not directly connected thereto is a second distance, and the first distance is the same as the second distance. In this way, the distances between different FPGA packaging modules and the connecting substrates are all the same, and the overall structural specifications of each part are unified, thereby improving the stability of the entire structure.

[0047] The FPGA packaging modules also include Xbar interconnect switches, and the Xbar interconnect switches in the FPGA packaging modules of adjacent layers are interconnected by the microbump structures in the overlapping regions. For example, as shown in FIG. 5 , a first FPGA packaging module 210 in adjacent layers includes a first Xbar interconnect switch array 214, and a second FPGA packaging module 220 in adjacent layers includes a second Xbar interconnect switch array 224. The first Xbar interconnect switch array 214 and the second Xbar interconnect switch array 224 are also interconnected by microbumps in the overlapping regions, allowing for more flexible sharing of wiring connections such as I / O connections and achieving more data processing. In this way, communication between the Xbar interconnect switch arrays in two adjacent layers is realized, thereby expanding the Xbar connection lines from two-dimensional to three-dimensional. Furthermore, FPGA programming allows interconnection to any node in the upper and lower layers, which is more flexible than the wire bonding-TSV method, which can only connect to fixed nodes.

[0048] It is apparent that the above examples are merely illustrative and do not limit the embodiments. Those skilled in the art can further make various other modifications and changes based on the above description. It is not necessary or possible to list all the embodiments here. Any obvious modifications and changes derived therefrom still fall within the scope of protection of the present application.

Claims

1. An FPGA three-dimensional chiplet packaging structure, comprising: a plurality of stacked FPGA packaging modules; and a connection substrate; The FPGA packaging module is provided with a micro-bump structure for interconnection with an FPGA chip, and the topology layout of the elements and the micro-bump structure in each of the FPGA packaging modules is the same; At least some of the microbump structures of the FPGA packaging modules of adjacent layers are laid out to overlap each other, and the FPGA chips in the adjacent FPGA packaging modules are interconnected by the microbump structures at the overlapping positions; The connection substrate is used to mount the stacked FPGA packaging modules and realize signal transmission of each of the FPGA packaging modules to the outside.

2. 2. The FPGA three-dimensional chiplet packaging structure according to claim 1, wherein the stacking method of the FPGA packaging modules is such that the FPGA packaging modules are completely overlapped and the projection patterns of the FPGA packaging modules of different layers onto the connection substrate are completely overlapped.

3. 2. The FPGA 3D chiplet packaging structure according to claim 1, wherein the stacking method of the FPGA packaging modules is such that the FPGA packaging modules of adjacent layers are partially offset and partially overlapped after being rotated horizontally by 180 degrees, and the FPGA packaging modules of adjacent layers are interconnected by micro-bump structures at the overlapping positions.

4. 4. The FPGA three-dimensional chiplet packaging structure according to claim 3, wherein the connecting substrate includes a main substrate and a height increasing substrate, the height increasing substrate is stacked on a portion of the main substrate, the FPGA packaging module not directly connected to the main substrate has a non-overlapping region, and the height increasing substrate at least partially corresponds to the non-overlapping region in the FPGA packaging module not directly connected to the main substrate and is electrically connected to the FPGA packaging module at the corresponding position.

5. 5. The FPGA 3D chiplet packaging structure of claim 4, wherein a distance between the main substrate and the FPGA packaging module directly connected thereto is a first distance, and a distance between the height-increasing substrate and the FPGA packaging module not directly connected thereto is a second distance, and the first distance and the second distance are equal.

6. 5. The FPGA three-dimensional chiplet packaging structure according to claim 4, wherein the height increasing substrate is provided with an I / O interface, the I / O interface being suitable for being electrically connected to the non-overlapping area.

7. 7. The FPGA three-dimensional chiplet packaging structure according to claim 1, wherein the FPGA packaging module includes a packaging substrate, the packaging substrate having an overlapping region for providing the micro-bump structures that are overlapped and interconnected, and the packaging substrate has, directly opposite the micro-bump structures located in the overlapping region, a front connection opening facing the micro-bump structures and a back connection opening on a surface opposite to the micro-bump structures, the front connection openings being electrically connected to the corresponding back connection openings, the front connection openings being connected to the micro-bump structures, and the back connection openings being suitable for connection to micro-bump structures at corresponding positions in the underlying FPGA packaging module.

8. the connection board is provided with connection wiring and a docking interface, the docking interface is used to connect the stacked FPGA packaging modules and realize signal transmission of each of the FPGA packaging modules to the outside via the connection wiring; 8. The FPGA three-dimensional chiplet packaging structure of claim 7, wherein the FPGA packaging module includes a first FPGA packaging module and a second FPGA packaging module, the second FPGA packaging module being stacked above the first FPGA packaging module, and a back connection opening located in the overlapping region of the first FPGA packaging module is electrically connected to a docking interface at a corresponding position on the connection substrate.

9. 9. The FPGA three-dimensional chiplet packaging structure according to claim 8, wherein the connecting substrate is provided with a substrate micro-bump structure, the substrate micro-bump structure is provided corresponding to the docking interface, is connected to the docking interface in a one-to-one correspondence, and is suitable for electrically connecting to the rear connection opening of the FPGA packaging module above.

10. The FPGA three-dimensional chiplet packaging structure of any one of claims 1 to 9, wherein the FPGA packaging module includes an Xbar interconnection switch, and the Xbar interconnection switches in the FPGA packaging modules of adjacent layers are interconnected by the microbump structure in the overlapping region.

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