Image sensor with adjustable floating diffusion structure

Abstract

An image sensor with a tunable floating diffusion (FD) structure is provided for applications such as inspection and metrology. One image sensor includes a sensing node electrically connected to a circuit of the image sensor and formed on a first side of a silicon layer adjacent to the circuit, the sensing node being formed by a voltage-controlled variable floating diffusion (VCVFD) structure. The VCVFD structure has a gate electrode configured to control a variable capacitance of the VCVFD structure via a voltage applied to the gate electrode by an electrical connection to the gate electrode. The VCVFD structure converts charge responsive to electron accumulation in a channel of the circuit into a voltage proportional to the amount of charge and dependent on the variable capacitance. The VCVFD may also be implemented in an electronic sensor pixel configured to detect electrons or x-rays as further described herein.

Description

[Technical Field]

[0001] The present invention relates generally to an image sensor with an adjustable floating diffusion structure (also referred to herein as a sensing node) particularly suitable for use in charge coupled devices (CCDs) for applications such as inspection and metrology. [Background technology]

[0002] The following descriptions and examples are not admitted to be prior art by virtue of their inclusion in this section.

[0003] Creating semiconductor devices, such as logic and memory devices, typically involves processing a substrate, such as a semiconductor wafer, using a number of semiconductor manufacturing processes to form various features and levels of the semiconductor device. For example, lithography is a semiconductor manufacturing process that involves transferring a pattern from a photomask to a resist that is placed on the semiconductor wafer. Additional examples of semiconductor manufacturing processes include, but are not limited to, chemical mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices may be placed and created on a single semiconductor wafer, which may then be separated into individual semiconductor devices.

[0004] The integrated circuit industry requires inspection tools with increasingly higher sensitivity and the ability to detect smaller defects and particles while maintaining high throughput at a lower cost of ownership. The semiconductor industry currently produces semiconductor devices with feature dimensions of approximately 20 nanometers (nm) or smaller. Within a few years, the industry will produce devices with feature dimensions of approximately 5 nm. Particles and defects just a few nm in size can reduce wafer yield, so they must be captured to ensure high-yield production. Furthermore, efforts are underway to speed up inspection and address the potential transition from current 300 mm diameter wafers to future 450 mm diameter wafers. Therefore, the semiconductor industry is driven by an ever-increasing demand for inspection tools that can achieve substantially higher sensitivity at substantially higher speeds.

[0005] Image sensors are key components of semiconductor inspection tools. They play a key role in determining defect detection sensitivity and inspection speed. Given their image quality, photosensitivity, and readout noise performance, charge-coupled devices (CCDs) are widely used as image sensors for semiconductor inspection applications. Signal-to-noise ratio (SNR) and dynamic range (DR) are important figures of merit for CCD image sensors. SNR indicates the sensor's ability to detect light signals above a certain noise-limited background, while DR quantifies the sensor's ability to adequately image both bright and low-light scenes.

[0006] Image sensors typically include a reverse-biased pn junction that acts as a capacitor to convert collected charge, generated by incident radiation or electrons, into a voltage that may then be buffered and / or amplified and converted into a digital signal. This reverse-biased pn junction is referred to herein as the floating diffusion (FD) region. The capacitance of the image sensor's FD region defines the upper and lower limits of the detectable optical signal and, subsequently, the dynamic range of the CCD image sensor. Having a relatively small FD capacitance reduces the lower limit of the optical signal detection level (because smaller capacitance results in a higher signal voltage per unit of collected charge), thereby allowing smaller signals to be detected, but at the expense of reducing the maximum detectable signal. Using a larger FD capacitance increases the maximum detectable signal but reduces the image sensor's sensitivity to low-level optical signals. Therefore, a need arises for a CCD image sensor that implements an adjustable FD and easily obtains a relatively high dynamic range, improving inspection systems and addressing all of the above limitations. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] U.S. Patent Application Publication No. 2016 / 0315114 [Patent Document 2] U.S. Patent Application Publication No. 2019 / 0199947 Summary of the Invention [Problem to be solved by the invention]

[0008] It would therefore be beneficial to develop an image sensor that does not have one or more of the above disadvantages. [Means for solving the problem]

[0009] The following description of various embodiments is not to be construed in any way as limiting the subject matter of the appended claims.

[0010] One embodiment relates to an image sensor comprising a silicon layer configured to generate electron-hole pairs when light is incident on a photosensitive area of ​​the silicon layer. The image sensor also comprises a circuit formed on a first side of the silicon layer. The circuit has a channel and a first gate electrode configured to control electron accumulation in the channel in response to light-induced generation of electron-hole pairs.

[0011] The image sensor further includes a sensing node electrically connected to the circuitry and formed on a first side of the silicon layer adjacent to the circuitry outside the photosensitive area, the sensing node being formed by a voltage-controlled variable floating diffusion (VCVFD) structure. The VCVFD structure has a source region and a channel region. The source region of the VCVFD structure is connected to the channel of the circuitry of the image sensor and to an output circuit. The VCVFD structure also includes a second gate electrode adjacent to the source region and configured to control the variable capacitance of the VCVFD structure via a voltage applied to the second gate electrode by electrical connection to the second gate electrode.

[0012] The VCVFD structure is configured to convert a charge responsive to the electron accumulation into a voltage proportional to the amount of charge and dependent on the variable capacitance. The output circuit is configured to generate an output responsive to the voltage output by the VCVFD structure. The image sensor may be further configured as described herein.

[0013] Another embodiment relates to a system configured to determine information about an analyte. The system includes an illumination subsystem configured to direct light generated by a light source toward the analyte. The system also includes an image sensor located in a path of light from the analyte and configured as described above. The light incident on the photosensitive area of ​​the silicon layer is light from the analyte. The system further includes a computer subsystem configured to determine information about the analyte based on an output generated by an output circuit of the image sensor. The system may be further configured as described herein.

[0014] A further embodiment relates to a computer-implemented method for determining information about an analyte, the method including directing light generated by a light source toward the analyte and detecting the light from the analyte with an image sensor configured as further described above. The light from the analyte is incident on a photosensitive area of ​​the image sensor. The method also includes determining information about the analyte based on an output generated by an output circuit of the image sensor.

[0015] The steps of the method may be performed as further described herein. The method may include any other steps of any other method described herein. The method may be performed by any of the systems described herein.

[0016] An additional embodiment relates to a non-transitory computer-readable medium storing program instructions executable on a computer system to perform a computer-implemented method of determining information about an analyte. The computer-implemented method includes the steps of the above-described method. The computer-readable medium may be further configured as described herein. The steps of the computer-implemented method may be performed as further described herein. In addition, the computer-implemented method for which the program instructions are executable may include any other steps of any other method described herein.

[0017] Some embodiments relate to an electronic sensor pixel including a silicon layer having an n-type buried channel layer forming a first surface of the silicon layer and a p-type electron-sensitive layer disposed between the buried channel layer and an opposing second surface of the silicon layer. The silicon layer also includes a floating diffusion disposed in the buried channel layer adjacent to a central region of the pixel. The floating diffusion includes a sensing node formed by a VCVFD structure. The VCVFD structure includes a VCVFD source region and a VCVFD channel region. The VCVFD source region is connected to a channel of the pixel and an output circuit of the pixel. The VCVFD structure also includes a VCVFD gate electrode adjacent to the VCVFD source region and configured to control a variable capacitance of the VCVFD structure via a voltage applied to the VCVFD gate electrode by an electrical connection to the VCVFD gate electrode. The VCVFD structure is configured to convert charge responsive to electrons in the n-type buried channel layer migrating toward the floating diffusion into a voltage proportional to the amount of charge and dependent on the variable capacitance.

[0018] The electronic sensor pixel also includes at least one gate structure disposed on the first surface, the resistive gate being configured such that an outer periphery of the gate structure substantially coincides with an outer periphery of the buried channel layer. The gate structure defines a central opening such that an inner periphery of the gate structure substantially surrounds and is spaced from a central region. The buried channel layer and the p-type electron sensitive layer are configured such that the p-type electron sensitive layer generates a plurality of electrons in response to each incident electron or X-ray photon, and the generated plurality of electrons are implanted into the buried channel layer. The resistive gate is configured such that when a potential difference between the inner and outer peripheries of the gate structure decreases, the resistive gate generates a first electric field that causes electrons in the n-type buried channel layer to move toward the floating diffusion. The electronic sensor pixel may be further configured as described herein.

[0019] Other objects and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings. [Brief explanation of the drawings]

[0020] [Figure 1A] FIG. 1 is a schematic diagram illustrating a side cross-sectional view of an embodiment of a voltage-controlled variable floating diffusion (VCVFD) structure. [Figure 1B] FIG. 1B is a schematic diagram showing a top view of the VCVFD structure of FIG. 1A. [Figure 2A] FIG. 1 is a schematic diagram showing a cross-sectional side view of another embodiment of a VCVFD structure including a field effect transistor (FET)-like structure with connected source and drain regions. [Figure 2B] FIG. 2B is a schematic diagram showing a top view of the VCVFD structure of FIG. 2A. [Figure 3] 1B includes the schematic diagram of FIG. 1A along with a profile of potential versus distance across the gate of a VCVFD structure and into the semiconductor layer below the gate. [Figure 4] FIG. 10 is a schematic diagram illustrating a side cross-sectional view of an additional embodiment of an image sensor configured as a back-illuminated charge-coupled device (CCD) including a VCVFD structure. [Figure 5] FIG. 1 is a schematic diagram illustrating a side view of an embodiment of a system configured to determine information about an analyte, including a sensor configured as described herein. [Figure 6A] 1 is a schematic diagram illustrating a plan view of an embodiment of an image sensor in which a VCVFD is electrically connected to a different number of columns of pixels. [Figure 6B] 1 is a schematic diagram illustrating a plan view of an embodiment of an image sensor in which a VCVFD is electrically connected to a different number of columns of pixels. [Figure 6C] 1 is a schematic diagram illustrating a plan view of an embodiment of an image sensor in which a VCVFD is electrically connected to a different number of columns of pixels. [Figure 7]FIG. 1 is a block diagram illustrating one embodiment of a non-transitory computer-readable medium storing program instructions executable on a computer system for performing one or more of the computer-implemented methods described herein. [Figure 8] 1 shows an exemplary SEM incorporating a backscattered electron detector and a secondary electron detector according to an embodiment of the present invention. [Figure 9] 1 illustrates an exemplary method for testing or examining a sample. [Figure 10A] 1 illustrates key aspects of an exemplary solid-state electron detector including multiple pixels with one output per pixel, according to an embodiment of the present invention. [Figure 10B] 1 illustrates key aspects of an exemplary solid-state electron detector including multiple pixels with one output per pixel, according to an embodiment of the present invention. [Figure 10C] 1 illustrates key aspects of an exemplary solid-state electron detector including multiple pixels with one output per pixel, according to an embodiment of the present invention. [Figure 11A] 1 illustrates an exploded and assembled front / top perspective view of a single pixel electronic sensor, in accordance with certain illustrative embodiments of the present invention; [Figure 11B] 1 illustrates an exploded and assembled front / top perspective view of a single pixel electronic sensor, in accordance with certain illustrative embodiments of the present invention; [Figure 12A] FIG. 11C is a simplified cross-sectional view showing the pixel of FIG. 11B in operation. [Figure 12B] FIG. 11C is a simplified cross-sectional view showing the pixel of FIG. 11B in operation. [Figure 13] FIG. 10 is a simplified plan view illustrating an exemplary layout for an amplifier utilized by a pixel, in accordance with an alternative embodiment of the present invention. [Figure 14] FIG. 10 is a simplified plan view illustrating a pixel layout according to another alternative embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and their detailed description are not intended to limit the invention to the particular forms disclosed, but on the contrary, are intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0022] Referring now to the drawings, it should be noted that the figures are not drawn to scale. In particular, the scale of some of the elements in the figures may be greatly exaggerated to emphasize the characteristics of the elements. It should also be noted that the figures are not drawn to the same scale. Elements shown in two or more figures that may be similarly configured are indicated using the same reference numeral. Unless otherwise noted herein, any of the elements described and shown may include any suitable commercially available elements.

[0023] FIELD OF THE INVENTION The embodiments described herein generally relate to image sensors, such as charge-coupled devices (CCDs), with adjustable floating diffusion (FD) structures for applications such as inspection and metrology. More specifically, the embodiments relate to FD capacitance, and in particular voltage-variable FD capacitance, for image sensors such as CCDs. Additionally, the embodiments described herein improve CCD image sensors for semiconductor inspection systems, enabling a relatively high dynamic range using a voltage-controlled variable floating diffusion (VCVFD) structure. The terms "floating diffusion" and "sensing node" are used interchangeably herein.

[0024] Currently, the FD region is formed as an n+ implant in the semiconductor layer. This configuration allows for the implementation of standard transistors (such as transfer and reset transistors) adjacent to the FD. The use of n+ implants to form the FD also provides good ohmic contact between the contact plug and the FD. However, this arrangement provides only a fixed pn junction capacitance, which cannot be changed after the CCD image sensor is produced.

[0025] Variable FD can be created by including several parallel fixed FD areas on the image sensor chip. An array of switches or pass transistors can selectively couple the parallel fixed FD areas to the sensor output circuit. An electronic signal can be applied to the gates of a subset or all of the pass transistors, electronically connecting selected fixed FD areas to the sensor output. Other electronic signals can turn off other pass transistors, disconnecting those fixed FD areas from the sensor output. The more parallel fixed FD areas connected to the sensor output, the greater the capacitance. Thus, the total capacitance attached to the sensor output can be electronically selected. One disadvantage of this approach is that at least one switch must be directly connected to the sensor output. The capacitance of this switch and its connection to the sensor output increases the capacitance of the FD connected to the sensor output, limiting the smallest achievable FD capacitance and, therefore, the sensitivity of such a CCD to substantially low light levels.

[0026] While such a switch-controlled variable FD may be useful in situations where sensitivity to substantially low light levels is not required, a variable FD controlled by an analog voltage may be more compact and a more desirable option for CCD image sensors suitable for use in semiconductor inspection systems. A variable FD whose capacitance value varies based on an applied voltage may allow for a wider range of capacitance than the limited quantum of capacitance selected by a binary control signal. What is desired is an analog voltage-controlled variable capacitor that can be incorporated into CCD image sensors fabricated in conventional CCD processes.

[0027] One embodiment of an image sensor includes a silicon layer configured to generate electron-hole pairs when light is incident on a photosensitive area of ​​the silicon layer. FIG. 4 illustrates some aspects of the design, production, and operation of an image sensor 400 configured as a back-illuminated CCD image sensor implementing a VCVFD structure 450. Electron-hole pairs are created when light 499 is absorbed in the silicon. Thus, light 499 is incident on the backside (also referred to herein as the “second side”) of the image sensor 400, which is opposite the frontside (also referred to herein as the “first side”) of the image sensor on which the image sensor circuitry is formed. The photosensitive area of ​​the sensor may include, for example, the entire area of ​​the sensor on which the image sensor circuitry (or pixels) is formed. The silicon layer may be configured to generate electron-hole pairs in any suitable manner known in the art.

[0028] In one embodiment, the silicon layer is a silicon epitaxial layer. In one such embodiment, the silicon epitaxial layer is 14 cm -3 For example, the epitaxial layer may comprise intrinsic or p-type doped silicon with a dopant concentration of less than about 10 15 cm -3With a larger dopant concentration, it may be fabricated on a heavily doped p-type silicon substrate. As shown in Figure 4, the sensor is fabricated in an intrinsic or lightly p-type doped epitaxial layer 401 with a thickness of a few micrometers to tens of micrometers.

[0029] In another such embodiment, the image sensor includes a thin p-type layer with a dopant concentration at least 10 times higher than the dopant concentration of the silicon epitaxial layer, the thin p-type layer being disposed on a second side of the silicon epitaxial layer opposite the first side of the silicon layer. In a back-illuminated image sensor, the (photosensitive) back side of the epitaxial layer 401 is where light 499 is incident. A substantially heavily doped p+ layer 403 may be formed on the back side of the epitaxial layer 401 by either ion implantation or bombardment of boron atoms from a thin boron layer deposited on the front side. The backside p+ layer 403 is "thin" in that it can be substantially shallow (a few nanometers to tens of nanometers) to ensure suitable sensitivity to ultraviolet (UV), deep ultraviolet (DUV), and vacuum ultraviolet (VUV) light. Under prolonged exposure to DUV or VUV light, charge and traps can accumulate in the silicon dioxide on the backside of the epitaxial layer 401, degrading sensor performance. The shallow p+ layer 403 introduces a fixed negative charge on the backside of the sensor, preventing the trapping of photo-generated charge in defects and preserving sensitivity to UV, DUV, and VUV light. An optional electrical connection 411 is made to the backside p+ layer 403 and may be used to apply a bias voltage to the backside of the sensor (e.g., to ground).

[0030] In additional embodiments, the image sensor includes an anti-reflective layer disposed on a second side of the silicon layer opposite the first side. For example, the anti-reflective layer may include a backside coating 480 deposited on the backside of the epitaxial layer 401. Depending on the wavelengths of interest, the backside coating 480 may be a substantially thin layer of high-purity boron or silicon dioxide, or one or more anti-reflective layers (e.g., made of alumina) to reduce the reflectivity and improve the sensitivity of the sensor at those wavelengths. For example, in addition to the range of doping levels described herein, the backside optical coating may be custom designed to be highly sensitive to the wavelengths of interest of the systems described further herein in which the sensor may be used.

[0031] The image sensor also includes circuitry formed on the first side of the silicon layer. The circuitry includes a channel and a first gate electrode configured to control electron accumulation in the channel in response to light-induced generation of electron-hole pairs. For example, when light 499 is absorbed in silicon, electron-hole pairs are created. While holes migrate to the backside where they recombine, an electric field created across the sensor by voltages applied to gate electrodes on the front side of the sensor, such as gates 420, 422, 424, and 426, accelerates electrons toward the channel formed in n-type layer 404, forming a column of light-sensitive pixels. While only four gates are shown for clarity only, in preferred embodiments, many more gates are used to form a substantially larger number of light-gathering pixels, from one pixel (e.g., a line sensor) to thousands of pixels per column.

[0032] A potential difference is applied to these gates via electrical connections 421, 423, 425, and 427 to control where (under which gate) the collected photogenerated electrons accumulate in n-type layer 404. Electrons accumulate under the gate that has the greatest potential below it. For example, if contact 427 connected to gate 426 is at a voltage of +5V and contact 425 connected to gate 424 is at a voltage of −5V, electrons will accumulate under gate electrode 426.

[0033] In addition to controlling the accumulation of charge, the gates are used to transfer accumulated charge from one pixel to another. For example, if electrons are accumulated under gate 426, they will be moved from gate 426 to under gate 424 by raising the voltage applied to gate 424 by contact 425 to a voltage more positive than the voltage applied to gate 426 and / or lowering the voltage applied to gate 426 by contact 427 to a voltage less (more negative) than the voltage applied to gate 424. Electrons can then be moved from gate 424 to 422, from gate 422 to gate 420, etc., by changing the voltages applied to electrodes 425, 423, and 421 accordingly.

[0034] As in CCD technology, the gates may be configured as two-phase, three-phase, or four-phase clocks (i.e., two, three, or four gates per pixel, respectively). Also, in sensors suitable for semiconductor inspection, such as time delay integration (TDI) sensors, the gates are clocked at a rate that causes charge transfer to occur in synchronization with the moving image on the sensor (e.g., in synchronization with the movement of a stage holding the specimen being inspected).

[0035] At one end of the photosensitive pixel gate, for example, when an electron is under gate 420, the electron is transferred to a first buffer gate such as 430 by applying a higher voltage to contact 431 connected to gate 430 compared to the voltage applied to contact 421 connected to gate 420. A more positive voltage (such as a few volts more positive) than the voltage applied to gate 430 is then applied to second buffer gate 435 by contact 436, causing the electron to transfer under second buffer gate 435. After this transfer, lowering first buffer gate 430 to a voltage less than the voltage applied by contact 421 to pixel gate 420 stops the transfer of electrons to the region under buffer gate 435 and allows the accumulation of electrons from the next image pixel under buffer gate 430.

[0036] In a preferred embodiment, sensor 400 may include additional gates similar to 440, each with an electrical connection such as 441, to form a readout register that transfers image signals from the circuitry (e.g., CCD pixels) to a VCVFD sensing node such as 450 for charge-to-voltage conversion. The number of additional gates may vary from a few to several tens (typically 2-32) depending on the application for which the sensor is used. Electrons are transferred from one gate to another in the readout register by appropriately sequencing the voltages applied to the gates, as in a CCD. In another embodiment, there may be no readout register, gate 440 may be omitted, and electrons may be transferred directly to a VCVFD structure, which may be configured as further described herein.

[0037] In one embodiment, the channel of the circuit comprises an n-type doped buried channel. 16 cm -3 An n-type layer 404 having a dopant concentration of n-type or p-type may be formed immediately below the top surface (front surface) of epitaxial layer 401. When the sensor is properly biased, layer 404 forms a buried channel used to collect and transport electrons as described above. At either end of n-type layer 404 may be p+-type layers 405 having a dopant concentration approximately twice or greater than the dopant concentration of the n-type layer. p+ layer 405 is grounded by one or more electrical contacts, such as 412, but may be grounded at multiple points.

[0038] A dielectric layer 408 is formed (e.g., grown) on the front surface of the epitaxial layer. The dielectric layer may include a single dielectric material such as silicon dioxide, multiple layers of dielectric material such as a silicon nitride layer on a silicon dioxide layer, or a three-layer stack such as silicon dioxide on silicon nitride on silicon dioxide. A suitable dielectric thickness ranges from about 50 nm to about 200 nm. The dielectric layer 408 may have openings etched appropriately to allow electrical contact to the underlying silicon, if desired. A plurality of gate electrodes, such as 420, 422, 424, 426, 430, 435, and 440, which may be made of polysilicon, are formed (e.g., deposited and patterned) on the dielectric layer 408. The gate electrodes are separated from one another by a dielectric material (not shown). Electrical connections, such as 421, 423, 425, 427, 431, 436, and 441, may be made to the gate electrodes. In a preferred embodiment, the gate electrodes overlap each other, for example as shown at 432, to control the fringing electric fields near the edges of the electrodes.

[0039] In one embodiment, the image sensor is configured as a CCD. In another embodiment, the image sensor is configured as a back-illuminated CCD. In some embodiments, the circuitry is configured as a CCD circuitry. In additional embodiments, the circuitry is configured as a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, the image sensors described herein may be configured as back-illuminated CCD image sensors implementing a VCVFD architecture. As further described above, the image sensor may have CCD pixels and circuitry on the front side of an intrinsic or lightly p-type doped silicon epitaxial layer, with a high-purity boron layer incorporated on the backside (illumination surface). Electrons generated by light at near-infrared (NIR), visible, UV, deep UV, very ultraviolet (VUV), extreme ultraviolet (EUV), and / or x-ray wavelengths are detected in the epitaxial layer and collected by the CCD pixels on the front side of the epitaxial layer due to an electric field generated across the epitaxial layer by appropriate voltages applied to the CCD pixels. Electrons collected by the CCD pixels are transferred to a VCVFD structure configured for charge-to-voltage conversion and connected to CCD readout circuitry. As described further herein, embodiments of the sensor may be configured as CCD sensors for inspection of semiconductor wafers, reticles, and printed circuit boards (PCBs).

[0040] In further embodiments, the image sensor is configured as a CCD configured to function as a time delay integration (TDI) sensor. For example, sensor embodiments described herein may be CCD sensors used as TDI sensors for inspection of wafers, reticles, PCBs, etc. Such image sensors may be configured such that the gates are clocked at a rate that causes charge transfer synchronously with moving images on the sensor (e.g., synchronously with the movement of a stage holding the specimen being inspected). Such sensor embodiments, as well as systems in which the sensors may be used, may be further configured as described in the Chuang et al. patent application, issued April 11, 2017, which is incorporated by reference as if fully set forth herein. For example, the sensors described herein may be configured as CCD sensors with internal avalanche amplification, as described in this patent.

[0041] The image sensor further includes a sensing node electrically connected to the circuit. For example, as shown in Figure 4, the image sensor includes a sensing node 450 (e.g., formed by gate electrodes 420, 422, 424, 426, 430, 435, and 440) connected to the circuit. The sensing node may be electrically connected to the circuit as described further herein.

[0042] The sensing node is formed on a first side of the silicon layer adjacent to the circuitry outside the photosensitive area. As such, the sensing node is adjacent to and receives signal charge from one or more gate electrodes, such as CCD gate electrodes, e.g., gate electrodes 420, 422, 424, 426, 430, 435, and 440. Accordingly, the embodiments described herein differ from complementary metal-oxide-semiconductor (CMOS) image sensor pixels, in which the VCVFD structure may have to be embedded within each pixel. In other words, in CMOS devices, the VCVFD structure may have to be formed in the photosensitive area of ​​the device, whereas in many of the embodiments described herein, the VCVFD structure can advantageously be formed outside the photosensitive area, as shown in FIG. 4 .

[0043] The sensing node 450 is formed by a VCVFD structure. Figures 1A and 1B show side and top views, respectively, of a basic VCVFD structure implemented on a silicon layer. The VCVFD structure includes a source region 104 and a channel region 108. As shown in Figures 1A and 1B, one end of the silicon layer 100 under the polysilicon gate has a concentration several orders of magnitude higher than the p-type doping 102 of the silicon layer, e.g., 10 per cubic centimeter. 18 ~10 20 atoms, is doped with n-type impurities to form a pn junction to the source 104 of the VCVFD structure. The source of the VCVFD structure is electrically connected (e.g., by electrical connection 106) to a sense amplifier, which reduces a voltage signal corresponding to the charge stored on the VCVFD capacitance to the image sensor output.

[0044] The source region of the VCVFD structure is connected to a channel of the image sensor circuitry (not shown in FIGS. 1A and 1B) and to an output circuitry (not shown in FIGS. 1A and 1B). The source region of the VCVFD structure may be connected to a channel as described further herein and as shown in FIG. 4. As described further herein, the source 104 may be connected to a channel of the circuitry such that the VCVFD structure receives charge 120 from the sensor circuitry.

[0045] In one embodiment, the source region of the VCVFD structure is connected to a charge reset structure in the image sensor. For example, the source 104 may be connected to an adjacent reset structure 122 shown in FIG. 1B, which is formed by a polysilicon gate 124 to which a reset gate (RG) voltage is applied via electrical connection 126 and an n-type drain 128 to which a fixed reset drain (RD) voltage is applied by electrical connection 130. After the voltage signal at the VCVFD source is read by a sense amplifier, the RG gate is biased, and charge is drained from the VCVFD source by connecting the VCVFD source to an RD voltage, which is typically higher than the VCVFD source voltage. The VCVFD structure is then reset to the RD voltage. When the reset is complete, the VCVFD source is disconnected from the RD voltage, allowing the next charge signal to be received from the image sensor circuitry.

[0046] In one embodiment, the source region of the VCVFD structure and the channel of the circuit are doped with the same polarity, with the source region of the VCVFD structure having a dopant concentration equal to or greater than the dopant concentration in the channel of the circuit. For example, as shown in FIG. 4, a VCVFD structure 450 may include a source 451 formed by an n+ type silicon region implanted and / or diffused in epitaxial layer 401. The dopant concentration of source 451 is typically several orders of magnitude higher than n-type layer 404, e.g., 10 18 cm -3 ~10 21 cm -3 The range is.

[0047] In another embodiment, the channel region of the VCVFD structure and the channel of the circuit are doped with the same polarity. For example, both the channel region of the VCVFD structure and the channel of the circuit may be n-type channels. The VCVFD channel and the channel of the circuit may be formed in the same step and may have the same or different dopant concentrations. Thus, in the same manner as the circuit, the VCVFD structure may be either a surface channel type or a buried channel type. For example, in some embodiments, the channel region of the VCVFD structure is configured as an n-type buried channel. In another embodiment, the channel region of the VCVFD structure is configured as an n-type surface channel. Thus, the gate electrode of the VCVFD structure may be one of an n-type buried channel or an n-type surface channel.

[0048] The VCVFD structure also includes a VCVFD gate electrode (also referred to herein as a "second gate electrode") adjacent to the source region. For example, the VCVFD gate electrode 452 shown in FIG. 4 can be formed using the same polysilicon material and the same dielectric layer 408 as the CCD pixel gates (e.g., gates 420, 422, 424, and 426), or different electrode and dielectric materials. As shown in FIG. 4 (and as shown more clearly in FIG. 1A and further described herein), the VCVFD gate 452 typically adjacent to and may slightly overlap the source 451. Also, similar to a CCD, the VCVFD structure 450 may include a reset transistor (not shown in FIG. 4) adjacent to the VCVFD source and connected to a fixed reset voltage. The reset transistor may be used to reset the VCVFD structure before transferring electrons from the pixel, as further described herein. The VCVFD structure shown in FIG. 4 may be connected to a charge reset structure as further shown and described in FIGS. 1B and 2B.

[0049] The VCVFD gate electrode is configured to control the variable capacitance of the VCVFD structure via a voltage applied to the VCVFD gate electrode through an electrical connection to the VCVFD gate electrode. For example, gate 452 is provided with electrical connection 453 through which the voltage applied to the VCVFD gate is controllable. In this manner, the VCVFD structure may be configured as an analog VCVFD structure for an image sensor, such as a CCD image sensor, that uses a metal-oxide-semiconductor (MOS) structure that includes a gate and a source. The gate-to-source voltage (V G ) is the threshold voltage (V T ), charge may be stored in the MOS inversion layer and the source bulk pn junction capacitor. The total capacitance of this FD structure is controllable via an analog gate voltage.

[0050] 1A, the VCVFD gate electrode of the VCVFD structure may include a polysilicon gate 112 separated from a silicon layer 100 by a relatively thin layer of oxide dielectric (i.e., gate oxide) 110. The polysilicon gate has an electrical connection 114 through which a voltage V G may be applied to a VCVFD gate, thereby forming a MOS structure. The lateral dimensions of this polysilicon gate may vary from a few micrometers to tens of micrometers depending on the desired VCVFD capacitance. The thickness of the oxide dielectric layer may vary from a few nanometers to tens of nanometers and may be determined by the CCD image sensor manufacturing process and the desired VCVFD capacitance.

[0051] 1A may be formed by locally implanting a higher density of p-type impurities at the surface of the silicon layer. The p+ ohmic contact may have an electrical connection 118 to connect the silicon layer to ground potential.

[0052] 3 shows a profile 302 of electrostatic potential versus distance across a line 300 (from point A to point B) that extends through the polysilicon gate and oxide dielectric into the semiconductor layer below the gate for the embodiment of the VCVFD structure of FIG. 1A. The total capacitance of the VCVFD structure is

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[0053] The VCVFD structure is configured to convert the charge responsive to the electron accumulation into a voltage proportional to the amount of charge and dependent on a variable capacitance. For example, the VCVFD structure converts the electron charge into a voltage proportional to the amount of charge and dependent on the total capacitance of the VCVFD structure, the total capacitance being determined by the sum of the fixed capacitance of the VCVFD source and the variable capacitance of the VCVFD gate, which is controlled by a voltage applied to electrode 453 shown in FIG. 4. Thus, during operation, charge collected from an image sensor (e.g., a CCD) is transferred to the VCVFD structure and stored in its source-bulk pn junction capacitor. The polysilicon gate voltage V G is the threshold voltage V of the MOS structure T , which is formed of an oxide dielectric and a silicon layer, the charge that accumulates in the channel 108 under the polysilicon gate is substantially small. On the other hand, when the polysilicon gate voltage V G is the threshold voltage V of the MOS structure TWhen .gtoreq..times ...

[0054] The VCVFD structure as described in FIGS. 1A and 1B can be formed using the same polysilicon gate and dielectric oxide material as the image sensor's pixel and charge transfer gate, with the polysilicon gate located adjacent to and slightly overlapping the standard pn junction FD region. The image sensor gate can be either a surface channel type or a buried channel type. The VCVFD structure as described in FIGS. 1A and 1B can also be formed with the source and gate of a drainless "partial" FET device. The partial FET structure can be either an enhancement mode (surface channel) type or a depletion mode (buried channel) type. In a preferred embodiment, the CCD gate and partial FET structure used to form the VCVFD structure are buried channel type, which is a better choice for use in CCD image sensors to avoid the charge transfer and noise performance issues inherent in surface channel devices.

[0055] In another embodiment, the VCVFD structure includes a drain region connected to the channel region of the VCVFD structure, and the source and drain regions of the VCVFD structure are electrically connected. FIGS. 2A and 2B show side and top views, respectively, of an alternative implementation of a VCVFD structure formed by an n-type source 204 and drain 206 of a FET on a p-type 202 silicon layer 200. The source and drain regions 204 and 206 are formed on either side of a channel 208 over which a polysilicon gate 214 is formed. The lateral dimensions of the polysilicon gate 214 may vary from a few micrometers to tens of micrometers depending on the desired VCVFD capacitance. The polysilicon gate is separated from the silicon layer 200 by a relatively thin layer of oxide dielectric 212 (i.e., gate oxide). The thickness of the oxide dielectric layer may vary from a few nanometers to tens of nanometers and may be determined by the CCD image sensor fabrication process and the desired VCVFD capacitance. The polysilicon gate is provided with an electrical connection 216 through which a voltage V G may be applied to the VCVFD gate.

[0056] As in the FET manufacturing process, the impurity concentration in the source and drain regions is typically 10 per cubic centimeter. 16 ~10 20The thickness of the FET is in the range of 10 ...

[0057] 2A and 2B, the FET source and drain regions are electrically connected and may be seen as two VCVFD structures connected in parallel to a sense amplifier by electrical connection 210. The source regions of the VCVFD structures are also connected to a channel of the image sensor circuitry and to output circuitry (not shown in FIGS. 2A and 2B). As described further herein, the source 204 may be connected to a channel of the circuitry, thereby causing the VCVFD structure to receive charge 222 from the sensor circuitry.

[0058] In one embodiment, the source region of the VCVFD structure is connected to a charge reset structure in the image sensor. For example, the adjacent reset structure 224 shown in FIG. 2B may be connected to both the source and drain regions, thereby draining charge from both regions during reset operations that occur between successive charge signal readout operations. The adjacent reset structure 224 shown in FIG. 2B is formed by a polysilicon gate 226 to which an RG voltage can be applied via electrical connection 228 and an n-type drain 230 to which a fixed RD voltage can be applied via electrical connection 232. The charge reset structure may be further configured as described herein.

[0059] 2A and 2B may be further configured as described herein. For example, a p+ ohmic contact 218 may be formed by locally implanting a higher density of p-type impurities at the surface of the silicon layer. The p+ ohmic contact may have an electrical connection 220 connecting the silicon layer to ground potential.

[0060] The image sensor's output circuitry is configured to generate an output responsive to the voltage output by the VCVFD structure. The output circuitry may be included in (or be one of) multiple circuits configured to amplify and / or process the signal generated by the sensor and control the sensor, and these circuits may be fabricated inside or adjacent to the photosensitive area. In FIG. 4, source 451 is provided with electrical connection 454 connecting it to CCD readout circuitry, which is typically formed by MOSFET transistors as described above. The VCVFD output voltage for connection 454 in FIG. 4 may be connected to a buffer or amplifier before being connected to the CCD output or an analog-to-digital converter (ADC).

[0061] Such a circuit is shown in FIG. 4 with a MOSFET transistor formed by source and drain implants 406, channel implant 407, gate dielectric 409, and gate electrode 410. Electrical connections such as 415, 416, and 417 may be made to the gate, source, and drain of the MOSFET transistor, respectively. Gate dielectric 409 may be substantially similar to and formed simultaneously with dielectric layer 408, or gate dielectric 409 may be formed of a different material and / or a different thickness than dielectric layer 408, depending, for example, on the desired transistor characteristics. While only one such transistor is shown in FIG. 4 for clarity only, typically such a circuit includes many transistors. In a preferred embodiment, MOSFET transistors with n-type channels are fabricated in p+ doped well 405, electrically isolating them from dark and photocurrents in epitaxial layer 401.

[0062] Structure 408a may also be substantially similar to dielectric layer 408, and may be formed simultaneously, for example, as a single dielectric layer that is then patterned to separate dielectric layer 408 and structure 408a. Alternatively, structure 408a may be formed of a different material and / or a different thickness than dielectric layer 408 and / or gate dielectric 409, for example, depending on the desired properties of structure 408a. Structure 408a may be any isolation structure formed between VCVFD structure 450 and the output circuitry, and may be formed above p-well 405. In this manner, the isolation structure may separate the readout circuitry from the sensor active area and the VCVFD structure.

[0063] In some embodiments, the circuitry is configured as a two-dimensional (2D) array of pixels. For example, in a CCD image sensor suitable for semiconductor inspection systems, multiple columns of pixels such as those described in FIG. 4 are laid out to form a 2D array of light-sensitive pixels. A clock signal is connected throughout the array and is used to simultaneously transfer charge from one pixel to the next within all or a group of columns. However, the sensor pixels can be laid out in different configurations than shown and may include more or fewer pixels than shown.

[0064] In another embodiment, the circuit is configured as multiple columns of pixels, including at least first and second columns of pixels, where the at least first and second columns of pixels include one or more pixels, and the sensing node is one of multiple sensing nodes in the image sensor, where the multiple sensing nodes include at least first and second sensing nodes, where the first and second sensing nodes are electrically connected to all of the one or more pixels in the first and second columns of pixels, respectively. More specifically, each of the sensing nodes may be electrically connected to only the first (or last) pixel in each of the columns. If the column includes two or more pixels, the first pixel is connected to the second pixel, the second pixel is connected to the third pixel, and so on. Thus, the sensing node may be directly connected to one pixel in a column or may be connected to other pixels in the same column through that one pixel. In this manner, the sensor may include a VCVFD structure for each column of pixels. More specifically, a first VCVFD structure may be electrically connected to all of the pixels in only a first column of pixels, a second VCVFD structure may be electrically connected to all of the pixels in only a second column of pixels different from the first column, etc. Each of the VCVFD structures may be configured as described herein. Thus, the structure shown in FIG. 4 may constitute one column of pixels electrically connected to one VCVFD structure, and an image sensor may include multiple sets of these structures arranged side by side on the sensor.

[0065] A more detailed diagram of such an image sensor is shown in FIG. 6A. Image sensor 600 includes four columns of pixels: 601-1, 601-2, 601-3, and 601-4. While four columns of pixels are shown in this figure, a sensor may include one or more such columns of pixels. Additionally, while each of the columns shown in FIG. 6A includes five pixels, each column may include one or more pixels. As shown in FIG. 6A, VCVFD 602-1 is electrically connected to the first or last pixel in column 601-1 and is therefore connected to all of the pixels in that column and not to pixels in any other columns. Similarly, VCVFD 602-2 is electrically connected to all of the pixels in only column 601-2, VCVFD 602-3 is electrically connected to all of the pixels in only column 601-3, and VCVFD 602-4 is electrically connected to all of the pixels in only column 601-4. Each VCVFD structure may have the same configuration as each other VCVFD structure. The image sensor may therefore include many more pixel circuits than VCVFD structures. For example, in each column of transistors or circuits, there may be one or more pixel circuits (tens or hundreds of pixel circuits) and only one VCVFD structure. This configuration provides benefits that are described further herein.

[0066] In a further embodiment, the circuit is configured as multiple columns of pixels, including at least first and second columns of pixels, each column including one or more pixels, and the sensing node is electrically connected to one or more pixels in the first and second columns of pixels. In other words, the sensor may include a VCVFD structure common to a group of two or more columns of pixels. One such embodiment of an image sensor is shown in FIG. 6B. In this embodiment, the image sensor 610 includes four columns, each including five pixels. The number of columns and the number of pixels in each column may vary as described above. In this embodiment, the VCVFD 613-1 is electrically connected to all of the pixels in columns 611-1 and 611-2 only, and the VCVFD 613-2 is electrically connected to all of the pixels in columns 611-3 and 611-4 only. The VCVFDs 613-1 and 613-2 may have the same configuration as each other and may be further configured as described herein. The image sensor may also include elements 612-1 and 612-2, which may include buffer gates, readout registers, etc., such as buffer gates 430 and 435 and readout register gate 440 shown in Figure 4. A VCVFD may therefore be electrically connected to each of these elements and, therefore, to the pixels connected thereto. In this manner, a VCVFD structure may be provided for a group of columns that are read out simultaneously.

[0067] Additionally, a single VCVFD structure may be electrically connected to pixels in more than two columns. For example, a first VCVFD structure may be electrically connected to all of the pixels in the first, second, and third columns, and a second VCVFD structure may be electrically connected to all of the pixels in the fourth, fifth, and sixth columns. Thus, the structure shown in FIG. 4 may form one of multiple columns of pixels electrically connected to a single VCVFD structure, and an image sensor may include multiple sets of this combination of structures arranged side-by-side on the sensor. One such embodiment of an image sensor is shown in FIG. 6C. In this embodiment, the image sensor 620 includes four columns, each of which includes five pixels. The number of columns and the number of pixels in each column may vary, as described above. In this embodiment, VCVFD 623 is electrically connected to all of the pixels in only columns 621-1, 621-2, 621-3, and 621-4, which may be all of the columns of pixels in the image sensor or only some of the columns of pixels in the sensor (in which case the image sensor may include two or more of the configurations shown in FIG. 6C ). VCVFD 623 may be further configured as described herein. The image sensor may also include elements 622-1, 622-2, 622-3, and 622-4, which may include buffer gates, readout registers, etc., such as buffer gates 430 and 435 and readout register gate 440 shown in FIG. 4 . Thus, VCVFD may be electrically connected to these elements and, therefore, to each of the pixels connected thereto.

[0068] When any image sensor configuration described herein includes two or more VCVFD structures, each of the VCVFD structures may have the same configuration as each of the other VCVFD structures. In addition, each VCVFD structure included in such an image sensor configuration may be further configured as described herein. Similar to the configuration described above and shown in FIG. 6A, the image sensors shown in FIGS. 6B and 6C may include many more pixel circuits than VCVFD structures. For example, for every three or more columns of transistors or circuits, there may be one or more pixel circuits (tens or hundreds of pixel circuits) and only one VCVFD structure. These configurations also provide the benefits described further herein.

[0069] In some embodiments, only one or two VCVFD structures connected to output circuitry may be used. For example, in preferred embodiments suitable for use in substantially high-speed inspection systems such as those used in the semiconductor industry, multiple VCVFD structures and their corresponding outputs (such as tens of outputs, hundreds of outputs, one output per column, or one output every two columns) may be used to simultaneously output multiple pixels to achieve substantially high data output rates. Such sensors may be hundreds to thousands of pixels long and include 2D arrays of approximately thousands of columns. Such sensors may be configured as further described herein.

[0070] In some embodiments, the circuit is configured as a pixel including at least first and second pixels, the sensing node is electrically connected to the first and second pixels, and the image sensor or computer subsystem is configured to calibrate the first and second pixels by calibrating the sensing node. In this manner, the embodiments described herein may be configured to enable pixel calibration by calibrating each sensing node rather than the pixel. In other words, by calibrating a sensing node, one can effectively calibrate each pixel electrically connected to that sensing node. For example, if a sensing node is coupled to all of the pixels in a column, the calibration response or sensitivity in that column should all be the same. Thus, because the image sensors described herein are likely to include substantially fewer sensing nodes than pixels, e.g., thousands of sensing nodes versus millions of pixels, the embodiments described herein can more quickly and easily calibrate each of the pixels by calibrating the sensing node rather than the pixels themselves. Other than calibrating the sensing nodes rather than the pixels themselves, calibration may be performed by the image sensor or computer subsystem in any suitable manner known in the art, which computer subsystem may be further configured as described herein.

[0071] In contrast to some of the above embodiments, in which each column includes multiple pixels, the image sensor embodiments described herein may include a single pixel in each column. The image sensor may therefore include a single line of pixels, with each column of pixel circuits including only a single pixel circuit. Each single pixel circuit may be formed by only one CCD gate, but may have multiple electrodes connected thereto to control the voltage applied across the gate and the potential in the CCD channel below the gate. Examples of such sensor pixel configurations are described in U.S. Patent No. 6,217,237 to Chuang et al., issued April 11, 2017, and U.S. Patent No. 6,217,237 to Chuang et al., issued January 29, 2019, both of which are incorporated by reference as if fully set forth herein. The image sensors described herein may be further configured as described in these patents.

[0072] In another embodiment, the image sensor is located in an inspection system such that light incident on the photosensitive area is from a specimen being inspected by the inspection system, and the inspection system is configured to detect defects on the specimen based on the output generated by the output circuitry of the image sensor. This embodiment is described further herein and may be configured as shown in FIG.

[0073] Another embodiment relates to a system configured to determine information about an analyte. Figure 5 illustrates an exemplary testing system 500 configured to test or measure an analyte 508, according to one or more embodiments described herein. The testing system 500 may be configured as a testing system or metrology system to test and / or measure the analyte 508.

[0074] The specimen 508 may be a wafer. The wafer may include any wafer known in the semiconductor arts. The embodiments also do not limit the specimens with which they may be used. For example, the embodiments described herein may be used with specimens such as reticles, photomasks, flat panels, printed circuit boards (PCBs), and other semiconductor specimens.

[0075] The specimen 508 may be placed on a stage assembly 512 to facilitate movement of the specimen 508. The stage assembly 512 may include any stage assembly known in the art, including, but not limited to, an XY stage, an R-Theta stage, etc. In another embodiment, the stage assembly 512 may adjust the height of the specimen 508 during inspection to maintain focus on the specimen 508. In yet another embodiment, a lens, such as the objective lens 550, may be moved up and down during inspection to maintain focus on the specimen 508.

[0076] The system includes an illumination subsystem configured to direct light generated by a light source toward the specimen. The illumination subsystem may include an illumination source 502 that outputs light L having a wavelength, for example, in the range of approximately 120 nm to approximately 2000 nm. OUT Illumination source 502 may be a light source such as a laser or a broadband light source. Additionally, illumination source 502 may include any other suitable light source known in the art.

[0077] The illumination subsystem may include one or more optical components, such as beam splitters, mirrors, lenses, apertures, and wave plates, that direct the light L OUT The optical components may be configured to adjust and direct the light L onto the specimen 508. The optical components may be configured to illuminate an area, a line, or a spot on the specimen 508. In one embodiment of the illumination subsystem, a beam splitter, or mirror 534, mirrors 537 and 538, and lens 552 direct the light L INTThe illumination subsystem may be configured to illuminate the specimen 508 from below so that light can be transmitted through the specimen 508 to allow inspection or measurement of the specimen 508. The illumination subsystem may additionally or alternatively illuminate the specimen 508 at an angle of incidence L oblique to the normal to the specimen surface. Obl , may include a beam splitter, or mirrors 534 and 535, mirror 536, and lens 551 configured to illuminate specimen 508 with light at an angle of incidence greater than, for example, 60°. In this embodiment, the specularly reflected light L Spec may be blocked or eliminated rather than concentrated.

[0078] The illumination subsystem may additionally or alternatively direct illumination light L onto the top surface of the specimen 508. IN The illumination subsystem may include optical elements 503 collectively configured to direct light from the light source to the specimen. For example, the illumination subsystem may include a lens 533 of optical elements 503, an illumination pupil aperture 531, an illumination tube lens 532, a beam splitter 540, and an objective lens 550, which collectively direct light from the light source to the specimen at an angle of incidence, which may be, for example, a normal or near-normal angle of incidence. The illumination tube lens 532 may be configured to image the illumination pupil aperture 531 onto a pupil in the objective lens 550. For example, the illumination tube lens 532 may be configured so that the illumination pupil aperture 531 and the pupil in the objective lens 550 are conjugated to one another. The illumination pupil aperture 531 may be configurable by switching a different aperture into position for the illumination pupil aperture 531 and / or adjusting the diameter or shape of the opening of the illumination pupil aperture 531. In this regard, the specimen 508 may be illuminated at a range of angles depending on the characterization (e.g., measurement or inspection) being performed under the control of the computing system 514. The illumination pupil aperture 531 also includes a polarizing element (not shown) to direct the illumination light L IN The polarization state of the light may be controlled.

[0079] The system also includes a sensor 506 located in the path of the light from the specimen. The sensor is configured as described further herein. The light from the specimen is incident on a light-sensitive area of ​​the image sensor. For example, when the specimen 508 is illuminated in one or more of the modes described above, the optical element 503 also captures light L reflected, scattered, diffracted, transmitted, and / or emitted from the specimen 508. R / S / T and collects the light L onto the sensor 506 of the detector assembly 504. R / S / T The sensor 506 and the detector assembly 504 may include any of the sensor embodiments described further herein. The detector assembly 504 is communicatively coupled to a computing system 514.

[0080] Computing system 514 is configured to store and / or analyze data from detector assembly 504 under the control of program instructions 518 stored on carrier medium 516. Computing system 514 may also be configured to control other elements of inspection system 500, such as stage 512, illumination source 502, and optical elements 503.

[0081] The optical element 503 may include a collection tube lens 522. The collection tube lens 522 may be configured to image a pupil in the objective lens 550 onto the collection pupil aperture 521. For example, the collection tube lens 522 may be configured so that the collection pupil aperture 521 and the pupil in the objective lens 550 are conjugated to one another. The collection pupil aperture 521 may be configurable by switching a different aperture into position for the collection pupil aperture 521 and / or adjusting the diameter or shape of the opening of the collection pupil aperture 521. In this regard, different ranges of angles of illumination reflected or scattered from the specimen 508 may be directed to the detector assembly 504 under the control of the computing system 514. The collection pupil aperture 521 may also include a polarizing element (not shown) to polarize the light L R / S / T A particular polarization of light can be selected for transmission to the sensor 506 .

[0082] The illumination pupil aperture 531 and / or the collection pupil aperture 521 may include a programmable aperture. Programmable apertures are generally described in Brunner, issued February 9, 2016, and Brunner, issued May 9, 2017, which are incorporated by reference herein in their entireties. Methods for selecting an aperture configuration for inspection are generally described in Kolchin et al., issued July 18, 2017, and Kolchin et al., issued August 8, 2017, which are incorporated by reference herein in their entireties. The embodiments described herein may be further configured as described in these patents.

[0083] The various optical elements and modes of operation shown in Figure 5 are merely illustrative of how sensor 506 may be used in inspection system 500 and are not intended to limit the scope of the present disclosure. An actual inspection system 500 may implement a subset or superset of the modes and optical elements shown in Figure 5. Additional optical elements and subsystems may be incorporated as needed for a particular application.

[0084] The system further includes a computer subsystem configured to determine information about the analyte based on the output generated by the output circuitry of the image sensor. For example, the computing system 514 shown in FIG. 5 may be configured in this manner. The computing system 514 may be coupled to the sensor 506 in any suitable manner (e.g., via one or more transmission media, which may include "wired" and / or "wireless" transmission media) so that the computing system can receive the output, images, etc., generated by the sensor 506. The computing system 514 may be configured to perform a number of functions using the output of the sensor as described herein, and any other functions as further described herein. This computing system may be further configured as described herein.

[0085] A computing system may include one or more computer subsystems (not shown), configured to perform one or more functions, such as determining information about an analyte based on the output of an image sensor. The computer subsystem of a computing system (and other computer subsystems described herein) may also be referred to herein as a computer system. Each of the computing systems and computer subsystems or systems described herein may take various forms, including a personal computer system, an image computer, a mainframe computer system, a workstation, a network appliance, an internet appliance, or other device. In general, the term "computer system" may be broadly defined to encompass any device having one or more processors that executes instructions from a storage medium. Computing systems and computer subsystems or systems may also include any suitable processor known in the art, such as a parallel processor. Additionally, computing systems and computer subsystems or systems may include computer platforms with high-speed processing and software, either as standalone or networked tools.

[0086] When a system includes two or more computer subsystems, the different computer subsystems may be coupled to one another such that images, data, information, instructions, etc., can be transmitted between the computer subsystems as described further herein. For example, the two or more computer subsystems may be coupled to one another by any suitable transmission medium (not shown), which may include any suitable wired and / or wireless transmission medium known in the art. Two or more of the computer subsystems may also be effectively coupled by a shared computer-readable storage medium (not shown).

[0087] FIG. 5 is provided herein to generally illustrate several configurations of systems that may include sensor embodiments described herein. Clearly, the system configurations described herein may be modified to optimize the performance of the system, as is typically done when designing a commercial system. In addition, the systems described herein may be implemented using existing systems (e.g., by adding the image sensor embodiments described herein and other functionality to the existing system), such as systems commercially available from KLA Corporation of Milpilas, California. For some such systems, the embodiments described herein may be provided as optional features of the existing system (e.g., in addition to other functionality of the system). Alternatively, the systems described herein may be designed “from scratch” to provide an entirely new system.

[0088] The computer subsystem may be configured to determine information in a number of different ways, depending on, for example, the analyte, the optical system configuration, and the information to be determined about the analyte. For example, in one embodiment, the system is configured as an inspection system, and the information about the analyte includes information about defects detected about the analyte based on the output. In such an embodiment, the computing system 514 may be configured to detect defects about the analyte 508 by applying a defect detection method to the output generated by the sensor 506. The computing system 514 may be coupled to the sensor 506 as described further herein such that it can receive the output generated by the sensor. Detecting defects about the analyte may be done with any suitable defect detection method and / or algorithm, in any suitable manner known in the art (e.g., by applying a defect detection threshold to the output and determining that any output having a value above the threshold corresponds to a defect (or potential defect)).

[0089] In another embodiment, the system is configured as a metrology system. In a further embodiment, the system is configured as a defect review system. For example, the system embodiment shown in FIG. 5 may be modified in one or more parameters to provide different imaging capabilities depending on the application for which it is used. In one such example, the system may be configured to have higher resolution when it is used for metrology rather than inspection. In other words, the system embodiment shown in FIG. 5 illustrates several general configurations for the system that can be adapted in numerous ways apparent to those skilled in the art to produce systems with different imaging capabilities that are more or less suitable for different applications.

[0090] Thus, the system may be configured to generate an output suitable for redetecting defects on the analyte in the case of a defect screening system, or to measure one or more properties of the analyte in the case of a metrology system. In defect screening system embodiments, computing system 514 may be configured to redetect defects on the analyte 508 by applying a defect redetection method to the output generated by sensor 506, and possibly using the output generated by the sensor to determine additional information about the redetected defects. In metrology system embodiments, computing system 514 may be configured to determine one or more properties of the analyte 508 using the output generated by the sensor.

[0091] Defect review typically involves re-detecting defects detected by the inspection process itself and generating additional information about the defects at higher resolution, e.g., using a system described herein, in a high magnification mode. Defect review is therefore performed at individual locations on the specimen where defects have been detected by inspection. Generally, the higher the resolution of the data about the defects generated by defect review, the better suited it is for determining attributes of the defects, such as profile, roughness, and more precise size information. Computing system 514 may be configured to determine such information about defects on the specimen in any suitable manner known in the art.

[0092] Metrology processes are used at various steps during semiconductor manufacturing processes to monitor and control the process. Metrology processes differ from inspection processes, in that defects are detected on a specimen, and metrology processes are used to measure one or more characteristics of the specimen that cannot be determined using currently used inspection tools. For example, metrology processes are used to measure one or more characteristics of the specimen, such as the dimensions (e.g., linewidth, thickness, etc.) of features formed on the specimen during the process, so that the performance of the process can be determined from the one or more characteristics. Additionally, if one or more characteristics of the specimen are unacceptable (e.g., outside a predetermined range for the characteristics), the measurements of the one or more characteristics of the specimen may be used to modify one or more parameters of the process so that additional specimens produced by the process have acceptable characteristics.

[0093] The metrology process also differs from a defect review process in that, unlike a defect review process in which defects detected by inspection are reviewed in the defect review, the metrology process may be performed at locations where no defects have been detected. In other words, unlike a defect review, the location on the specimen where the metrology process is performed may be independent of the results of the inspection process performed on the specimen. In particular, the location where the metrology process is performed may be selected independent of the inspection results. Additionally, because the location on the specimen where the metrology process is performed may be selected independent of the inspection results, the location on the specimen where the defect review is performed may be determined before the inspection process is performed on the specimen, unlike a defect review in which the location on the specimen where the metrology process is performed cannot be determined until the inspection results for the specimen are generated and available. The computing system 514 may be configured to determine any suitable characteristic of the specimen in any suitable manner known in the art.

[0094] In any of the system embodiments described herein, the computing system 514 shown in FIG. 5 may be configured to generate results, which include at least information determined about the analyte based on the output generated by the image sensor, and possibly any other output generated by the computing system. The results may have any suitable format (e.g., a KLARF file, which is a proprietary file format used by tools commercially available from KLA; a results file generated by Klarity, a tool commercially available from KLA; lot results; etc.). Additionally, all of the embodiments described herein may be configured to store the results of one or more steps of the embodiments on a computer-readable storage medium. The results may include any of the results described herein and may be stored in any manner known in the art. The storage medium may include any of the storage media described herein or any other suitable storage medium known in the art. After the results are stored, they can be accessed on the storage medium, used by any of the method or system embodiments described herein, formatted for display to a user, used by another software module, method, system, etc., to perform one or more functions on the analyte or another analyte.

[0095] Such functionality includes, but is not limited to, modifying a process, such as a production process or step, that has been or will be performed on the specimen, using feedback, feedforward, in situ methods, etc. For example, the computer subsystem may be configured to determine one or more modifications to a process that has been or will be performed on the specimen based on the detected defects and / or other determined information. The modifications to the process may include any suitable modifications to one or more parameters of the process. For example, if the determined information is a defect detected on the specimen, the computer subsystem preferably determines those modifications so that, for example, the defect can be reduced or prevented on other specimens subjected to the review process, the defect can be corrected or eliminated on the specimen in another process performed on the specimen, the defect can be compensated for in another process performed on the specimen, etc. The computer subsystem may determine such changes in any suitable manner known in the art.

[0096] Those changes can then be transmitted to a semiconductor production system (not shown) or to a storage medium (not shown in FIG. 5 ) accessible to both the computer subsystem and the semiconductor production system. The semiconductor production system may or may not be part of the system embodiments described herein. For example, the systems described herein may be coupled to a semiconductor production system via, for example, one or more common elements, such as a housing, a power supply, a specimen manipulation device or mechanism, etc. The semiconductor production system may include any semiconductor production system known in the art, such as a lithography tool, an etching tool, a chemical-mechanical polishing (CMP) tool, and a deposition tool.

[0097] Each of the above system embodiments may be further configured according to any other embodiment described herein.

[0098] Another embodiment relates to a computer-implemented method for determining information about an analyte. The method includes directing light generated by a light source toward the analyte. The method also includes detecting the light from the analyte with an image sensor. The image sensor is configured as further described herein. For example, the light from the analyte is incident on a photosensitive area of ​​a silicon layer of the image sensor. The method further includes determining the information about the analyte based on an output generated by an output circuit of the image sensor.

[0099] Each of the method steps may be performed as further described herein. The method may also include any other steps that may be performed by a system described herein. The method steps may be performed by a system described herein, which may be configured according to any of the embodiments described herein.

[0100] An additional embodiment relates to a non-transitory computer-readable medium storing program instructions executable on a computer system for performing a computer-implemented method for determining information about an analyte. One such embodiment is shown in Figure 7. In particular, as shown in Figure 7, a non-transitory computer-readable medium 700 includes program instructions 702 executable on a computer system 704. The computer-implemented method may include any step of any of the methods described herein.

[0101] Program instructions 702 implementing methods such as those described herein may be stored on a computer-readable medium 700. The computer-readable medium may be a storage medium such as a magnetic or optical disk, magnetic tape, or any other suitable non-transitory computer-readable medium known in the art.

[0102] The program instructions may be implemented in any of a variety of ways, including procedure-based techniques, component-based techniques, and / or object-oriented techniques, among others. For example, the program instructions may be implemented using ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes ("MFC"), SSE (Streaming SIMD Extensions), or other techniques or ways, as desired.

[0103] The computer system 704 may be configured according to any of the embodiments described herein.

[0104] While the VCVFD structure is particularly suitable for use in light-based systems such as those described above, it may also be an exemplary sensing node for sensors configured for other applications, such as electronic sensors or x-ray sensors. For example, the VCVFD structure may be incorporated into electronic sensor pixels and electronic sensors such as those described below.

[0105] The resistive gate in the individual electronic sensor pixels described below is one important difference from conventional CMOS image sensor pixels. Electronic sensor pixels are photosensitive (unless an opaque coating is applied), but their relatively large size means they are not useful in light-based inspection systems. The electric field created by the resistive gate (when an appropriate operating voltage is applied) allows the pixels to be relatively large while also being reasonably fast (approximately 100 MHz readout rate). Otherwise, the drift time of electrons from one corner of the pixel to the sensing node may become too long for high-speed operation.

[0106] For electronic sensor applications, for example, for sensors incorporated into electron beam systems similar to that shown in Figure 8 (described below), the sensor may be configured to detect electrons or x-rays. For inspection systems that use light, there are typically few incident signal electrons or x-ray photons per unit time, but each incident electron or x-ray photon generates many (typically tens to thousands) electron-hole pairs when absorbed in silicon.

[0107] In one mode, individual arriving high-energy electrons (e.g., above about 1 keV in energy) or X-ray photons (with energies from a few hundred eV to roughly 20 keV-30 keV) are counted, their energies being determined (approximately) from the number of electron-hole pairs created (i.e., the collected signal). In this mode, the floating diffusion capacitance is preferably relatively small, ideally on the order of a few femtofarads (fF), allowing a substantially small signal to be measured with minimal noise.

[0108] In another mode, signals from secondary electrons (typically 20 keV to 50 keV in energy) are collected. Although secondary electrons are more numerous than higher energy electrons and X-ray photons, they generate only about 10 or fewer electron-hole pairs per incident electron. Depending on the mode of operation, a higher floating diffusion capacitance may be preferable when a relatively large signal is detected. The VCVFD allows the floating diffusion capacitance to be changed depending on the system operating mode.

[0109] In one embodiment of an electronic sensor pixel, the pixel includes a silicon layer including an n-type buried channel layer forming a first surface of the silicon layer and a p-type electron-sensitive layer disposed between the buried channel layer and an opposing second surface of the silicon layer, each of which may be configured as described below.

[0110] The silicon layer also includes a floating diffusion disposed in the buried channel layer adjacent to the central region of the pixel. The floating diffusion includes a sensing node formed by a VCVFD structure. The VCVFD structure includes a VCVFD source region and a VCVFD channel region. The VCVFD source region is connected to the pixel's channel and output circuitry. The VCVFD structure also includes a VCVFD gate electrode adjacent to the VCVFD source region and configured to control the variable capacitance of the VCVFD structure via a voltage applied to the VCVFD gate electrode through an electrical connection to the VCVFD gate electrode. The VCVFD structure is configured to convert charge corresponding to electrons in the n-type buried channel layer migrating toward the floating diffusion into a voltage proportional to the amount of charge and dependent on the variable capacitance. This VCVFD structure is further described herein and may be configured, for example, as shown in Figures 1A, 1B, 2A, and 2B. The VCVFD structure may be connected to the pixel as shown in Figure 4. In addition, the VCVFD structure may be formed into a floating diffusion FD as shown in Figures 10A, 10B, and 11A.

[0111] The electronic sensor pixel also includes at least one gate structure disposed on the first surface, the resistive gate being configured such that an outer periphery of the gate structure substantially coincides with an outer periphery of the buried channel layer. The gate structure defines a central opening such that an inner periphery of the gate structure substantially surrounds and is spaced from a central region. The buried channel layer and the p-type electron sensitive layer are configured such that the p-type electron sensitive layer generates a plurality of electrons in response to each incident electron, and the generated plurality of electrons are injected into the buried channel layer. The resistive gate is configured such that when a potential difference applied between the inner and outer peripheries of the gate structure decreases, the resistive gate generates a first electric field that causes electrons in the n-type buried channel layer to move toward the floating diffusion. The electronic sensor pixel may be further configured as described herein. These elements may also be configured as described herein.

[0112] The following description is incorporated herein from commonly owned patent application Brown et al., published March 3, 2016, which is incorporated by reference as if fully set forth herein. The embodiments of electronic sensor pixels, electronic sensors, and electron beam systems described therein are exemplary of the types of pixels, sensors, and systems in which the VCVFD structures described herein may be incorporated. However, it is expressly contemplated that the VCVFD structures described herein may be used in electronic sensor pixels, electronic sensors, and electron beam systems having other configurations known in the art. The embodiments described herein may be further configured as described in the above-referenced patent publications.

[0113] 8 shows an exemplary scanning electron microscope (SEM) 800, also referred to as an inspection or review system, configured to inspect or review a sample 831, such as a semiconductor wafer, reticle, or photomask. SEM 800 generally includes an electron gun (source) 840, electron optics including an upper row 841 and a lower row 842, a stage 830 for supporting and positioning sample 831, and a system computer 860.

[0114] In one embodiment, electron gun 840 includes a cathode 801, such as a thermal field emission or Schottky cathode, a single crystal tungsten cathode, or a LaB6 cathode, and an extraction and focusing electrode 802. Electron gun 840 generates a primary electron beam 850 having a desired beam energy and beam current.

[0115] The upper row of electron optical elements 841 includes one or more focusing lenses 807 that demagnify the primary beam and create a small spot on the sample 831. Typically, a spot size of about 1 to several nanometers is preferred for generating high-resolution images for sample examination. For sample inspection, larger spot sizes may be used to more quickly scan the sample 831. While a single focusing lens 807 may be sufficient when the spot size is about 100 nanometers or larger, two or more focusing lenses are typically required for spot sizes of tens of nanometers or smaller. The focusing lens 807 may include a magnetic lens, an electrostatic lens, or both. The upper row 841 may also include one or more deflection plates 805 that scan the primary electron beam over the area of ​​the sample 831. The deflection plates 805 may be located on either side of the focusing lens 807 as shown, within the focusing lens 807 (not shown), or after the focusing lens 807. The deflection plates 805 may include electrostatic deflection plates or a combination of magnetic and electrostatic deflection plates. In one embodiment, there may be no deflection plates in the upper row 841. Instead, all deflection plates may be included in the lower row 842.

[0116] The lower row 842 includes a final (oil immersion) lens 810 to focus the primary electron beam to a small spot on the sample 831. The final lens 810 may include a magnetic lens (not shown) or a combination of a magnetic lens and an electrostatic lens (not shown). To achieve a small spot size at the sample 831, the final lens 810 is placed close to the sample 831 so that the sample is immersed in the magnetic field of the lens. This can reduce aberrations in the electron spot on the sample 831. The lower row 842 also includes deflection plates 809, which work in combination with deflection plates 805 (if present) to scan the primary electron beam over the area of ​​the sample 831.

[0117] Sample 831 is placed on stage 830 to facilitate movement of different regions of sample 831 under the electron column. Stage 830 may include an XY stage or an R-θ stage and, in one embodiment, is configured to support and position multiple sample types typically inspected in the integrated circuit industry (e.g., unpatterned semiconductor wafers, patterned semiconductor wafers, reticles, or photomasks). In a preferred embodiment, stage 830 is capable of adjusting the height of sample 831 and maintaining focus during inspection. In other embodiments, a focus or height sensor (not shown) may be implemented on or near final lens 810 to adjust the height of sample 831 or to provide a signal for adjusting the focus of final lens 810. In one embodiment, the focus or height sensor may be an optical sensor.

[0118] Secondary and backscattered electrons are emitted from an area of ​​sample 831 as primary electron beam 850 is scanned by electron optics across that area. The secondary electrons may be collected and accelerated by electrode 820 and directed toward secondary electron detector 821. Electron optics for collecting, accelerating, and / or focusing secondary electrons are described in U.S. Patent No. 6,222,297, entitled "Apparatus and Method for E-Beam Dark-Field Imaging," by Masnaghetti et al., which is incorporated herein by reference. As described in the patent, the electron optics for the secondary electron detector may include descanning optics to at least partially counteract the effect of deflection plates 809 on the path of the secondary electrons. In some embodiments of the present invention, descanning electron optics are not required and may be eliminated. This is because descanning can be largely achieved by an ASIC included within the secondary electron detector as described herein. Secondary electron detector 821 is preferably a solid-state electron detector, such as one of the solid-state electron detectors described herein, and is configured to generate image data signals ID2 in response to the detected secondary electrons, where the image data signals ID2 are transmitted to computer 860 and utilized to generate an image of the associated scanned sample area, thereby facilitating visual inspection of defects D. Other electron optics and detector configurations and methods for detecting and analyzing secondary electrons that may be used in combination with the systems and methods described herein are described in patent documents to Lent et al., entitled "Apparatus and method for e-beam dark imaging with perspective control," and to James et al., entitled "Apparatus and method for obtaining topographical dark-field images in a scanning electron microscope," both of which are incorporated herein by reference.

[0119] The backscattered electrons may be detected by a backscattered electron detector, such as those shown at 822a and 822b, which may be implemented by one of the solid-state electron detectors described herein and configured to generate an image data signal ID1 in response to the detected backscattered electrons, which data signal ID1 is also transmitted to computer 860 and utilized to generate an image of the associated scanned sample area. Preferably, the backscattered electron detector is located as close as possible to sample 831, such as at position 822a (i.e., between final lens 810 and sample 831). However, the gap between sample 831 and final lens 810 may be small, such as about 2 mm or less, and clearance for, for example, a focus or height sensor may be required, making it impractical to locate the backscattered electron detector at position 822a. Alternatively, the backscattered electron detector may be located on the opposite side of the pole piece of final lens 810 from sample 831, such as at position 822b. Note that the backscattered electron detector must not block the primary electron beam 850. The backscattered electron detector may have a hole in it or may include multiple detectors (such as two, three, or four separate detectors) positioned around the path of the primary electron beam 850 so as to efficiently capture backscattered electrons while not blocking the path of the primary electron beam 850.

[0120] The incident energy of the primary electron beam 850 on the sample 831 depends on the potential difference between the cathode 801 and the sample 831. In one embodiment, the stage 830 and sample 831 may be held near ground potential, and the incident energy adjusted by changing the potential of the cathode 801. In another embodiment, the incident energy on the sample 831 may be adjusted by changing the potential of the stage 830 and sample 831 with respect to ground. In either embodiment, the final lens 810 and backscattered electron detectors 822a and / or 822b must all be close to each other and at a potential close to the sample 831 and stage 830 (e.g., less than about 1000 V with respect to the sample 831 and stage 830) to avoid arcing with respect to the sample 831. This small potential difference causes backscattered electrons from the sample 831 to be accelerated only slightly or not at all from the sample to the backscattered electron detectors 822a and / or 822b. Because the incident energy on sample 831 can be quite low for some semiconductor samples (e.g., about 500 eV to 2 keV) to avoid damage to those samples, the energy of the backscattered electrons when they strike backscattered electron detectors 822a and / or 822b is quite low. Therefore, it is important for the sensitivity of the SEM that backscattered electron detectors 822a and 822b generate many electron-hole pairs from a single low-energy backscattered electron (e.g., an electron having an energy of about 2 keV or less). Conventional silicon detectors inevitably have a thin oxide coating, such as a native oxide, on the silicon surface, which blocks most electrons with energies less than about 2 keV from reaching the silicon, or alternatively, have a thin metal (e.g., Al) coating on the surface that scatters and absorbs a significant proportion of the incident low-energy electrons. In a preferred embodiment, the solid-state electron detectors described herein have a pinhole-free, high-purity boron coating on their surface. The pinhole-free, high-purity boron coating prevents oxidation of the silicon and allows for efficient detection of low-energy electrons (including electrons with energies less than 1 keV).A method for making a silicon detector with a pinhole-free, high-purity boron coating, and the design of such a detector, is described in patent application Ser. No. 09 / 109,297, filed March 10, 2013, by Chern et al., entitled "Back-Illuminated Sensor With Boron Layer," which is incorporated herein by reference.

[0121] The bubble located in the lower left portion of FIG. 8 represents the incident backscattered or secondary electrons e utilized by one or more of electron detectors 821, 822a, and 822b, all within a single monolithic semiconductor (e.g., epitaxial silicon) structure 824. INCIDENT 827-F. The sensor 823 converts each incident electron e INCIDENT (or X-ray photons) 827 and a p-type electron sensitive layer 827 configured to generate electrons e 825 electrons e that represent at least some of 825 and a charge (voltage) V collected on the floating diffusion FD. FD The buried channel layer 825 is disposed on the upper surface 827-B of the electron sensitive layer 827 and receives the electrons e generated by the electron sensitive layer 827. 827 The floating diffusion FD is located within the buried channel layer 825 to facilitate efficient collection of electrons e 825 and thereby the charge (voltage) V to be measured. FD is the electron e captured by the floating diffusion FD FDAccording to an embodiment of the present invention, the p-type electron sensitive layer 827, the n-type buried channel layer 825, the n+ floating diffusion FD, and the amplifier 829 are collectively fabricated by diffused dopants on the internal semiconductor structure 824, so that the overall incident electron-to-read conversion occurs entirely within the semiconductor structure 824. An optional high-purity boron layer 828 is formed on the bottom surface 827-F of the electron sensitive layer 827 to enhance the conversion of the incident electrons e INCIDENT passes through a high-purity boron layer 828 before impinging on an electron-sensitive layer 827. As described in more detail below, in addition to the sensor 823, each solid-state electron detector includes at least one analog-to-digital converter 826 that converts the output signal OS to digital form for transmission to a computer 860 as a digital image data signal IDx (i.e., signal ID1 in the case of backscattered electron detector 822a or 822b, or signal ID2 in the case of secondary electron detector 821).

[0122] The various circuits and systems of SEM 800 have been briefly described above in simplified form, with it being understood that these circuits and systems may include additional features and perform additional functions. For example, while backscattered electron detector 822a / 822b and secondary electron detector 821 of SEM 800 have been described above as including simplified sensor 823 to briefly introduce certain important features of the present invention, it is understood that backscattered electron detector 822a / 822b and secondary electron detector 821 are preferably implemented using multi-pixel electron detectors, as described below. Also, in addition to generating images of the scanned sample area, computer 860 may be configured to perform additional functions, such as determining the presence and / or type of defects based on incident electron energy values ​​indicated in the image data signals, using methods described below.

[0123] 9 illustrates an exemplary method 900 for inspecting or reviewing a sample, such as a semiconductor wafer, reticle, or photomask. The method illustrated in FIG. 9 may be repeated for each area on the sample to be inspected or reviewed. In a review SEM, the area to be reviewed may have been previously identified by optical or SEM inspection as potentially containing defects or particles.

[0124] For each area on a sample to be inspected or reviewed, the exemplary method 900 begins in step 901. A master clock signal is generated in step 902 and used to control the timing of the scanning of the primary electron beam and the acquisition of image data.

[0125] A beam deflection scan pattern is generated in step 904. This beam deflection scan pattern generates voltages and / or currents that go to beam deflection plates, such as those shown at 805 and 809 in Figure 8. The pattern may be a raster scan, a serpentine pattern, a rectangular spiral, or other pattern that covers an area of ​​the sample. The scan pattern may also include, for example, delays and dummy scans, where no data is collected and to control charging of the sample surface.

[0126] A first pixel clock signal is generated in step 906. The first pixel clock signal is synchronous with the master clock signal. The first pixel clock signal may have the same frequency as the master clock signal, a multiple of the master clock signal, a sub-multiple of the master clock signal (i.e., the master clock signal frequency divided by an integer), or a multiple of the master clock signal frequency.

[0127] In step 908, the signal collected by the backscattered electron detector is read out and digitized for each period of the first pixel clock signal.

[0128] In step 910, a second pixel clock signal is generated that is synchronized with the master clock signal. The second pixel clock signal may be at the same frequency as the master clock signal, a multiple of the master clock signal, a submultiple of the master clock signal (i.e., the master clock signal frequency divided by an integer), or an integer multiple of the master clock signal frequency. The second pixel clock signal may also be at the same frequency as the first pixel clock signal. In one embodiment, the first pixel clock signal is used for both the first and second pixel clock signals, and a separate second pixel clock signal is not generated.

[0129] In step 912, for each period of the second pixel clock signal (or the first pixel clock signal if the second pixel clock signal is not used), the signal collected at the secondary electron detector is read out and digitized.

[0130] In step 914, the digitized backscattered and secondary electron signals are used to determine the presence of one or more defects in the scanned area. Defects may include the presence of material that should not be there (such as particles), the absence of material that should be there (e.g., as can occur with excessive etching conditions), or misshapen patterns.

[0131] In optional step 916, for each defect found in step 914, a defect type or material type of the defect may be determined. For example, high atomic number elements generally scatter a greater percentage of incident electrons than low atomic number elements. The backscattered electron signal may be used to infer the presence or absence of high atomic number elements (such as metals). In step 916, when reviewing the area being previously inspected, previous inspection data (optical and / or e-beam) may be used in combination with the digitized backscattered and secondary electron signals to better determine the defect or material type. In one embodiment, steps 914 and 916 may be combined into a single step that simultaneously determines the presence and type of the defect.

[0132] The method 900 may be repeated from the beginning for each area on the sample that is to be examined or inspected.

[0133] Figure 10A shows an exemplary simplified multi-pixel electron detector 1000 for use in a screening SEM, such as SEM 800 shown in Figure 8, or other SEM system. The electron detector 1000 generally includes a sensor circuit 1010 and a signal processing circuit 1020. In the preferred embodiment shown in Figure 10A, the sensor circuit 1010 is fabricated on a silicon structure (chip) 1011, and the signal processing circuit 1020 is fabricated on a separate silicon structure (chip) 1021, for reasons that will become clear below. In an alternative embodiment (not shown), both the sensor and the signal processing circuit are fabricated on the same silicon chip.

[0134] Referring to the lower portion of Figure 10A, sensor 1010 includes 16 pixels 1015-11 to 1015-44 arranged in an array of four rows and four columns (4x4). For convenience, the "rows" of pixels are aligned along an arbitrarily assigned X-axis direction in Figure 10A, whereby pixels 1015-11 to 1015-14 form a first row, pixels 1015-21 to 1015-24 form a second row, pixels 1015-31 to 1015-34 form a third row, and pixels 1015-41 to 1015-44 form a fourth row. Similarly, the "columns" of pixels are arranged along the Y-axis shown in FIG. 10A, whereby pixels 1015-11 through 1015-41 form a first column, pixels 1015-12 through 1015-42 form a second column, pixels 1015-13 through 1015-43 form a third column, and pixels 1015-14 through 1015-44 form a fourth column. In practical applications, it is expected that the sensor circuit will include arrays of 16x16, 32x32, 64x64, or more pixels, where the pixels in these larger arrays include similar features as the simplified 4x4 array described below. Also, the number of pixels in each row / column of the array need not be a power of two, nor need the number of pixels in each row equal the number of pixels in each column. In one embodiment (e.g., for backscattered electron detector 822a or 822b shown in FIG. 8), sensor 1010 includes a hole (not shown) in the middle of the sensor to allow the primary electron beam to pass through the sensor. Although pixels 1015-11 through 1015-44 are depicted as having a square shape, the pixels may also be rectangular or hexagonal.

[0135] According to an aspect of the invention, each pixel of sensor circuit 1010 includes an electron-sensitive buried channel, floating diffusion, and amplifier circuit structure similar to that described above with reference to FIG. 8. Referring to pixel 1015-41 in FIG. 10A as an example, each pixel generally includes a p-type electron-sensitive region 1012A, an n-type buried channel layer 1016, a floating diffusion FD, and an amplifier 1017. The p-type electron-sensitive region 1012A is formed by a portion of epilayer 1012 underlying pixel 1015-41 and functions in the manner described above with reference to FIG. 8 to generate a plurality of electrons in response to incident electrons. The buried channel layer 1016 is formed by n-type dopant diffusing into epilayer 1012 over electron-sensitive region 1012A and functions to transmit electrons generated by electron-sensitive region 1012A to the floating diffusion FD. The floating diffusion FD, illustrated for convenience using a schematic capacitor symbol, is formed by n+ dopants diffusing into the buried channel layer 1016 and functions to collect at least a portion of the electrons generated by the electron sensitive region 1012A, thereby generating a corresponding charge (voltage) in the manner described above with reference to FIG. 8. The amplifier 1017 includes transistors M1, M2, and M3 and functions to generate an associated output signal OS41, the voltage level of which is determined by the number of electrons collected on the floating diffusion FD in any given read operation. Each pixel also includes a reset transistor RT that functions to reset the voltage level of the pixel floating diffusion FD after each read operation.

[0136] The sensor circuit 1010 is depicted cut away in FIG. 10A to show a preferred embodiment in which pixels 1015-11 through 1015-44 are fabricated on a film structure including an epitaxial (epi) layer 1012 and a boron layer 1013. In one embodiment, the substrate 1011 is a p+ (i.e., heavily p-doped) substrate, and the epi layer 1012 is a p-epi layer (i.e., a layer with a low concentration of p-dopants). Preferably, the thickness T of the epi layer 1012 is between about 40 micrometers (μm) and 100 μm to obtain good mechanical strength while limiting and maintaining the time it takes for electrons to drift from the electron-sensitive region to the buried channel layer to less than about 10 ns. Depending on the mechanical support provided by the substrate 1011, the epi layer 1012 may be thinner than 40 μm, such as between about 10 μm and 40 μm. After the epi layer 1012 is formed, one or more additional layers (not shown) are formed on the epi layer 1012 (e.g., a gate oxide layer, a silicon nitride gate layer, and one or more dielectric layers), and one or more doped regions are formed in the epi layer 1012 (e.g., channel regions associated with the n-type buried channel portion 1016, the n+ floating diffusion FD, the reset transistor RT, and the amplifier 1017, along with doped regions associated with front-side circuit elements (not shown) forming the control circuit 1018, which are located in the peripheral region of the pixel array. Forming the various pixel transistors and front-side circuit elements includes implanting or doping portions of the front side of the epi layer, and may involve patterning the gate layer. Portions of the substrate 1011 disposed beneath the pixels 1015-11 through 1015-44 are then removed (thinned) to expose the electron-sensitive (front) surface 1012-ES, and a boron layer 1013 is formed on the electron-sensitive surface 1012-ES. Additional details regarding the formation of the film structure shown in Figure 10A are described, for example, in commonly owned and co-pending patent application Ser. No. 09 / 029,999, entitled "Back-Illuminated Sensor With Boron Layer," filed March 10, 2013, by Chern et al., which is incorporated herein by reference in its entirety.

[0137] 10B is a simplified diagram showing the example pixel 1015-41 of FIG. 10A in more detail. Specifically, amplifier 1017 includes a first NMOS transistor M1 having a drain terminal connected to a voltage source V, a gate terminal connected to and controlled by the charge stored in the floating diffusion FD, and a source terminal connected to the drain terminal of a second NMOS transistor M2 and the gate terminal of a third NMOS transistor M3. The gate and source terminals of transistor M2 are grounded, and the drain terminal of transistor M3 is connected to voltage source V, such that the output terminal of amplifier 1017 is formed by the source terminal of transistor M3. Pixel 1015-41 also includes an NMOS reset transistor RT having a source terminal connected to the floating diffusion FD, a gate terminal controlled by a reset control signal RG, and a drain terminal connected to a reset voltage RD. During operation of pixel 1015-41, each detection / readout cycle begins by resetting floating diffusion FD to voltage RD via toggling reset transistor RT, then waiting a predetermined detection cycle, and then sampling output signal OS41. If zero incident (i.e., backscattered or secondary) electrons are incident on the electron-sensitive region of pixel 1015-41 during the detection cycle, the voltage levels of floating diffusion FD and output signal OS41 do not change significantly from their reset values ​​at readout. If one or more incident (i.e., backscattered or secondary) electrons are incident on the electron-sensitive region of pixel 1015-41 during the detection cycle, the voltage level on floating diffusion FD changes (becomes more negative) by an amount proportional to the number and energy (in terms of the number of electrons accumulating in floating diffusion FD) of the incident electrons detected during that detection / readout cycle (or the sum of the energies, if multiple electrons are incident during that detection / readout cycle). When operating at a 100 MHz operating speed, 100 million detection / readout cycles are performed per second for each pixel.

[0138] According to a preferred embodiment of the present invention, shown in FIG. 10B, the floating diffusion of each pixel is located in a central region of that pixel, and each pixel has a nominal lateral size dimension of approximately 250 μm or less to facilitate the transfer of electrons to the floating diffusion during each detection / readout cycle. Briefly referring to FIG. 10A, the lateral size dimension is measured in the XY plane parallel to the silicon structure 1011 and indicates the area occupied by each pixel. Referring to FIG. 10B, the floating diffusion FD is located in a central region C (FIG. 11A) of the area occupied by pixel 1015-41, where the width of pixel 1015-41 is indicated by width dimension X1 and the length of pixel 1015-41 is indicated by dimension Y1. According to this preferred embodiment, both dimensions X1 and Y1 are approximately 250 μm or less to facilitate high-speed readout operations. Due to the drift velocity of electrons in silicon, when readout of the pixels 10-41 at data rates of about 100 MHz or greater is desired, the lateral size of each pixel preferably does not exceed about 250 μm, thereby allowing electrons to be shot into the centrally located floating diffusion FD in about 10 nanoseconds (ns) or less. For slower operation, pixels larger than 250 μm may be acceptable. For operation at speeds much faster than 100 MHz, pixel dimensions smaller than 250 μm are preferred.

[0139] 10A , the analog-to-digital converters 1025-11 through 1025-44 are fabricated on a semiconductor substrate 1021 along with an optical signal processing circuit 1028-1 and an optical signal transmission circuit 1028-2, according to known techniques. In one embodiment, to facilitate one-to-one signal connections between the pixels 1015-11 through 1015-44 and the analog-to-digital converters 1025-11 through 1025-44, as described below, the analog-to-digital converters 1025-11 through 1025-44 are arranged in a pattern that generally mirrors the array pattern (matrix) formed by the pixels 1015-11 through 1015-44. The digital values ​​generated by the analog-to-digital converters 1025-11 through 1025-44 are transmitted by conductors 1029 to a processing circuit 1028-1 that is configured to, for example, calculate the approximate energy of the incident electrons based on digitized output signals (image data) received from associated pixels of the sensor circuit. An optional high speed data transmission circuit 1028-2 is utilized, for example, to transmit the image data signal ID to an external processing system (eg, a computer).

[0140] In one embodiment, in addition to the array of analog-to-digital converters 1025-11 through 1025-44, the signal processing circuit 1020 includes a processing circuit 1028-1 configured to calculate the approximate energy of incident electrons based on, for example, digitized output signals (image data) received from associated pixels of the sensor circuit. In another embodiment, the signal processing circuit 1020 also includes a high-speed data transmission circuit 1028-2 for transmitting the image data signal ID to an external processing system (e.g., a computer).

[0141] 10A , each output signal OS11 to OS44 generated by each pixel 1015-11 to 1015-44 is transmitted via an associated conductive path (indicated by a dotted line) to an associated analog-to-digital converter 1025-11 to 1025-44 disposed on the signal processing circuit 1020. For example, pixel 1015-11 transmits output signal OS11 to analog-to-digital converter 1025-11 via a dedicated conductive path, pixel 1015-12 transmits output signal OS12 directly to analog-to-digital converter 1025-12, etc. In a preferred embodiment described below with reference to FIG. 10C , output signals OS11 to OS44 may be transmitted via metal pads, solder balls / bumps, or similar structures that provide a separate signal path between each pixel and its associated analog-to-digital converter.

[0142] As described herein, each pixel has multiple signals or electrical connections, such as gate, control signals, power, and ground. Connecting each of these signals individually to each pixel may result in too high a wiring density for a cost-effective practical assembly. Preferably, most or all of these signals are connected together between adjacent pixels and are provided in convenient locations, such as near the edge of the sensor, where external electrical connections can be made. For example, as shown in FIG. 10A , signals RD, RG, and VOD are transmitted from control circuit area 1018 to pixels in each row via metal conductors (signal lines) 1019. In an actual device, four or more signals may be connected together between pixels, but three signals are shown here to illustrate the principle. External connections for signals such as RD, RG, and VOD may be made with bond wires, solder balls or bumps (discussed below with reference to FIG. 10C ), or other techniques. 10A, to simplify wiring and allow the use of only a single layer of metal, connections between signals may be made primarily or exclusively in one direction, such as the horizontal direction shown. For example, if there is a large enough area outside the active area of ​​the sensor, or two or more layers of metal, the wiring may be easily made in two dimensions where the additional cost can be justified.

[0143] In contrast to the shared signal lines of the sensor circuit 1010, as shown in the upper portion of FIG. 10A, each analog-to-digital converter 1025-11 to 1025-44 of the signal processing circuit 1020 is coupled to the processing circuit 1028-1 via an individual conductor (signal line) 1029 to maximize data transfer and processing.

[0144] FIG. 10C illustrates an exemplary electronic detector 1000A, including an electronic sensor 1010A, an ASIC (signal processing circuit) 1020A, and a substrate 1001. The substrate 1001 provides mechanical support for the electronic detector 1000A and allows for external electrical connections (not shown) to the electronic detector 1000A. The substrate 1001 may comprise silicon or a ceramic material. The electronic sensor 1010A and the ASIC 1020A are fabricated on separate silicon substrates (die or chip), which are then stacked together as shown. Alternatively, the electronic sensor 1010A and the ASIC 1020A may be located on opposite sides of the substrate 1001 or side-by-side on the substrate 1001 (not shown). The electron sensor 1010A is preferably a multi-pixel electron sensor similar to that shown in Figures 10A and 10B, and even more preferably includes pixels such as those described below, for example with reference to Figures 11A and 11B. In operation, the electron detector 1000A is positioned such that the electron sensitive surface 1012-ES faces a sample or other electron source, whereby detected electrons are incident on the electron sensitive surface 1012-ES and detected as described herein.

[0145] The electronic sensor 1010A is electrically connected to the ASIC 1020A by solder balls or bumps 1006. In a preferred embodiment, the output signal generated by each pixel 1015 of the electronic sensor 1010A is transmitted to an associated analog-to-digital converter 1025 of the ASIC 1020A via an associated solder ball / bump 1006. For example, an output signal OS11 generated by a pixel 1015-11 is transmitted via an associated conductor to a first pad 1009 located on the underside of the sensor 1010A, and from the first pad 1009 via an associated solder ball / bump 1006-11 to a second pad located on the ASIC 1020A, from which the output signal OS11 is transmitted to an input terminal of the associated analog-to-digital converter 1025-11. One or more solder balls / bumps 1006 may also be used to transmit signals to the ASIC 1020A (e.g., from circuitry 1028) to the control circuitry 1018 of the sensor 1010A. These balls or bumps also provide mechanical support for and thermal conduction to the electronic sensor 1010A. Alternatively, solder balls or bumps may be used to mount the electronic sensor 1010A directly to the substrate 1001 (not shown). It may also be possible for metal pads to be provided on the electronic sensor 1010A to provide electrical connection to the electronic sensor 1010A, for example, to face 1012-ES of the electronic sensor 1010A, via wire bonds.

[0146] The ASIC 1020A may be mounted directly to the substrate 1001 as shown, or may be mounted and electrically connected to the substrate 1001 by solder balls or bumps (not shown). If the ASIC 1020A includes through-silicon vias, solder balls or bumps may be used on both sides of the ASIC 1020A. Metal pads 1007 and 1027 and / or wire bonds 1039 may be used to make electrical connections between the ASIC 1020A and the substrate 1001. Similar wire bond connections may be made between the sensor 1010A and the substrate 1001, or all connections between the substrate 1001 and the sensor 1010A may be made through the ASIC 1020A. The ASIC 1020A may include a single ASIC or two or more ASICs. For example, in one embodiment, ASIC 1020A may include two ASICs, one ASIC containing primarily analog functions and the other ASIC containing primarily digital functions. Additional integrated circuits, such as a fiber optic transmitter or fiber optic receiver (not shown), may also be implemented on substrate 1001.

[0147] The ASIC 1020A preferably includes an analog-to-digital converter 1025 configured to digitize output signals from the pixels 1015 of the electronic sensor 1010A. In one embodiment, the ASIC 1020A includes one analog-to-digital converter 1025 for each pixel 1015, allowing all pixels 1015 to be digitized in parallel at high speeds, such as at speeds of 100 MHz or greater. At high digitization rates, such as 100 MHz or greater, each analog-to-digital converter 1025 may require 8, 6, or fewer bits because each pixel 1015 detects, at most, a small number of electrons per clock cycle. It is easier to design converters with fewer bits and operate at high speeds. Because analog-to-digital converters with fewer bits occupy a smaller area of ​​silicon, it may be practical to have a large number, such as 1024 or more, on a single ASIC.

[0148] ASIC 1020A preferably implements a portion of the method shown in Figure 9. For example, when electron detector 1000A is used as a backscattered electron detector, ASIC 1020A may implement step 908, or when the electron detector is used as a secondary electron detector, ASIC 1020A may implement step 912. ASIC 1020A may further incorporate circuitry to generate the first pixel clock signal or the second pixel clock signal described in Figure 9, or may receive a pixel clock signal from an external circuit.

[0149] When electron detector 1000A is used as a secondary electron detector, ASIC 1020A may implement secondary electron descanning similar in effect to that implemented by the electron-optical elements in the above-referenced patent application Ser. No. 09 / 149,999. ASIC 1020A may sum signals from groups of pixels corresponding to secondary electrons emitted from the sample over a range of angles and output the sum as a single signal. As the beam deflection changes, ASIC 1020A may sum different groups of pixels under the deflection change that correspond to approximately the same range of angles. Because the same master clock is used to generate or synchronize the beam deflection and generate or synchronize the first and second pixel clocks, ASIC 1020A has the necessary timing information to adjust which groups of pixels to sum in synchronization with the beam deflection scan.

[0150] When the electron current is low and the pixel clock rate is high enough so that the average number of electrons per pixel is much less than one, the charge collected at a single pixel in a single pixel clock period can be used to determine whether an electron was detected at that pixel in that clock period, and if so, the approximate energy of that electron. A boron coating on the electron sensor surface is necessary to enable this capability. Without the boron coating, few or no electrons are produced per incident electron when the incident electron energy is less than about 1 keV. With a boron coating approximately 5 nm thick, approximately 100 electrons are produced for every incident 1 keV electron. Such a signal is detectable above the noise level if the floating diffusion capacitance is small enough to generate more than about 10 microvolts (μV) per electron. In one embodiment, the floating diffusion capacitance is small enough so that the floating diffusion generates more than about 20 μV per electron. For such low level signals, coupling each pixel to its corresponding analog-to-digital converter with as short a path as possible is important to keep noise levels low and stray capacitance low. By attaching the electronic sensors directly to the ASIC, it is possible to make the path from each pixel to its corresponding analog-to-digital converter very short.

[0151] When individual electrons are detectable, ASIC 1020A may use the signal level to determine the approximate energy of the electrons, and ASIC 1020A may further threshold, count, or discard the electrons according to their energy in order to detect or classify one or more types of defects or materials on the sample.

[0152] 11A and 11B are exploded and assembled perspective views, respectively, of a simplified pixel 1100 of an electronic sensor (e.g., sensor 1010 described above with reference to FIG. 10A) according to another exemplary specific embodiment of the present invention. Similar to the pixel described above, pixel 1100 preferably has a size (nominal lateral dimension) of approximately 200 μm to 250 μm.

[0153] Referring to FIG. 11A , similar to the pixel features described above, pixel 1100 includes a p-type electron sensitive layer 1157A, an n-type buried channel layer 1155 disposed on the p-type electron sensitive layer 1157A, an n+ floating diffusion FD formed in the n-type buried channel layer 1155, an amplifier 1110, and an optional high-purity boron layer 1160 disposed below the p-type electron sensitive layer 1157A.

[0154] The buried channel layer 1155 and the electron-sensitive layer 1157A are disposed on the epitaxial silicon layer 1157 such that the top of the buried channel layer 1155 coincides with (forms) the top (first) surface 1157-S1 of the epitaxial silicon layer 1157, and the electron-sensitive layer 1157A comprises a portion of the epitaxial silicon layer 1157 that is disposed between the buried channel layer 1155 and the bottom (electron-sensitive) surface 1157-S2 of the epitaxial silicon layer 1157. The epitaxial silicon layer 1157 preferably has a thickness of about 10 μm to 100 μm and is lightly p-doped to have a resistivity of about 10 to 2000 Ω cm, in one embodiment. Thicker epilayers provide greater mechanical strength but may generate more dark current. Lower doping levels (higher resistivity) may require layers thicker than about 20 μm or 30 μm to maintain a fully depleted state in the bulk of the silicon. Too low a doping level is undesirable as it leads to increased dark current.

[0155] The buried channel layer 1155 is created below the top surface 1157-S1 of the epitaxial silicon layer 1157 by n-type doping diffused using known techniques. The doping concentration of the buried channel layer 1155 should be several orders of magnitude greater than the doping concentration of the epitaxial silicon layer 1157, so that the epitaxial silicon layer 1157 is fully depleted during operation. In a preferred embodiment, the concentration of n-type dopants in the buried channel layer 1155 is about 10 16 ~5×1016 cm -3 is.

[0156] The floating diffusion FD comprises a relatively small n+ doped region disposed in the buried channel layer 1155, which is configured to collect electrons generated in the pixel 1100 in response to incident backscattered or secondary electrons. In one preferred embodiment, the floating diffusion FD has a nominal lateral size of about 1-5 μm, and the concentration of n-type dopants in the floating diffusion FD is about 10 19 ~10 21 cm -3 The connection for transmitting the stored charge to amplifier 1110 is made to the floating diffusion FD using known techniques.

[0157] A high-purity boron layer 1160 is preferably deposited on the back or bottom surface 1157-S2 of the epitaxial silicon layer 1157. The boron layer 1160 is preferably about 2 nm to 10 nm thick. As explained in the patent application by Chern et al., filed March 10, 2013, entitled "Back-Illuminated Sensor With Boron Layer," incorporated by reference above, during the boron deposition process, some boron diffuses into the epitaxial silicon layer 1157 for a few nanometers, forming a thin, highly doped p+ layer adjacent to the high-purity boron layer 1160. This p+ layer is important for optimal operation of the sensor. This p+ layer creates an electric field that directs electrons toward the buried channel 1155, reducing dark current from the backside of the epitaxial silicon layer 1157 and increasing the conductivity of the silicon surface, allowing the sensor to function at low as well as high incident electron currents. In one embodiment, during deposition of the high-purity boron layer 1160, additional boron can be diffused into the silicon. This can be done in one of several ways. In one exemplary method, a layer of boron thicker than the final desired thickness is deposited (e.g., a 6-8 nm layer may be deposited when a final thickness of 5 nm is required), and the boron can be diffused into the silicon epitaxial layer 1157 by holding the sensor at or above the deposition temperature (e.g., about 800° C.-950° C.) for several minutes. In another exemplary embodiment, a layer of boron a few nm thick may be deposited on the silicon, then boron may be driven in at or above the deposition temperature, and then the final desired thickness of boron (e.g., 5 nm) may be deposited.

[0158] According to aspects of this embodiment, the amplifier 1110 is formed in and on an elongated p-well region 1159, which extends vertically from the top surface 1157-S1 into the electron-sensitive layer 1157A and extends outward from a point adjacent the central region C of the pixel (i.e., toward the outer edge 1155-OPE of the n-type buried channel layer 1155). Note that while the p-well region 1159 is shown separate from the silicon epitaxial layer 1157 in FIG. 11A for convenience, it actually comprises a p-type doped region of the silicon epitaxial layer 1157. In alternative embodiments, the p-well 1159 is either contained entirely within the square-shaped peripheral boundary of the pixel 1100 or extends beyond the peripheral boundary (e.g., into an adjacent pixel). In one embodiment, the p-well 1159 is formed by implanting boron at a concentration substantially higher than the dopant concentration in the silicon epitaxial layer 1157, and the n-type channel regions 1112 of the various transistors of the amplifier 1110 are then formed in the p-well 1159, whereby the p-well 1159 serves to prevent electrons from migrating directly from the epitaxial silicon layer into the channel region 1112. In one embodiment, the p-well extends under the floating diffusion and the channel region of the pixel's reset transistor (described below with reference to FIG. 13) and prevents electrons from migrating directly from the epitaxial silicon layer into the floating diffusion.

[0159] 11A, one or more dielectric layers 1154 cover the buried channel. The dielectric layers 1154 may include a single silicon dioxide layer, or a silicon nitride layer on a silicon dioxide layer, or a silicon oxide layer on a silicon nitride layer on a silicon dioxide layer. The thickness of the individual layers may be about 20 nm to 50 nm.

[0160] According to another aspect, pixel 1100 further includes a resistive gate 1151, the gate including one or more polycrystalline or amorphous silicon gate structures 1170 disposed on dielectric layer 1154 and configured to cover a majority of top surface 1157-S1. As shown in FIG. 11A, resistive gate 1151 includes an outer periphery 1151-OPE that substantially coincides with the periphery of pixel 1100 (i.e., generally coincides with the outer periphery 1155-OPE of buried channel layer 1155) and defines a central region 1151-CO such that an inner periphery 1151-IPE (i.e., inner edge of gate structure 1170) of resistive gate 1151 surrounds and is laterally spaced from central pixel region C (e.g., as shown in FIG. 11B). In one embodiment, the gate structure 1170 comprises polycrystalline silicon having a relatively low doping level (e.g., having a resistance greater than about 30 Ω per cm) such that when the potential difference between the inner periphery 1151-IPE and the outer periphery 1151-OPE decreases, the resistive gate 1151 generates an associated electric field that biases electrons in the buried channel layer 1155 toward the central region C of the pixel, in a manner described below with reference to Figures 12A and 12B. To facilitate operation of the resistive gate 1151 such that electrons from all peripheral side areas of the pixel 1100 are biased toward the central region C for collection by the floating diffusion FD, the resistive gate 1151 also includes elongated conductors (e.g., metal wires) 1171 and 1172 disposed on the gate structure 1170 along and adjacent the outer periphery 1151-OPE and inner periphery 1151-IPE, respectively. As explained below, a negative potential, such as a voltage of −5 V, is applied to elongated conductor 1171 relative to elongated conductor 1172. The resulting potential difference between conductors 1171 and 1172 creates a substantially radially decreasing potential in gate structure 1170 (i.e., between inner periphery 1151-IPE and outer periphery 1151-OPE) that directs electrons in the buried channel (see FIG. 11B) toward floating diffusion FD.An additional connection to gate structure 1170 may be provided between conductors 1171 and 1172 and held intermediate the potentials applied to conductors 1171 and 1172 to modify the potential gradient across resistive gate 1151. Additional details regarding the composition of resistive gate 1151 may be found in the document entitled "Inspection System Using BackSide Illuminated Linear Sensor," filed by Armstrong et al. on May 25, 2007, and published as a patent application by Armstrong et al. on March 31, 2011, which is incorporated herein by reference in its entirety.

[0161] According to another aspect, pixel 1100 further includes one or more optional additional gate structures disposed between resistive gate 1151 and floating diffusion FD to further direct electrons onto the floating diffusion FD or to control when electrons are collected / deposited onto the floating diffusion FD. For example, pixel 1100 includes a C-shaped heavily doped polycrystalline gate structure 1153 disposed on dielectric layer 1154 and inside inner periphery 1151-IPE of resistive gate 1151. A constant or switching voltage may be applied to gate structure 1153 to control charge transfer from a portion of buried channel layer 1155 under resistive gate 1151 to floating diffusion FD and ensure efficient charge transfer. 12A and 12B, the gate structure 1153 is used as a summing gate, to which a low voltage such as 0 V (relative to the bottom surface 1157-S2 or the boron layer 1160) is applied during reset and a high voltage such as 10 V is applied during readout. In addition to the summing gate 1153, one or more additional gates, such as a buffer gate, a transfer gate, and an output gate, may be formed by associated additional gate structures interposed between the resistive gate 1151 and the floating diffusion FD. Such gates are well known in CCD technology and may be operated in a similar manner in this electronic sensor. See, for example, "Electronic Devices for CCD Applications," by ...

[0162] FIG. 11B shows a simplified pixel 1100 in a partially assembled state. As shown, most of the pixel 1100 (i.e., most of the top surface 1157-S1) is covered by an amorphous silicon or polysilicon gate structure 1170, which forms the resistive gate 1151. The exposed area above the p-well region 1159 (denoted by the dashed box) is shown as empty for illustrative purposes, but actually contains various connecting structures and gates associated with the transistors forming the amplifier 1110 and the reset transistor RT. An exemplary layout of these structures and gates is described below with reference to FIG. 13. In one embodiment (not shown), the summing gate 1153 overlaps (i.e., extends over and is separated by a suitable insulator, maintaining electrical isolation between) the inner periphery 1151-IPE (see FIG. 11A) of the resistive gate 1151. This overlapping arrangement prevents fringing fields in the silicon below the gap between the two gate structures. These fringing fields can trap electrons in the buried channel or move them in unexpected directions.

[0163] 12A and 12B are simplified cross-sectional views showing pixel 1100 during an exemplary detection / readout period (operation), where FIG. 12A shows the floating diffusion FD reset to a reset voltage (i.e., OS 400 is the reset voltage level V RST 12B shows pixel 1100 at time T0 during or just after the output signal OS 400 When the above method is read (i.e., OS 400 is a voltage level V determined by the number of electrons accumulated on the floating diffusion FD between time T0 and T1. FD 12A and 12B show pixel 1100 at a next time point T1 (when the pixel is equal to 1100). Note that the individual layers shown in Figures 12A and 12B are not drawn to scale and have been greatly exaggerated to show them more clearly.

[0164] Referring to FIG. 12A, the backside surface, coated with high-purity boron layer 1160, is preferably held at a potential similar to the outer edge of the resistive gate (e.g., 0 V in this example). Because boron is conductive and the silicon directly below high-purity boron layer 1160 is heavily doped with boron, the backside surface may be sufficiently conductive so that connecting to it at one or several points provides a sufficiently low impedance path for operation of the sensor at high incident currents, such as currents of approximately 10-50 nanoamperes (nA). The electric field created by these potential differences directs electrons (e.g., E 1160) created in the epitaxial silicon (electron-sensitive) region 1157A by backscattered or secondary electrons entering the sensor through high-purity boron layer 1160 toward the buried channel 1155, as indicated by the arrows on the electrons. A potential difference is applied across resistive gate 1151 between the outer edge of pixel 1100 and the inner edge of gate structure 1170 via conductors 1171 and 1172. In one example, 0 V is applied to the outer edge via conductor 1171 and 5 V is applied to the inner edge via conductor 1172, as shown. The resulting potential difference across gate structure 1170 creates an electric field that drives electrons (such as E1151) located in buried channel 1155 toward the center of pixel 1100 (i.e., moving these electrons toward floating diffusion FD).

[0165] 12A and 12B, summing gate 1153 is used to control electrons and inject them into floating diffusion FD. For example, as shown in FIG. 12A, when electrons are prevented from moving to floating diffusion FD (e.g., during reset), the voltage applied to summing gate 1153 is much lower than that applied to conductor 1172, so that the electric field prevents electrons from easily flowing to floating diffusion FD and deposits them in buried channel 1155 below 1172 (shown as electrons E1151). Conversely, as shown in FIG. 12B, when electrons are moving to floating diffusion FD (e.g., just before readout), summing gate 1153 receives a relatively high positive charge (compared to the voltage applied to conductor 1172, e.g., 10 V compared to 5 V applied to conductor 1172 as shown), causing electrons below conductor 1172, such as E1153, to move toward floating diffusion FD. Since the floating diffusion FD acts as a capacitor, the voltage V on the floating diffusion FD during readout FD becomes more negative as more charges (electrons) are deposited. For small signals, the voltage V FDAlthough the change in is proportional to the deposited charge (i.e., the capacitance of the floating diffusion FD remains substantially constant), as the amount of charge increases, the capacitance change and voltage increase are not linear. While operation in the linear region is generally preferred, in one embodiment, operation in the nonlinear region may be used to compress high dynamic range signals. While sensitivity (charge-to-voltage conversion rate) and speed depend on the capacitance of the floating diffusion FD being small, it is generally preferable to keep the floating diffusion FD as small as possible and minimize the size (and therefore capacitance) of structures connected to the floating diffusion FD, including connections to the channel of the reset transistor and the gate of transistor M1. By implementing the FD as a VCVFD, an appropriate floating diffusion capacitance can be selected with the control voltage applied to the VCVFD as described above, depending on the system operating mode and expected signal levels. In this way, a high dynamic range may be possible using the VCVFD as a means to accommodate both small signals (smallest capacitance) and large signals (higher capacitance depending on adjustment of the VCVFD gate).

[0166] It should be noted that the voltage values ​​referenced in the above examples are merely examples. Different values ​​may be used, with the optimum values ​​depending on a number of factors, including the desired speed of operation of the sensor, the shape of the gate(s), the doping profile, and the thickness of the dielectric layer 1154. It should be noted that it is typically convenient to define the back side (i.e., the electron-sensitive side) of the sensor as 0V (although this voltage may be away from ground if the electron detector is floated at a potential other than ground), and the conductor 1171 is preferably connected to a similar potential.

[0167] In an alternative embodiment, instead of switching the voltages on the reset transistor and various gates of each pixel, the reset transistor and various gates are held at a fixed potential, allowing electrons generated in the epitaxial silicon (electron-sensitive) region 1157A to continuously flow to the floating diffusion FD. In this mode, the voltage on the reset gate RG (FIG. 10B) must be held at a voltage that places the reset transistor RT in a highly resistive and partially conducting state (e.g., a channel resistance of about 500 kΩ to several MΩ), rather than "off" (corresponding to a channel resistance of several hundred MΩ or more) or "on" (corresponding to a channel resistance of a few kΩ or less).

[0168] In this embodiment, the gates between the inner edge of resistive gate 1170 and floating diffusion FD must each be held at successively higher voltages than conductor 1172, which will drive electrons in buried channel 1155 toward floating diffusion FD. For example, if conductor 1172 is at a potential of 5V, summing gate 1153 can be held at a voltage of 6V. If there is another gate (not shown) between the inner edge of resistive gate 1170 and summing gate 1153, the other gate can be held at, for example, 6V and summing gate 1153 can be held at 7V. The reset drain RD (FIG. 10B) must be held at a much more positive voltage than the innermost gates (such as summing gate 1153) to hold floating diffusion FD at a potential sufficiently higher than all of the gates to pull electrons in the buried channel. For example, reset drain RD may be held at 15V.

[0169] As will be readily appreciated, the capacitances of the channel of the reset transistor RT and the floating diffusion FD form an RC time constant, which determines how quickly the voltage on the floating diffusion FD decays to the reset drain RD voltage after electrons arrive at the floating diffusion FD. For example, if the analog-to-digital converter samples each pixel at 100 MHz (i.e., once every 10 ns), an RC time constant of approximately 20 ns or 30 ns may be appropriate. In this example, if the capacitance of the floating diffusion is approximately 10 fF, the reset gate RG voltage should be set so that the resistance of the channel of the reset transistor RT is approximately 2.5 MΩ, giving a time constant of approximately 25 ns.

[0170] This embodiment is possible with the sensors disclosed herein because each pixel is connected to its own analog-to-digital converter. In conventional two-dimensional CCD or CMOS image sensors, when the number of analog-to-digital converters is less than the number of pixels, charge must be stored and continuously read out. Furthermore, conventional CMOS image sensors use transistors and gates with surface channels rather than buried channels. In contrast to buried channels, surface channels generate noise and cannot transfer small charges without loss.

[0171] FIG. 13 is a simplified plan view of a partial pixel 1100A, particularly illustrating an exemplary layout including a floating diffusion FD, amplifier 1110A, and reset transistor RT utilized by pixel 1100A according to certain exemplary embodiments of the present invention. In one embodiment, pixel 1100A is substantially similar to pixel 1100 described above (i.e., the floating diffusion FD is located in a central region of pixel 1100A), and therefore unillustrated portions of pixel 1100A are omitted for clarity. In FIG. 13, doped regions (e.g., floating diffusion FD) are indicated by dotted shaded regions, conductive structures (e.g., polysilicon or metal) are indicated by hatched regions, and vertical metal vias are indicated by boxes containing "X" symbols. Note that the various amplifier polysilicon or metal structures are separate (i.e., non-contiguous) and are patterned and interconnected using standard techniques. In this example, reset transistor RT is located directly below floating diffusion FD, and amplifier 1110A includes transistors M1, M2, and M3 connected and functioning in a manner similar to that described above with reference to Figure 10B. Additional connections and vias associated with the structure shown in Figure 13 are omitted for simplicity.

[0172] 13, floating diffusion FD is disposed adjacent to p-well region 1159A, which is formed in the manner described above and includes various n-type channel regions associated with reset transistor RT and transistors M1-M3 of amplifier 1110A. For example, reset transistor RT includes n-type channel region 1112A disposed in p-well region 1159A directly below and connected to floating diffusion FD and receiving reset voltage RD. RTTransistor M1 includes a gate structure controlled by a reset gate signal RG. Transistor M1 is disposed in a p-well region 1159A directly below reset transistor RT and includes an n-type channel region 1112A including a gate structure connected to floating diffusion FD, a drain structure connected to system voltage VOD, and a source structure connected to the drain structure of transistor M2 and the gate structure of transistor M3. M1 Transistor M2 is located in p-well region 1159A directly below transistor M1 and includes n-type channel region 1112A, which includes gate and source structures connected to ground. M2 Transistor M3 is located in p-well region 1159A directly below transistor M2 and has a drain structure connected to system voltage VOD and provides pixel 1100A's output signal OS to an associated analog-to-digital converter via metal pad or solder ball / bump 1106 in an arrangement similar to that shown and described with reference to FIG. 1100A and a source structure that serves to transmit an n-type channel region 1112A. M3 It should be noted that the metal pad for the OS is located away from the center of pixel 1100A and may, in one embodiment, cover part of one or more adjacent pixels.

[0173] In one embodiment, the reset transistor RT is controlled to discharge the floating diffusion FD to a reset voltage RD using a reset gate voltage RG that is sufficiently positive to turn on the reset transistor RT. RD should be more positive than the voltages applied to the various pixel gates (e.g., the resistive gate 1151 and summing gate 1153 described above with reference to FIGS. 11A and 11B). For example, referring to the example shown in FIG. 12B, where the summing gate 1153 is controlled using 10 V, the reset drain voltage RD may have a voltage value of approximately 15 V to 20 V. The reset transistor RT must be periodically turned on to discharge electrons stored in the floating diffusion FD. When the incident electron current impinging on the pixel is small, it may not be necessary to discharge (reset) the floating diffusion FD each time the pixel is readout. When the incident current is high, the floating diffusion FD may need to be reset every pixel clock period.

[0174] 14 shows a partially simplified exemplary sensor 1400 arranged in accordance with another embodiment of the present invention, illustrating an alternative layout pattern in which p-well region 1459-1 of pixel 1440-1 extends into the space occupied by another adjacent pixel 1440-2, and at least one control signal utilized by pixel 1440-1 is connected to a single line 1419-21 that passes through adjacent pixel 1440-2. The p-well region and signal line described in this example are formed and function in a manner similar to p-well region 1159 and signal line 1019, respectively, described in more detail above with reference to FIGS. Note that metal wire bundles 1419-1 and 1419-2 extend above all other structures, are separated from the underlying polysilicon structures (e.g., resistive gate 1470-1 or resistive gate 1470-2) by a layer of borophosphosilicate glass or other dielectric material, and are connected to the underlying structures through metal vias (not shown). Also, some structures of pixels 1440-1 and 1440-2 are omitted from FIG. 14 for simplicity and clarity.

[0175] As previously mentioned, the amorphous or polycrystalline gate structure utilized to create the resistive gate (and any additional gates, such as the aforementioned summing gate 1153) in each pixel essentially covers the entire pixel area except for the central region (i.e., to allow access to the floating diffusion) and the area where the p-well is formed. In the example described above with reference to Figures 11A and 11B, the p-well region 1159 is located entirely within the square-shaped boundary of each pixel, such that the resistive and summing gates extend entirely around the remaining perimeter of the pixel 1100. However, in some cases, the M3 amplifier transistor may require a width that extends beyond the boundary of the pixel below it.

[0176] To accommodate the extended M3 transistor shape, the pixels of sensor 1400 are configured to share a portion of their space with adjacent pixels. Specifically, resistive gate structure 1470-1 of pixel 1440-1 is formed in a generally "H" shaped pattern to provide space for both its own elongated p-well region 1459-1 and the portion of p-well region 1459-0 extending downward from the previous pixel (not shown). Similarly, resistive gate structure 1470-2 of pixel 1440-2 is formed in the same "H" shaped pattern to accommodate the lower portion of p-well 1459-1 and the upper portion of p-well region 1459-2.

[0177] As previously mentioned, the pixels in each row of sensor 1400 share common signal lines that extend along the entire row to peripherally located control circuitry (not shown). In the case shown in FIG. 14, signal line bundle 1419-1 spans the row containing pixel 1440-1, and signal line bundle 1419-2 spans the row containing pixel 1440-2. Due to the extension of p-well regions to adjacent pixels, it may be efficient in some cases to provide signal connections from the signal line bundles that span adjacent pixels. For example, signal line 1419-21 is connected via conductor 1419-21A to a transistor structure (not shown) located in p-well region 1459-1, thereby providing a signal (e.g., 0V / ground) to pixel 1440-1 from signal bundle 1419-2 that spans adjacent pixel 1440-2. Similarly, signal line 1419-11 of signal bundle 1419-1 provides a signal to a transistor structure (not shown) located in p-well region 1459-0.

[0178] Figure 14 also shows preferred locations for solder bumps / balls 1406-1 and 1406-2 in pixels 1440-1 and 1440-2 (i.e., the bottom left quarter of each pixel area). Note that the illustrated sizes of solder bumps / balls 1406-1 and 1406-2 in pixels 1440-1 and 1440-2 are generally accurate for a nominal lateral (e.g., diagonal) pixel size of 250 μm and standard solder bumps / balls. In alternative embodiments with different sized pixels or different sized solder balls or bumps, the relative sizes of the pads and pixels may vary significantly from those shown in Figure 14.

[0179] The electron detectors described herein in embodiments may also detect X-rays: if the X-rays emitted by the sample have sufficient energy, such as an energy of about 1 keV or greater, they may be sufficient to generate electrons that are detected when absorbed in the electron sensor.

[0180] The systems and methods described herein may be used with any of the systems and methods described in patent application Ser. No. 09 / 020097, filed by Jiang et al., entitled "Tilt-Imaging Scanning Electron Microscope," filed by Jiang et al., on Mar. 18, 2013; patent application Ser. No. 09 / 020097, filed by Neill et al., entitled "Auger Elemental Identification Algorithm," filed by Neill et al., on Jun. 7, 2013; patent application Ser. No. 09 / 020097, filed by Shadman et al., entitled "Charged-particle energy analyzer," filed by Shadman et al., on Mar. 17, 2011; and patent application Ser. No. 09 / 020097, filed by Abbott et al., entitled "Use of design information and defect image information in defect classification," all of which are incorporated herein by reference.

[0181] In one embodiment, the electronic sensor pixel includes a boron layer disposed on the second surface of the epitaxial silicon layer. For example, in an embodiment in which the floating diffusion (FD) is implemented using a VCVFD structure, the sensor may also include a boron coating (such as boron coating 1160 shown in FIGS. 11A and 11B), which may be important for electron detectors as well as DUV, VUV, and EUV detectors. In another embodiment, the electronic sensor pixel includes a beryllium coating disposed on the second surface of the epitaxial silicon layer to block most electrons from reaching the epitaxial silicon layer while allowing most X-rays to reach the layer. In an additional embodiment, the electronic sensor pixel includes a thin foil disposed in front of the second surface of the epitaxial silicon layer. For example, a beryllium coating or thin foil in front of the sensor (in this context, "thin" may be defined as a thickness of approximately 5 μm to 100 μm) may be effective for blocking electrons in X-ray detectors. In some such embodiments, the boron coating 1160 shown in FIGS. 11A and 11B may instead be replaced with a beryllium coating or thin foil, or a beryllium coating or thin foil may be used in addition to the boron coating 1160.

[0182] Embodiments of the electronic sensor pixel, electronic sensor, and electron beam system may be further configured as described herein. For example, in one embodiment, the silicon layer is a silicon epitaxial layer. In one such embodiment, the silicon epitaxial layer is 10 14 cm -3 It comprises intrinsic or p-type doped silicon with a dopant concentration of less than 1000 .mu.m.

[0183] In another embodiment of the electronic sensor pixel in which the floating diffusion (FD) is implemented as a VCVFD, the VCVFD source region and the n-type buried channel layer are doped with the same polarity, and the VCVFD source region has a dopant concentration equal to or greater than the dopant concentration in the n-type buried channel layer. In some embodiments, the VCVFD source region is connected to a charge reset structure. In further embodiments, the VCVFD channel region and the n-type buried channel layer are doped with the same polarity. In an additional embodiment, the silicon layer is a silicon epitaxial layer, and the p-type electron sensitive layer has a dopant concentration at least 10 times higher than the dopant concentration of the silicon epitaxial layer.

[0184] In some embodiments, the electronic sensor pixel is one of a plurality of electronic sensor pixels arranged in a two-dimensional array of pixels in an image sensor. Such an array of pixels may be arranged as shown in Figures 6A, 6B, and 6C, where instead of the VCVFD being located at one end of a column of pixels, each pixel may include its own VCVFD structure, as further described above.

[0185] Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art from this description. For example, an image sensor, a system including an image sensor, and a method for determining information about an analyte are provided. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the invention. It is understood that the form of the invention shown and described herein is the preferred embodiment; elements and materials may be substituted for those shown and described herein, parts and processes may be reversed, and certain features of the invention may be utilized independently, all as would become apparent to one skilled in the art after having the benefit of this description of the invention. Changes may be made to the elements described herein without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

1. 1. An image sensor, comprising: a silicon layer configured to generate electron-hole pairs when light is incident on a photosensitive area of ​​the silicon layer; a circuit formed on a first side of the silicon layer, the circuit having a channel and a first gate electrode configured to control electron accumulation in the channel in response to generation of the electron-hole pairs; a sensing node electrically connected to the circuitry and formed on the first side of the silicon layer adjacent to the circuitry outside the photosensitive area, the sensing node being formed by a voltage controlled variable floating diffusion (VCVFD) structure; Equipped with The VCVFD structure is a source region and a channel region, the source region of the VCVFD structure being connected to the channel of the circuit of the image sensor and an output circuit; a second gate electrode adjacent to the source region and configured to control the variable capacitance of the VCVFD structure via a voltage applied to the second gate electrode by an electrical connection to the second gate electrode; and the VCVFD structure is configured to convert a charge responsive to the electron accumulation into a voltage proportional to the amount of the charge and dependent on the variable capacitance; The output circuit is configured to generate an output responsive to the voltage output by the VCVFD structure. An image sensor comprising:

2. 10. The sensor of claim 1, wherein the image sensor is configured as a charge-coupled device.

3. 10. The sensor of claim 1, wherein the image sensor is configured as a back-illuminated charge-coupled device.

4. 10. The sensor of claim 1, wherein the image sensor is configured as a charge coupled device configured to function as a time delay integration sensor.

5. 10. The sensor of claim 1, wherein the circuit is configured as a charge coupled device circuit.

6. 10. The sensor of claim 1, wherein the circuit is configured as a metal oxide semiconductor field effect transistor (MOSFET).

7. 2. The sensor of claim 1, wherein the silicon layer is a silicon epitaxial layer.

8. The silicon layer is a silicon epitaxial layer, and the silicon epitaxial layer is １４ cm －３ 2. The sensor of claim 1, comprising intrinsic or p-type doped silicon with a dopant concentration of less than 1000 .mu.m.

9. 10. The sensor of claim 1, wherein the channel of the circuit comprises an n-type doped buried channel.

10. 2. The sensor of claim 1, wherein the source region of the VCVFD structure and the channel of the circuit are doped with the same polarity, and the source region of the VCVFD structure has a dopant concentration equal to or greater than a dopant concentration in the channel of the circuit.

11. 2. The sensor of claim 1, wherein the source region of the VCVFD structure is further connected to a charge reset structure in the image sensor.

12. 2. The sensor of claim 1, wherein the channel region of the VCVFD structure and the channel of the circuit are doped with the same polarity.

13. 2. The sensor of claim 1, wherein the silicon layer is a silicon epitaxial layer, and the image sensor further comprises a thin p-type layer having a dopant concentration at least 10 times higher than a dopant concentration of the silicon epitaxial layer, the thin p-type layer being disposed on a second side of the silicon epitaxial layer opposite the first side.

14. 10. The sensor of claim 1, wherein the image sensor further comprises an anti-reflective layer disposed on a second side of the silicon layer opposite the first side.

15. 10. The sensor of claim 1, wherein the circuit is configured as a two-dimensional array of pixels.

16. 2. The sensor of claim 1, wherein the circuit is configured as a plurality of columns of pixels, including at least first and second columns of pixels, the at least first and second columns of pixels including one or more pixels, the sensing node being one of a plurality of sensing nodes in the image sensor, the plurality of sensing nodes including at least first and second sensing nodes, the first and second sensing nodes being electrically connected to all of the one or more pixels in the first and second columns of pixels, respectively.

17. 2. The sensor of claim 1, wherein the circuit is configured as a plurality of columns of pixels, including at least first and second columns of pixels, the at least first and second columns of pixels including one or more pixels, and the sensing node is electrically connected to the one or more pixels in the first and second columns of pixels.

18. 2. The sensor of claim 1, wherein the channel region of the VCVFD structure is configured as an n-type buried channel.

19. The sensor of claim 1 , wherein the channel region of the VCVFD structure is configured as an n-type surface channel.

20. 10. The sensor of claim 1, wherein the VCVFD structure further includes a drain region connected to the channel region of the VCVFD structure, the source region and the drain region of the VCVFD structure being electrically connected.

21. 2. The sensor of claim 1, wherein the circuit is configured as a pixel including at least first and second pixels, the sensing node is electrically connected to the first and second pixels, and the image sensor or computer subsystem is configured to calibrate the first and second pixels by calibrating the sensing node.

22. 10. The sensor of claim 1, wherein the image sensor is located in an inspection system such that the light incident on the photosensitive area is light from a specimen being inspected by the inspection system, and the inspection system is configured to detect defects on the specimen based on the output generated by the output circuitry of the image sensor.

23. 1. A system configured to determine information about a specimen, comprising: an illumination subsystem configured to direct light generated by the light source toward the specimen; an image sensor positioned in a path of light from the specimen, a silicon layer configured to generate electron-hole pairs when the light from the specimen is incident on a photosensitive area of ​​the silicon layer; a circuit formed on a first side of the silicon layer, the circuit including a channel and a first gate electrode configured to control electron accumulation in the channel in response to generation of the electron-hole pairs; a sensing node electrically connected to the circuitry and formed on the first side of the silicon layer adjacent to the circuitry outside the photosensitive area, the sensing node being formed by a voltage controlled variable floating diffusion (VCVFD) structure; and The VCVFD structure is a source region and a channel region, the source region of the VCVFD structure being connected to the channel of the circuit of the image sensor and an output circuit; a second gate electrode adjacent to the source region and configured to control the variable capacitance of the VCVFD structure via a voltage applied to the second gate electrode by an electrical connection to the second gate electrode; Including, the VCVFD structure is configured to convert a charge responsive to the electron accumulation into a voltage proportional to the amount of the charge and dependent on the variable capacitance; the output circuit is configured to generate an output responsive to the voltage output by the VCVFD structure. an image sensor; a computer subsystem configured to determine information about the analyte based on the output; and A system comprising:

24. 24. The system of claim 23, wherein the system is further configured as an inspection system, and the information about the specimen includes information about defects detected on the specimen based on the output.

25. An electronic sensor pixel, a silicon layer, an n-type buried channel layer forming a first surface of the silicon layer; a p-type electron-sensitive layer disposed between the buried channel layer and the opposing second surface of the silicon layer; A floating diffusion disposed in the buried channel layer adjacent to a central region of the pixel, the floating diffusion including a sensing node formed by a voltage-controlled variable floating diffusion (VCVFD) structure, the VCVFD structure comprising: a VCVFD source region and a VCVFD channel region, the VCVFD source region being connected to the channel of the pixel and an output circuit of the pixel; a VCVFD gate electrode adjacent to the VCVFD source region and configured to control the variable capacitance of the VCVFD structure via a voltage applied to the VCVFD gate electrode by an electrical connection to the VCVFD gate electrode; Including, The VCVFD structure is configured to convert a charge responsive to electrons in the n-type buried channel layer moving toward the floating diffusion into a voltage proportional to the amount of the charge and dependent on the variable capacitance. Floating diffusion and a silicon layer having a resistive gate having at least one gate structure disposed on the first surface, the gate structure having an outer periphery configured to substantially coincide with an outer periphery of the buried channel layer, the gate structure defining a central opening such that an inner periphery of the gate structure substantially surrounds and is spaced from the central region; Equipped with the buried channel layer and the p-type electron sensitive layer are configured such that the p-type electron sensitive layer generates a plurality of electrons in response to each incident electron or X-ray photon, and the generated electrons are implanted into the buried channel layer; The resistive gate is configured such that when a potential difference between an inner periphery and an outer periphery of the gate structure decreases, the resistive gate generates a first electric field that causes electrons in the n-type buried channel layer to move toward the floating diffusion. An electronic sensor pixel comprising:

26. 26. The electronic sensor pixel of claim 25, further comprising a boron layer disposed on the second surface of the epitaxial silicon layer.

27. 26. The electronic sensor pixel of claim 25, further comprising a beryllium coating disposed on the second surface of the epitaxial silicon layer.

28. 26. The electronic sensor pixel of claim 25, further comprising a thin foil disposed in front of the second surface of the epitaxial silicon layer.

29. 26. The electronic sensor pixel of claim 25, wherein the silicon layer is a silicon epitaxial layer.

30. The silicon layer is a silicon epitaxial layer, and the silicon epitaxial layer is １４ cm －３ 26. The electronic sensor pixel of claim 25, characterized in that it comprises intrinsic or p-type doped silicon with a dopant concentration of less than .

31. 26. The electronic sensor pixel of claim 25, wherein the VCVFD source region and the n-type buried channel layer are doped with the same polarity, and the VCVFD source region has a dopant concentration equal to or greater than a dopant concentration in the n-type buried channel layer.

32. 26. The electronic sensor pixel of claim 25, wherein the VCVFD source region is further connected to a charge reset structure.

33. 26. The electronic sensor pixel of claim 25, wherein the VCVFD channel region and the n-type buried channel are doped with the same polarity.

34. 26. The electronic sensor pixel of claim 25, wherein the silicon layer is a silicon epitaxial layer, and the p-type electron sensitive layer has a dopant concentration that is at least 10 times higher than a dopant concentration of the silicon epitaxial layer.

35. 26. The electronic sensor pixel of claim 25, wherein the electronic sensor pixel is one of a plurality of electronic sensor pixels arranged in a two-dimensional array of pixels in an image sensor.

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