Structure including a surface layer attached to a carrier with a contamination-limited charge trapping layer and its manufacturing method - Patent Application 20070122997

Abstract

The device comprises a ferroelectric surface layer (20) containing lithium, a dielectric layer (16) comprising an oxide and disposed in contact with the ferroelectric surface layer, and a substrate (10) in contact with the dielectric layer, the substrate including a charge trapping layer (14) disposed on a carrier (12), the charge trapping layer (14) being disposed between the carrier (12) and the dielectric layer (16), the dielectric layer (16) having a thickness of 150 nm to 500 nm, preferably 150 nm to 300 nm, the concentration of nitrogen in the dielectric layer (16) and the surface roughness of the charge trapping layer (14) being such that the charge trapping layer (14) is 5.10 11 at / cm 2 The device has a dose of lithium less than

Description

[Technical Field]

[0001] The present invention relates to a structure comprising a surface layer attached to a carrier with a charge trapping layer, which structure is capable of limiting contamination of the charge trapping layer by contaminants. The invention extends to a method for manufacturing this structure. [Background technology]

[0002] Integrated devices are usually produced on substrates in the form of wafers, which primarily serve as a support for their fabrication. However, the increasing integration and expected performance of these devices leads to an increasingly tight coupling between their performance and the characteristics of the substrate on which they are formed. This is especially the case for radio frequency (RF) devices, which process signals with frequencies between approximately 3 kHz and 300 GHz and are used in particular in the telecommunications sector (telephones, Wi-Fi, Bluetooth, etc.).

[0003] As an example of device / substrate coupling, the electromagnetic fields generated by a high-frequency signal propagating through a device penetrate the bulk of the substrate and interact with any charge carriers found there, leading to insertion loss, which unnecessarily dissipates some of the signal's power, and potentially crosstalk between components.

[0004] Thus, a high-resistivity silicon-on-insulator (HR SOI) substrate is known, comprising a carrier substrate made of silicon with a resistivity greater than 1 kΩ·cm, a dielectric layer on the carrier substrate, and a silicon surface layer disposed on the dielectric layer. The carrier substrate may also include a charge trapping layer disposed near, and preferably in contact with, the dielectric layer. The trapping layer may comprise undoped polycrystalline silicon. The manufacture of this type of substrate is described, for example, in the literature, FR 2860341, FR 2933233, FR 2953640, U.S. Patent No. 2015115480, U.S. Patent No. 7268060, U.S. Patent No. 6544656, or WO 20211008742.

[0005] Surface acoustic wave (SAW) devices are also known, having a composite structure that integrates a surface layer of ferroelectric material with a charge trapping layer to form a substrate similar to that described in the previous paragraph, as detailed in, for example, the document WO 2020 / 200986. These devices are used in a variety of applications, particularly in electronics applications, where they form the central element of filters, oscillators, delay lines, or transformers.

[0006] When an alternating current electrical signal is applied to a transducer formed from one or more electrodes in contact with a ferroelectric material, a corresponding mechanical signal (i.e., oscillation or vibration) is generated within the material in addition to radio waves as described above, and the electrical signal is converted into a mechanical signal that has a frequency dependence relative to the alternating current electrical signal, which dependence depends on other factors, including the properties of the one or more electrodes, the properties of the ferroelectric material, and the properties of the semiconductor carrier of the device.

[0007] However, acoustic wave devices take advantage of this dependency to provide one or more functions that depend on the frequency and therefore on the properties of the carrier. A dielectric layer inserted between the ferroelectric layer and its carrier allows improving the mechanical behavior of the transducer, more specifically limiting the occurrence of parasitic responses, inductive losses related to the properties of the substrate, and interface effects within the stack. Increasing the operating frequency may require a thinner dielectric layer for purely mechanical reasons.

[0008] The problem is the same whether considering a semiconductor substrate or a ferroelectric substrate: a charge trapping layer, by trapping possible charge carriers, limits their interaction with the electromagnetic fields generated by high frequency signals emanating from devices formed on the substrate, allowing these devices to achieve high levels of performance.

[0009] Nevertheless, a continuing trend in the development of these devices is to employ ever higher operating frequencies, which require thinner and thinner dielectric layers interposed between the surface layer and the trapping layer.

[0010] However, thinning the dielectric layer helps contaminating species (e.g., hydrogen originally contained in the surface layer or introduced during device fabrication, or lithium in the case of ferroelectric surface layers made of lithium niobate or lithium tantalate) to diffuse towards the charge trapping layer.

[0011] When they diffuse through the dielectric layer, these contaminating species occupy charge trapping sites in the trapping layer, reducing the efficiency of the trapping layer and impairing the overall performance of the device. Summary of the Invention

[0012] The object of the present invention is to at least partially address the problem of contamination of the charge trapping layer, which is exacerbated by the thinness of the dielectric layer, and more particularly to propose a structure comprising a surface layer attached to a carrier with a charge trapping layer that limits contamination of the charge trapping layer, and a method for manufacturing such a structure.

[0013] To this end, the subject of the present invention is a device comprising a ferroelectric surface layer containing lithium, a dielectric layer comprising an oxide and arranged in contact with the ferroelectric surface layer, and a substrate in contact with the dielectric layer, the substrate comprising a charge trapping layer arranged on a carrier, the charge trapping layer being arranged between the carrier and the dielectric layer, the dielectric layer having a thickness of 150 nm to 500 nm, preferably 150 nm to 300 nm, wherein the concentration of nitrogen in the dielectric layer and the surface roughness of the charge trapping layer are such that the charge trapping layer is 5.10 11 at / cm 2 The device has an amount of lithium less than

[0014] An advantage of the structure according to the invention is that it maintains the efficiency of the trapping function of the charge trapping layer even when the dielectric layer separating it from the surface layer is thinned, while preventing said charge trapping layer from being contaminated by chemical species, in particular hydrogen and lithium present in the surface layer, which tend to passivate the charge trap sites.

[0015] The structure according to the invention therefore makes it possible to provide a substrate with a piezoelectric layer, with the aim of manufacturing components designed to operate at high frequencies and exhibiting excellent performance.

[0016] According to other non-limiting features of the first aspect of the present invention, considered individually or in any technically feasible combination: - The nitrogen concentration in the dielectric layer is 5.10 20 at / cm 3 ~10 22 at / cm 3and the surface roughness of the trapping layer may be less than 800 nm, preferably less than 400 nm, and even more preferentially less than 100 nm in peak-to-valley measurement; The dielectric layer may have a thickness of 150 nm to 250 nm; - The nitrogen concentration in the dielectric layer is 10 21 at / cm 3 ~6.10 21 at / cm 3 may be; The dielectric layer may be a silicon oxide layer, and the hydrogen concentration of the dielectric layer may be strictly less than the nitrogen concentration of the dielectric layer; The hydrogen concentration of the dielectric layer may be at least one-third of the nitrogen concentration of the dielectric layer; - The hydrogen concentration in the dielectric layer is 10 22 at / cm 3 may be less than; The amount of lithium in the charge trapping layer is 10 11 at / cm 2 may be less than; the ferroelectric surface layer may comprise lithium niobate or lithium tantalate; The charge trapping layer may comprise polycrystalline silicon; The ferroelectric surface layer may be made of a monocrystalline material.

[0017] A second aspect of the present invention is a method for manufacturing a device comprising a ferroelectric layer, the method comprising the steps of: forming a charge trapping layer on a carrier to form a substrate; smoothing an exposed surface of the trapping layer to reduce the roughness of the exposed surface to less than a threshold roughness; forming a dielectric layer having a thickness of 150 nm to 500 nm on at least the smoothed charge trapping layer and optionally on a donor substrate comprising a ferroelectric material; bonding the donor substrate and the substrate together with the dielectric layer; and removing a portion of the donor substrate to form a ferroelectric surface layer, the threshold roughness and the nitrogen concentration in an oxide layer comprised in the dielectric layer being such that the amount of lithium in the charge trapping layer is less than 5.10 at the end of the manufacturing method. 11 at / cm 2 wherein the number of steps is selected to be less than or equal to 1.

[0018] According to non-limiting features of the second aspect of the present invention, considered individually or in any technically feasible combination: - The nitrogen concentration in the dielectric layer is 5.10 20 at / cm 3 ~10 22 at / cm 3 and the surface roughness of the trapping layer may be less than 800 nm, preferably less than 400 nm, and even more preferentially less than 100 nm in peak-to-valley measurement; The smoothing step may include chemical mechanical polishing of the charge trapping layer; The charge trapping layer may comprise polycrystalline silicon; The manufacturing method may include forming a weakened surface by implanting a light chemical species into the donor substrate to define a surface layer, and the step of removing a portion of the donor substrate may include separating the surface layer at the weakened surface. [Brief explanation of the drawings]

[0019] Other features and advantages of the present invention will become apparent from the following detailed description of the invention which refers to the accompanying drawings.

[0020] [Figure 1] 1 shows the structure that is the subject of this specification. [Figure 2] A method for manufacturing the structure shown in FIG. 1 is shown. [Figure 3] 1 shows a schematic diagram of the mechanism for diffusing chemical species in a structure and the concept of peak-valley measurement according to the present invention. [Figure 4] 2 is a graph showing the required oxide thickness for the structure of FIG. 1; DETAILED DESCRIPTION OF THE INVENTION

[0021] FIG. 1 shows a structure 1 including a substrate 10 incorporating a carrier 12 and a charge trapping layer 14 on the carrier, a surface layer 20 disposed on the substrate 10, and a dielectric layer 16 interposed between the surface layer 20 and the substrate 10, preferably in direct contact with the surface layer 20 and the charge trapping layer 14.

[0022] The surface layer 20 is a layer that makes it possible to provide functionality to devices fabricated on or in the structure 1, for example piezoelectric functionality.

[0023] Conventionally, the structure 1 may be in the form of a circular wafer, the diameter of which may be 100, 200, 300 or even 450 mm.

[0024] Thus, as presented in the documents forming the prior art presented in the introduction, structure 1 can be produced in many ways. Very generally, structure 1 may be produced by a manufacturing method involving bonding substrate 10 and a donor substrate, with a dielectric layer 16 inserted between these two elements, followed by a step of removing a portion of the donor substrate to form surface layer 20. The step of removing a portion of the donor substrate may be performed by chemical-mechanical thinning of this substrate. Nevertheless, structure 1 is preferentially produced by applying the Smart Cut™ technology, in which the layer intended to form surface layer 20 is delimited by a weakened plane formed by implantation of light chemical species such as hydrogen into the donor substrate. This layer is then separated from the donor substrate, which is bonded to a carrier via dielectric layer 16, by breaking at the weakened plane, so that surface layer 20 remains fixed to substrate 10 with trapping layer 14 and dielectric layer 16 interposed therebetween.

[0025] Fabrication of such structures results in the introduction of hydrogen into the layer, for example, through hydrogen implantation during the Smart Cut process and through hydrogen generation in bonds interposed between the surface layer and the substrate through the dielectric layer. Furthermore, when the surface layer is a ferroelectric layer containing lithium niobate or lithium titanate, lithium is also present in the layer. These two elements, hydrogen and lithium, can diffuse into the trapping layer and occupy charge trapping sites, thus passivating them and thereby significantly reducing the usefulness of the trapping layer.

[0026] The substrate 10 typically has a thickness of several hundred microns. Preferentially, the substrate has a high resistivity, greater than 1000 ohm-cm, and more preferentially greater than 2000 ohm-cm. This limits the density of charges, i.e., holes or electrons, that tend to move within the substrate. Nevertheless, the present invention is not limited to substrates 10 having such resistivities, and provides RF performance advantages even when the substrate has more typical resistivities on the order of several hundred ohm-cm, e.g., less than 1000 ohm-cm, or less than 500 ohm-cm, or even less than 10 ohm-cm.

[0027] For reasons of availability and cost, the carrier 12 is preferably made of single-crystal silicon. For example, it may be a CZ silicon substrate with a low interstitial oxygen content of 6-10 ppm, or particularly a FZ silicon substrate with a very low interstitial oxygen content. It may also be a CZ silicon substrate with a high interstitial oxygen content (high Oi) of more than 26 ppm. Alternatively, the carrier 12 may be formed from another material, such as sapphire, glass, quartz, or silicon carbide. In certain circumstances, particularly when the trapping layer 14 is sufficiently thick, e.g., greater than 30 microns, the carrier 12 may have a typical resistivity of less than 1 kΩ·cm.

[0028] The trapping layer 14 may be of very different nature, as reported in the literature forming the prior art. Generally, it is an amorphous layer with structural defects, such as dislocations, grain boundaries, amorphous zones, gaps, inclusions, pores, etc. These structural defects form traps for easily flowing charges in the material, for example at the sites of imperfect or pendant chemical bonds. Therefore, conduction in the trapping layer is prevented or limited, and as a result, the trapping layer has a high resistivity.

[0029] Advantageously, for ease of implementation, this trapping layer 14 is formed of a layer of polycrystalline silicon. Its thickness may be comprised between 0.3 and 3 μm, especially when formed on a resistive carrier 12. However, other thicknesses below or above this range are quite possible, depending on the level of RF performance of the structure 1.

[0030] Prior to the deposition of the charge trapping layer 14, it is advantageous to provide an amorphous layer, for example made of silicon dioxide, on the carrier 12 in order to maintain the polycrystalline quality of this layer during any heat treatments that the structure 1 may be subjected to.

[0031] Alternatively, trapping layer 14 may be formed by implanting heavy species such as argon into the surface thickness of support 12 to create structural defects that constitute electrical traps therein. Layer 14 may also be formed by porosifying the surface thickness of support 12.

[0032] The dielectric layer is typically composed of silicon oxide and contains preferentially nitrogen, which is useful for forming a barrier layer to prevent the diffusion of chemical species, particularly the hydrogen and lithium mentioned above.

[0033] The surface layer 20 may be of any suitable nature. It is very preferentially made of a monocrystalline material. If the structure 1 is intended to receive semiconductor integrated components, the surface layer 20 may be made of monocrystalline silicon or any other semiconductor material. In such cases, lithium contamination may originate from the equipment used to manufacture the structure. If the structure 1 is intended to receive a surface acoustic wave filter, the surface layer 20 may be made of a piezoelectric and / or ferroelectric material, such as lithium tantalate or lithium niobate. In this case, in addition to possible external contamination, lithium contamination may also originate from the surface layer itself. The surface layer 20 may also include finished or semi-finished integrated components formed on a donor substrate and attached to the substrate 10 during the process of manufacturing the structure 1. Generally, the thin layer may have a thickness of 10 nm to 10 μm.

[0034] Now, with reference to FIG. 2, a method for manufacturing a structure according to the structure shown in FIG. 1, in which the surface layer 20 is a ferroelectric layer, will be described.

[0035] According to this method, a charge trapping layer 14 made of polycrystalline silicon is formed by depositing it on a carrier 12 made of silicon, for example by LPCVD techniques carried out at 600° C. to 650° C. The trapping layer 14 has a thickness of about 500 nm, or even 1 micron.

[0036] The trapping layer 14 is then polished by a chemical-mechanical polishing (CMP) process, removing approximately 100-200 nanometers from the trapping layer, resulting in a layer with a thickness of 500-1000 nanometers, exhibiting a surface roughness of less than 300 nm, preferentially less than 140 nm, or even more preferentially less than 100 nm, in peak-to-valley measurements. By way of non-limiting example, a peak-to-valley roughness of 800 nm can be obtained with the deposition of a charge trapping layer made of polycrystalline silicon of a few microns (approximately 4 μm). Such roughness can make it possible to avoid parasitic modes present in POI (Piezoelectric-On-Insulator) type structures, in particular those with piezoelectric layer thicknesses greater than the wavelengths used, due to the radiation of these volume modes in the volume and their interaction with interfaces.

[0037] Preferably, to reduce the hydrogen content of the trapping layer, a first annealing of this layer may be performed in a low hydrogen atmosphere (i.e., less than 5 ppm) at a temperature between the deposition temperature and 1000°C. Advantageously, the temperature of the first annealing is above 620°C, preferentially below 900°C, for at least one hour, preferentially several hours. The hydrogen present in the trapping layer 14 can be reduced to a concentration of 10 ppm or less without degrading the polycrystalline character of the trapping layer through recrystallization effects. 18 at / cm 3 , preferably 10 17 at / cm 3 These preferential annealing conditions effectively release the ions below the threshold.

[0038] Deposited on the trapping layer 14, for example by a PECVD technique carried out at a temperature of 600°C to 800°C, is a dielectric layer 16 made of a silicon oxide layer containing nitrogen with a thickness of 300 nm to 1000 nm, which forms the dielectric layer 16 of the structure 1. The layer is then polished, for example by a chemical mechanical polishing (CMP) process, which results in the removal of approximately 200 to 800 nanometers of oxide, to provide a surface that exhibits a roughness of less than 0.3 nm RMS over a 5 x 5 micron field or a 30 x 30 micron field as measured by atomic force microscopy. The dimensions of the measurement field are adjusted by the practitioner to obtain a characteristic that is representative of the layer in question. Here, the dielectric layer 16 has a thickness of 150 nm to 500 nm, preferentially 150 nm to 250 nm, and is 10 20 at / cm 3 , but preferably remains less than the nitrogen concentration in dielectric layer 16.

[0039] To reduce this concentration, a second "densification" anneal, similar to the first anneal described above, may be applied. This is therefore an anneal in a low hydrogen atmosphere (i.e., less than 5 ppm), exposing the dielectric layer 16 to a temperature higher than its deposition temperature. This may be a neutral or oxidizing atmosphere. Preferentially, this temperature is higher than 800°C, typically between 800°C and 900°C. The annealing is continued for at least one hour, and preferentially several hours, to release hydrogen from the dielectric layer 16 and possibly from the trapping layer 14. At the end of this densification anneal, the dielectric layer 16 has a hydrogen content of 10 20 at / cm 3 The trapping layer 14 has a hydrogen concentration of less than 10 18 at / cm 3 Less than 10 17 at / cm 3 The hydrogen concentration is

[0040] The presence of nitrogen in the silicon oxide layer improves its barrier effect with respect to the diffusion of chemical species such as lithium and hydrogen. The applicant has estimated by simulation and confirmed by experiment that a reduction in the roughness of the trapping layer is accompanied by a reduction in the nitrogen content required to obtain a satisfactory barrier effect. Therefore, 5.10 20 at / cm 3 ~10 22 at / cm 3 , preferably 10 21 at / cm 3 ~6.10 21 at / cm 3 This nitrogen concentration, in combination with a trapping layer having a roughness of less than 800 nm, preferentially less than 400 nm and preferentially less than 100 nm in peak-to-valley measurement, makes it possible to obtain a sufficient barrier effect of the dielectric layer in order to manufacture on the substrate thus obtained devices capable of operating at high frequencies. The upper limit of the above range does not constitute an upper limit for the nitrogen concentration in order to obtain a barrier effect, but rather ensures a nitrogen concentration low enough to allow the structure according to the invention to be applied to known devices without the risk of adversely affecting their performance.

[0041] The importance of minimizing roughness in peak-valley measurements is empirically illustrated by Figure 3. Each roughness peak 310 in the trapping layer 14 creates one or more preferred paths (indicated by straight arrows) for migration of chemical species through the dielectric layer 16 due to local thinning of the dielectric layer 16 at these peaks 310. Figure 3 is merely a schematic diagram used for illustration purposes and is in no way an actual representation of the layers in an actual device.

[0042] As shown in Figure 3, the peak-valley measurement consists in measuring the sum Sum of the maximum depth S1 of the depressions (deepest valleys) on the surface Sur in question and the maximum height S2 of the peaks (highest protrusions) on this surface, the depth and height being measured relative to the average height Moy of this surface, for example over a given surface of the sample. In the case of measurements by atomic force microscopy, for example, an observation surface corresponding to a square with sides of 30 μm can be considered, but to verify the peak-valley measurement, a square with sides of 5 μm or more can alternatively be considered.

[0043] The thickness of the oxide layer forming the dielectric layer 16 can be minimized as a function of its nitrogen concentration and the maximum amount of lithium that is considered acceptable in the charge trapping layer. Therefore, the minimum thickness of the oxide layer is estimated as the sum of half the roughness in peak-valley measurement and the minimum oxide thickness, which depends on the nitrogen concentration, and this minimum thickness decreases as the nitrogen concentration increases. The thickness of the dielectric layer 16 is measured between the average depth of the charge trapping layer and the surface of the oxide layer.

[0044] Quantity is understood to mean the amount of atoms of a given chemical species across the thickness of the layer, i.e., the amount contained in the volume defined by the surface given as the surface area of ​​the layer and the projection of this surface perpendicular to the layer. Quantity may be expressed as the number of atoms per unit of surface area of ​​the layer.

[0045] The graph shown in Figure 4 summarizes this situation. The oxide layer thickness Tk, expressed in nanometers, is on the x-axis, and is shown in PV, while the peak-to-valley roughness of the charge trapping layer, expressed in nanometers, is on the y-axis. For this graph, the curves identified by [N]1, [N]2, [N]3, and [N]4 are each approximately 10 20 , 1.10 21 , 3.10 21 , and 10 22 at / cm 3 and 5.10 per square centimeter in the charge trapping layer, respectively. 11It represents the minimum thickness of the oxide layer depending on PV to obtain the maximum allowable amount of lithium fixed in lithium atoms. A value PV of 0 corresponds to a perfectly smooth charge trapping layer, which gives the minimum thickness of oxide to be deposited to sufficiently restrict the diffusion of chemical species, especially lithium, into the layer for a given nitrogen concentration in this layer.

[0046] Preferably, the oxide layer forming the dielectric layer 16 has a ratio of nitrogen to hydrogen concentration that is beneficial for blocking hydrogen diffusion, in which there is an excess of nitrogen relative to the amount of hydrogen, i.e., a ratio of nitrogen to hydrogen concentration strictly greater than 1, preferably greater than 1.5, and even more preferably greater than 3, as measured by SIMS (Secondary Ion Mass Spectroscopy). Thus, the hydrogen concentration in the dielectric layer is preferably about 10 22 at / cm 3 less than, more preferably about 10 21 at / cm 3 less than, and even more preferably about 10 20 at / cm 3 is less than.

[0047] It should be noted that if the dielectric layer 16 is formed on the trapping layer 14 and these two layers are deposited at a relatively low temperature as described above, it is not necessary to apply the first and second annealing processes after each deposition step. After forming the dielectric layer 16 on the trapping layer 14 at a low temperature, one annealing process can be performed under the same conditions as the first and second annealing processes. In other words, in this case, it is not necessary to apply a specific annealing process to the trapping layer 14 before depositing the dielectric layer 16.

[0048] As illustrated by this embodiment, it is generally preferable to dispose the dielectric layer 16 on the carrier 12 (via the trapping layer 14) rather than on the donor substrate 200. This is because the carrier 12 can generally be heat-treated at the temperatures of the first and / or second annealing, which is not necessarily the case for the donor substrate 200. For example, the donor substrate may have a weakened surface or may be composed of or include components of a ferroelectric material with a relatively low Curie temperature, which in each of these cases limits the thermal history that can be applied to the donor substrate to several hundred degrees in a relatively short time of less than an hour. Nevertheless, the present invention does not exclude the possibility that the dielectric layer 16 may be at least partially formed on the donor substrate 200 in certain preferred cases.

[0049] The structure obtained at this stage is shown in Figure 2(a).

[0050] Concurrent with the preparation of the substrate 10, hydrogen ions are implanted into a lithium tantalate ferroelectric donor substrate 200 through a first surface 210 of the substrate to form a buried weakened surface 220. A superficial layer 20 is thus defined between this weakened surface 220, the first surface 210 of the donor substrate, and a complementary layer 22 comprising the remainder of the donor substrate.

[0051] The donor substrate obtained at this stage is shown in FIG. 2(b).

[0052] The donor substrate 200 is bonded to a silicon oxide layer 16 disposed on a carrier 12, as shown in FIG. 2(c), and then the donor substrate 200 is fractured at the weakened surface 220 by a moderate heat treatment at about 400°C. The complementary layer 22 of the donor substrate is released to expose the free surface 230 of this layer, which may then be prepared to improve its crystalline quality and surface condition. This preparation involves thinning the first layer by chemical mechanical polishing and a heat treatment step at 500°C for 1 hour in a neutral atmosphere. The resulting structure, shown in FIG. 2(d), is the structure of FIG. 1.

[0053] Although the above method applies to a ferroelectric layer of lithium tantalate used as the surface layer 20, other types of ferroelectric or piezoelectric materials such as lithium niobate may also be employed. Furthermore, instead of a ferroelectric surface layer, a semiconductor surface layer such as a silicon layer or a semiconductor surface layer that includes silicon such as single crystal silicon may also be employed.

[0054] The fabrication method detailed above therefore makes it possible to obtain a structure in which contamination of the trapping layer by harmful species, in particular hydrogen and lithium, remains sufficiently limited to produce devices that can operate satisfactorily at high frequencies. Specifically, for example, for a sufficiently thick oxide layer disposed directly on the surface of the trapping layer 14 with a roughness of less than 300 nm in peak-to-valley measurements, 5.10 20 at / cm 3 ~10 22 at / cm 3 The nitrogen content of the charge trapping layer 14 is 5.10 11 at / cm 2 The hydrogen concentration is maintained below 10 20 at / cm 3 Less than 10 19 at / cm 3 less than, and even more preferably less than 10 18 at / cm 3 This results in the system being kept below this level.

[0055] Naturally, the invention is not limited to the described embodiments and variations in implementation may be applied thereto without departing from the scope of the invention as defined by the claims.

Claims

1. A device, a ferroelectric surface layer (20) containing lithium, a dielectric layer (16) comprising an oxide and placed in contact with said ferroelectric surface layer; a substrate (10) in contact with said dielectric layer, said substrate comprising a charge trapping layer (14) arranged on a carrier (12), said charge trapping layer (14) being arranged between said carrier (12) and said dielectric layer (16); The device comprises: the dielectric layer (16) has a thickness of 150 nm to 500 nm, preferably 150 nm to 300 nm; The concentration of nitrogen in the dielectric layer (16) and the surface roughness of the charge trapping layer (14) are 5.10 １１ at / cm ２ having an amount of lithium less than The nitrogen concentration of the dielectric layer is 5.10 ２０ at / cm ３ ~10 ２２ at / cm ３ and A device, characterized in that the surface roughness of the trapping layer (14) is less than 800 nm, preferably less than 400 nm, and even more preferentially less than 100 nm, in peak-to-valley measurement.

2. The device of claim 1, wherein the dielectric layer (16) has a thickness of between 150 nm and 250 nm.

3. The nitrogen concentration of the dielectric layer (16) is 10 ２１ at / cm ３ ~6.10 ２１ at / cm ３ 3. The device according to claim 1 or 2, wherein:

4. The device according to any one of claims 1 to 3, wherein the dielectric layer is a silicon oxide layer, and the hydrogen concentration of the dielectric layer (16) is strictly less than the nitrogen concentration of the dielectric layer (16).

5. The device of claim 4, wherein the hydrogen concentration in the dielectric layer (16) is at least one-third of the nitrogen concentration in the dielectric layer (16).

6. The hydrogen concentration in the dielectric layer (16) is 10 ２２ at / cm ３ The device according to any one of claims 1 to 5, wherein the thickness is less than 1 / 2 mm.

7. The amount of lithium in the charge trapping layer (14) is 10 １１ at / cm ２ The device according to any one of claims 1 to 6, wherein the

8. A device according to any one of the preceding claims, wherein the ferroelectric surface layer (20) comprises lithium niobate or lithium tantalate.

9. The device of any one of claims 1 to 8, wherein the charge trapping layer (14) comprises polycrystalline silicon.

10. 10. A device according to any one of the preceding claims, wherein the ferroelectric surface layer (20) is made of a single crystal material.

11. 1. A method for manufacturing a device, comprising: - forming a charge trapping layer (14) on a carrier (12) to form a substrate (10); - smoothing the exposed surface of the trapping layer (14) to reduce the roughness of the exposed surface below a threshold roughness; - forming a dielectric layer (16) having a thickness of 150 nm to 500 nm on at least said smoothed charge trapping layer (14) and optionally on a donor substrate (200) comprising a ferroelectric material containing lithium; - bonding said donor substrate (200) and said substrate (10) by said dielectric layer (16); - removing a portion of the donor substrate to form a lithium-containing ferroelectric surface layer (20), The threshold roughness and the nitrogen concentration of the oxide layer contained in the dielectric layer (16) are determined by the fact that the amount of lithium in the charge trapping layer is 5.10 at the end of the manufacturing method. １１ at / cm ２ is selected to be less than The nitrogen concentration of the dielectric layer is 5.10 ２０ at / cm ３ ~10 ２２ at / cm ３ and A method wherein the surface roughness of said trapping layer (14) is less than 800 nm, preferably less than 400 nm, and even more preferentially less than 100 nm, in peak-to-valley measurement.

12. The method of claim 11 , wherein the smoothing step comprises chemical mechanical polishing of the charge trapping layer (14).

13. The method of claim 11 or 12, wherein the charge trapping layer (14) comprises polycrystalline silicon.

14. 14. The method of claim 11, further comprising forming a weakened surface (220) by implanting light chemical species into the donor substrate (200) to define the surface layer (20), and removing a portion of the donor substrate comprises separating the surface layer (20) at the weakened surface (220).

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