METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A BACKSIDE POWER DISTRIBUTION NETWORK USING A LASER LIFT-OFF LAYER - Patent application

Abstract

A method for manufacturing a semiconductor device is disclosed. The method includes forming a stack on a first substrate. A laser lift-off layer is interposed between the stack and the first substrate. The method includes forming a plurality of first interconnect structures on a first surface of the stack. The method includes attaching a second substrate to the stack on the first surface, the plurality of first interconnect structures being interposed between the stack and the second substrate, and removing the first substrate by applying radiation to the laser lift-off layer. The method includes forming a plurality of second interconnect structures on a second surface of the stack opposite the first surface.

Description

[Technical Field]

[0001] Cross-references to related patents and applications This application claims the benefit of U.S. Non-Provisional Patent Application No. 18 / 104,272, filed January 31, 2023, which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates generally to methods for fabricating semiconductor devices having backside power delivery networks, and particularly to methods for such devices that use laser lift-off layers. [Background technology]

[0003] The semiconductor industry is growing rapidly due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) In most cases, this improvement in integration density has been achieved by iteratively reducing the size of minimum features, allowing more components to be integrated into a given area. Summary of the Invention [Means for solving the problem]

[0004] At least one aspect of the present disclosure is directed to a method for manufacturing a semiconductor device. The method may include forming a stack on a first substrate, where a laser lift-off layer is interposed between the stack and the first substrate, forming a plurality of first interconnect structures on a first side of the stack, attaching a second substrate to the stack on the first side, where the plurality of first interconnect structures are interposed between the stack and the second substrate, applying radiation to the laser lift-off layer to remove the first substrate, and forming a plurality of second interconnect structures on a second side of the stack opposite the first side.

[0005] In some embodiments, at least a portion of the plurality of second interconnect structures operatively function as a power delivery network.

[0006] In some embodiments, the method may further include growing a first semiconductor layer on a third substrate, followed by growing a stack on the first semiconductor layer, and attaching the first substrate to the stack, the laser lift-off layer and the dielectric layer being interposed between the first substrate and the first of the second semiconductor layers.

[0007] In some embodiments, the method may further include removing the third substrate to expose the first semiconductor layer, removing the first semiconductor layer to expose a second one of the second semiconductor layers, and patterning the stack followed by forming a plurality of first interconnect structures. The stack includes a plurality of second semiconductor layers and a plurality of third semiconductor layers alternately stacked on top of each other. The first semiconductor layers include a first concentration of germanium, the second semiconductor layers each include a second concentration of germanium, and the third semiconductor layers each include silicon. The second concentration is substantially lower than the first concentration. The first semiconductor layer serves as an etch stop layer for the step of removing the third substrate, which includes at least a wet etching process.

[0008] In some embodiments, the laser lift-off layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, titanium nitride, metals, and metal oxides.

[0009] At least another aspect of the present disclosure is directed to a method for manufacturing a semiconductor device. The method may include forming a stack on a first substrate, sequentially forming a laser lift-off layer and a dielectric layer on a second substrate, inverting the second substrate and attaching the dielectric layer to a first side of the stack, removing the first substrate from a second side of the stack, the second side being opposite the first side, forming a plurality of device features using the stack, forming a plurality of first interconnect structures on the second side, removing the second substrate through the laser lift-off layer to expose the first side of the stack, and forming a plurality of second interconnect structures on the first side.

[0010] In some embodiments, at least a portion of the plurality of second interconnect structures operatively function as a power delivery network.

[0011] In some embodiments, the method may further include attaching a third substrate to a second side of the stack and inverting the stack followed by removing the second substrate.

[0012] In some embodiments, the method may further include growing a first semiconductor layer between the second surface of the stack and the first substrate. The stack includes a plurality of second semiconductor layers and a plurality of third semiconductor layers alternately stacked on top of each other. The first semiconductor layer includes a first concentration of germanium, the second semiconductor layers each include a second concentration of germanium, and the third semiconductor layers each include silicon. The second concentration is substantially lower than the first concentration. The first semiconductor layer serves as an etch stop layer for the step of removing the first substrate, which includes at least a wet etching process.

[0013] In some embodiments, the laser lift-off layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, titanium nitride, metals, and metal oxides.

[0014] Yet another aspect of the present disclosure may be directed to a method for manufacturing a semiconductor device. The method may include forming a stack on a first substrate, the stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on one another, sequentially forming a laser lift-off layer and a dielectric layer on a second substrate, inverting the second substrate and attaching the dielectric layer to a first side of the stack, removing the first substrate from a second side of the stack opposite the first side, forming a plurality of device features using the stack, forming a plurality of first interconnect structures over the plurality of device features, attaching a third substrate to the second side of the stack, inverting the third substrate together with the second substrate, removing the second substrate by applying radiation to the laser lift-off layer, and forming a plurality of second interconnect structures on the device feature opposite the plurality of first interconnect structures.

[0015] In some embodiments, the laser lift-off layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, titanium nitride, metals, and metal oxides.

[0016] These and other aspects and implementations are described in detail below. The foregoing information and the following detailed description, including illustrative examples of various aspects and implementations, provide an overview or framework for understanding the nature and characteristics of the claimed aspects and implementations. The drawings provide illustrations and a further understanding of the various aspects and implementations, and are incorporated into and constitute a part of this specification. It will be readily understood that multiple aspects can be combined, and that features described in connection with one aspect of the invention can be combined with other aspects. The aspects may be implemented in any convenient form. As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

[0017] Non-limiting embodiments of the present disclosure will now be described, by way of example, with reference to the accompanying drawings, which are schematic and are not intended to be drawn to scale. Unless otherwise indicated as representing background art, the drawings depict aspects of the present disclosure. For clarity, not every component is necessarily labeled in every drawing. [Brief explanation of the drawings]

[0018] [Figure 1] 1 illustrates a flowchart of a method for forming an isolation structure for a transistor structure, according to one embodiment. [Figure 2A] 2A-2C illustrate cross-sectional views of the device during various manufacturing stages of the method of FIG. 1, according to one embodiment. [Figure 2B] 2A-2C illustrate cross-sectional views of the device during various manufacturing stages of the method of FIG. 1, according to one embodiment. [Figure 2C] 2A-2C illustrate cross-sectional views of the device during various manufacturing stages of the method of FIG. 1, according to one embodiment. [Figure 2D] 2A-2C illustrate cross-sectional views of the device during various manufacturing stages of the method of FIG. 1, according to one embodiment. [Figure 2E] 2A-2C illustrate cross-sectional views of the device during various manufacturing stages of the method of FIG. 1, according to one embodiment. [Figure 2F] 2A-2C illustrate cross-sectional views of the device during various manufacturing stages of the method of FIG. 1, according to one embodiment. [Figure 2G] 2A-2C illustrate cross-sectional views of the device during various manufacturing stages of the method of FIG. 1, according to one embodiment. [Figure 2H] 2A-2C illustrate cross-sectional views of the device during various manufacturing stages of the method of FIG. 1, according to one embodiment. [Figure 2I] 2A-2C illustrate cross-sectional views of the device during various manufacturing stages of the method of FIG. 1, according to one embodiment. [Figure 2J] 2A-2C illustrate cross-sectional views of the device during various manufacturing stages of the method of FIG. 1, according to one embodiment. [Figure 2K] 2A-2C illustrate cross-sectional views of the device during various manufacturing stages of the method of FIG. 1, according to one embodiment. [Figure 2L]2A-2C illustrate cross-sectional views of the device during various manufacturing stages of the method of FIG. 1, according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0019] Reference will now be made to the exemplary embodiments illustrated in the drawings, and specific language will be used to describe the embodiments herein, although it will be understood that no limitation of the claims or the scope of the present disclosure is intended in this regard. Variations and further modifications to the features of the invention illustrated herein, and further applications of the principles of the subject matter illustrated herein, which may occur to those skilled in the art having the benefit of this disclosure, are intended to be within the scope of the subject matter disclosed herein. Other embodiments may be used and / or other changes may be made without departing from the spirit or scope of the disclosure. The exemplary embodiments described in the detailed description are not intended to limit the subject matter presented.

[0020] The present disclosure provides various embodiments of methods for forming a semiconductor device having power rails formed on the backside of at least some of the transistors. In various embodiments, each of the transistors may be configured with any of a variety of transistor structures (e.g., a gate-all-around (GAA) transistor structure, a FinFET structure, a channel-all-around (CAA) transistor structure, etc.). The methods disclosed herein may include forming a laser lift-off layer disposed between the backside of a stack of several semiconductor layers (some of which may later form the transistors' respective conductive channels) and a carrier substrate. The carrier substrate is generally formed as a sacrificial substrate to provide mechanical support for the stack during the formation of the transistors and some frontside interconnect structures above the transistors (commonly referred to as front-end-of-line (FEOL) processing and back-end-of-line (BEOL) processing, respectively). In existing technologies, such carrier substrates are removed through a polishing process (e.g., a chemical-mechanical polishing (CMP) process), which can sometimes damage the already formed transistors and frontside interconnect structures. By using a laser lift-off layer to remove the carrier substrate, the methods of the present disclosure can advantageously avoid these challenges. For example, the carrier substrate can be easily removed through application of radiation (e.g., laser) onto the laser lift-off layer without any mechanical force being applied to the transistor or the frontside interconnect structure. Furthermore, once the carrier substrate is removed, the backside of the transistor can be made available, allowing several power rails to be formed on the backside of the transistor.

[0021] FIG. 1 illustrates a flowchart of a method 100 for forming a backside interconnect structure for a transistor structure, according to one or more embodiments of the present disclosure. For example, at least some of the operations (or steps) of method 100 may be used to form several interconnect structures on the backside of a FinFET structure, a GAA transistor structure, a CAA transistor structure, a vertical transistor structure, or the like. At least some of such backside interconnect structures may form a power delivery network for the transistor structure, i.e., a network that delivers power to the transistor structure. It should be noted that method 100 is merely an example and is not intended to limit the present disclosure. Thus, it should be understood that additional operations may be provided before, during, and after method 100 of FIG. 1, and that some other operations may only be briefly described herein.

[0022] In some embodiments, the operations of method 100 may be associated with cross-sectional views of an exemplary semiconductor device 200 (e.g., including a GAA transistor structure) at various stages of fabrication as shown in Figures 2A-2L, respectively, and described in further detail below. It should be understood that the semiconductor device 200 shown in Figures 2A-2L may not include a completed GAA transistor structure for purposes of simplicity. For example, the following views of semiconductor device 200 may not show or include source / drain structures coupled to opposite sides of each of the channels or gate electrodes enveloping each of the channels.

[0023] 1, Figure 2A is a cross-sectional view of a semiconductor device 200 at one of various stages of fabrication, with a stack 210 formed on a first substrate 202, according to various embodiments of the present disclosure. The cross-sectional view of Figure 2A may be taken in a direction perpendicular to the length of one or more channels of the semiconductor device 200 (e.g., the length of the active / dummy gate structures of the semiconductor device 200).

[0024] The first substrate 202 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. In some embodiments, the first substrate 202 may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or graded substrates, may also be used. For example, the semiconductor material of the first substrate 202 may include silicon; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof.

[0025] In various embodiments, a first substrate 202 may be provided for epitaxially growing a stack 210 thereon. The stack 210 includes several first semiconductor layers 214 and several second semiconductor layers 216 arranged alternately on top of one another along a vertical direction. As described below, the first semiconductor layers 214 may be later removed or replaced with an enveloping gate structure of a GAA transistor, and the second semiconductor layers 216 may collectively function as the channel of the GAA transistor. Accordingly, the first semiconductor layers 214 and the second semiconductor layers 216 are sometimes referred to as a "sacrificial layer 214" and a "channel layer 216," respectively. For example, in FIG. 2A , one of the second semiconductor layers 216 is disposed on top of one of the first semiconductor layers 214, and then another of the first semiconductor layers 214 is disposed on top of the second semiconductor layer 216, etc.

[0026] The semiconductor layers 214 and 216 may have different thicknesses. Furthermore, the first semiconductor layer 214 may have different thicknesses. The second semiconductor layer 216 may have different thicknesses. The thickness of each of the semiconductor layers 214 and 216 may range from a few nanometers to tens of nanometers. In some embodiments, the layer of the stack 210 closest to the first substrate 202 may be thicker than the other semiconductor layers 214 and 216. In one embodiment, each of the first semiconductor layers 214 has a thickness in a range from about 5 nanometers (nm) to about 20 nm, and each of the second semiconductor layers 216 has a thickness in a range from about 5 nm to about 20 nm.

[0027] In various embodiments, the first semiconductor layer 214 and the second semiconductor layer 216 have different compositions. For example, the first and second semiconductor layers 214 and 216 have compositions that result in different oxidation rates and / or different etch selectivities between the layers. In one embodiment, the first semiconductor layer 214 is silicon germanium (Si 1-x Ge x ), and the second semiconductor layers 216 each include silicon (Si). In one embodiment, each of the second semiconductor layers 216 may be, for example, not intentionally doped when formed, undoped, or substantially doped (e.g., approximately 0 cm -3 ~Approx. 1×10 17 cm -3 Each of the first semiconductor layers 214 is silicon with an extrinsic dopant concentration of less than 50% (x<0.5) Ge by mole fraction. 1-x Ge x For example, Ge is Si in mole ratio. 1-x Ge x may comprise approximately 15% to 35% of the first semiconductor layer 214. Furthermore, the first semiconductor layers 214 may include different compositions therebetween, and the second semiconductor layers 216 may include different compositions therebetween.

[0028] Alternatively or additionally, either of the semiconductor layers 214 and 216 may include other materials, such as compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. The materials of the semiconductor layers 214 and 216 may be chosen based on providing different oxidation rates and / or etch selectivities.

[0029] In some embodiments, when the first substrate 202 is disposed relatively lower in the stack 210, the stack 210 further includes an optional semiconductor layer 212 interposed between the nearest first semiconductor layer 214 (to the first substrate 202) and the first substrate 202. The semiconductor layer 212 may be similar to the first semiconductor layer 210, but have a different germanium molar ratio (e.g., substantially higher than the germanium molar ratio of the first semiconductor layer 214). Such a semiconductor layer 212 may function as an etch stop layer during removal of the first substrate 202, as will be described below.

[0030] Semiconductor layers 214 and 216 may be epitaxially grown from first substrate 202 or semiconductor layer 212 (if formed). For example, each of semiconductor layers 214 and 216 may be grown by a chemical vapor deposition (CVD) process, such as a molecular beam epitaxy (MBE) process, a metalorganic CVD (MOCVD) process, and / or other suitable epitaxial growth process. During epitaxial growth, the crystalline structure for first substrate 202 or semiconductor layer 212 may extend upward, such that semiconductor layers 214 and 216 have the same or similar crystalline orientation as first substrate 202 or semiconductor layer 212.

[0031] 1, Figure 2B is a cross-sectional view of a semiconductor device 200 at one of various stages of fabrication, according to various embodiments, provided with a second substrate 220 covered by a laser lift-off (LLO) layer 222 and a dielectric layer 224. The cross-sectional view of Figure 2B may be taken in a direction perpendicular to the length of one or more channels of the semiconductor device 200 (e.g., the length of the active / dummy gate structures of the semiconductor device 200).

[0032] In various embodiments, an LLO layer 222 and a dielectric layer 224 are sequentially formed on a second substrate 220. The dielectric layer 224 may be utilized to bond the second substrate 220 to the stack 210 (as shown below in FIG. 2C ), with the LLO layer 222 interposed between the second substrate 220 and the dielectric layer 224. The second substrate 220 may be configured to provide mechanical support for a workpiece (including, for example, certain device features and frontside interconnect structures shown below). Additionally, the second substrate 220 may be easily removed (e.g., without any polishing process) in some embodiments by utilizing the LLO layer 222.

[0033] The second substrate 220 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants), or a dielectric, such as silicon dioxide glass. In some embodiments, the second substrate 220 can be a wafer, such as a silicon wafer, or a glass panel. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or graded substrates, can also be used. For example, the semiconductor material of the second substrate 220 may include silicon; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof.

[0034] The LLO layer 222 can be induced to thermally dissociate upon application of a laser, thereby allowing the second substrate 220 to be subsequently removed from the workpiece. In some embodiments, the LLO layer 222 can comprise a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, titanium nitride, metals, and metal oxides. The LLO layer 222 can be deposited or thermally grown on the second substrate 220. The dielectric layer 224 can be configured as an interlayer dielectric (ILD) or intermetal dielectric (IMD) material. The dielectric layer 224 can comprise one or more low-k dielectric materials, such as silicon oxide (SiO2).

[0035] 1, Figure 2C is a cross-sectional view of a semiconductor device 200 at various stages of fabrication with a second substrate 220 attached to a first substrate 202, according to various embodiments of the present disclosure. The cross-sectional view of Figure 2C may be taken in a direction perpendicular to the length of one or more channels of the semiconductor device 200 (e.g., the length of the active / dummy gate structures of the semiconductor device 200).

[0036] As shown, the second substrate 220 is attached (e.g., directly bonded) to the first substrate 202, with the LLO layer 222, the dielectric layer 224, and the stack 210 interposed therebetween. Specifically, in the example of FIG. 2C , the second semiconductor layer 214 (of the stack 210) that is furthest from the first substrate 202 contacts the dielectric layer 224. In various embodiments, the stack 210 has a first side 210A and a second side 210B. The first side 210A is configured to form several front-side interconnect structures, and the second side 210B is configured to form several back-side interconnect structures. Accordingly, the first side 210A and the second side 210B are sometimes referred to as the “front side 210A” and the “back side 210B,” respectively.

[0037] 1, FIG. 2D is a cross-sectional view of semiconductor device 200 at various stages of fabrication in which the workpiece (i.e., partially formed semiconductor device 200) has been flipped, according to various embodiments of the present disclosure. The cross-sectional view of FIG. 2D may be taken in a direction perpendicular to the length of one or more channels of semiconductor device 200 (e.g., the length of active / dummy gate structures of semiconductor device 200). Once flipped, front surface 210A is above back surface 210B, as shown in FIG. 2D.

[0038] 1 , FIG. 2E is a cross-sectional view of semiconductor device 200 at various stages of fabrication with first substrate 202 removed, according to various embodiments of the present disclosure. The cross-sectional view of FIG. 2E may be taken in a direction perpendicular to the length of one or more channels of semiconductor device 200 (e.g., the length of active / dummy gate structures of semiconductor device 200). In some embodiments, first substrate 202 is removed by at least one of a polishing process or a wet etching process. Given the high germanium mole fraction, semiconductor layer 212 may act as an etch stop layer during removal of first substrate 202.

[0039] 1, Figure 2F is a cross-sectional view of semiconductor device 200 at various stages of fabrication with semiconductor layer 212 removed, according to various embodiments of the present disclosure. The cross-sectional view of Figure 2F may be taken in a direction perpendicular to the length of one or more channels of semiconductor device 200 (e.g., the length of active / dummy gate structures of semiconductor device 200). In some embodiments, having different germanium mole ratios between semiconductor layer 212 and semiconductor layer 214 allows semiconductor layer 212 to be selectively removed using a suitable etchant.

[0040] 1, Figure 2G is a cross-sectional view of semiconductor device 200 at various stages of fabrication, with several active regions, e.g., 210A, 210B, and 210C, defined within stack 210. In some embodiments, the cross-sectional view of Figure 2G may be taken in a direction perpendicular to the length of one or more channels of semiconductor device 200 (e.g., the length of active / dummy gate structures of semiconductor device 200).

[0041] Removing the semiconductor layer 212 exposes one of the first (top) semiconductor layers 214 on the front side 210A of the stack, and the stack 210 can then be patterned to form active regions, e.g., 210A-210C. For example, a mask layer 225 (which may include multiple layers, e.g., a pad oxide layer and an overlying pad nitride layer) is formed on the top semiconductor layer (e.g., 214 in FIG. 2G). The pad oxide layer may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process. The pad oxide layer may serve as an adhesion layer between the top semiconductor layer 214 and the overlying pad nitride layer. In some embodiments, the pad nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbonitride, the like, or a combination thereof. The pad nitride layer may be formed, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0042] The mask layer 225 may then be patterned using photolithography techniques. Generally, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove portions of the photoresist material. The remaining photoresist material protects underlying materials, such as the mask layer in this example, from subsequent processing steps, such as etching. For example, photoresist material is used to pattern a pad oxide layer and a pad nitride layer to form a patterned mask.

[0043] The patterned mask may then be used to pattern exposed portions of semiconductor layers 214 and 216 to form several trenches (or openings) and thereby define device regions 211A-211C, each disposed between adjacent trenches. When multiple active areas are formed, such trenches may be disposed between any adjacent ones of the active areas. In some embodiments, device regions 211A-211C are formed by etching trenches in semiconductor layers 214 and 216 (if formed) using, for example, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching may be anisotropic. In some embodiments, the multiple trenches may be strips that are parallel to one another (when viewed from above) and closely spaced relative to one another. In some embodiments, the trenches may each be continuous and surround a corresponding one of device regions 211A-C.

[0044] 1, Figure 2H is a cross-sectional view of semiconductor device 200 at one of various stages of fabrication, including several device features 230 and several frontside interconnect structures 234. In some embodiments, the cross-sectional view of Figure 2H may be taken in a direction perpendicular to the length of one or more channels of semiconductor device 200 (e.g., the length of active / dummy gate structures of semiconductor device 200).

[0045] In various embodiments, after defining the device regions 211A-211C, several processes may be performed to form several device features (including, for example, device feature 230), resulting in several (e.g., GAA) transistors. For example, once the device regions 211A-211C are defined, at least one dummy gate structure may be formed to cover (e.g., across) the device regions 211A-211C. Next, the respective portions of each of the device regions 211A-211C not covered by the dummy gate structure are replaced with an epitaxial structure that may function as the source / drain regions of the GAA transistor. Next, the semiconductor (sacrificial) layer 214 and dummy gate structure of the device regions 211A-211C are replaced with the device feature 230, which is a gate structure (hereinafter "gate structure 230"). Each of these gate structures 230 may include a gate metal with a gate dielectric between the gate metal and the semiconductor (channel) layer 216, such that the gate structure surrounds (encloses) a corresponding number of the semiconductor (channel) layer 216. After the gate structures 230 are formed, in some embodiments, several GAA transistors are completed. For example, each of the gate structures 230, along with its surrounding semiconductor layer 216 and corresponding source / drain regions, may form a GAA transistor. Next, on the front side 210A, front side interconnect structures 234 may be formed over the GAA transistors. These front side interconnect structures 234, formed of a metal material (e.g., copper), are generally embedded in a dielectric layer 236 having an IMD material, such as layered silicon. Such a layer formed of a dielectric layer 236 containing one or more front side interconnect structures 234 is typically referred to as a metal wiring layer. While FIG. 2I shows one such metal wiring layer, it should be understood that multiple metal wiring layers may be formed over the GAA transistors.

[0046] Corresponding to operation 118 of FIG. 1 , FIG. 2I is a cross-sectional view of semiconductor device 200 at one of various stages of fabrication, with third substrate 240 attached (e.g., bonded) to a workpiece. In some embodiments, the cross-sectional view of FIG. 2I may be taken in a direction perpendicular to the length of one or more channels of semiconductor device 200 (e.g., the length of active / dummy gate structures of semiconductor device 200). As shown, third substrate 240 is in contact with dielectric layer 236. In some embodiments, third substrate 240 may be configured to provide mechanical support for the workpiece while certain interconnect structures are formed on the backside of the transistor, as described below.

[0047] The third substrate 240, like the substrate 220, can be a bulk semiconductor, a semiconductor substrate such as a semiconductor-on-insulator (SOI) substrate, an insulator, or the like. In some embodiments, the third substrate 240 can be a blank wafer or a wafer such as a silicon wafer that can have active devices formed therein. Although not shown, the substrate 240 can have contact structures that are electrically connected directly or indirectly to the interconnect structure 234 through a hybrid bonding process.

[0048] 1, FIG. 2J is a cross-sectional view of semiconductor device 200 at various stages of fabrication in which the workpiece (i.e., partially formed semiconductor device 200) has been flipped, according to various embodiments of the present disclosure. The cross-sectional view of FIG. 2J may be taken in a direction perpendicular to the length of one or more channels of semiconductor device 200 (e.g., the length of active / dummy gate structures of semiconductor device 200). Once flipped, back surface 210B is above front surface 210A, as shown in FIG. 2J.

[0049] 1, Figure 2K is a cross-sectional view of semiconductor device 200 at various stages of fabrication with second substrate 220 removed, according to various embodiments of the present disclosure. The cross-sectional view of Figure 2K may be taken in a direction perpendicular to the length of one or more channels of semiconductor device 200 (e.g., the length of active / dummy gate structures of semiconductor device 200).

[0050] In various embodiments, the second substrate 220 can be removed through a laser lift-off (LLO) process. In such an LLO process, radiation or other optical energy (e.g., a laser beam) irradiates the workpiece through the exposed surface of the second substrate 220, and the radiation passes through the second substrate 220 and into the LLO layer 222 (FIG. 2J). In various embodiments, the second substrate 220 can be optically transparent to the wavelength of the optical energy. As a non-limiting example, the laser radiation incident on the second substrate 220 can be 248 nm radiation from a KrF pulsed excimer laser with a 38 ns pulse width. The energy passing through the second substrate 220 is then absorbed by the LLO layer 222, which causes thermal chemical dissociation in the LLO layer 222. The workpiece (which includes the GAA transistors and frontside interconnect structures, meanwhile, bonded to the third substrate 240) can be peeled, separated, or otherwise detached from the second substrate 220. Therefore, the LLO layer 222 is sometimes referred to as a release layer. The LLO process can be carried out in either a vacuum, air, or other ambient environment, and is generally carried out at high temperatures (eg, above 250° C.).

[0051] 1, Figure 2L is a cross-sectional view of a semiconductor device 200 at one of various stages of fabrication, with several backside interconnect structures 254 formed therein, according to various embodiments of the present disclosure. The cross-sectional view of Figure 2L may be taken in a direction perpendicular to the length of one or more channels of the semiconductor device 200 (e.g., the length of the active / dummy gate structures of the semiconductor device 200).

[0052] As shown, backside interconnect structures 254 are formed on the backside 210B of the GAA transistor relative to the frontside interconnect structures 234 formed on the frontside 210A of the GAA transistor. These backside interconnect structures 254 are typically formed of a metallic material (e.g., copper). In some embodiments, at least a portion of the backside interconnect structures 254 may operatively function as a power distribution network for the GAA transistor, i.e., a network that supplies or conveys power to the GAA transistor. The frontside structures 234 may be formed as hybrid bond interconnects or may indirectly connect to interconnects that may be further connected through a hybrid bonding process. Thus, the frontside may enable connection between two devices directly bonded to each other, while the backside interconnects allow shared connections, such as power and / or ground, to be provided from outside the bonded devices / substrates.

[0053] In the above description, specific details have been set forth, such as the particular configuration of the processing system and descriptions of the various components and processes used therein. However, it should be understood that the technology herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numerical values, materials, and configurations have been set forth to provide a thorough understanding. However, embodiments may be practiced without such specific details. Because components having substantially the same functional structure are designated by similar reference numerals, redundant description may be omitted.

[0054] To aid in understanding various embodiments, various techniques have been described as multiple separate operations. The order of description should not be construed as implying that these operations are necessarily order dependent. In fact, these operations need not be performed in the order presented. The operations described may be performed in a different order than in the described embodiments. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0055] As used herein, "substrate" or "target substrate" generally refers to an object to be processed according to the present invention. A substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be a base substrate structure such as a semiconductor wafer, a reticle, or a layer, e.g., a thin film, on or overlying the base substrate structure. As such, substrate is not limited to any particular base structure, underlying layer, or overlying layer, whether patterned or not, but is intended to include such layers or base structures and any combination of layers and / or base structures. While this specification may refer to particular types of substrates, this is for illustrative purposes only.

[0056] Those skilled in the art will appreciate that many variations can be made to the operation of the techniques described above while still achieving the same objectives of the present invention. Such variations are intended to be included within the scope of the present disclosure. Accordingly, the above description of embodiments of the present invention is not intended to be limiting. Rather, any limitations to embodiments of the present invention are set forth in the following claims.

Claims

1. 1. A method for manufacturing a semiconductor device, comprising: forming a stack on a first substrate, a laser lift-off layer interposed between the stack and the first substrate; forming a plurality of first interconnect structures on a first surface of the stack; attaching a second substrate to the stack on the first surface, the plurality of first interconnect structures being interposed between the stack and the second substrate; removing the first substrate by applying radiation to the laser lift-off layer; forming a plurality of second interconnect structures on a second surface of the stack opposite the first surface; A method comprising:

2. The method of claim 1 , wherein at least a portion of the plurality of second interconnect structures operatively function as a power distribution network.

3. growing a first semiconductor layer on a third substrate, and subsequently growing the stack on the first semiconductor layer; attaching the first substrate to the stack, the laser lift-off layer and the dielectric layer being interposed between the first substrate and a first one of the second semiconductor layers; The method of claim 1 further comprising:

4. removing the third substrate to expose the first semiconductor layer; removing the first semiconductor layer to expose a second one of the second semiconductor layers; patterning the stack followed by the step of forming a plurality of first interconnect structures; The method of claim 3 further comprising:

5. The method of claim 3 , wherein the stack comprises a plurality of second semiconductor layers and a plurality of third semiconductor layers alternately stacked on top of each other.

6. 6. The method of claim 5, wherein the first semiconductor layer comprises a first concentration of germanium, the second semiconductor layer comprises a second concentration of germanium, and the third semiconductor layer comprises silicon.

7. The method of claim 6 , wherein the second concentration is substantially less than the first concentration.

8. 8. The method of claim 7, wherein the first semiconductor layer serves as an etch stop layer for the step of removing the third substrate, the step including at least a wet etching process.

9. 10. The method of claim 1, wherein the laser lift-off layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, titanium nitride, metals, and metal oxides.

10. 1. A method for manufacturing a semiconductor device, comprising: forming a stack on a first substrate; sequentially forming a laser lift-off layer and a dielectric layer on the second substrate; attaching the dielectric layer to a first surface of the stack; removing the first substrate from a second side of the stack, the second side being opposite the first side; forming a plurality of device features using the stack; forming a plurality of first interconnect structures on the second surface; removing the second substrate through the laser lift-off layer to expose the first surface of the stack; forming a plurality of second interconnect structures on the first surface; A method comprising:

11. The method of claim 10 , wherein at least a portion of the plurality of second interconnect structures operatively function as a power delivery network.

12. attaching a third substrate to the second side of the stack; Thereafter, removing the second substrate. The method of claim 10 further comprising:

13. The method of claim 10 , further comprising growing a first semiconductor layer between the second side of the stack and the first substrate.

14. The method of claim 13 , wherein the stack comprises a plurality of second semiconductor layers and a plurality of third semiconductor layers alternately stacked on top of each other.

15. 15. The method of claim 14, wherein the first semiconductor layer comprises a first concentration of germanium, the second semiconductor layer comprises a second concentration of germanium, and the third semiconductor layer comprises silicon.

16. The method of claim 15 , wherein the second concentration is substantially less than the first concentration.

17. 17. The method of claim 16, wherein the first semiconductor layer acts as an etch stop layer for the step of removing the first substrate, the step including at least a wet etching process.

18. 11. The method of claim 10, wherein the laser lift-off layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, titanium nitride, metals, and metal oxides.

19. 1. A method for manufacturing a semiconductor device, comprising: forming a stack on a first substrate, the stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on top of each other; sequentially forming a laser lift-off layer and a dielectric layer on the second substrate; attaching the dielectric layer to a first surface of the stack; removing the first substrate from a second side of the stack, the second side being opposite the first side; forming a plurality of device features using the stack; forming a plurality of first interconnect structures over the plurality of device features; attaching a third substrate to the second side of the stack; removing the second substrate by applying radiation to the laser lift-off layer; forming a plurality of second interconnect structures on the device feature opposite the plurality of first interconnect structures; A method comprising:

20. 20. The method of claim 19, wherein the laser lift-off layer comprises a material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, titanium nitride, metals, and metal oxides.

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