Molybdenum carrier substrate for surface-emitting infrared light-emitting diode devices
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-03-23
- Publication Date
- 2026-03-25
AI Technical Summary
Conventional carrier substrates for surface-emitting infrared light-emitting diodes (IR-LEDs) made of gallium arsenide (GaAs) and germanium (Ge) are expensive and require additional processing steps, and existing methods to reduce light absorption by the substrate are only partially effective.
The use of a molybdenum conductive carrier substrate with a random textured surface and a reflective mirror structure, including a dielectric film and metal layers, to enhance light extraction efficiency by randomly distributing reflected light.
Improves light extraction efficiency by increasing the probability of photons escaping the device, resulting in higher light output compared to conventional LEDs.
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Abstract
Description
[Background technology]
[0001] Conventional carrier substrates for surface-emitting infrared light-emitting diodes (IR-REDs) are made of gallium arsenide (GaAs), germanium (Ge), or silicon. GaAs and Ge substrates are sometimes expensive substrates and require additional processing steps to be formed into surface-emitting IR-REDs. [Brief explanation of the drawings]
[0002] The invention will be better understood from the following description, given by way of example with reference to the drawings that accompany this specification.
[0003] [Figure 1] FIG. 1 is a block diagram illustrating an exemplary device in which one or more features of the present invention may be implemented. [Figure 2] FIG. 2 is a cross-sectional view of a light-emitting film having a randomly textured surface grown and deposited on a sacrificial semiconductor substrate. [Figure 3] FIG. 3 shows the light emitting film of FIG. 2 with a dielectric film, a metal film and a metal-semiconductor contact region. [Figure 4] FIG. 4 is a cross-sectional view of a conductive carrier having a substrate and a metal layer, illustrating the formation of a conductive carrier having a substrate and a metal layer. [Figure 5] FIG. 5 is a cross-sectional view of an optoelectronic semiconductor device according to an exemplary embodiment. [Figure 6] FIG. 6 is a flowchart illustrating an exemplary method for manufacturing an optoelectronic semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0004] Briefly, as will be described in more detail below, the present invention relates to optoelectronic semiconductor devices, and more particularly to light emitting diodes (LEDs), such as infrared (IR) LEDs.
[0005] The IR-LED of the present invention includes a top contact, a molybdenum conductive carrier, and a light-emitting film disposed between the top contact and the molybdenum conductive carrier. Also described below is a method for fabricating an optoelectronic semiconductor device.
[0006] Conventional IR LEDs have a gallium arsenide (GaAs) conductive substrate and are based on semiconductor compounds such as indium phosphide (InP), zinc selenide (ZnSe), gallium nitride (GaN), and their ternary and quaternary compounds containing In and aluminum (Al). A typical LED has a light-emitting region or film grown on the semiconductor compound substrate by techniques such as metalorganic chemical vapor deposition (MOCVD), liquid phase epitaxy (LPE), or molecular beam epitaxy (MBE). The light-emitting film has a p-n junction (the boundary between p-type and n-type semiconductor materials). Two electrodes, typically grown on the bottom and top sides of the device, generate a current that flows through the p-n junction, generating photons whose wavelength depends on the specific semiconductor material. The light-emitting film emits light in all directions, with the light emitted toward the semiconductor substrate being absorbed by the semiconductor substrate.
[0007] A known method to suppress this absorption is to grow a thick "window layer" between the substrate and the light-emitting region, increasing the distance between the light-emitting region and the absorbing substrate. However, this window layer is transparent and absorbs only a small portion of the light that passes through it. Light directed toward the substrate will still be absorbed by the substrate. Another known method is to grow an internal semiconductor reflective layer, such as a distributed Bragg reflector (DBR), between the substrate and the light-emitting film. However, this DBR is only partially reflective. Thus, these known methods only provide a partial solution to the absorption problem.
[0008] Yet another method to reduce absorption is to bond the substrate with the grown and deposited light-emitting region to another semiconductor carrier that is completely transparent to the wavelength of the emitted light. This bonding is done so that the original substrate material is spaced apart from the carrier. The absorbing part can then be removed, leaving only the light-emitting region bonded to the transparent carrier. The device can be packaged so that the light that passes through the transparent carrier can be reflected (and directed). In this package, the device is bonded to a reflective material. However, this solution is complex because perfectly matching different semiconductor types is problematic and difficult to achieve at low cost.
[0009] The term "random texture," as used herein when referring to a face, surface, or interface, is intended to mean that the face, surface, or interface is characterized by an asymmetric structure, by way of example and not limitation, irregular protrusions including uneven portions, or by way of example and not limitation, ridges with numerous random edges or angles.
[0010] Furthermore, according to Snell's law, only photons that reach the film surface at angles smaller than the critical angle for total internal reflection (defined by the respective refractive indices of the materials at that interface) can exit the emissive film. In three dimensions, photons must reach the surface at an angle within a specific "exit cone" to escape the emissive film. Other photons will be reflected multiple times before finally being absorbed.
[0011] The use of random texture results in diffuse reflection of light at the surface of the light-emitting film or underlying layer opposite the conductive carrier, causing photons to travel in a random direction, i.e., light that undergoes total internal reflection at the top surface of the light-emitting film (the surface away from the conductive carrier that allows light to escape from the device) will be reflected back to the top surface by this surface at a random angle.
[0012] Therefore, the amount of photons that strike the top surface at angles within the exit cone increases. Light that reflects off the textured surface and returns to the luminescent film is randomly distributed at different angles, thereby improving the light extraction efficiency of optoelectronic semiconductor devices.
[0013] To further increase light extraction efficiency, the upper layer between the top contact and the light-emitting film or the light-emitting film may include a roughened upper surface facing the top contact. The light-emitting film and / or the upper layer may have at least one lateral side, which may include a random surface texture. The upper layer is preferably a window layer or a current spreading layer.
[0014] The optoelectronic semiconductor device includes a conductive carrier having a top contact and a molybdenum metal conductive carrier substrate. A metal layer is deposited on the molybdenum metal conductive carrier substrate. A light-emitting film is located between the top contact, the mirror layer, and the molybdenum metal conductive carrier substrate.
[0015] The optoelectronic semiconductor device has a top surface located between a top contact and a light emitting film facing the top contact.
[0016] The optoelectronic semiconductor device has lateral aspects on the light emitting film.
[0017] The optoelectronic semiconductor device has a mirror structure with a dielectric film.
[0018] An optoelectronic semiconductor device has a dielectric film grown and deposited on its upper surface.
[0019] The optoelectronic semiconductor device has an etched contact opening and a mirror structure that forms the contact by deposition.
[0020] The optoelectronic semiconductor device has a light emitting film contained in a substrate layer.
[0021] The optoelectronic semiconductor device has a molybdenum metallic conductive carrier substrate bonded to a substrate layer.
[0022] The optoelectronic semiconductor device has a solder layer joining a molybdenum metal conductive carrier substrate to a substrate layer.
[0023] The optoelectronic semiconductor device has a top contact with an electrode.
[0024] A method for forming an optoelectronic semiconductor device includes depositing a first metal layer on a molybdenum metal conductive carrier substrate, forming a mirror structure on a gallium arsenide substrate member, bonding the first metal layer to a second metal layer, and removing at least a portion of the gallium arsenide substrate layer and depositing one or more electrodes.
[0025] A conventional chip is shown in Figure 1. In a first step, a light-emitting film 21, typically 7 μm to 30 μm thick, is grown and deposited on a GaAs substrate 11. The light-emitting film 21 has an active (light-emitting) layer (not shown), which can be AlGaAs and n-type and p-type semiconductor layers (not shown). When current is passed through the device, light is generated within the film 21. Light impinging on the compound-air interface at angles off the exit cone is reflected from surfaces 31, 32, and 33 of the light-emitting film 21. Furthermore, light directed toward interface 6, located between the light-emitting film 21 and the substrate 11, is completely absorbed by the substrate 11.
[0026] The conventional chip shown in FIG. 1 can be modified so that surface 32 has a random surface texture, as shown in FIG. 2. Surface texturing is preferably achieved using conventional methods by treating the wafer with hydrogen fluoride (HF), nitric acid (HNO), or other chemical etchants, resulting in a random surface morphology typically with an average roughness of 5 nm (50 Å) to 70 nm (700 Å). Light that reflects from the textured surface and returns to the film is randomly distributed at different angles. This morphology therefore increases the probability that light striking surface 32 (light striking surface 32 at angles within the "exit cone") will exit light-emitting film 21.
[0027] The next step is to form mirror films 3, 4, and 5, as shown in Figure 3. Note that the surfaces of the mirror films 3, 4, and 5 facing the light-emitting film 21 have a random texture that is complementary to the random texture of the surface 32 of the light-emitting film 21. That is, the mirror films 3, 4, and 5 and the light-emitting film 21 are in direct contact over the entire surface 32. The mirror layers (e.g., films 3, 4, and 5) reflect light generated by the layer 21 back to the LED.
[0028] For this purpose, a dielectric film 3, such as silicon dioxide (SiO2) or silicon nitride (Si3N4), is grown on top of the textured surface 32 using a method such as conventional plasma-enhanced chemical vapor deposition (PECVD). The thickness of the dielectric film 3 is typically 0.03 μm to 0.5 μm. For electrical current to flow through the semiconductor material 21, a contact area must be formed. To this end, contact holes 4 are etched into the dielectric film 3. The contact holes 4, typically with a contact diameter of 2 μm to 20 μm, are formed using chemical etchants such as HF or conventional lithography techniques using a plasma etch tool. After the contact holes 4 are formed, a reflective metal 5 is grown using a conventional metal growth and deposition tool. The metal layer 5 can contain gold (Au) or silver (Ag) to form a highly reflective mirror. The metal layer 5 has a barrier metal that prevents material diffusion toward the semiconductor interface 32. A typical metal composition for the p-type contact is considered to be a AuZn / TiW-based composition, with a total thickness of 0.1 μm to 0.5 μm. The combination of an appropriate dielectric layer 3 and a reflective metal layer 5 results in a highly reflective mirror. The textured pattern 32 covered by the reflective mirror layers 3, 4, and 5 acts as a "diffuse mirror" that randomly reflects light generated by the light-emitting film 21 in all directions.
[0029] The high reflectivity of the mirror ensures that the light output of a surface-emitting diode is higher than that of a conventional LED, for example, even small changes in reflectivity (such as between Ag and Au) are visible.
[0030] FIG. 4 shows a cross-sectional view of a surface-emitting diode (SLED) having a conductive carrier substrate 1, a metal layer 2, and a substrate 11 with a light-emitting film 21 and mirror systems 3, 4, and 5. Substrate 1 is a molybdenum substrate coated with metal layer 2. Figure 4 also shows the molybdenum conductive carrier 1 and metal layer 2 bonding portion of the components shown in FIG. 3. Metal layer 2 is grown on the conductive molybdenum wafer substrate 1. Metal layer 2 is a conventional metal electrode structure typically used on conductive substrates, such as AuZn for p-type materials or AuGe for n-type materials, typically 0.1 μm to 0.5 μm thick. Another metal layer (not shown), typically 1 μm to 5 μm thick, is grown on top of metal layer 2 (note that this other metal layer contains the material required for eutectic bonding, such as AuSn).
[0031] Also described herein is a method for forming a molybdenum conductive carrier 1 having a substrate and a carrier wafer substrate 11 / metal layer 5. The mirror layer can be formed by etching contact openings 4 followed by growing contacts (such as electrodes 12). This growth can be performed by removing unused areas. A metal layer 5 (such as a solder layer) for bonding can also be grown.
[0032] Next, metal layer 2 is bonded to metal layer 5. Prior to the formation of the optoelectronic semiconductor device, the entire bonded substrate 11 is rotated together with the light emitting film 21, mirror components 3, 4, 5, and molybdenum conductive carrier 1. After rotation, the substrate 11 portion is removed.
[0033] More specifically, wet etching can be used to remove substrate 11 and form layers upon which electrodes will be grown, as described below.
[0034] Wafer bonding is performed, for example, using a eutectic bonding process. In this process, the chip shown in FIG. 3 is flipped so that the GaAs substrate faces up. For the device shown in FIG. 4, substrate 1 is a molybdenum conductive carrier substrate. Metal layer 5 of the chip in FIG. 3 and metal layer 2 of the conductive carrier in FIG. 4 are then bonded together as shown in FIG. 5. Wafer bonding is performed by applying a controlled pressure to the formed chip in a heat treatment furnace (apparatus) under an inert atmosphere.
[0035] After wafer bonding, the light-absorbing GaAs conductive substrate 11 is removed using a conventional etchant such as a sulfuric acid:hydrogen peroxide:water (H2SO4:H2O2:H2O) solution or a mechanical polishing device. In a final step, the top electrode 12 is added using conventional lithography and metal electrode formation methods.
[0036] Additionally, a metal layer can be added to the bottom of the device shown in Figure 5, i.e., a metal backing layer can be added underneath the carrier substrate 1.
[0037] FIG. 6 is a flowchart illustrating an exemplary method for manufacturing an optoelectronic semiconductor device according to an exemplary embodiment.
[0038] In step 610, a first metal layer is deposited and grown on the molybdenum conductive carrier wafer 1. For example, referring back to Figures 4 and 5, the first metal layer can be metal layer 2 and a conventional metal electrode.
[0039] Next, the mirror layer is formed on the GaAs substrate 11 having the light emitting region 21 (step 620). This can be done by etching contact openings, attaching contacts, and growing / depositing them (step 630), as described above. The growth / deposition step can be done by lifting off the unused areas.
[0040] In step 640, the first metal layer is bonded to the second metal layer, after which the substrate 11, bonded carrier wafer with light emitting region 21, mirror layers 3, 4, 5 and molybdenum conductive wafer are rotated for further processing (step 650).
[0041] At this point, portions of the substrate are removed (step 660). As explained above, wet etching can be used to remove the conductive carrier substrate 11 and form a layer upon which the electrodes will be grown. Again, conventional etchants such as a sulfuric acid:hydrogen peroxide:water (H2SO4:H2O2:H2O) solution, or mechanical abrasive equipment can be used.
[0042] Next, electrodes are grown 670. For example, the electrodes can be added using conventional lithographic or metal electrode formation methods.
[0043] It should be noted that many variations are possible based on the above description, and although various combinations of features and elements have been described above, each feature or element can be used alone, i.e., without other features or elements, or in various combinations, i.e., with or without other features and elements. [Explanation of symbols]
[0044] 1 Conductive carrier substrate 2 metal layer 3. Dielectric layer, dielectric film 4 Contact openings, contact holes 5 metal layer 6 Interface 11 GaAs substrate 21 Luminescent film, luminescent area 31, 32, 33 surface 32 Textured patterns, semiconductor interfaces 3, 4, 5 Mirror film, mirror components 610, 620, 630, 640, 650, 660, 670 steps
Claims
1. Optoelectronic semiconductor device, Upper contact and A conductive carrier having a metallic molybdenum conductive carrier substrate, A mirror component having a reflective metal layer deposited on the aforementioned molybdenum conductive carrier substrate, A dielectric film deposited on the reflective metal layer, It has a light-emitting film located between the upper contact and the mirror component, The mirror component is located between the light-emitting film and the metal molybdenum conductive carrier substrate, and The light-emitting film includes a first textured surface having a first texture, and the mirror component includes a second textured surface having a second texture complementary to the first texture of the first textured surface. An optoelectronic semiconductor device characterized by the following features.
2. The optoelectronic semiconductor device according to claim 1, wherein the first textured surface of the light-emitting film is located between the light-emitting film facing the upper contact and the upper contact.
3. The optoelectronic semiconductor device according to claim 1, wherein the dielectric film has a plurality of openings, and at least a portion of the plurality of openings has inclined side walls.
4. The optoelectronic semiconductor device according to claim 1, wherein the dielectric film has the second textured surface.
5. The optoelectronic semiconductor device according to claim 4, wherein the dielectric film is deposited on the first textured surface of the light-emitting film, and the second textured surface of the dielectric film is in contact with the first textured surface of the light-emitting film.
6. The optoelectronic semiconductor device according to claim 1, wherein the mirror component is formed by etching to create a contact opening and depositing a contact portion.
7. The optoelectronic semiconductor device according to claim 1, wherein the light-emitting film is included in the substrate layer.
8. The optoelectronic semiconductor device according to claim 7, wherein the metallic molybdenum conductive carrier substrate is bonded to the substrate layer.
9. Furthermore, the optoelectronic semiconductor device according to claim 8, further comprising a solder layer for bonding the metal molybdenum conductive carrier substrate to the substrate layer.
10. The optoelectronic semiconductor device according to claim 1, wherein the upper contact has an electrode.
11. A first metal layer is deposited on a metallic molybdenum conductive carrier substrate. A light-emitting film is formed on a gallium arsenide substrate layer, and this light-emitting film is configured to include a first textured surface having a first texture. A mirror component is formed on the light-emitting film, and this mirror component includes a second textured surface having a second texture complementary to the first texture of the first textured surface of the light-emitting film, and the mirror component has a dielectric film. The first metal layer is bonded to the second metal layer, At least a portion of the gallium arsenide substrate layer is removed, and Deposit one or more electrodes. A method for forming an optoelectronic semiconductor device, characterized by the following:
12. The method according to claim 11, wherein, in the formation of the light-emitting film, the light-emitting film is deposited between one or more electrodes, the mirror component, and the metal molybdenum conductive carrier substrate.
13. The method according to claim 12, wherein the light-emitting film has a lateral surface.
14. The method according to claim 11, wherein the dielectric film has a plurality of openings, and at least a portion of the plurality of openings has inclined side walls.
15. The method according to claim 14, wherein, in the formation of the mirror component, the dielectric film is further deposited on the first textured surface of the light-emitting film, and the second textured surface of the dielectric film is used to grow the dielectric film in contact with the first textured surface of the light-emitting film.
16. Furthermore, the method according to claim 11, wherein the contact opening is etched and the mirror component is formed by deposition of material in the contact area.
17. The method according to claim 11, wherein the light-emitting film is included in the substrate layer.
18. Furthermore, the method according to claim 11, wherein the metal molybdenum conductive carrier substrate is bonded to the gallium arsenide substrate layer.
19. The method according to claim 18, further comprising depositing a solder layer for bonding the metallic molybdenum conductive carrier substrate to the gallium arsenide substrate layer.
20. The method according to claim 11, wherein the electrode is deposited by lithography.