Epitaxial nitride ferroelectric device and method for fabricating same

Abstract

A transistor device having a ferroelectric gate dielectric layer is provided. The transistor device includes a substrate and a heterostructure supported by the substrate, the heterostructure including a buffer layer supported by the substrate, a channel layer supported by the buffer layer, a barrier layer supported by the channel layer, and a gate dielectric layer supported by the barrier layer, the gate dielectric layer including a ferroelectric nitride alloy containing a Group IIIB element.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application entitled "Epitaxial Nitride Ferroelectric Device," filed January 7, 2023, and assigned Serial No. 63 / 437,670, the entire disclosure of which is expressly incorporated herein by reference. [Technical Field]

[0002] The present disclosure relates generally to ferroelectric nitride materials. [Background technology]

[0003] Due to the formation of an intrinsic two-dimensional electron gas (2DEG), III-nitride high-mobility transistor (HEMT) devices tend to operate in depletion mode. Depletion mode operation, unfortunately, consumes more power and poses safety issues. Therefore, E-mode operation has been a long-desired goal.

[0004] The ability to control and tune the electric polarization of semiconductor materials has been explored to enable the design and development of various devices, including microelectronic memory devices for neuromorphic computing and artificial intelligence, reconfigurable filters for mobile communications, micro / nanoelectromechanical systems, and tunable two-dimensional electron / hole gas (2DEG / 2DHG) heterojunctions. Wurtzite III-nitride semiconductors, such as AlN, GaN, InN, and their alloys, possess strong polarization effects along the c-axis, including spontaneous and piezoelectric polarization. However, the polarization direction of conventional III-nitrides cannot be electrically switched without causing dielectric breakdown.

[0005] Ferroelectric gate stacks have been used to amplify gate voltage controllability in connection with negative capacitance field-effect transistors (NC-FETs). In these applications, precise control of the gate stack structure is useful. Attempts have been made to integrate different ferroelectric materials with the 2DEG in AlGaN / GaN heterostructures, including LNO, PZT, and In2Se3. Summary of the Invention

[0006] According to one aspect of the present disclosure, a transistor device includes a substrate and a heterostructure supported by the substrate, the heterostructure including a buffer layer supported by the substrate, a channel layer supported by the buffer layer, a barrier layer supported by the channel layer, and a gate dielectric layer supported by the barrier layer, the gate dielectric layer including a ferroelectric nitride alloy including a Group IIIB element.

[0007] According to another aspect of the present disclosure, a method of fabricating a transistor device includes providing a buffer layer supported by a substrate; epitaxially growing a channel layer supported by the buffer layer; epitaxially growing a barrier layer supported by the channel layer; and growing a gate dielectric layer supported by the barrier layer, wherein the gate dielectric layer comprises a III-nitride ferroelectric alloy, and the III-nitride ferroelectric alloy comprises a Group IIIB element.

[0008] In relation to any one of the preceding aspects, the devices and / or methods described herein may alternatively or additionally include or involve any combination of one or more of the following aspects or features: The ferroelectric nitride alloy has a switchable polarization in the out-of-plane direction. The barrier layer is configured to act as a dielectric layer such that the transistor device has a bilayer gate dielectric structure. The barrier layer comprises a III-nitride alloy. The barrier layer and the channel layer have different bandgaps. The gate dielectric layer is single crystalline. The gate dielectric layer has a wurtzite structure. The buffer layer comprises a III-nitride semiconductor material. The channel layer comprises a III-nitride semiconductor material. The barrier layer comprises a III-nitride semiconductor material. The gate dielectric layer comprises ScAlN. The gate dielectric layer has a scandium content ranging from about 0.05 to about 0.5. The buffer layer is in contact with the channel layer. The channel layer is in contact with the barrier layer. The gate dielectric layer is in contact with the barrier layer. The barrier layer and the channel layer define an interface such that a channel is formed in the channel layer. The III-nitride alloy is configured such that no metal is present on a surface of the barrier layer in contact with the gate dielectric layer. The heterostructure further includes a charge storage layer disposed between the barrier layer and the gate dielectric layer. The charge storage layer includes a single-digit monolayer. The charge storage layer includes ScN. The growth of the channel layer and the growth of the barrier layer are performed in a sequential growth procedure. The step of growing the barrier layer includes interrupting the epitaxial growth after the barrier layer is formed and annealing the barrier layer at a temperature of the growth chamber so that the metal on the surface of the barrier layer evaporates. The method further includes forming a charge storage layer after growing the barrier layer and before growing the gate dielectric layer, the charge storage layer including a single-digit monolayer. Growing the gate dielectric layer includes controlling a nitrogen flow such that a V / III flux ratio is greater than 1. The method further includes depositing a metal layer for source / drain contacts and performing an annealing process to establish ohmic contact between the metal layer and the channel layer.Growing the gate dielectric layer includes annealing the wurtzite structure of the gate dielectric layer at a temperature higher than the temperature at which the wurtzite structure is grown. Growing the gate dielectric layer includes performing a non-sputter epitaxial growth procedure under nitrogen-rich conditions. The gate dielectric layer is grown at a growth temperature in the range of about 650 degrees Celsius or less. The channel layer, barrier layer, and gate dielectric layer are grown without removing the substrate from the reaction chamber.

[0009] For a more complete understanding of the present disclosure, reference should be made to the following detailed description and the accompanying drawings, in which like reference numerals identify like elements throughout. [Brief explanation of the drawings]

[0010] [Figure 1] (a) shows a schematic diagram of a transistor device having an epitaxial ScAlN / AlGaN / GaN ferroelectric HEMT device structure according to an example; (b) shows a method of fabricating a HEMT device structure according to an example; (c) shows an HAADF-STEM image of an example device captured from the gate stack region; (d) shows corresponding EDS mapping showing elemental distribution in the example device; and (e) shows a high magnification HAADF-STEM image showing atomic stacking at the heterostructure interface of an example device. [Figure 2] 1 shows graphical plots of (a) JV loop and (b) PV loop measured from an exemplary capacitor structure, with non-switching current contributions subtracted, and (c) shows PUND measurement results for the capacitor structure. [Figure 3] (a) shows a graphical plot of the logarithmic scale transfer characteristic of, for example, an epitaxial ferroelectric HEMT measured at different drain voltages, with the dashed curve being the corresponding gate current, and (b) shows a graphical plot of the linear scale transfer curve of the characteristic and the corresponding transconductance, with the curves scaled to better show the trend. [Figure 4]1 shows graphical plots of (a) transfer characteristics over different gate voltage scan ranges according to an example, illustrating Vth tuning due to ferroelectric switching of the barrier stack, and (b) output characteristics of an exemplary device after different poling voltages. [Figure 5] 10 shows a graphical plot of (a) transfer curves with different Vg steps according to an example, and (b) sub-threshold swing calculated according to the transfer curves showing steep slope behavior according to an example. [Figure 6] 1 is a flow diagram of a method for fabricating a transistor device having a ferroelectric gate dielectric layer, according to an example. [Figure 7] 1 illustrates (a) a schematic diagram of a transistor device having a ferroelectric gate dielectric layer according to an example, and (b) a graphical plot of an I-V curve showing the shift in threshold voltage (Vth) with increasing gate preset voltage (E-mode operation is achieved after presetting the gate voltage to 12V). DETAILED DESCRIPTION OF THE INVENTION

[0011] Embodiments of the disclosed devices and methods may assume a variety of forms. Specific embodiments are shown in the drawings and described below, with the understanding that the disclosure is intended to be illustrative. The disclosure is not intended to limit the invention to the specific embodiments described and illustrated herein.

[0012] A transistor device having a ferroelectric gate dielectric layer is described. The ferroelectric gate dielectric layer is disposed within a gate stack or other heterostructure of the transistor device in which a channel (e.g., a two-dimensional electron gas (2DEG) channel) is formed. The transistor device can therefore be configured as a high electron mobility transistor (HEMT) device. In some cases, the layers of the heterostructure are composed of or otherwise include III-nitride materials. A method for fabricating such a transistor device is also described, including epitaxial growth of the layers of the heterostructure. Full epitaxial growth (e.g., by molecular beam epitaxy, MBE) allows high-quality ferroelectric-dielectric gate stacks for steep-gradient III-nitride field-effect transistors to be realized.

[0013] As described below, the disclosed transistor device can be constructed as a ferroelectric transistor based on a fully epitaxial ScAlN / AlGaN / GaN heterostructure. The atomically sharp interface confirmed the high quality of the heterostructure. A clockwise hysteresis loop dominated by trapping and a counterclockwise hysteresis loop dominated by ferroelectric charge coupling were observed in the measured transfer characteristics. The threshold voltage tuning range was found to be highly dependent on the measurement conditions, indicating that channel pinch-off is coupled to ferroelectric switching. This coupling amplifies the controllability of the gate voltage, resulting in a subthreshold swing of less than 60 mV / dec when tuning the gate voltage from positive to negative. These results reveal a unique ferroelectric charge coupling in epitaxial ferroelectric / 2DEG heterostructures, thereby enabling the realization of ferroelectric-enhanced transistor devices.

[0014] The integration of ferroelectric gate dielectric layers and other semiconductor device layers can be useful in connection with a wide variety of device designs and applications. For example, the integration of ferroelectrics with high-electron-mobility transistors (HEMTs) can be used to fabricate nitride semiconductor-based memory devices, E-mode HEMT devices, and reconfigurable HEMT devices for functional and multi-domain electronics.

[0015] Ferroelectric gate dielectric layers can be used to provide reconfigurable devices, including devices that are reconfigurable during operation. Reconfigurability can be useful in a variety of ways, including, for example, reducing power consumption, reducing cost and chip space, and reducing chip complexity. For these and other purposes, reconfigurable devices can be programmed to operate under different modes.

[0016] In some cases, the heterostructures of the disclosed devices include one or more nitride layers, such as III-nitride semiconductor layers, which provide excellent radiation resistance and high-temperature stability, which can be useful in connection with a variety of devices and applications, including, for example, memory applications in which data is stored in harsh environments.

[0017] A ferroelectric gate dielectric layer may be used to provide ferroelectric coupling and / or a ferroelectric charge trapping gate stack, which may be used to adjust the threshold voltage (Vth) of a HEMT device. For example, in ferroelectric coupling, a positive Vth shift is established with the help of a negative gate bias, which polarizes the ferroelectric layer relative to the polarization of the barrier layer (e.g., an AlGaN layer) and compensates for the 2DEG in the channel. In an exemplary charge trapping scenario, a positive voltage is used to inject electrons into the gate stack, which are then trapped there, causing a positive shift in the threshold voltage. In reconfigurable memory applications, ferroelectric charge coupling can be expected due to trap instability. Therefore, the threshold voltage adjustment mechanism in an exemplary epitaxial heterostructure (e.g., an ScAlN / AlGaN / GaN heterostructure) is addressed.

[0018] The ferroelectric gate dielectric layer of the heterostructure of the disclosed device may be composed of or otherwise include a Sc-alloyed III-nitride material. Sc-alloyed III-nitride materials, such as ScAlN, have the same wurtzite structure as conventional III-nitride materials and possess large ferroelectric polarization and a large coercive field. The large polarization provides more design room for ferroelectric charge coupling, while the large coercive field provides good depolarization resistance. The use of a full epitaxial growth procedure to form the ferroelectric layer allows the ferroelectric layer to be grown on top of the III-nitride heterostructure. The resulting direct integration is useful for several reasons, including fewer defects, higher stability, and better tunability.

[0019] In one example, a ferroelectric HEMT device was fabricated based on an epitaxial ScAlN / AlGaN / GaN heterostructure grown by MBE. The ScAlN layer of the heterostructure had a thickness of approximately 27 nm, with a Sc content of approximately 30%. The AlGaN layer of the heterostructure was approximately 10 nm thick, with a Sc content of approximately 30%. The thickness and / or composition may vary in other examples. As described below, a clear hysteresis and a large threshold voltage tuning range of approximately 3.8 V were achieved with an on / off ratio of over 107. The device exhibited multiple distinct operating modes with different poling sequences. A voltage amplification effect due to ferroelectric switching was also observed, resulting in a subthreshold swing of less than 60 mV / dec. The example and other devices described herein may be useful in nonvolatile and reconfigurable RF and power electronics applications, as well as in memory devices and steep-gradient transistors.

[0020] Epitaxially grown Sc x Al 1-x Although described in connection with the example of an N layer, the disclosed methods and devices can be applied to a wide variety of nitride alloys (e.g., tantalum nitride (Ta3N5), ZnSi2N, and III-nitride alloys). Accordingly, the disclosed methods and devices may include or involve the incorporation of scandium into other III-nitride wurtzite structures. For example, the disclosed methods and devices may be applied to the incorporation of scandium into one or more epitaxially grown ScN layers. x Al y Ga 1-x-y Layer, Sc x Ga 1-x N layer, or Sc x In 1-xThe heterostructure may include or involve an N layer. The composition, structure, fabrication, and other characteristics of the heterostructure may also differ from the described examples. For example, the heterostructure may include additional or alternative epitaxially grown layers of ferroelectric and non-ferroelectric properties. The disclosed methods and devices are not limited to Group III nitride alloys containing scandium. For example, the Group III nitride alloy may include additional or alternative Group IIIB elements such as yttrium (Y) and lanthanum (La).

[0021] Although described in connection with examples having III-nitride-based layers, the disclosed methods and devices are not limited to heterostructures that include III-nitride semiconductor layers as buffers, channels, barriers, or other layers or components of heterostructures or devices. Other semiconductor materials may be used, including, for example, GaAs, InP, and alloys thereof. Still other types of materials may alternatively or additionally be used in heterostructures, including, for example, two-dimensional transition metal dichalcogenides, oxide materials (e.g., gallium oxide or gallium oxide-based materials), diamond, silicon carbide, and silicon.

[0022] Although some aspects of the disclosed methods are described in connection with MBE growth procedures, additional or alternative non-sputter epitaxial growth procedures may be used. For example, metalorganic chemical vapor deposition (MOCVD) and hydride vapor phase epitaxy (HVPE) growth procedures may be used. Still other procedures may be used, including, for example, pulsed laser deposition procedures.

[0023] 1(a) shows a schematic diagram of a HEMT device 100 having an ScAlN / AlGaN / GaN ferroelectric heterostructure 102 according to one example. In this example, the entire heterostructure 102 was epitaxially grown on a commercially available semi-insulating GaN / sapphire template 104 in a Veeco GENxplor MBE system. The epilayers of the heterostructure 102 consist of undoped GaN with a thickness of about 120 nm, AlGaN with a thickness of about 10 nm, and AlGaN with a thickness of about 10 nm. 0.3 Ga 0.7N, and Sc with a thickness of about 27 nm 0.3 Al 0.7 N, and the channel carrier concentration and mobility are 8.2 × 10 cm -2 and 1025 cm / (V / s).

[0024] Part (b) of FIG. 1 illustrates the steps of the device fabrication method used to fabricate the exemplary device 100. In this case, photoresist was deposited and patterned for source-drain contacts 106, followed by a slight etch of approximately 25 nm by inductively coupled plasma (ICP). A Ti / Al / Ni / Au metal stack was then deposited, lifted off, and annealed at 600° C. for 5 minutes in a N ambient to form the source-drain contacts 106. A deep ICP etch (e.g., approximately 220 nm) is then performed to define mesa isolation and device regions. The fabrication also includes gate deposition (e.g., Ni / Au deposition) and lift-off to form the gate contact 108. In the example characterized herein, the gate length and width are 5 μm and 10 μm, respectively, and the source-drain distance is approximately 20 μm. These and other device dimensions may vary in other cases.

[0025] Parts (c)-(e) of Figure 1 show high-resolution TEM images of the heterostructure 102. Part (c) of Figure 1 shows a HAADF-STEM image captured from the gate stack region, showing the abrupt, sharp, and clean interfaces between the ScAlN gate dielectric layer 110, the AlGaN barrier layer 112, and the undoped GaN layer 114. The corresponding energy dispersive spectroscopy (EDS) maps of Ga, Al, Sc, N, O, Ni, and Au elements are shown in part (d) of Figure 1, confirming the chemical composition of each layer.

[0026] In this example, a thin native oxide layer exists on the ScAlN surface, primarily due to the large oxygen affinity for both Sc and Al. This layer does not affect device performance except by acting as an additional thin dielectric layer. In other cases, no oxide layer is present.

[0027] To confirm the epitaxial relationship, we took a high-magnification HAADF-STEM image of the ScAlN / AlGaN / GaN stacked region (Figure 1(e)). The epitaxially grown ScAlN layer 110 inherits the wurtzite atomic stacking order from the AlGaN layer 112 and the GaN layer 114. Furthermore, the entire heterostructure has atomically sharp interfaces (labeled as dashed lines 116 and 118 in part (e) of Figure 1). The transition regions between layers 110, 112, and 114 are only about one to two monolayers thick, benefiting from the atomic-scale thickness controllability of MBE growth. The 2DEG formed in the GaN channel near the AlGaN barrier layer 112 is indicated by dashed line 120 in Figure 1(e).

[0028] Next, the ferroelectric properties of the ferroelectric semiconductor test structure are described. The test structure consists of a metal layer, a 27 nm Sc 0.3 Al 0.7 The first layer is a 27 nm thick Sc layer. 0.3 Al 0.7 An N layer was grown on the n-GaN layer. In this case, the n-GaN layer had a 1×10 19 cm -3 The test structure contains a metal-ferroelectric-semiconductor configuration to study the intrinsic ferroelectric properties of the ScAlN layer.

[0029] Parts (a) and (b) of Figure 2 show the current-voltage (JV) and polarization-voltage (PV) characteristics of the test structure measured using a triangular waveform after subtracting the non-switching current. Part (c) of Figure 2 shows the current-voltage (JV) and polarization-voltage (PV) characteristics of the test structure measured using a triangular waveform after subtracting the non-switching current. 2 We further present positive-up-down-negative-down (PUND) measurements demonstrating a remanent polarization of . This giant switchable polarization is a hallmark of emerging nitride ferroelectrics and may be useful, for example, to significantly enhance polarization engineering in nitride-based heterostructures and devices.

[0030] We now address the hysteretic transfer characteristics of an exemplary HEMT device.

[0031] Figure 3 shows the measured transfer characteristics of a HEMT device with an ScAlN / AlGaN / GaN heterostructure. Both forward sweep (gate voltage Vg from negative to positive) and reverse sweep (Vg from positive to negative) curves are captured to demonstrate the hysteresis induced by ferroelectric switching. During the measurements, the drain voltage was varied to adjust the electric field profile in the channel. Overall, the transfer curves show a clear and significant counterclockwise hysteresis, indicating successful ferroelectric coupling of the ScAlN gate dielectric. However, a small clockwise hysteresis region can be observed near the forward threshold voltage (Vth). Under a large positive bias, electrons are injected and trapped in the barrier layer, as evidenced by a dramatic increase in gate current, causing a positive shift in Vth when Vg is swept from positive to negative. As the channel begins to deplete, electrons in the barrier layer are released, and the classic counterclockwise hysteresis associated with ferroelectric charge coupling reappears. Optimizing the growth conditions can reduce the effects of trapping and detrapping processes. It should also be noted that the Vth tuning range is highly dependent on the drain voltage (Vd) during measurement, with a maximum value of approximately 3.8 V when Vd = 0.5 V, indicating that channel depletion during reverse scanning begins from the drain side. Due to the high-quality epitaxial gate stack, the device exhibits gate-leakage-limited off-current and yields a maximum on / off ratio of 3 × 107. The linear-scale transfer curve and corresponding transconductance are further plotted in part (b) of Figure 3. Fine tuning of the threshold voltage Vth and transconductance may be useful in reconfigurable radio frequency (RF), memory, and other devices.

[0032] The device also exhibited gate-voltage-dependent hysteresis and output characteristics. To investigate the ferroelectric charge coupling in the gate stack, we measured the transfer characteristics over different positive gate voltage scan ranges. As shown in Figure 4(a), the transfer curve exhibits negligible hysteresis when the maximum positive gate voltage Vg is less than 2 V, indicating that ferroelectric switching does not occur at this stage. Further increasing the maximum positive gate voltage Vg gradually switches the polarity of the ferroelectric ScAlN layer to the same direction as the AlGaN and GaN layers, resulting in an increase in the 2DEG density in the channel and a negative shift in the threshold voltage Vth during the reverse scan, as shown in Figure 4(a). When the gate voltage Vg exceeds 6 V, the gate leakage current increases sharply.

[0033] Part (b) of Figure 4 shows the output characteristics when the gate voltage Vg is scanned from 0 V to -6 V in steps of -1 V after switching the polarity of the ScAlN layer to opposite (blue, or darker gray) or parallel (red, or lighter gray) to the polarity of the AlGaN / GaN layer. The nonvolatile feature of ferroelectric polarization results in two separate programmable output curves, which may be useful for realizing nonvolatile reconfigurable ferroelectric HEMTs and other devices.

[0034] Steep subthreshold swing from ferroelectric gate voltage amplification In ferroelectric HEMTs, the channel carrier concentration is co-determined by the polarization of the ferroelectric layer and the polarization discontinuity at the AlGaN / GaN interface. When the polarity of the ferroelectric layer is switched to be opposite to that of the AlGaN and GaN layers, the ferroelectric polarization helps to deplete the 2DEG in the channel. When the polarity of the ferroelectric layer is switched to be parallel to that of the AlGaN and GaN layers, the polarization of the ferroelectric layer helps to attract electrons and increase the 2DEG density in the channel. This enhanced modulation of the 2DEG from the ferroelectric polarization amplifies the controllability of the gate and leads to improved subthreshold performance.

[0035] Figure 5 shows the transfer characteristics and extracted subthreshold swing (SS) values ​​with different V steps for one example. SS values ​​of less than 250 mV / dec were obtained for the forward scan, which is smaller than most conventional HEMT structures and can be attributed to the large dielectric constant of the ScAlN layer. In contrast, SS values ​​obtained for the reverse scan were even smaller, and a wide, steep window with SS values ​​less than 60 mV / dec was observed, clearly demonstrating ferroelectric switching amplification gate voltage control. During the reverse scan, ferroelectric switching begins at approximately 6 V, which is thought to reverse the polarity of the ScAlN layer relative to the polarity of the AlGaN / GaN layer, resulting in abrupt depletion of the 2DEG.

[0036] During the measurements, the measurement time for each gate voltage Vg step was the same. In this case, the smaller the gate voltage Vg step, the longer the total poling time, resulting in a smaller hysteresis window, which is consistent with our results. The wide, stable, and steep-slope operation of the exemplary epitaxial ferroelectric HEMT device may be useful for realizing high-performance transistor devices.

[0037] The Sc content, thickness, and other properties of the wurtzite phase ScAlN layers of the disclosed devices and methods can be taken from the examples described herein. For example, the Sc content, x, can vary from about 0.05 to about 0.5 in some cases. However, the Sc content can be outside this range.

[0038] The disclosed devices and methods may include one or more elements, aspects, or other features described in International Application No. PCT / US2022 / 028365, filed May 9, 2022, published as WO2023 / 022768, and entitled "Epitaxial Nitride Ferroelectronics," the entire disclosure of which is incorporated herein by reference.

[0039] 6 illustrates a method 600 for fabricating a transistor device having a heterostructure with a ferroelectric gate dielectric layer, according to one example. Method 600 may be used to fabricate the example devices and / or other devices described herein.

[0040] Method 600 may begin at act 602, where a substrate is prepared and / or otherwise provided. In some cases, act 602 includes providing a sapphire substrate in act 604. Alternative or additional materials may be used, including, for example, silicon, bulk GaN, bulk AlN, or other semiconductor materials. Still other materials may be used, including, for example, silicon carbide. The substrate may be cleaned in act 606. In some cases, native or other oxide layers may be removed from the substrate surface in act 608. In other cases, additional or alternative processing may be performed, including, for example, doping or deposition procedures. Thus, the substrate may or may not have a uniform composition. The substrate may be a uniform or composite structure.

[0041] In operation 610, one or more buffer layers are provided. Each buffer layer is supported by a substrate. In some cases, the layers are provided along with the substrate. Thus, operation 610 may be performed prior to (e.g., in preparation for) performing an epitaxial growth procedure in which some epitaxial layers of the heterostructure are formed. In other cases, the buffer layer(s) are formed (e.g., grown or deposited) on a substrate. The layers may or may not be in contact with the substrate. The buffer layer(s) may or may not act as a growth template for one or more layers of the heterostructure.

[0042] In some cases, the layer is composed of or includes a semiconductor material. For example, a III-nitride layer, such as a semi-insulating GaN layer, can be grown or otherwise formed on a substrate. As noted above, other compounds or other semiconductor materials can be used, including, for example, AlGaN and non-III-nitride materials. In this manner, a heterostructure can be formed on the semiconductor layer.

[0043] In some cases, act 610 may include growing the semiconductor layer in an epitaxial growth chamber in which the epitaxial growth procedure for the heterostructure is performed. As a result, the substrate can remain in the epitaxial growth chamber, e.g., not be removed from the epitaxial growth chamber, between forming the semiconductor layer and performing the epitaxial growth procedure for growing the wurtzite structure.

[0044] In step 612, a channel layer of the heterostructure is grown. In some cases, the channel layer is composed of or includes undoped GaN. Additional or alternative materials may be used, including other III-nitride and non-III-nitride materials. The channel layer may be grown by performing an epitaxial growth procedure, such as MBE, used to grow the layers of the heterostructure.

[0045] In step 614, a barrier layer of the heterostructure is grown. In some cases, the barrier layer is composed of or includes AlGaN. Additional or alternative materials may be used, including other III-nitride and non-III-nitride materials. The epitaxial growth procedure used to grow the channel layer may be continued to grow the barrier layer (e.g., a sequential growth procedure). Thus, the substrate may remain in the same growth chamber during acts 612 and 614.

[0046] After growth of the barrier layer, operation 614 can include one or more operations in preparation for growth of the ferroelectric gate dielectric layer. In the example of FIG. 6, growth is interrupted in operation 616. The growth interruption can include closing one or more shutters of the growth chamber. Then, in operation 618, the temperature of the growth chamber can be increased to anneal the barrier layer to a level where the metal on the surface of the barrier layer evaporates. Such removal of metal atoms along the surface can help improve the quality of the ferroelectric gate dielectric layer.

[0047] In step 620, a ferroelectric gate dielectric layer is grown. As described herein, the ferroelectric gate dielectric layer may be composed of or otherwise include an alloy of III-nitride materials. For example, the III-nitride material may be AlN. Additional or alternative III-nitride materials may be used, including, for example, gallium nitride (GaN), indium nitride (InN), and alloys thereof. As also described herein, the epitaxial growth procedure is performed and configured to incorporate scandium and / or another IIIB element into the alloy of III-nitride materials. Thus, the alloy may include, for example, Sc x Al 1-x N. In some cases, operation 620 includes operation 622 in which an MBE procedure is performed. In other cases, an MOCVD or other non-sputter epitaxial growth procedure is performed.

[0048] Act 620 can form part of a series or sequence of growth procedures used to form other layers of the heterostructure. The growth procedures can be performed in a common or same growth chamber without removal therefrom. Thus, act 620 can include act 624, in which epitaxial growth continues in the same chamber. Thus, successive layers of the heterostructure can be grown without exposure to the ambient. Thus, the quality of the interfaces between the layers can be improved.

[0049] The growth temperature may be at a level such that the ferroelectric layer has a wurtzite structure that exhibits a breakdown field strength greater than the ferroelectric coercivity of the wurtzite structure, and therefore the gate dielectric layer can exhibit ferroelectric switching and other behaviors.

[0050] In some cases, the growth temperature is lower than expected given the III-nitride material. In some instances, the growth temperature level is significantly lower than the temperature at which III-nitride materials are typically grown. For example, the growth temperature level may be such that attempting to grow a structure made of III-nitride material (i.e., scandium-free) at that growth temperature level is not worthwhile. The resulting structure would be of poor quality (e.g., have too many defects) to be useful. Nevertheless, growth of a single crystal (e.g., a single crystalline layer of the alloy) of a scandium-containing alloy at the growth temperature level can be achieved. For example, in some cases, Sc x Al 1-x The N alloy may be epitaxially grown at a growth temperature of about 650°C or about 750°C, even though the corresponding (scandium-free) III-nitride material, AlN, is conventionally grown at much higher temperatures, e.g., about 1000°C. Conversely, attempts to grow AlN at about 650°C, about 750°C, or temperatures below about 650°C or 750°C result in such poor structure that it is useless. In contrast, epitaxially grown ScN grown at such low temperatures or even lower temperatures x Al 1-x The N layer is unexpectedly single crystalline and of high quality.

[0051] Low growth temperatures may be applied when the nitrogen-to-metal (V / III) flux ratio is slightly or moderately nitrogen-rich. For example, the V / III flux ratio may range from about 1:1 to about 2:1. In other cases where the nitrogen-to-metal flux ratio is highly unbalanced, i.e., in the extremely N-rich regime as described herein, the growth temperature may be higher. For example, the V / III flux ratio may be greater than about 2:1. In such highly unbalanced cases, the growth temperature may be at a level that includes and / or otherwise falls within a range of temperatures at which III-nitride materials (i.e., scandium-free) would typically be grown.

[0052] Highly unbalanced, very N-rich conditions can be used in conjunction with the formation of the wurtzite structure by sputter deposition. x Al 1-x The aforementioned deficiencies presented by past efforts using sputtering to achieve ferroelectric layers such as N layers are avoided as a result of the use of highly unbalanced, extremely N-rich conditions.

[0053] For slight to moderate imbalances in N-richness, the Sc content at conventional AlN growth temperatures (and other temperatures beyond the upper limit) is x Al 1-x The growth of the N layer was unexpectedly x Al 1-x This leads to the formation of dislocations and / or other leakage paths in the NScxAl1-xN layer. x Al 1-x The breakdown field strength level of the N layer is too low (e.g., below the ferroelectric coercivity level), and therefore this layer does not exhibit ferroelectric behavior.

[0054] In some cases (e.g., for a slightly to moderately unbalanced N-rich case), the growth temperature may be about 650°C or less or about 750°C or less. The growth temperature may correspond to the temperature measured by a thermocouple in the growth chamber. The growth temperature at the epitaxial surface may be slightly different. Therefore, the growth temperature is approximated via the temperature measurement by the thermocouple.

[0055] The upper limit of the growth temperature range for slightly to moderately imbalanced N-rich cases may vary depending on the alloy and / or epitaxial growth technique. For example, for other slightly to moderately imbalanced N-rich cases, the upper limit of the growth temperature may be higher, such as about 680°C or about 690°C. For still other slightly to moderately imbalanced N-rich cases, the upper limit may be lower, including, for example, about 600°C or about 620°C.

[0056] The growth temperature may vary if other process parameters differ from those described above. For example, a higher growth temperature may be used when the nitrogen-to-metal flux ratio is highly or extremely unbalanced, as described below. The nitrogen-to-metal flux ratio may be set in operation 626, in which the nitrogen flow is controlled. In some cases, the non-balanced flux ratio may be set to highly or extremely nitrogen (N)-rich conditions, such as a nitrogen-to-metal flux ratio of 2 to 1 or greater. In such cases, the growth temperature may fall within a range corresponding to the temperatures for growing other III-nitride layers of the device, for example, in operations 612 and 614. For example, a growth temperature of about 1000 degrees Celsius may be used. In other examples of highly or extremely N-rich growth conditions, a lower growth temperature may be used, for example, a growth temperature in the range of about 600°C to about 1000°C, as in the example above.

[0057] Controlling the flux ratio between the metal source and the nitrogen source is important, e.g., for Sc x Al 1-x This may be useful for improving the material quality of N-containing nitride semiconductors. In conventional III-nitrides, slightly metal-rich growth conditions are often used to improve the surface morphology, interface control, and crystal quality during the MBE growth process. However, based on the Sc-Al-N phase diagram, N-rich growth conditions are more favorable for the growth of ScAlN to avoid the formation of Sc-Al intermetallic phases and ScAlN perovskite phases. Depending on whether the film is grown under N-poor or N-rich conditions, the amount of cation vacancies (V) can be significantly increased. cationThe formation energy levels of defects such as SiO2 (SiO2) and nitrogen vacancies (VN) may be different, which may further affect the electrical properties including, for example, leakage current and breakdown strength.

[0058] Such highly N-rich growth conditions can be used in conjunction with MBE, MOCVD, and other epitaxial growth processes. Highly N-rich growth conditions can also be utilized in conjunction with films formed by sputter deposition.

[0059] At each level within the preferred growth temperature range, the resulting wurtzite structure is single crystalline. x Al 1-x The N-layer is single-crystalline to a degree that is not achievable by sputtering-based procedures. Such procedures can only produce structures with X-ray diffraction rocking curve linewidths of a few degrees at best. In contrast, structures grown by the disclosed method exhibit X-ray diffraction rocking curve linewidths on the order of hundreds of arc-seconds or less, which is well over an order of magnitude. In this way, leakage current paths are minimized or otherwise sufficiently reduced so that the resulting wurtzite structure has an appropriately high breakdown field strength level, e.g., a breakdown field strength level significantly greater than the ferroelectric coercivity.

[0060] The above-mentioned differences in crystalline quality as evidenced by X-ray diffraction rocking curve linewidths can also be used to distinguish between single-crystalline and polycrystalline structures. As used herein, the term "polycrystalline" refers to a structure having an X-ray diffraction rocking curve linewidth on the order of a few degrees or more. As used herein, the term "single-crystalline" refers to a structure having an X-ray diffraction rocking curve linewidth that is at least an order of magnitude smaller than a few degrees.

[0061] When comparing the wurtzite structure of layers grown by MBE or other non-sputtering techniques (e.g., MOCVD or HVPE) with that of sputtering deposition techniques, the microstructure of the former technique is more uniform, with a highly ordered stacking arrangement of atoms. In sputter-deposited layers, domains with cubic phase or in-plane misorientation are readily observed. The presence of these misaligned domains inhibits complete polarization switching and even leads to rapid loss of polarization during fatigue testing. With regard to phase purity, the highly crystallographic orientation of layers grown by MBE or other non-sputtering techniques exhibits more repeatable ferroelectric switching, which is useful in many device applications.

[0062] The ferroelectric layer can then be annealed in operation 630. The annealing can be performed at a temperature higher than the growth temperature. In some cases, the annealing temperature ranges from about 700°C to about 1500°C. Example films prepared with such annealing have demonstrated stable polarization switching with further reduced leakage current compared to unannealed films. The uniformity of the film or device is also improved by annealing, thereby further improving the polarization switching behavior of the ferroelectric Sc-III-N alloy. The underlying mechanism for improved performance and uniformity with annealing is attributed to a reduction in threading dislocation and defect densities, which typically act as electrical leakage paths. This utility of post-growth annealing is realized despite past concerns that high processing temperatures could result in loss of ferroelectric properties.

[0063] Sc x Al 1-x Such post-growth high temperature annealing of N can be performed in situ in the same growth chamber (e.g., the same MBE chamber) in act 632. In other cases, the annealing is performed ex situ in a chamber dedicated to the annealing procedure.

[0064] The annealing process may be carried out under high vacuum (e.g., in situ in the growth chamber) in act 634. In other cases, the annealing may be carried out using nitrogen plasma irradiation or under nitrogen gas flow in act 636.

[0065] The annealing procedure described above can be performed in connection with films grown under any of the growth conditions described above. For example, the annealing procedure may be performed after growth under slightly to moderately N-rich conditions at a growth temperature of about 650° C. or less, or about 750° C. or less. The annealing procedure may also be performed after growth under other non-equilibrium flux ratios (e.g., N-rich or extremely N-rich conditions) at a growth temperature above about 650° C. or above about 750° C.

[0066] Method 600 may include act 638, in which source and drain regions are defined and etched after growth of the wurtzite structure. Operation 638 may include performing a plasma etching procedure, although alternative or additional etching procedures may be used.

[0067] One or more metal layers may then be deposited in act 640. A lift-off step may then be performed to form source and drain regions in the areas defined in step 638. The composition and other properties of the source and drain regions may vary.

[0068] Method 600 may include performing an annealing procedure in act 642. The annealing process may be configured to form ohmic contacts between the metal layer of the source / drain regions and the channel layer.

[0069] 6, the device region (e.g., a mesa) is defined and etched in operation 644. The gate region is defined in operation 646, and one or more metal layers are deposited in operation 648. A lift-off procedure can then be performed to define the gate.

[0070] Method 600 may include one or more additional operations. For example, one or more acts may be directed to forming additional layers of a heterostructure of additional components of the device. For example, one or more operations may be configured to form additional metal layers for interconnects and / or other connections. The nature of the regions or structures may vary according to the nature of the device.

[0071] The order of operations in method 600 may differ from the example shown in Figure 6. For example, one or more annealing operations may be performed at different points in the manufacturing process.

[0072] Several different types of devices can be fabricated by the method 600 of FIG. 6 and / or other methods of fabricating heterostructures having a wurtzite structure of alloys of III-nitride materials incorporating scandium. For example, the ferroelectric Sc x Al 1-x N or other alloys may be useful in various types of nonvolatile memory devices (e.g., FeRAM, FeFET, FTL, and FeSFET devices), various types of reconfigurable electronic and other devices (e.g., Fe-HEMT, Fe-capacitor, and SAW devices), various types of photodetection, photovoltaic, and optoelectronic devices (e.g., self-powered photodetectors and solar cell devices), and various homojunction devices (e.g., devices that use laterally distributed charge plates to tune the Fermi levels of adjacent layers). Still other types of devices can be fabricated, including, for example, Fe-based thin film bulk acoustic wave resonator (FBAR) devices.

[0073] FIG. 7 illustrates a ferroelectric HEMT device 700 according to one example. The device 700 may have one or more layers, regions, components, or other elements in common with one or more of the devices described above. In this case, the device 700 has a charge storage (or trapping) layer 702 disposed between a ferroelectric gate dielectric layer 704 and a barrier layer 706. The charge storage layer 702 may include a monolayer of ScN. The ScN monolayer acts as a charge storage layer by capturing electrons injected from a gate electrode 708. The trapped electrons result in a higher potential across the barrier layer 706, which causes a right shift in the threshold voltage and enables enhancement mode operation. For example, this approach of using a monolayer ScN as a charge trapping layer serves as an alternative (or additional) method for stabilizing or otherwise providing enhanced mode operation in Fe-HEMT devices (e.g., separate from ferroelectric polarization).

[0074] The thickness of the charge storage layer 702 may vary. For example, in some cases, several monolayers may be provided. In the example of Figure 7, the charge storage layer 702 may have one or two monolayers.

[0075] The charge storage layer 702 is formed after the growth of the barrier layer 706 and before the growth of the ferroelectric gate dielectric layer 704. For example, the charge storage layer 702 can be formed during the transition between the epitaxial growth of the ferroelectric gate dielectric layer 704 and the epitaxial growth of the barrier layer 706. For example, in some cases, the charge storage layer 702 is formed during or at the end of the growth interruption act 616 ( FIG. 6 ). For example, the growth interruption act 616 can include a period during which the Sc shutter is opened after the Al and Ga shutters are closed. Alternatively or additionally, the formation of the charge storage layer 702 may be performed before the growth interruption act 616.

[0076] The composition of the charge storage layer 702 may differ from the example of Figure 7. For example, other nitride semiconductor materials may be used. For example, the composition of the charge storage layer 702 may vary according to the composition (e.g., group IIIB element) of the gate dielectric layer 704.

[0077] As shown in Figure 7(b), poling the gate to a more positive voltage gradually increases the threshold voltage due to the increased trapped electron density. Using a negative gate voltage, the threshold voltage can be further programmed back to its initial state, which may be useful in conjunction with reconfigurable Fe-HEMT devices, for example, by adding more design room.

[0078] The above is an example of a ferroelectric transistor based on a fully epitaxial ScAlN / AlGaN / GaN heterostructure. The example shows atomically sharp interfaces, confirming the high quality of the heterostructure. A counterclockwise hysteresis loop induced by ferroelectric charge coupling was successfully demonstrated in the measured transfer characteristics. The threshold voltage tuning range was found to be highly dependent on the measurement conditions, with a maximum tuning range of approximately 3.8 V, demonstrating the giant channel carrier modulation effect of ferroelectric switching. This modulation also helps amplify the controllability of the gate voltage, resulting in a subthreshold swing of less than 60 mV / dec when tuning the gate voltage from positive to negative. These results reveal fundamental ferroelectric charge coupling in epitaxial ferroelectric / 2DEG heterostructures and enable the fabrication of ferroelectric-enhanced transistors.

[0079] Although the present disclosure has been described with reference to particular embodiments, these embodiments are merely illustrative and do not limit the present disclosure. Modifications, additions, and / or deletions can be made to the embodiments without departing from the spirit and scope of the present disclosure.

[0080] The foregoing description is given for clarity of understanding only, and no unnecessary limitations should be understood therefrom.

Claims

1. 1. A transistor device comprising: A substrate; a heterostructure supported by the substrate; The heterostructure comprises: a buffer layer supported by the substrate; a channel layer supported by the buffer layer; a barrier layer supported by the channel layer; a gate dielectric layer supported by the barrier layer and comprising a ferroelectric nitride alloy containing a Group IIIB element.

2. The transistor device of claim 1 , wherein the ferroelectric nitride alloy has a switchable polarization in an out-of-plane direction.

3. The transistor device of claim 1 , wherein the barrier layer is configured to function as a dielectric layer such that the transistor device has a bilayer gate dielectric structure.

4. The transistor device of claim 1 , wherein the barrier layer comprises a III-nitride alloy.

5. The transistor device of claim 1 , wherein the barrier layer and the channel layer have different bandgaps.

6. The transistor device of claim 1 , wherein the gate dielectric layer is single crystalline.

7. The transistor device of claim 1 , wherein the gate dielectric layer has a wurtzite structure.

8. The transistor device of claim 1 , wherein the buffer layer comprises a III-nitride semiconductor material.

9. The transistor device of claim 1 , wherein the channel layer comprises a III-nitride semiconductor material.

10. The transistor device of claim 1 , wherein the barrier layer comprises a III-nitride semiconductor material.

11. The transistor device of claim 1 , wherein the gate dielectric layer comprises ScAlN.

12. The transistor device of claim 1, wherein the gate dielectric layer has a scandium content ranging from about 0.05 to about 0.

5.

13. the buffer layer is in contact with the channel layer, the channel layer is in contact with the barrier layer, The transistor device of claim 1 , wherein the gate dielectric layer is in contact with the barrier layer.

14. The transistor device of claim 1 , wherein the barrier layer and the channel layer define an interface such that a channel is formed in the channel layer.

15. The transistor device of claim 1 , wherein the III-nitride alloy is configured such that there is no metal present at a surface of the barrier layer that contacts the gate dielectric layer.

16. The transistor device of claim 1 , wherein the heterostructure further comprises a charge storage layer disposed between the barrier layer and the gate dielectric layer.

17. 17. The transistor device of claim 16, wherein the charge storage layer comprises a single-digit number of monolayers.

18. The transistor device of claim 16 , wherein the charge storage layer comprises ScN.

19. 1. A method of fabricating a transistor device, comprising: providing a buffer layer supported by a substrate; epitaxially growing a channel layer supported by the buffer layer; epitaxially growing a barrier layer supported by the channel layer; growing a gate dielectric layer supported by the barrier layer; The method, wherein the gate dielectric layer comprises a Group III-nitride ferroelectric alloy, the Group III-nitride ferroelectric alloy comprising a Group IIIB element.

20. 20. The method of claim 19, wherein the steps of growing the channel layer and growing the barrier layer are performed in a sequential growth procedure.

21. The step of growing the barrier layer includes, after forming the barrier layer, interrupting the epitaxial growth; 20. The method of claim 19, further comprising annealing the barrier layer at a temperature of a growth chamber so that metal on the surface of the barrier layer evaporates.

22. 20. The method of claim 19, further comprising forming a charge storage layer after growing the barrier layer and before growing the gate dielectric layer, the charge storage layer comprising single digit monolayers.

23. 20. The method of claim 19, wherein growing the gate dielectric layer comprises controlling a nitrogen flow such that a V / III flux ratio is greater than 1.

24. depositing a metal layer for source / drain contacts; 20. The method of claim 19, further comprising: performing an annealing process to establish an ohmic contact between the metal layer and the channel layer.

25. 20. The method of claim 19, wherein growing the gate dielectric layer comprises annealing the wurtzite structure of the gate dielectric layer at a temperature higher than the temperature at which the wurtzite structure grows.

26. 20. The method of claim 19, wherein growing the gate dielectric layer comprises performing a non-sputter epitaxial growth procedure under nitrogen-rich conditions.

27. 20. The method of claim 19, wherein the gate dielectric layer is grown at a growth temperature in the range of about 650 degrees Celsius or less.

28. 20. The method of claim 19, wherein the channel layer, the barrier layer, and the gate dielectric layer are grown without removal from a reaction chamber.

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