Uniform silicon germanium channels in nanosheet architectures

Abstract

A horizontal gate-all-around device and fabrication method are described. The horizontal gate-all-around device includes a semiconductor material between the source and drain regions of the device. The method includes forming a cladding material on a first material and then forming a tensile film on the cladding layer. The strained tensile film results in a uniform SiGe channel.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments of the present disclosure relate generally to semiconductor devices, and more particularly to horizontal gate-all-around device structures and methods and apparatus for forming horizontal gate-all-around device structures. [Background technology]

[0002]

[0002] Transistors are key components of most integrated circuits. A transistor's drive current, and therefore its speed, is proportional to its gate width, so faster transistors generally require larger gate widths. Therefore, there is a trade-off between transistor size and speed, and to address the conflicting goals of transistors with maximum drive current and minimum size, "fin" field-effect transistors (FinFETs) have been developed. FinFETs feature a fin-shaped channel region that significantly increases the size of transistors without significantly increasing the transistor's footprint, and are currently being applied in many integrated circuits. However, FinFETs also have drawbacks.

[0003]

[0003] As transistor device feature sizes continue to shrink to achieve increased circuit density and higher performance, improved transistor device structures are needed to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and horizontal gate-all-around (hGAA) structures. The hGAA device structure includes several lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. The inventors believe that the hGAA structure provides good electrostatic control and can be widely adopted in complementary metal-oxide-semiconductor (CMOS) wafer fabrication.

[0004]

[0004] The performance of logic gates is related to the properties of the materials used and the thickness and area of ​​the structural layers. However, tailoring some gate properties to accommodate device scaling presents challenges. Furthermore, space limitations between wires on horizontal gate-all-around (hGAA) devices limit the thickness of the gate dielectric material for I / O transistors.

[0005]

[0005] Silicon germanium (SiGe) channels are one of the attractive features for gate-all-around (GAA) (nanowire or nanosheet) designs to achieve high-mobility PMOS. One approach is to form a uniform SiGe layer around a silicon nanosheet and then continue the gate stack process. This improves performance, but reduces the compressive strain in the channel, which does not fully demonstrate the benefits of the SiGe channel. In planar technology, SiGe PFET channels have been mass-produced by so-called condensation. In this approach, the SiGe layer is oxidized at high temperatures, typically above 1000°C, which is sufficient to consume the SiGe layer and diffuse the Ge to obtain a uniform SiGe film. However, conventional condensation at 1000°C is too high for GAA architectures. For example, dopants at the junctions diffuse, degrading device performance.

[0006] Therefore, there is a need for improved methods for forming PMOS electronic devices. Summary of the Invention

[0007]

[0007] One or more embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one embodiment, the method includes selectively etching a superlattice structure on a substrate, the superlattice structure comprising a plurality of first layers of a first material and a plurality of second layers of a corresponding second material arranged alternately in a plurality of stacked pairs extending between a source region and a drain region, selectively etching the superlattice structure removing each of the plurality of second layers to form a plurality of voids in the superlattice structure and a plurality of nanosheets comprising the plurality of first layers, forming a cladding material around each of the plurality of nanosheets comprising the plurality of first layers, forming a tensile film around the cladding material, the tensile film having a tensile stress and imparting a tensile strain to the plurality of nanosheets, optionally curing the tensile film, heat-treating the plurality of nanosheets, and removing the tensile film to form the plurality of nanosheets of cladding material.

[0008] Further embodiments are directed to an electronic device. In one embodiment, the electronic device comprises a PMOS with a uniform SiGe channel between its source and drain regions, and an NMOS with a Si channel between its source and drain regions.

[0009]

[0009] So that the features of the present disclosure described above may be understood in detail, a more particular description of the present disclosure briefly summarized above will be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure, which may also admit of other equally effective embodiments. [Brief explanation of the drawings]

[0010] [Figure 1]

[0010] FIG. 1 is a process flow diagram of a method for forming a semiconductor device according to some embodiments of the present disclosure. [Figure 2]

[0011] FIG. 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 3]

[0012] FIG. 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 4]

[0013] FIG. 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 5]

[0014] FIG. 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 6]

[0015] FIG. 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 7]

[0016] FIG. 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 8]

[0017] FIG. 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 9]

[0018] FIG. 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 10]

[0019] FIG. 1 is a cross-sectional view of a device according to one or more embodiments. [Figure 11]

[0020] FIG. 1 is a schematic diagram of a cluster tool in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0021] To facilitate understanding, where possible, the same reference numerals have been used to designate identical elements that are common to multiple figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further description.

[0012]

[0022] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0013]

[0023] The term "substrate," as used herein and in the appended claims, refers to a surface or portion of a surface upon which a process acts. Those skilled in the art will also understand that a reference to a substrate may refer to only a portion of a substrate, unless the context clearly dictates otherwise. Furthermore, a reference to deposition on a substrate may refer to both a bare substrate and a substrate upon which one or more films or features have been deposited or formed.

[0014]

[0024] As used herein, the term "substrate" refers to any substrate or any material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film treatment directly on the surface of the substrate itself, the present disclosure also provides that any of the disclosed film treatment steps may be performed on an underlying layer formed on the substrate, as disclosed in more detail below. The term "substrate surface" is intended to include an underlying layer as the context indicates. Thus, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0015]

[0025] The term "on" indicates that there is contact between elements, although there may be intervening elements or layers. The term "directly on" indicates that there is direct contact between elements, with no intervening elements.

[0016]

[0026] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably and refer to any gas species capable of reacting with the substrate surface.

[0017]

[0027] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors may be formed on the semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped substrate regions and exhibit a doping profile suitable for a particular application. The gate is disposed on the channel region and includes a gate dielectric interposed between the gate electrode in the substrate and the channel region. In one or more embodiments, the gate surrounds all of the nanosheets between the bottom substrate and the channel.

[0018]

[0028] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement-mode field-effect transistors generally display very high input impedance at low temperatures. Conductivity between the drain and source terminals is controlled by an electric field within the device, which is generated by a voltage difference between the body and gate of the device. The three terminals of a FET are the source (S), where carriers enter the channel, the drain (D), where carriers exit the channel, and the gate (G), which is the terminal that modulates the channel conductivity. Conventionally, the current entering the channel at the source (S) is designated IS, and the current entering the channel at the drain (D) is designated ID. The drain-to-source voltage is designated VDS. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., ID) can be controlled.

[0019]

[0029] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the voltage across the gate determines the device's conductivity. This ability to change conductivity in response to an applied voltage is used to amplify or switch electronic signals. MOSFETs are based on modulation of charge concentration by a metal-oxide-semiconductor (MOS) capacitor between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET contains two additional terminals (source and drain), each connected to a separate highly doped region separated by a body region. These regions can be p-type or n-type, but both are the same type, opposite the type of the body region. The source and drain are highly doped (unlike the body), and a "+" symbol is indicated after the doping type.

[0020]

[0030] If the MOSFET is n-channel, or nMOSFET, the source and drain are n+ regions and the body is p region. If the MOSFET is p-channel, or pMOSFET, the source and drain are p+ regions and the body is n region. The source is so named because it is the source of charge carriers (electrons in the case of n-channel and holes in the case of p-channel) that flow through the channel. Similarly, the drain is where the charge carriers exit the channel.

[0021]

[0031] As used herein, the term "fin field effect transistor (FinFET)" refers to a MOSFET transistor constructed on a substrate with gates located on two or three sides of the channel, forming a double or triple gate structure. FinFET devices are given the generic name FinFET because the channel region forms a "fin" on the substrate. FinFET devices have fast switching times and high current densities.

[0022]

[0032] As used herein, the term "gate-all-around (GAA)" is used to refer to an electronic device (e.g., a transistor) in which a gate material surrounds a channel region on all sides. The channel region of a GAA transistor may comprise a nanowire or nanoslab, a bar-shaped channel, or other suitable channel configuration known to those skilled in the art. In one or more embodiments, the channel region of a GAA device comprises multiple horizontal nanowires or horizontal bars spaced vertically apart, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0023]

[0033] As used herein, the term "nanowire" refers to a wire measuring 1 nanometer (10 -9Nanowires refer to nanostructures having diameters on the order of 1000 to 10000 nm. Nanowires can also be defined as structures with a length-to-width ratio greater than 1000. Alternatively, nanowires can be defined as structures with thickness or diameter constrained to tens of nanometers or less, but with unlimited length. Nanowires are used in transistor and some laser applications and, in one or more embodiments, are made of semiconducting, metallic, insulating, superconducting, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and nonvolatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness ranging from about 0.1 nm to about 1000 nm.

[0024]

[0034] Silicon germanium (SiGe) channels are one of the attractive features for gate-all-around (GAA) (nanowire or nanosheet) fabrication to achieve high-mobility PMOS. One approach is to form a uniform SiGe layer around a silicon nanosheet and then continue the gate stack process. This improves performance, but reduces the compressive strain in the channel, thereby not fully demonstrating the benefits of the SiGe channel. In planar technologies, SiGe PFET channels have been mass-produced by so-called condensation. In this approach, the SiGe layer is oxidized at high temperatures, typically above 1000 °C, which is sufficient to consume the SiGe layer and diffuse the Ge to obtain a uniform SiGe film. However, conventional condensation at 1000 °C is too high for GAA architectures. For example, dopants at the junctions diffuse, degrading device performance.

[0025]

[0035] One or more embodiments advantageously provide a method for forming a uniform SiGe channel in a gate-all-around (GAA) device with a low thermal budget and no silicon core. More specifically, a tensile-strained film is used to form the uniform SiGe channel at low temperatures. Unlike conventional high-temperature anneals that degrade junction designs, the method of one or more embodiments advantageously results in minimal or no degradation of the GAA device.

[0026]

[0036] One or more embodiments of the present disclosure are directed to methods for forming horizontal gate-all-around (GAA) devices. Some embodiments advantageously provide an integrated method for forming complementary metal-oxide-semiconductor (CMOS) devices with a uniform SiGe channel for PMOS while maintaining a silicon channel material for NMOS. In some embodiments, the uniform SiGe channel is formed at low temperatures using a tensile strain layer, resulting in minimal or no degradation of the GAA device.

[0027]

[0037] Embodiments of the present disclosure are illustrated by diagrams that illustrate devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The illustrated processes are merely illustrative of possible uses of the disclosed processes, and one of ordinary skill in the art will recognize that the disclosed processes are not limited to the applications shown.

[0028]

[0038] One or more embodiments of the present disclosure are described with reference to the figures. In one or more embodiment methods, transistors, such as gate-all-around transistors, are fabricated using standard process flows. In some embodiments, the method for forming a hGAA device is enhanced to use a tensile strain layer.

[0029]

[0039] FIG. 1 illustrates a process flow diagram of a method 10 for forming a semiconductor device according to some embodiments of the present disclosure. Method 10 is described below with reference to FIGS. 2-10, which illustrate stages in the fabrication of semiconductor structures, particularly gate-all-around (GAA) devices, according to some embodiments of the present disclosure. Method 10 of one or more embodiments may be part of a multi-step fabrication process for semiconductor devices. Thus, the method may be performed in any suitable process chamber coupled to a cluster tool. The cluster tool may include process chambers for fabricating semiconductor devices, such as chambers configured for etching, deposition, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in the fabrication of semiconductor devices.

[0030]

[0040] The method 10 begins at 12 by providing a substrate 200 having an upper surface 202 (as shown in FIG. 2). The term "providing," as used in this manner, means making the substrate 200 available for processing. For example, the substrate 200 may be provided by being placed in a suitable processing chamber. In some embodiments, the substrate 200 may be a bulk semiconductor substrate. The term "bulk semiconductor substrate" refers to a substrate composed entirely of semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor substrate 200 may include one or more materials such as silicon dioxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In some embodiments, the semiconductor material may be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. In some embodiments, the substrate may be doped to provide a high dose of dopant at a first location on the surface of the substrate 200 to prevent turn-on of parasitic bottom devices. A superlattice structure is formed on the first location. For example, in some embodiments, the surface of the substrate is doped to a depth of about 100 nm. 18 atoms / cm 3 ~about 10 19 atoms / cm 3 The dopant density may be .gtoreq..times ...

[0031]

[0041] In step 14 of method 10, at least one superlattice structure 204 is formed on top surface 202 of substrate 200 (as shown in FIG. 2). Superlattice structure 204 includes a plurality of first layers 224 and a corresponding plurality of second layers 226, arranged alternately into a plurality of stacked pairs. In some embodiments, the plurality of stacked layers includes silicon (Si) and silicon germanium (SiGe). In some embodiments, the plurality of first layers 224 and the corresponding plurality of second layers 226 can include any number of lattice-matched material pairs suitable for forming superlattice structure 204. In some embodiments, the plurality of first layers 224 and the corresponding plurality of second layers 226 include between 2 and 50 pairs, or between 2 and 20 pairs, of lattice-matched materials.

[0032]

[0042] Typically, the parasitic devices will reside at the bottom of the superlattice structure 204. In some embodiments, implantation of dopants into the substrate is used, as described above, to inhibit turn-on of the parasitic devices. In some embodiments, the substrate 200 is etched to include portions of the substrate that are not removed at the bottom of the superlattice structure 204, allowing the portions of the substrate to act as a bottom release layer for the superlattice structure 204.

[0033]

[0043] In some embodiments, the thickness of first layer 224 and second layer 226 is in the range of about 2 nm to about 50 nm, or in the range of about 3 nm to about 20 nm. In some embodiments, the average thickness of first layer 224 is within 0.5 to 2 times the average thickness of second layer 226.

[0034]

[0044] In some embodiments, dielectric material 246 is deposited on substrate 200 using conventional chemical vapor deposition techniques. In some embodiments, dielectric material 246 is recessed below top surface 202 of substrate 200 such that the bottom of superlattice structure 204 is formed from substrate 200.

[0035]

[0045] In some embodiments, a replacement gate structure (e.g., dummy gate structure 208) is formed on the superlattice structure 204. The dummy gate structure 208 defines a channel region of a transistor device. The dummy gate structure 208 may be formed using any suitable conventional deposition and patterning process known in the art.

[0036]

[0046] In some embodiments, sidewall spacers 210 are formed along the outer sidewalls of dummy gate structures 208. Sidewall spacers 210 in some embodiments comprise a suitable insulating material known in the art, such as, for example, silicon nitride (SiN), silicon oxide (SiOx), silicon oxynitride (SiON), silicon carbide (SiC), etc. In some embodiments, sidewall spacers 210 are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0037]

[0047] In some embodiments, buried source and drain regions 232 and 234 are formed in the source and drain trenches, respectively. In some embodiments, the source region 232 is formed adjacent a first end of the superlattice structure 204, and the drain region 234 is formed adjacent a second, opposite end of the superlattice structure. In the embodiment shown in FIG. 2 , one of the source and drain regions 232 and 234 is not shown on the front side of the superlattice structure 204. The other end of the superlattice structure 204 has the other of the source and drain regions 232 and 234. In some embodiments, the source and / or drain regions 232 and 234 are formed from any suitable semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), or silicon germanium (SiGe). In some embodiments, the source and drain regions 232 and 234 may be formed using any suitable deposition process, such as an epitaxial deposition process.

[0038]

[0048] In some embodiments, an interlevel dielectric (ILD) layer 220 is blanket deposited over the substrate 200, including the source / drain regions 232, 234, the dummy gate structure 208, and the sidewall spacers 210. The ILD layer 220 may be deposited using conventional chemical vapor deposition techniques (e.g., plasma-enhanced chemical vapor deposition and low-pressure chemical vapor deposition). In embodiments, the ILD layer 220 is formed from any well-known dielectric material, such as, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride (SiN), and silicon oxynitride (SiON). The ILD layer 220 is then polished using conventional chemical mechanical planarization to expose the top of the dummy gate structure 208. In some not-shown embodiments, the ILD layer 220 is polished to expose the top of the dummy gate structure 208 and the top of the sidewall spacers 210.

[0039]

[0049] In some embodiments, the dummy gate structure 208 is removed to expose the channel region 214 of the superlattice structure 204, as shown in FIG. 3 . The ILD layer 220 protects the source / drain regions 232, 234 during removal of the dummy gate structure 208. The dummy gate structure 208 may be removed using conventional etching methods, such as plasma dry etching or wet etching. In some embodiments, the dummy gate structure 208 comprises polysilicon, and the dummy gate structure is removed by a selective etching process. In some embodiments, the dummy gate structure 208 comprises polysilicon, and the superlattice structure 204 comprises alternating layers of silicon (Si) and silicon germanium (SiGe).

[0040]

[0050] 4 illustrates a relevant portion of the electronic device of FIG. 3, showing an end view of the superlattice structure 204 having alternating layers of a first material 224 and a second material 226. As shown in FIG. 5, in step 16 of method 10, a wire release process selectively etches between the first material 224 layers of the superlattice structure 204. The wire release process forms a plurality of voids 225 between the first material 224 layers, resulting in a plurality of nanosheets 244 comprising the first layer 224 extending between the source and drain regions.

[0041]

[0051] For example, if the superlattice structure 204 is composed of a silicon (Si) layer and a silicon germanium (SiGe) layer, the silicon germanium (SiGe) is selectively etched to form channel nanowires (also referred to as nanosheets). The release layer (second material 226), e.g., silicon germanium (SiGe), can be removed using any known etchant that is selective to the semiconductor material layer 224, and that etches the release layer (second material 226) at a significantly faster rate than the semiconductor material layer (first material 224). In some embodiments, a selective dry etching or wet etching process may be used. In some embodiments, when the semiconductor material layer (first material 224) is silicon (Si) and the release layer (second material 226) is silicon germanium (SiGe), the silicon germanium (SiGe) layer may be selectively removed using a wet etchant, such as, but not limited to, an aqueous carboxylic acid / nitric acid / HF solution and an aqueous citric acid / nitric acid / HF solution. After the release layer (second material 226) is removed, gaps 225 remain between the semiconductor material layers (first material 224). The gaps 225 between the semiconductor material layers (first material 224) have a thickness of about 3 nm to about 20 nm. The remaining semiconductor material layer forms a vertical array of channel nanowires connected to the source / drain regions 232, 234. The channel nanowires run parallel to the top surface 202 of the substrate 200 and are aligned with each other to form a single row of channel nanowires. The formation of source region 232 and drain region 234, and the optional formation of a lateral etch stop layer (not shown), advantageously provides self-alignment and structural integrity in the formation of the channel structure.

[0042]

[0052] In optional step 18, as shown in FIG. 6, nanosheet 244 is subjected to an optional process in which nanosheet 244 comprising first material 224 is trimmed from initial thickness T0 (as shown in FIG. 5) to nanosheet 244 having a reduced thickness T1 (as shown in FIG. 6).

[0043]

[0053] Nanosheet 244 is trimmed by any suitable etching process known to one of skill in the art that is compatible with first material 224. In some embodiments, nanosheet 244 is trimmed by exposure to a wet etching process, such as an aqueous alkaline medium such as KOH-, NaOH-, or TMAH-solution. In some embodiments, nanosheet 244 is trimmed by exposure to a dry etching process. In one or more embodiments, the dry etching process includes exposing nanosheet 244 to reactive ion etching (RIE) with gases common to etching silicon, a remote plasma source, ammonia (NH), and hydrogen (H).

[0044]

[0054] In some embodiments, the reduction in thickness of the nanosheet is 50% or more of the initial thickness T0. In some embodiments, the initial thickness T0 is in the range of 4 nm to 10 nm, or in the range of 5 nm to 9 nm, or in the range of 6 nm to 8 nm. In some embodiments, the reduced thickness T1 is in the range of 1 / 3 to 1 / 5 of the initial thickness T0, or in the range of 1 nm to 3 nm. In some embodiments, trimming the nanosheet reduces the thickness of the nanosheet from an initial thickness T0 in the range of 6 nm to 8 nm to a reduced thickness T1 in the range of 1 nm to 3 nm or in the range of 2 nm to 3 nm.

[0045]

[0055] In step 20, cladding material 250 is formed around each of the plurality of first layers 224 of nanosheets 244. Cladding material 250 is formed on the nanosheets, with or without performing optional step 18. Cladding material 250 may be formed by any suitable process known to those skilled in the art. In some embodiments, cladding material 250 comprises silicon germanium (SiGe) or germanium (Ge). In one or more embodiments, cladding material 250 comprises germanium in the range of 0% to 100% or in the range of 15% to 50%.

[0046]

[0056] In some embodiments, the cladding material 250 is epitaxially grown on the plurality of first layers 224 of nanosheets 244. In one or more embodiments, the cladding material may be fabricated via chemical vapor deposition (CVD) epitaxy at temperatures ranging from 450°C to 850°C.

[0047]

[0057] In one or more embodiments, cladding material 250 has any suitable thickness, hi some embodiments, cladding material 250 has a thickness in the range of 2 nm to 5 nm.

[0048]

[0058] 1 and 8, in step 22, an etch stop layer 256 and a tensile film 260 are formed around the cladding material 250. The etch stop layer 256 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the etch stop layer 256 is an oxide material. In one or more embodiments, the etch stop layer 256 has a thickness in the range of 0 nm to 3 nm, or in the range of 0 nm to 2 nm, or in the range of 0 nm to 1 nm.

[0049]

[0059] In one or more embodiments, the etch stop layer 256 comprises an oxide of the cladding material 250 and may be formed by any suitable oxidation process known to those skilled in the art. In some embodiments, the etch stop layer 256 is formed by an atomic layer deposition (ALD) process having a low processing temperature in the range of 250°C to 450°C, optionally with a plasma treatment or enhancement. In some embodiments, the etch stop layer 256 is formed by rapid plasma oxidation (RPO) of the cladding material 250. In some embodiments, the RPO process exposes the substrate 200 to an oxygen-containing plasma (e.g., molecular oxygen (O), ozone (O)) at a temperature in the range of 350°C to 9000°C, or at a temperature in the range of 350°C to 800°C. In some embodiments, the RPO process exposes the substrate 200 to an oxygen-containing plasma (e.g., molecular oxygen (O), ozone (O)) at a pressure in the range of 5 torr to 600 torr.

[0050]

[0060] In one or more embodiments, the tensile film 260 advantageously enhances germanium (Ge) diffusion to form a uniform silicon germanium (SiGe) channel. Additionally, the tensile film 260 helps control the channel thickness by preventing oxidation of the silicon germanium (SiGe).

[0051]

[0061] Tensile membrane 260 may comprise any suitable material known to those skilled in the art, in one or more embodiments, tensile membrane 260 comprises one or more of silicon nitride (SiN), amorphous silicon (a-Si), polysilicon, and silicon carbonitride (SiCN).

[0052]

[0062] In one or more embodiments, the tensile membrane 260 has a tensile stress in the range of 500 MPa to 2000 MPa, including in the range of 600 MPa to 1700 MPa. As used herein, the term "tensile stress" refers to the force provided by the tensile membrane, and the term "tensile strain" refers to the force the membrane exerts on the substrate material.

[0053]

[0063] The tensile film 260 can have any suitable thickness. In one or more embodiments, the tensile film 260 has a thickness in the range of 25 nm to 50 nm. In such embodiments, without wishing to be bound by theory, it is believed that the tensile film 260 is deposited to effectively fill the dummy gate region and provide the highest level of strain in the nanosheet. In other embodiments, the tensile film has a thickness in the range of 1 nm to 4 nm.

[0054]

[0064] Referring to FIG. 1, in step 24, the device is optionally cured using ultraviolet (UV) light at a temperature in the range of about 300°C to about 500°C, including in the range of about 400°C to about 480°C.

[0055]

[0065] In other embodiments, UV curing is not used in step 24, but instead the device is optionally subjected to a plasma treatment. In one or more embodiments, the plasma includes one or more of hydrogen (H), ammonia (NH), and nitrogen (N).

[0056]

[0066] In yet another embodiment, no UV curing or plasma treatment is performed in step 24.

[0057]

[0067] 1 and 9, in step 26 of method 10, nanosheet 244 undergoes a rapid thermal oxidation (RTO) process and a rapid thermal annealing (RTA) process. In some embodiments, the RTO / RTA process involves ramping the temperature of the substrate from a starting temperature (e.g., room temperature) to a maximum temperature in the range of 700°C to 1050°C, including in the range of 700°C to 850°C, at a rate of 25°C / sec or greater, 50°C / sec or greater, at 5 to 780 torr for a period of 1 to 5 minutes. During the rapid thermal oxidation (RTO) process / rapid thermal annealing (RTA) process, the process environment in some embodiments includes one or more of oxygen (O), ozone (O), hydrogen (H), and optionally a mixture of O / N gas, H / O gas, or H / N gas.

[0058]

[0068] The rapid thermal oxidation (RTO) / rapid thermal annealing (RTA) process of step 26 results in a rearrangement of germanium (Ge) atoms in the nanosheets 244, with the cladding material 250 effectively replacing the first layer 224. In one or more embodiments, removing the first material from the plurality of nanosheets includes exposing the semiconductor device to one or both of a rapid thermal oxidation (RTO) and a rapid thermal annealing (RTA) process to diffuse germanium (Ge) from the cladding material into the first material, effectively removing / replacing the first layer. Without wishing to be bound by theory, it is believed that the plurality of nanosheets 244 with the cladding material 250 are strained (the tensile membrane 260 pulls the lattice apart, allowing for more Ge intermixing / diffusion).

[0059]

[0069] 1 and 10, in step 28 of method 10, tensile film 260 and oxide etch stop layer 156 are removed by any suitable etching process. In some embodiments, removing etch stop layer 156 and tensile film 260 includes exposing the substrate to a solution of dilute hydrofluoric acid (~1:100-1:150 HF:HO) at room temperature or exposing the substrate to a solution of hot phosphoric acid (HPO) at about 165°C.

[0060]

[0070] Referring to FIG. 1 , steps 30 and 32 of method 10 represent one or more post-tensile film removal processes according to some embodiments. The one or more post-tensile film removal processes can be any process known to those skilled in the art for completing a hGAA device. For example, in some illustrated embodiments, a capping layer can be formed or grown on the semiconductor material layer. The capping layer can be any suitable oxide formed by any suitable technique known to those skilled in the art. In some embodiments, the capping layer comprises a silicon capping layer.

[0061]

[0071] In one or more embodiments not shown, a high-k dielectric layer may be formed on the capping layer. The high-k dielectric layer may be any suitable high-k dielectric material deposited by any suitable deposition technique known to those skilled in the art. In some embodiments, the high-k dielectric layer comprises hafnium oxide. In some embodiments, a conductive material such as titanium nitride, tungsten, cobalt, or aluminum may be formed on the high-k dielectric layer. The conductive material may be formed using any suitable deposition process, such as atomic layer deposition (ALD), to ensure formation of a layer having a uniform thickness around each of the semiconductor material layers.

[0062]

[0072] In some non-illustrated embodiments, gate electrodes may be formed on the substrate 200, surrounding each of the doped semiconductor material layers. The gate electrodes may be formed from any suitable gate electrode material known in the art. The gate electrode material is deposited using any suitable deposition process, such as atomic layer deposition (ALD), to ensure that the gate electrodes are formed around and between each of the semiconductor material layers. The resulting device formed using the methods described herein is a lateral gate-all-around device in accordance with embodiments of the present disclosure. Some embodiments of the present disclosure are directed to lateral gate-all-around devices having a uniform silicon germanium (SiGe) channel.

[0063]

[0073] Some embodiments of the present disclosure are directed to electronic devices comprising a PMOS with a SiGe channel between the source and drain regions and an NMOS with a Si channel between the source and drain regions.

[0064]

[0074] Some embodiments of the present disclosure are directed to integrated processes performed within a single cluster tool. Figure 11 is a schematic top view of an exemplary multi-chamber processing system 400 in accordance with one or more embodiments. Figure 11 shows a schematic top view of an example multi-chamber processing system 400 in accordance with embodiments of the present disclosure. The processing system 400 generally includes a factory interface 402, load lock chambers 404, 406, transfer chambers 408, 410 with respective transfer robots 412, 414, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430. As described in detail herein, wafers within the processing system 400 can be processed in and transferred between the various chambers without exposing the wafers to an ambient environment outside the processing system 400 (e.g., an atmospheric ambient environment that may exist within a factory). For example, wafers can be processed in and transferred between various chambers in low pressure (e.g., about 40-80 Torr or less) or vacuum environments without breaking the low pressure or vacuum environment between various processes performed on the wafers in processing system 400. Thus, processing system 400 can provide an integrated solution for partial processing of wafers.

[0065]

[0075] 11 , the factory interface 402 includes a docking station 440 and a factory interface robot 442 to facilitate wafer transfer. The docking station 440 is configured to receive one or more front-opening unified pods (FOUPs) 444. In some examples, each factory interface robot 442 generally comprises a blade 448 disposed at one end of the respective factory interface robot 442 configured to transfer wafers from the factory interface 402 to the load lock chambers 404, 406.

[0066]

[0076] The load lock chambers 404, 406 have respective ports 450, 452 coupled to the factory interface 402 and respective ports 454, 456 coupled to the transfer chamber 408. The transfer chamber 408 further has respective ports 458, 460 coupled to the holding chambers 416, 418 and respective ports 462, 464 coupled to the processing chambers 420, 422. Similarly, the transfer chamber 410 has respective ports 466, 468 coupled to the holding chambers 416, 418 and respective ports 470, 472, 474, 476 coupled to the processing chambers 424, 426, 428, 430. Ports 454, 456, 458, 460, 462, 464, 466, 468, 470, 472, 474, and 476 may be, for example, slit valve openings with slit valves to allow wafers to pass through by transfer robots 412 and 414 and to provide a seal between the respective chambers to prevent gas from passing between the respective chambers. Generally, every port is open to transfer a wafer; otherwise, the port is closed.

[0067]

[0077] The load lock chambers 404, 406, the transfer chambers 408, 410, the holding chambers 416, 418, and the processing chambers 420, 422, 424, 426, 428, 430 may be fluidly connected to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly connected to the various chambers. In operation, the factory interface robot 442 transfers a wafer from a FOUP 444 to the load lock chamber 404 or 406 through port 450 or 452. The gas and pressure control system then pumps down the load lock chamber 404 or 406. The gas and pressure control system further maintains an internal low-pressure or vacuum environment (which may include an inert gas) within the transfer chambers 408, 410 and the holding chambers 416, 418. Thus, pumping down the load lock chambers 404 or 406 facilitates passing wafers between, for example, the atmospheric environment of the factory interface 402 and the low pressure or vacuum environment of the transfer chamber 408 .

[0068]

[0078] With the wafer in the load lock chamber 404 or 406 pumped down, the transfer robot 412 transfers the wafer from the load lock chamber 404 or 406 to the transfer chamber 408 via port 454 or 456. The transfer robot 412 can then transfer the wafer to either of the processing chambers 420 or 422 via respective ports 462 or 464 for processing, or to the holding chambers 416 or 418 via respective ports 458 or 460 for holding awaiting further transfer. Similarly, the transfer robot 414 can access the wafer in the holding chamber 416 or 418 via port 466 or 468 and transfer the wafer to either of the processing chambers 424, 426, 428, or 430 via respective ports 470, 472, 474, or 476 for processing, or to the holding chambers 416 or 418 via respective ports 466 or 468 for holding awaiting further transfer. Transfer and holding of wafers within and between the various chambers can be done in a low pressure or vacuum environment provided by gas and pressure control systems.

[0069]

[0079] Processing chambers 420, 422, 424, 426, 428, and 430 may be any suitable chambers for processing wafers. In some embodiments, processing chamber 420 may perform an annealing process, processing chamber 422 may perform a cleaning process, and processing chambers 424, 426, 428, and 430 may perform an epitaxial growth process. In some examples, processing chamber 422 may perform a cleaning process, processing chamber 420 may perform an etching process, and processing chambers 424, 426, 428, and 430 may perform their respective epitaxial growth processes.

[0070]

[0080] A system controller 490 is coupled to the processing system 400 to control the processing system 400 or its components. For example, the system controller 490 can control the operation of the processing system 400 using direct control of the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430 of the processing system 400 or by controlling the controllers associated with the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430. During operation, the system controller 490 enables data collection and feedback from each chamber to adjust the performance of the processing system 400.

[0071]

[0081] The system controller 490 generally includes a central processing unit (CPU) 492, memory 494, and support circuits 496. The CPU 492 can be any type of general-purpose processor that may be used in an industrial setting. The memory 494, or non-transitory computer-readable medium, is accessible by the CPU 492 and may be one or more of a memory, such as a random access memory (RAM), a read-only memory (ROM), a floppy disk, a hard disk, or other form of local or remote digital storage. The support circuits 496 are coupled to the CPU 492 and may include cache, clock circuits, an input / output subsystem, power supplies, etc. The various methods disclosed herein may generally be implemented by the CPU 492 executing computer instruction code stored in the memory 494 (or the memory of a particular process chamber) as, for example, a software routine under the control of the CPU 492. When the computer instruction code is executed by the CPU 492, the CPU 492 controls the chamber to perform processes according to the various methods.

[0072]

[0082] Other processing systems may be implemented in other configurations. For example, more or fewer processing chambers may be coupled to the transfer apparatus. In the illustrated example, the transfer apparatus includes transfer chambers 408, 410 and holding chambers 416, 418. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transfer apparatus in a processing system.

[0073]

[0083] Throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0074]

[0084] Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will recognize that the described embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure may include modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a semiconductor device, comprising: selectively etching a superlattice structure on a substrate, the superlattice structure comprising a plurality of first layers of a first material and a plurality of second layers of a corresponding second material arranged alternately in a plurality of stacked pairs extending between a source region and a drain region, wherein selectively etching the superlattice structure removes each of the plurality of second layers to form a plurality of voids in the superlattice structure and a plurality of nanosheets comprising the plurality of first layers; forming a cladding material around each of the plurality of nanosheets comprising the plurality of first layers; forming a tensile film around the cladding material, the tensile film having a tensile stress and imparting a tensile strain to the plurality of nanosheets; Optionally, curing the tensile membrane; and heat-treating the plurality of nanosheets; removing the tensile film to form a plurality of nanosheets of clad material; A method comprising:

2. The method of claim 1 , wherein the first material comprises silicon (Si) and the second material comprises silicon germanium (SiGe).

3. The method of claim 1 , wherein the cladding material comprises silicon germanium (SiGe).

4. The method of claim 3 , wherein the cladding material comprises 15% to 50% germanium (Ge).

5. The method of claim 1 , further comprising forming an etch stop layer around the cladding material before forming the tensile membrane.

6. The method of claim 1 , wherein the tensile membrane has a tensile stress in the range of 500 MPa to 2000 MPa.

7. 2. The method of claim 1, wherein heat treating the plurality of nanosheets comprises exposing the semiconductor device to one or more of a rapid thermal oxidation (RTO) process, a rapid thermal annealing (RTA) process, and a rapid plasma oxidation (RPO) process to diffuse germanium (Ge) from the cladding material into the first material.

8. 8. The method of claim 7, wherein the RTO / RTA process ramps the temperature of the substrate from a starting temperature to a maximum temperature in the range of 700 to 850 degrees Celsius.

9. The method of claim 8 , wherein forming an etch stop layer comprises rapid plasma oxidation (RPO) of a portion of the cladding material.

10. The method of claim 1 , wherein the tensile film is UV cured at a temperature in the range of 300° C. to about 500° C.

11. exposing the tensile film to a plasma treatment, the plasma comprising hydrogen (H ２ ), ammonia (NH ３ ), and nitrogen (N ２ 10. The method of claim 1, further comprising exposing the tensile membrane to a plasma treatment, the plasma treatment comprising one or more of:

12. The method of claim 1 , wherein removing the tensile film comprises etching.

13. 10. The method of claim 1, wherein the tensile membrane has a tensile stress in the range of 600 MPa to 1700 MPa.

14. The method of claim 1 , wherein the tensile film comprises one or more of silicon nitride (SiN), amorphous silicon (a-Si), polysilicon, and silicon carbonitride (SiCN).

15. The method of claim 1 , wherein the tensile film has a thickness in the range of 1 nm to 4 nm.

16. The method of claim 1 , wherein the tensile film has a thickness in the range of 25 nm to 50 nm.

17. 10. The method of claim 1, further comprising trimming the plurality of nanosheets to reduce a thickness of the nanosheets from an initial thickness in a range of 6 nm to 8 nm to a reduced thickness in a range of 2 nm to 3 nm before forming the cladding material.

18. 10. The method of claim 1, further comprising forming a high-k metal gate in contact with the plurality of nanosheets of cladding material.

19. 10. The method of claim 1, further comprising forming the source region adjacent a first end of the superlattice structure and the drain region adjacent a second, opposite end of the superlattice structure.

20. a PMOS with a uniform SiGe channel between the source and drain regions; an NMOS having a Si channel between a source region and a drain region; An electronic device comprising:

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