Silicon superjunction structure for improved throughput

Abstract

Superjunction devices with improved manufacturing throughput can be formed by forming narrow trenches lined with a P-type liner that are quickly filled with a passive fill material. Instead of etching a trench with an aspect ratio large enough to reliably fill it with doped P-type material, the trench aspect ratio can be reduced to reduce the size of the device. This smaller trench can then be lined with a relatively thin (e.g., about 1 μm to about 2 μm) P-type liner instead of completely filling the trench with P-type material. Filling the trench with the passive fill material is performed at a relatively high temperature in just a few minutes, which likely causes voids or seams to form in the passive fill material. However, because the passive fill material does not affect the operation of the device, defects of this type may be present in the device.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 18 / 171,119, entitled "SILICON SUPER JUNCTION STRUCTURES FOR INCREASED THROUGHPUT," filed February 17, 2023, which is incorporated by reference in its entirety into this specification.

[0002]

[0002] The present technology relates to semiconductor systems, processes, and apparatus. In particular, the present technology relates to processes and systems for improving the scaling of high aspect ratio power devices. [Background technology]

[0003]

[0003] Integrated circuits are made possible by processes that form intricately patterned layers of material on substrate surfaces. Fabricating patterned materials on substrates requires controlled methods for forming and removing material. As devices become increasingly miniaturized, features within integrated circuits become smaller and the aspect ratios of structures can become larger, making it difficult to maintain the dimensions of these structures during processing steps. Increased exposure during processing can result in recessed features within the material that may have uneven or tapered sidewalls, depending on the process. Developing materials with straight sidewalls can become more challenging. Additionally, backfilling recessed features with material without seams and / or voids can also become more challenging.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technology addresses these and other needs. Summary of the Invention

[0005] In some embodiments, a superjunction device may include a first N-type region extending vertically upward from a substrate. The substrate may form a first contact region for the device. The device may also include a second N-type region extending vertically upward from the substrate to a second contact region of the device. The device further includes a trench between the first N-type region and the second N-type region. The trench may be lined with a P-type liner along sidewalls of the trench. The P-type liner may contact a third contact region of the device. The trench may be filled with a passive fill material between the P-type liners.

[0006] In some embodiments, a superjunction device may include a silicon substrate forming a drain region for the device, a gate region, a source region, an N-type region extending from the silicon substrate upward to the gate region, a P-type region extending from the silicon substrate upward to the source region, and a passive fill material extending upward to the source region. The P-type region may be between the passive fill material and the N-type region. The passive fill material may include voids or seams inside the passive fill material.

[0007] In some embodiments, a method of forming a superjunction device can include forming an N-type material on a substrate and etching a trench in the N-type material. The trench can extend from a top surface of the N-type material downward to at least a top surface of the substrate to form a first N-type region and a second N-type region. The method can also include forming a P-type liner in the trench and filling the trench with a passive fill material.

[0008]

[0008] In any of the embodiments, any and all of the following features may be implemented in any combination without limitation: The height of the P-type liner may be about 40 μm or more. The width of the P-type liner may be about 200 nm or less. The first contact region may include a drain of the superjunction transistor. The second contact region may include a gate of the superjunction transistor. The third contact region may include a source of the superjunction transistor. The superjunction transistor may have a breakdown voltage of about 650 V or more. The width of the trench may be about 2 μm or less. The doping concentration of the P-type liner may be higher than the doping concentration of the second N-type region. The void or seam may be at least 1 μm from a bottom of the passive fill material. The void or seam may be at least 1 μm from a top of the passive fill material. An aspect ratio of the area occupied by the P-type region and the passive fill material may be about 20 or more. The aspect ratio of the area occupied by the P-type region and the passive fill material may be about 40 or greater. The trench may be filled with the passive fill material in less than 15 minutes. The trench may be filled with the passive fill material without one or more growth-etch cycles. The passive fill material may include undoped silicon. The trench may be filled with the passive fill material at a temperature of about 900°C or greater. The method may also include planarizing the top surface of the device to remove excess passive fill material after filling the trench with the passive fill material. The trench may be etched below the top surface of the substrate. A P-type liner may be grown on the sidewalls of the trench as a P-doped epitaxial silicon liner. The doping concentration of the N-type material may be about 1e14 dopant / cm 3 and approximately 1e16 dopant / cm 3 and the doping concentration of the P-type liner may be greater than about 8 times the doping concentration of the N-type material.

[0009] The nature and advantages of various embodiments can be further understood by reference to the remaining portions of the specification and drawings, where like reference numerals are used throughout the several views to refer to similar configuration elements. In some instances, a sublabel is associated with a reference numeral to indicate one of multiple similar configuration elements. When reference is made to a reference numeral without specification to an existing replacement symbol, it is intended to refer to all such multiple similar components. [Brief explanation of the drawings]

[0010] [Figure 1]

[0010] A top view of one embodiment of a deposition, etching, baking, and curing chamber processing system that may be included or configured in accordance with some embodiments of the present technique is shown. [Figure 2]

[0011] 1 illustrates a superjunction device according to some embodiments. [Figure 3]

[0012] 1 illustrates a flowchart of a method for forming a superjunction device that enables reduced pitch and faster trench fill, according to some embodiments. [Figure 4A]

[0013] 1A-1C illustrate a structure shown at stages for forming a superjunction device according to some embodiments. [Figure 4B] 1A-1C illustrate a structure shown at stages for forming a superjunction device according to some embodiments. [Figure 4C] 1A-1C illustrate a structure shown at stages for forming a superjunction device according to some embodiments. [Figure 4D] 1A-1C illustrate a structure shown at stages for forming a superjunction device according to some embodiments. [Figure 4E] 1A-1C illustrate a structure shown at stages for forming a superjunction device according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0014] Superjunction devices with improved manufacturing throughput can be formed by forming narrow trenches lined with a P-type liner that are quickly filled with a passive fill material. Instead of etching a trench with an aspect ratio large enough to reliably fill it with doped P-type material, the trench aspect ratio can be reduced to reduce the size of the device. This smaller trench can then be lined with a relatively thin (e.g., about 1 μm to about 2 μm) P-type liner instead of completely filling the trench with P-type material. The trench can then be filled with passive fill material inside the P-type liner. Filling the trench with passive fill material is performed at a relatively high temperature in just a few minutes, which likely causes voids or seams to form in the passive fill material. However, because the passive fill material does not affect the operation of the device, defects of this type may be present in the device.

[0012]

[0015] As device sizes continue to shrink, many material layers may be reduced in thickness and size to accommodate device miniaturization. Features within semiconductor structures may become smaller, and the aspect ratio of the features may increase. As the aspect ratio of a feature increases, it may become more difficult to uniformly etch the feature without tapering the sides of the feature or compromising the feature dimensions or integrity, due to increased exposure closer to the surface of the structure being processed. Furthermore, refilling features with higher aspect ratios may become increasingly difficult due to pinch-off at the top of the feature, which prevents the feature from filling without seams and / or voids.

[0013]

[0016] In forming power device structures, conventional techniques have limited device scaling for features with increased aspect ratios due to the inherent effects of long etching and deposition processes. For example, in superjunction structures, p-type silicon pillars are formed by filling trenches etched in n-type silicon with p-type silicon. In these structures, the on-resistance is controlled by the pitch or width of the different materials. This resistance can be improved by reducing the width of the p-type silicon pillars. Scaling of p-type silicon pillars is limited by the etching and the ability to fill trenches without seams or voids. For example, increasing the aspect ratio with conventional etching can result in pitch degradation and feature tapering due to the extended exposure of the upper regions of the formed features. Furthermore, the filling process for high aspect ratio features can lead to pinch-off before the deeper regions of the feature are filled. As a result, conventional techniques have been limited to lower aspect ratio or shorter structures to limit performance impact or device failure. Thus, many conventional techniques have limited ability to prevent structural defects in the final device or improve upon past designs.

[0014]

[0017] The present technology overcomes these challenges by redefining the way pillars are formed within the base material. By forming smaller features of the thin epitaxial liner before backfilling, the pillars of material can be maintained at significantly smaller widths than prior art. More specifically, the width of the pillars of material can be defined by the width of the epitaxial liner rather than the width of the recessed feature. Furthermore, the recessed features can be made smaller than prior art and quickly backfilled with passive fill material because voids or seams in the passive fill material do not affect device operation. By modifying the formation process itself, the present technology can provide features with larger aspect ratios and also significantly increase throughput when manufacturing multiple devices.

[0015]

[0018] While the remainder of the disclosure will routinely identify particular etching and deposition processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to a variety of other processes, such as those that may occur in the described chambers. Accordingly, the present technology should not be considered limited to use with the described etching or deposition processes alone. This disclosure will discuss one possible system that can be used with the present technology before describing the systems and methods or steps of an exemplary process sequence according to some embodiments of the present technology. It should be understood that the present technology is not limited to the described apparatus, and the discussed processes can be performed in any number of processing chambers and systems.

[0016]

[0019] 1 illustrates a top view of one embodiment of a deposition, etch, bake, and cure chamber processing system 100 that may be included in or configured in accordance with some embodiments of the present technology. In the figure, a pair of front-opening unified pods 102 provide substrates of various sizes that are received by a robotic arm 104 and placed in a low-pressure holding area 106 before being placed in one of the substrate processing chambers 108a-108f positioned in tandem sections 109a-109c. A second robotic arm 110 may be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-108f. Each substrate processing chamber 108a-f may be equipped to perform several substrate processing steps, including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma treatment, degassing, orientation, and other substrate processing, as well as the dry etching processes described herein.

[0017]

[0020] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a material film on a substrate or wafer. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit material on a substrate, and a third pair of processing chambers (e.g., 108a-b) may be used to cure, anneal, or otherwise process the deposited film. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to deposit and cure a film on a substrate. Any one or more of the described processes may be performed in additional chambers separate from the fabrication system shown in different embodiments. It should be understood that additional configurations of deposition chambers, etch chambers, annealing chambers, and curing chambers for material films are contemplated by system 100. Additionally, any number of other processing systems may be utilized with the present techniques, which may incorporate chambers for performing any of the specific steps. In some embodiments, a chamber system that may provide access to multiple processing chambers while maintaining reduced pressure environments in various sections, such as the holding area and transfer area described above, may allow operations to be performed in multiple chambers while maintaining a particular reduced pressure environment between individual processes.

[0018]

[0021] System 100, or more specifically, chambers incorporated within system 100 or other processing systems, can be used to fabricate structures in accordance with some embodiments of the present technique. FIG. 2 illustrates a superjunction device 200 according to some embodiments. Device 200 in FIG. 2 is illustratively depicted as a superjunction transistor, such as a superjunction MOSFET. However, the principles described herein can be used to form any superjunction device, and the description is not limited to superjunction transistors.

[0019]

[0022] System 200 may include several different electrical contacts. Device 200 may include a source contact 206 electrically coupled to an N+ region 207 formed in a P-well 205. Collectively, source contact 206, N+ source region 207, and P-well 205 may be referred to as the “source region” of device 200. The device may be formed on a silicon substrate 226. Silicon substrate 226 may form a drain region of device 200. Although not explicitly shown in FIG. 2 , the drain region formed by substrate 226 may include a conductive contact similar to source contact 206. Device 200 may also include a gate region including gate contact 202 and gate oxide 209. Each of the source, drain, and gate regions may include other layers or regions not explicitly shown in FIG. 2 . Furthermore, these contacts may also be more generally referred to in this disclosure as “first,” “second,” and “third” contacts, distinguishing one contact from the other in a manner that is not transistor-specific. For example, in this implementation of the transistor, the drain region may be referred to as the first contact region, the gate region may be referred to as the second contact region, and the source region may be referred to as the third contact region.

[0020]

[0023] The interior region of device 200 may include multiple N-doped and / or P-doped regions. These regions may also be referred to as "pillars" because they typically extend upward from silicon substrate 226 to the top of device 200. Device 200 may include a first N-type region 208. First N-type region 208 extends vertically upward from silicon substrate 226 to the top of device 200. Device 200 may also include a P-type region 210. P-type region 210 also extends vertically upward from silicon substrate 226 to a source region of device 200. Device 200 may also include a second N-type region 212. Second N-type region 212 similarly extends upward from silicon substrate 226 to a gate region. Note that device 200 may also include additional contact regions, P-type regions (e.g., P-type region 214), and N-type regions (e.g., N-type region 216). Some of them are shown in Figure 2.

[0021]

[0024] Typically, the width 220 of the P-type region 210 and the width 222 of the second N-type region 212 are approximately the same in a standard superjunction device. Furthermore, the doping level of the P-type region 210 (N A ) and the doping level of the N-type region 212 (N D ) is also equal. For optimal performance, charge should be balanced between second N-type region 212 and P-type region 210 according to the following equation: N A W p =N D W n (1)

[0022]

[0025] By carefully balancing the charge between the N-type and P-type pillars in device 200, these regions can be fully depleted of each other to form a depletion region throughout the bulk of device 200. Full depletion significantly increases the breakdown voltage of device 200 without reducing the doping concentration. This allows the device to have very high doping concentrations in the N-type regions, as long as the balance is maintained according to equation (1) above.

[0023]

[0026] The breakdown voltage of device 200 is also a function of device height 224. Typically, the greater the height 224 of device 200, the higher the breakdown voltage of device 200. However, as the size of device 200 decreases, circuit designers typically focus on reducing the width of the N-type pillars within the P-type pillars. In particular, pitch 228 must be reduced to reduce the size of device 200. As a technical issue, manufacturing limitations limit how much the critical dimension or width of features can be reduced for a given height 224 of device 200 due to the aspect ratio of these features. In particular, forming the device typically involves forming N-type material on top of silicon substrate 226. Trenches are then etched in the N-type regions, leaving N-type mesas including, for example, N-type region 208 and N-type region 212. The trenches are then filled with P-type material to form P-type regions, such as P-type region 210 and P-type region 214. Thus, the aspect ratio of the trench limits the width of the trench for a given height.

[0024]

[0027] For example, device 200 of FIG. 2 may be rated as a 650V device. Specifications for this 650V device include a height 224 of approximately 40 μm. The width 220 of P-type region 210 is approximately 2 μm (also known as the critical dimension or “CD”). Therefore, the aspect ratio of the trenches etched to form P-type region 210 is 40 / 2=20. Pitch 228 is approximately 4 μm and may be defined as the distance between the centers of consecutive N-type regions. An aspect ratio of 20 has been found to be an acceptable feature size for current etching and filling processes for devices of this size. Increasing the aspect ratio beyond 20 at this size can cause problems when etching the trenches. In particular, the trenches may be eroded at the top, resulting in sloped sidewalls and a poorly defined lower portion within the trench. Increasing the aspect ratio can also cause problems when filling the trenches. When material is deposited into the trench, the material may block the trench at the top before it fills through its height, causing voids or seams in the P-type region that may interfere with the operation of device 200.

[0025]

[0028] At high aspect ratios, such as 20, special procedures are typically required to ensure complete trench filling. For example, when filling trenches with P-type epitaxial silicon, the approach typically involves a selective epitaxial fill process for high-aspect ratio trenches. This process utilizes multiple alternating growth and etching steps to avoid the formation of voids and / or seams. Specifically, a layer of fill material is grown within the trench and then etched back to prevent pinch-off and maintain a uniform surface. Typically, a single growth step results in premature pinch-off at the top of the trench, preventing precursor gases from reaching the bottom of the trench for decomposition and epitaxial growth. While this process produces completely filled trenches, it takes a significant amount of time. For example, the high-aspect ratio trenches described herein can take up to three hours per wafer to complete the fill process. This results in extremely low throughput, significantly limiting the mass production of wafers containing superjunction devices. Furthermore, it is very difficult to control defects in the P-type fill material. If the defects are not properly monitored and controlled, they can adversely affect device performance by increasing leakage current and reducing breakdown voltage. Therefore, there are many technical challenges in the current fabrication of superjunction devices.

[0026]

[0029] The embodiments described herein solve this problem by creating high-voltage devices by using a liner to create a P-type region instead of etching and filling the trench. The trench can be lined with a P-type liner and then filled with a passive fill material, such as an undoped silicon material. The passive fill material deposits or grows relatively quickly within the trench, and voids or seams may form. However, these voids or seams are acceptable because the passive fill material does not affect the operation of the device. Because the trench does not need to be carefully and completely filled, the aspect ratio of the trench can be large. For example, the width of the trench can be reduced, which in turn can reduce the pitch and device size.

[0027]

[0030] 3 shows a flowchart 300 of a method for forming a superjunction device that enables reduced pitch and faster trench fill according to some embodiments. The method of flowchart 300 may be performed in one or more processing chambers, such as the chambers incorporated in system 100 described above. The method of flowchart 300 may or may not include one or more steps prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be performed before the steps described. The method may also include several optional steps, as shown in the figures, that may or may not be specifically associated with some embodiments of methods according to the present technology.

[0028]

[0031] 4A-4E illustrate a structure shown in stages for forming a superjunction device, according to some embodiments. The method of flowchart 300 describes the steps shown generally in FIGS. 4A-4E, which will be described in conjunction with the steps of the method. It should be understood that these figures show only partial schematic views with limited detail, and that in some embodiments, a substrate may include any number of semiconductor sections having aspects as shown in the figures, as well as alternative structural aspects that can still benefit from any of the aspects of the present technology.

[0029]

[0032] The method of flowchart 300 may include forming 302 a first N-type region on a substrate. As shown in FIG. 4A , structure 400 may include a substrate 426. The substrate 426 may have a substantially planar or textured surface in various embodiments. The substrate 426 may be a material such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, a doped or undoped silicon wafer, a patterned or unpatterned wafer, silicon-on-insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. As a non-limiting example, in some embodiments, the substrate may be or include an N+ material such as N+ silicon. The substrate 426 may have various dimensions, such as a 200 mm or 300 mm diameter wafer, as well as a rectangular or square panel. Disposed within the processing region of the semiconductor processing chamber may be a substrate 426. While illustrated as a planar substrate, it should be understood that the substrate 426 is included merely to represent an underlying structure, which may include any number of layers or features on a wafer or other substrate, and upon which structures, such as those described below, may be formed.

[0030]

[0033] Above the substrate 426, the structure 400 may include a first N-type material. The first N-type material may be disposed along at least a portion or all of the substrate 426. The first N-type material may be N-type silicon, and may be doped with phosphorus, arsenic, or a combination of both, or other similar materials. The first N-type material may form the first N-type region 408 and the second N-type region 412, although the mesas or pillars of these regions (and potentially other N-type regions) may not be apparent until after one or more trenches are etched in a following step. The height of the first N-type material and the final first N-type region 408 can be about 20 μm or more, between about 20 μm and about 30 μm, between about 30 μm and about 40 μm, between about 40 μm and about 50 μm, between about 50 μm and about 60 μm, between about 60 μm and about 70 μm, between about 70 μm and about 80 μm, about 80 μm or more, about 90 μm or more, etc.

[0031]

[0034] In some embodiments, a hard mask, photoresist, or any other mask material may be disposed along the first N-type material to facilitate patterning of the first N-type material. For example, a first mask may be formed over the first N-type material, and a second mask may be formed over the first mask. In some embodiments, either or both masks may be any number of materials to facilitate structure formation, such as oxide, nitride, carbide, or some combination of materials. For example, the first mask may be or include silicon nitride, and the second mask may be or include silicon oxide, or some other mask material. A single mask may be provided over the first N-type material, and it is contemplated that the embodiment shown in FIG. 4A is merely one example structure 400.

[0032]

[0035] The method of flowchart 300 may also include etching 304 a trench 433 in the first N-type material. As shown in FIG. 4A , a pattern may be etched or formed through the first mask and / or the second mask to form a feature such as trench 433. The trench 433 may be etched through the first mask and / or the second mask using any etch process and any etch reactant. In some embodiments, the etch may completely remove the second mask when the pattern is transferred into the underlying N-type material.

[0033]

[0036] Etching the first N-type material may form one or more trenches in the material. The trenches 433 may be formed to a depth of about 10 μm or more, about 15 μm or more, about 20 μm or more, about 25 μm or more, about 30 μm or more, about 35 μm or more, about 40 μm or more, about 45 μm or more, about 50 μm or more, about 55 μm or more, about 60 μm or more, about 65 μm or more, about 70 μm or more, about 75 μm or more, about 80 μm or more, about 85 μm or more, about 90 μm or more, about 95 μm or more, about 100 μm or more, or more. As shown in FIG. 4A , the trenches 433 may extend all the way down to the top surface of the substrate 426. In some embodiments, the trenches 433 may extend below the top surface of the substrate 426 such that the trenches 433 penetrate into the substrate 426. As will be described below, this provides a surface onto which epitaxial silicon may grow from substrate 426 when trench 433 is filled, thereby also electrically contacting the P-type liner to substrate 426. Thus, the height of trench 433 corresponds to or exceeds any of the heights described above for first N-type region 408. For example, trench 433 may be approximately 40 μm high or slightly higher when extending into substrate 426 for a 650 V device.

[0034]

[0037] The trenches 433 may have an aspect ratio, or depth-to-width ratio, of about 50 or less, about 40 or less, about 30 or less, about 25 or less, about 20 or less, about 15 or less, about 10 or less, or even lower. As discussed above, this procedure allows the trenches to be etched to a smaller width 454 for a given height 424. This, in turn, increases the aspect ratio and decreases the pitch 428. For example, while the current pitch 428 for standard 650V devices is about 7 μm, resulting in trench 433 widths 454 of about 3.5 μm, embodiments described herein may reduce the pitch 428 to about 6 μm or less, about 5 μm or less, about 4 μm or less, about 3 μm or less, or about 2 μm or less. Trenches 433 with widths 454 as small as 1 micron (μm) may not be possible without the methods described herein for 650V devices with heights of about 40 μm or greater.

[0035]

[0038] The method of flowchart 300 may include forming (306) a P-type liner 450 in trench 433. FIG. 4B illustrates forming P-type liner 450 in trench 433 according to some embodiments. The deposition or formation may be performed in any number of ways, and in some embodiments, a material may be formed conformally around the trench feature. P-type liner 450 may be p-type silicon and may be deposited by, for example, atomic layer deposition, grown epitaxially, or fabricated by any number of other processes capable of producing a conformal coating around trench 433. P-type liner 450 may be characterized by a thickness of between about 50 nm and about 100 nm, between about 100 nm and about 150 nm, between about 150 nm and about 200 nm, between about 200 nm and about 250 nm, between about 250 nm and about 300 nm, greater than about 300 nm, etc. The P-type liner 450 may also be characterized by a thickness of about 200 nm or less, about 150 nm or less, about 100 nm or less, about 90 nm or less, about 80 nm or less, about 70 nm or less, about 60 nm or less, about 50 nm or less, about 40 nm or less, about 30 nm or less, about 20 nm or less, about 10 nm or less, about 5 nm or less, or less. The P-type liner 450 may be a silicon-containing material doped with boron or other similar materials. In some embodiments, the P-type liner 450 may also include germanium.

[0036] P-type liner 450 may substantially cover the sidewall portion of first N-type region 408 in trench 433. In some embodiments, P-type liner 450 may also be formed on the lower portion of trench 433. Based on conformal coverage around the structure, P-type liner 450 may be seam- and / or void-free, even to a depth of several hundred nanometers. This can result in significant improvements in final device performance compared to prior art techniques that may not only have seams or voids, but also reduced or incomplete coverage at greater depths. However, it is anticipated that some pores may be present in P-type liner 450, depending on the formation and thickness.

[0037]

[0039] The method of flowchart 300 may further include filling 308 the trench 433 with a passive fill material. FIG. 4C illustrates the formation of a passive fill material 460 according to some embodiments. The passive fill material 460 may fill the trench 433 by backfilling the interior region of the trench 433 between the sidewalls where the P-type liner 450 is formed. In some embodiments, the passive fill material 460 may be formed as a single-step process. For example, the passive fill material 460 may be formed without using one or more of the growth-etch cycles typically used to uniformly fill the trench 433. This single-step process may fill the trench 433 with the passive fill material 460 in about 15 minutes or less, or about 20 minutes or less, depending on the process.

[0038]

[0040] A variety of materials can be used for the passive fill material 460. For example, the passive fill material 460 can include undoped silicon, which is electrically neutral compared to the N-doped and / or P-doped silicon used elsewhere in the structure 400. Other similar materials can also be used. A P-type liner 450 can surround the passive fill material 460 in the trench 433.

[0039]

[0041] In some embodiments, the passive fill material 460 can be formed quickly using a relatively high temperature to reduce processing time. For example, the temperature during formation of the passive fill material 460 can be increased to about 750°C or higher, about 800°C or higher, about 850°C or higher, about 900°C or higher, about 950°C or higher, about 1000°C or higher, etc.

[0040]

[0042] Although typically avoided, these embodiments allow for the formation of voids or seams, such as void 453 shown in FIG. 4C. Void 453 can be tolerated in this case because passive fill material 460 is electrically neutral within structure 400. Therefore, void 453 can be tolerated without affecting the performance of structure 400. In some embodiments, void 453 can be tolerated at a distance 497 of at least 1 μm from the top of structure 400 and / or at a distance 458 of at least 1 μm from the bottom of trench 433 or the top of substrate 426.

[0041]

[0043] Further processing may include removing portions of the passive fill material 460 and any remaining mask material by planarizing the structure, such as with a chemical-mechanical polishing process. FIG. 4D shows the planarized structure with filled trenches, according to some embodiments. At this stage, the P-type liner 450 may alternatively be referred to as a P-type region 410 because it is ready to perform its function within the structure 400. The pitch 428 may be as small as 2 μm, with approximately 1 μm of the width 422 of the first N-type region 408, approximately 200 nm of the width 457 of the P-type region 410, and approximately 800 nm of the width 462 of the passive fill material 460. Note that FIG. 4D is not drawn to scale.

[0042]

[0044] The doping level of the first N-type region 408 can remain the same as that of the 650V device of Figure 2. For example, the doping level of the first N-type region 408 can be about 1e14 dopant / cm 3 and approximately 1e16 dopant / cm 3 (e.g., in some embodiments, between 7e15 dopant / cm 3) The doping level of P-type region 410 may be about 8 times or more, about 9 times or more, about 10 times or more, etc., the doping level of first N-type region 408. In particular, the doping level of P-type region 410 may be increased to balance equation (1) above, such that the product of the doping level of first N-type region 408 and width 422 of first N-type region 408 is equal to the product of the doping level of P-type region 410 and width 457 of P-type region 410 (i.e., the thickness of P-type liner 450).

[0043]

[0045] Further processing may include forming remaining contact regions for structure 400. FIG. 4E shows structure 400 with contact regions, according to some embodiments. Structure 400 may include gate region 402 and / or source region 406 to complement the drain region formed by substrate 426. First N-type region 408 may extend vertically upward from substrate 426 or the drain region. Second N-type region 412 may also extend vertically upward from substrate 426 to gate region 402 of structure 400. A trench between first N-type region 408 and second N-type region 412 may be lined with a P-type liner 450 along the sidewalls of the trench to form P-type region 410. P-type region 410 contacts the drain formed by substrate 426 and may extend upward to contact source region 406 of the device. Passive fill material 460 may also extend upward to source region 406. The structure 400 may include voids 453 in the passive fill material 460 after the structure 400 is completed.

[0044]

[0046] In the above description, for purposes of explanation, numerous details are presented in order to facilitate an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details, or with additional details.

[0045]

[0047] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, some well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Therefore, the foregoing description should not be deemed to limit the scope of the technology.

[0046]

[0048] Where a range of values ​​is given, unless the context clearly indicates otherwise, each intervening value between the upper and lower limit of that range is specifically disclosed, to the smallest unit of the lower limit. Any smaller ranges between any stated or unstated intervening value in a stated range, and any other stated or intervening value in that stated range, are also included. The upper and lower limits of such narrower ranges may individually be included or excluded from that range. Each range where either, neither, or both limits are included in this narrower range is also encompassed within the technology, even though there may be specifically excluded limits in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0047]

[0049] As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a pillar" includes a plurality of such pillars, a reference to "the layer" includes a reference to one or more layers and equivalents thereof known to those skilled in the art, and so on.

[0048]

[0050] Additionally, the terms "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including," when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or operations, but do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

[0049]

[0051] The foregoing description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the foregoing description of various embodiments will provide an enabling disclosure for implementing at least one embodiment. It will be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of some embodiments, as set forth in the appended claims.

[0050]

[0052] Specific details are provided in the foregoing description to provide a thorough understanding of the embodiments. However, it will be understood that some embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form so as not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail so as not to obscure the embodiments.

[0051]

[0053] It should also be noted that the particular embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. While the flowcharts have described operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Furthermore, the order of operations may be rearranged. A process terminates when an operation is completed, but there may be additional steps not included in the diagram. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination may correspond to the return of the function to the calling function or to the main function.

[0052]

[0054] The term "computer-readable medium" includes, but is not limited to, portable or non-portable storage devices, optical storage devices, wireless channels, and various other media that can store, preserve, or convey instruction(s) and / or data. A code segment or machine-executable instructions may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be connected to another code segment or a hardware circuit by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

[0053]

[0055] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented by software, firmware, middleware, or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine-readable medium. Processor(s) may perform the necessary tasks.

[0054]

[0056] Furthermore, for illustrative purposes, the methods have been described in a particular order. It should be understood that in alternative embodiments, the methods may be performed in an order different from that described. It should also be understood that the methods described above may be performed by hardware components or embodied in sequences of machine-executable instructions, which may be used to cause a machine, such as a general-purpose or special-purpose processor, or a logic circuit programmed with the instructions, to perform the method. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disk, a floppy diskette, ROM, RAM, EPROM, EEPROM, a magnetic or optical card, flash memory, or any other type of machine-readable medium suitable for storing electronic instructions. Alternatively, the methods may be implemented by a combination of hardware and software.

Claims

1. a first N-type region extending vertically upward from a substrate, said substrate forming a first contact region for the device; a second N-type region extending vertically upward from the substrate to a second contact region of the device; and 1. A superjunction device comprising: a trench between the first N-type region and the second N-type region, the trench lined with a P-type liner along sidewalls of the trench, the P-type liner contacting a third contact region of the device, the trench filled with a passive fill material between the P-type liners.

2. The height of the P-type liner is about 40 μm or more. The superjunction device of claim 1 .

3. The width of the P-type liner is about 200 nm or less. The superjunction device of claim 1 .

4. the first contact region includes a drain of a superjunction transistor; the second contact region includes a gate of the superjunction transistor; The superjunction device of claim 1 , wherein the third contact region comprises a source of the superjunction transistor.

5. The superjunction device according to claim 4 , wherein the superjunction transistor has a breakdown voltage of about 650 V or more.

6. The trench has a width of about 2 μm or less. The superjunction device of claim 1 .

7. The superjunction device of claim 1 , wherein the doping concentration of said P-type liner is higher than the doping concentration of said second N-type region.

8. a silicon substrate forming a drain region for the device; Gate region, Source region, an N-type region extending upward from the silicon substrate to the gate region; a P-type region extending upward from the silicon substrate to the source region; and 1. A superjunction device comprising: a passive fill material extending upward to the source region, the P-type region being between the passive fill material and the N-type region, the passive fill material including a void or seam inside the passive fill material.

9. 9. The superjunction device of claim 8, wherein the void or the seam is at least 1 μm from the bottom of the passive fill material and the void or the seam is at least 1 μm from the top of the passive fill material.

10. 9. The superjunction device of claim 8, wherein an aspect ratio of the area occupied by said P-type region and said passive fill material is about 20 or greater.

11. 10. The superjunction device of claim 8, wherein an aspect ratio of the area occupied by the P-type region and the passive fill material can be about 40 or greater.

12. 1. A method of forming a superjunction device, comprising: forming an N-type material on a substrate; etching a trench in the N-type material, the trench extending from a top surface of the N-type material downward to at least a top surface of the substrate to form a first N-type region and a second N-type region; forming a P-type liner in the trench; and filling the trench with a passive fill material.

13. 13. The method of claim 12, wherein the trench is filled with the passive fill material in less than 15 minutes.

14. 13. The method of claim 12, wherein the trench is filled with the passive fill material without undergoing one or more grow-etch cycles.

15. The method of claim 12 , wherein the passive fill material comprises undoped silicon.

16. The method of claim 12 , wherein the trench is filled with the passive fill material at a temperature of about 900° C. or greater.

17. 13. The method of claim 12, further comprising planarizing a top surface of the device to remove excess passive fill material after filling the trench with the passive fill material.

18. The method of claim 12 , wherein the trench is etched below the top surface of the substrate.

19. 13. The method of claim 12, wherein the P-type liner is grown on the sidewalls of the trench as a P-doped epitaxial silicon liner.

20. The doping concentration of the N-type material is about 1e14 dopant / cm 3 and about 1e16 dopant / cm 3 13. The method of claim 12, wherein the doping concentration of the P-type liner is between about 8 times the doping concentration of the N-type material.

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