Silicon superjunction structure for high voltage resistance

Abstract

Superjunction devices with increased voltage ratings can be formed by decreasing the width and increasing the doping concentration of the P-type region while increasing the overall device height. However, instead of etching a trench in the N-type material to fill with P-type material, a trench can be etched for both the P-type region and the adjacent N-type region. This allows the overall device height to be increased while maintaining a feasible aspect ratio for the trench. The P-type material can then be formed as a sidewall liner on the trench. This liner is relatively thin compared to the remaining width of the trench. The trench can then be filled with N-type material. The P-type region thereby fills the space between the N-type regions without any voids or seams. Meanwhile, the P-type region has a width that would not be achievable using conventional etch-and-fill methods for the P-type region alone.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 18 / 171,090, entitled "SILICON SUPER JUNCTION STRUCTURES FOR INCREASED VOLTAGE," filed February 17, 2023, which is incorporated by reference in its entirety into this specification.

[0002]

[0002] The present technology relates to semiconductor systems, processes, and apparatus. In particular, the present technology relates to processes and systems for improving the scaling of high aspect ratio power devices. [Background technology]

[0003]

[0003] Integrated circuits are made possible by processes that form intricately patterned layers of material on substrate surfaces. Fabricating patterned materials on substrates requires controlled methods for forming and removing material. As devices become increasingly miniaturized, features within integrated circuits become smaller and the aspect ratios of structures can become larger, making it difficult to maintain the dimensions of these structures during processing steps. Increased exposure during processing can result in recessed features within the material that may have uneven or tapered sidewalls, depending on the process. Developing materials with straight sidewalls can become more challenging. Additionally, backfilling recessed features with material without seams and / or voids can also become more challenging.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technology addresses these and other needs. Summary of the Invention

[0005] In some embodiments, a superjunction device may include a first N-type region extending vertically upward from a substrate. The substrate may form a first contact region for the device. The device may also include a second N-type region extending vertically upward from the substrate to a second contact region of the device, and a P-type region extending vertically upward from the substrate to a third contact region of the device. The P-type region may be disposed between the first N-type region and the second N-type region. The width of the P-type region may occupy about 10% or less of the combined width of the P-type region and the second N-type region.

[0006] In some embodiments, a superjunction device can include a silicon substrate forming a drain region for the device, a gate region, a source region, an N-type region extending from the silicon substrate upward to the gate region, and a P-type region extending from the silicon substrate upward to the source region, the device having a breakdown voltage of about 1000 V or greater.

[0007] In some embodiments, a method for forming a superjunction device may include forming a first N-type material on a substrate. The N-type region may have a height of about 70 μm or more above the substrate. The method may also include etching a trench in the first N-type material. The trench may extend from a top surface of the first N-type material downward to at least a top surface of the substrate to form the first N-type region. The method may further include forming a P-type liner on a sidewall portion of the first N-type region in the trench. The method may further include filling the trench with N-type material to form a second N-type region such that the P-type liner is between the first N-type region and the second N-type region.

[0008]

[0008] In any of the embodiments, any and all of the following features may be implemented in any combination without limitation: The height of the P-type region may be about 70 μm or more. The width of the P-type region may be about 200 nm or less. The first contact region may include a drain of the superjunction transistor. The second contact region may include a gate of the superjunction transistor. The third contact region may include a source of the superjunction transistor. The superjunction transistor may have a breakdown voltage of about 1200 V or more. The combined width of the P-type region and the second N-type region may be about 4 μm or less. The doping concentration of the P-type region may be higher than the doping concentration of the second N-type region. The height of the N-type region may be about 80 μm. The aspect ratio of the area occupied by the N-type region and the P-type region may be about 20 or less. The width of the area occupied by the N-type region and the P-type region may be about 4 μm or less. The trench may be etched below the top surface of the substrate. The method may also include forming a passivation layer on the P-type liner. The method may further include removing the passivation layer before filling the trench. The P-type liner may also be formed on a lower portion of the trench. The method may also include performing a directional etch to remove the P-type liner from a lower portion of the trench while leaving the P-type liner along a sidewall portion of the trench. The P-type liner may be about 300 nm or less. The doping concentration of the N-type region may be about 1e14 dopant / cm 3 and approximately 1e16 dopant / cm 3 The doping concentration of the P-type region may be greater than about 8 times the doping concentration of the N-type region.

[0009] The nature and advantages of various embodiments can be further understood by reference to the remaining portions of the specification and drawings, where like reference numerals are used throughout the several views to refer to similar configuration elements. In some instances, a sublabel is associated with a reference numeral to indicate one of multiple similar configuration elements. When reference is made to a reference numeral without specification to an existing replacement symbol, it is intended to refer to all such multiple similar components. [Brief explanation of the drawings]

[0010] [Figure 1]

[0010] A top view of one embodiment of a deposition, etching, baking, and curing chamber processing system that may be included or configured in accordance with some embodiments of the present technique is shown. [Figure 2]

[0011] 1 illustrates a superjunction device according to some embodiments. [Figure 3]

[0012] 1 illustrates an example of a 1300V superjunction device according to some embodiments. [Figure 4]

[0013] 1 illustrates a flowchart of a method for forming a high voltage superjunction device according to some embodiments. [Figure 5A]

[0014] 1A-1C illustrate a structure shown in stages for forming a high voltage superjunction device according to some embodiments. [Figure 5B] 1A-1C illustrate a structure shown in stages for forming a high voltage superjunction device according to some embodiments. [Figure 5C] 1A-1C illustrate a structure shown in stages for forming a high voltage superjunction device according to some embodiments. [Figure 5D] 1A-1C illustrate a structure shown in stages for forming a high voltage superjunction device according to some embodiments. [Figure 5E]1A-1C illustrate a structure shown in stages for forming a high voltage superjunction device according to some embodiments. [Figure 5F] 1A-1C illustrate a structure shown in stages for forming a high voltage superjunction device according to some embodiments. [Figure 5G] 1A-1C illustrate a structure shown in stages for forming a high voltage superjunction device according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0015] Superjunction devices with increased voltage ratings can be formed by decreasing the width and increasing the doping concentration of the P-type region while increasing the overall device height. However, instead of etching a trench in the N-type material to fill with P-type material, a trench can be etched for both the P-type region and the adjacent N-type region. This allows the overall device height to be increased while maintaining a feasible aspect ratio for the trench. The P-type material can then be formed as a sidewall liner on the trench. This liner is relatively thin compared to the remaining width of the trench. The trench can then be filled with N-type material. The P-type region thereby fills the space between the N-type regions without any voids or seams. Meanwhile, the P-type region has a width that would not be achievable using only conventional etch-and-fill methods for P-type regions.

[0012]

[0016] As device sizes continue to shrink, many material layers may be reduced in thickness and size to accommodate device miniaturization. Features within semiconductor structures may become smaller, and the aspect ratio of the features may increase. As the aspect ratio of a feature increases, it may become more difficult to uniformly etch the feature without tapering the sides of the feature or compromising the feature dimensions or integrity, due to increased exposure closer to the surface of the structure being processed. Furthermore, refilling features with higher aspect ratios may become increasingly difficult due to pinch-off at the top of the feature, which prevents the feature from filling without seams and / or voids.

[0013]

[0017] In forming power device structures, conventional techniques have limited device scaling for features with increased aspect ratios due to the inherent effects of long etching and deposition processes. For example, in superjunction structures, p-type silicon pillars are formed by filling trenches etched in n-type silicon with p-type silicon. In these structures, the on-resistance is controlled by the pitch or width of the different materials. This resistance can be improved by reducing the width of the p-type silicon pillars. Scaling of p-type silicon pillars is limited by the etching and the ability to fill trenches without seams or voids. For example, increasing the aspect ratio with conventional etching can result in pitch degradation and feature tapering due to the extended exposure of the upper regions of the formed features. Furthermore, the filling process for high aspect ratio features can lead to pinch-off before the deeper regions of the feature are filled. As a result, conventional techniques have been limited to lower aspect ratio or shorter structures to limit performance impact or device failure. Thus, many conventional techniques have limited ability to prevent structural defects in the final device or improve upon past designs.

[0014]

[0018] The present technology overcomes these challenges by redefining how pillars are formed within the base material. By forming a thin epitaxial liner within the generally wider features before backfilling, the pillars of material can be maintained at significantly smaller widths than in conventional techniques. More specifically, the width of the pillars of material can be defined by the width of the epitaxial liner rather than the width of the recessed feature. In fact, because two pillars can be deposited on the sidewalls of each recessed feature, the recessed features can be wider than in conventional techniques. After forming material on the sidewalls, the recessed feature can be backfilled with additional base material. By modifying the formation process itself, the present technology can provide features with larger aspect ratios and also prevent or reduce defects in the final device due to more uniform filling and coverage.

[0015]

[0019] While the remainder of the disclosure will routinely identify particular etching and deposition processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to a variety of other processes, such as those that may occur in the described chambers. Accordingly, the present technology should not be considered limited to use with the described etching or deposition processes alone. This disclosure will discuss one possible system that can be used with the present technology before describing the systems and methods or steps of an exemplary process sequence according to some embodiments of the present technology. It should be understood that the present technology is not limited to the described apparatus, and the discussed processes can be performed with any number of processing chambers and systems.

[0016]

[0020] 1 illustrates a top view of one embodiment of a deposition, etch, bake, and cure chamber processing system 100 that may be included in or configured in accordance with some embodiments of the present technology. In the figure, a pair of front-opening unified pods 102 provide substrates of various sizes that are received by a robotic arm 104 and placed in a low-pressure holding area 106 before being placed in one of the substrate processing chambers 108a-108f positioned in tandem sections 109a-109c. A second robotic arm 110 may be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-108f. Each substrate processing chamber 108a-f may be equipped to perform several substrate processing steps, including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma treatment, degassing, orientation, and other substrate processing, as well as the dry etching processes described herein.

[0017]

[0021] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a material film on a substrate or wafer. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit material on a substrate, and a third pair of processing chambers (e.g., 108a-b) may be used to cure, anneal, or otherwise process the deposited film. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to deposit and cure a film on a substrate. Any one or more of the described processes may be performed in additional chambers separate from the fabrication system shown in different embodiments. It should be understood that additional configurations of deposition chambers, etch chambers, annealing chambers, and curing chambers for material films are contemplated by system 100. Additionally, any number of other processing systems may be utilized with the present techniques, which may incorporate chambers for performing any of the specific steps. In some embodiments, a chamber system that may provide access to multiple processing chambers while maintaining reduced pressure environments in various sections, such as the holding area and transfer area described above, may allow operations to be performed in multiple chambers while maintaining a particular reduced pressure environment between individual processes.

[0018]

[0022] System 100, or more specifically, chambers incorporated within system 100 or other processing systems, can be used to fabricate structures in accordance with some embodiments of the present technique. FIG. 2 illustrates a superjunction device 200 according to some embodiments. Device 200 in FIG. 2 is illustratively depicted as a superjunction transistor, such as a superjunction MOSFET. However, the principles described herein can be used to form any superjunction device, and the description is not limited to superjunction transistors.

[0019]

[0023] System 200 may include several different electrical contacts. Device 200 may include a source contact 206 electrically coupled to an N+ region 207 formed in a P-well 205. Collectively, source contact 206, N+ source region 207, and P-well 205 may be referred to as the “source region” of device 200. The device may be formed on a silicon substrate 226. Silicon substrate 226 may form a drain region of device 200. Although not explicitly shown in FIG. 2 , the drain region formed by substrate 226 may include a conductive contact similar to source contact 206. Device 200 may also include a gate region including gate contact 202 and gate oxide 209. Each of the source, drain, and gate regions may include other layers or regions not explicitly shown in FIG. 2 . Furthermore, these contacts may also be more generally referred to in this disclosure as “first,” “second,” and “third” contacts, distinguishing one contact from the other in a manner that is not transistor-specific. For example, in this implementation of the transistor, the drain region may be referred to as the first contact region, the gate region may be referred to as the second contact region, and the source region may be referred to as the third contact region.

[0020]

[0024] The interior region of device 200 may include multiple N-doped and / or P-doped regions. These regions may also be referred to as "pillars" because they typically extend upward from silicon substrate 226 to the top of device 200. Device 200 may include a first N-type region 208. First N-type region 208 extends vertically upward from silicon substrate 226 to the top of device 200. Device 200 may also include a P-type region 210. P-type region 210 also extends vertically upward from silicon substrate 226 to a source region of device 200. Device 200 may also include a second N-type region 212. Second N-type region 212 similarly extends upward from silicon substrate 226 to a gate region. Note that device 200 may also include additional contact regions, P-type regions (e.g., P-type region 214), and N-type regions (e.g., N-type region 216). Some of them are shown in Figure 2.

[0021]

[0025] Typically, the width 220 of the P-type region 210 and the width 222 of the second N-type region 212 are approximately the same in a standard superjunction device. Furthermore, the doping level of the P-type region 210 (N A ) and the doping level of the N-type region 212 (N D ) is also equal. For optimal performance, charge should be balanced between second N-type region 212 and P-type region 210 according to the following equation: N A W p =N D W n (1)

[0022]

[0026] By carefully balancing the charge between the N-type and P-type pillars in device 200, these regions can be fully depleted of each other to form a depletion region throughout the bulk of device 200. Full depletion significantly increases the breakdown voltage of device 200 without reducing the doping concentration. This allows the device to have very high doping concentrations in the N-type regions, as long as the balance is maintained according to equation (1) above.

[0023]

[0027] The breakdown voltage of device 200 is also a function of the height 224 of device 200. Typically, the greater the height 224 of device 200, the greater the breakdown voltage of device 200. However, manufacturing constraints limit the height 224 of device 200 due to the aspect ratio of features. In particular, forming the device typically involves forming an N-type material on top of a silicon substrate 226. Trenches are then etched in the N-type regions, leaving N-type mesas including, for example, N-type region 208 and N-type region 212. The trenches are then filled with P-type material to form P-type regions, such as P-type region 210 and P-type region 214. Therefore, the aspect ratio of the trench limits the depth of the trench unless the width of the trench is increased. However, increasing the width of the trench increases the overall size of device 200. Given that device sizes are scaled down, increasing the device size to increase the breakdown voltage is not a feasible option in most applications.

[0024]

[0028] For example, device 200 of FIG. 2 may be rated as a 650V device. Specifications for this 650V device include a height 224 of approximately 40 μm. The width 220 of P-type region 210 is approximately 2 μm (also known as the critical dimension or “CD”). Therefore, the aspect ratio of the trenches etched to form P-type region 210 is 40 / 2=20. Pitch 228 is approximately 4 μm and may be defined as the distance between the centers of consecutive N-type regions. An aspect ratio of 20 has been found to be an acceptable feature size for current etching and filling processes for devices of this size. Increasing the aspect ratio beyond 20 at this size can cause problems when etching the trenches. In particular, the trenches may be eroded at the top, resulting in sloped sidewalls and a poorly defined lower portion within the trench. Increasing the aspect ratio can also cause problems when filling the trenches. When material is deposited into the trench, the material may block the trench at the top before it fills through its height, causing voids or seams in the P-type region that may interfere with the operation of device 200.

[0025]

[0029] 3 shows an example of a 1300V superjunction device 300 according to some embodiments. Similar to the 650V device of FIG. 2, this device 300 may include source, gate, and drain regions and a silicon substrate 326. The central portion of the device may include alternating pillars, such as a first N-type region 308, a P-type region 310, a second N-type region 312, an additional P-type region 314, and an additional N-type region 316.

[0026]

[0030] This 1300 V superjunction device 300 provides roughly twice the breakdown voltage of the 650 V device of FIG. 2. To double the voltage, the height 324 of device 300 is doubled. However, doubling the height 324 of device 300 also doubles the aspect ratio of the trench required to form P-type region 310. For example, doubling the height 324 of device 300 to approximately 80 μm and maintaining the width 320 of P-type region 310 at 2 μm doubles the aspect ratio to approximately 40. Etching a trench with an aspect ratio of this height tends to result in a poorly defined trench that is difficult or impossible to fill without seams or voids. Therefore, the only option to maintain the higher voltage of device 300 is to increase the width or critical dimension of the trench accordingly. For example, to maintain an aspect ratio of 20, the trench width would need to be doubled to 4 μm. This produces a pitch of 328, which is also double the pitch 228 of 650V device 200. Thus, device 300 has twice the overall width of 650V device 200. Doubling the size of the device is not a feasible option for most applications.

[0027]

[0031] Embodiments described herein solve this problem by producing high-voltage devices by using a liner to create P-type regions instead of etching and filling trenches. For example, these techniques can be used to form devices with breakdown voltages of about 1000 V or greater, such as 1300 V. In one embodiment, the height of the device may be doubled to about 80 μm, and a trench may be etched having a width or critical dimension of 4 μm. This results in a trench with an aspect ratio of 20, as described above for the 650 V device 200. However, contrary to the device 200 shown in FIG. 2, the trench may be lined with P-type material and then filled with N-type material. This produces very narrow P-type regions (e.g., between 50 nm and 300 nm), and the resulting pitch between the N-type regions is still 4 μm. This produces a 1300 V device with the same overall width as the 650 V device described above.

[0028]

[0032] 4 shows a flowchart 400 of a method for forming a high-voltage superjunction device according to some embodiments. The method of flowchart 400 may be performed in one or more processing chambers, such as the chambers incorporated in system 100 described above. The method of flowchart 400 may or may not include one or more steps prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be performed before the steps described. The method may also include some optional steps, as shown in the figures, that may or may not be specifically associated with some embodiments of methods according to the present technology.

[0029]

[0033] 5A-5G illustrate a structure shown in stages for forming a high-voltage superjunction device according to some embodiments. The method of flowchart 400 describes the steps shown generally in FIGS. 5A-5G, which will be described in conjunction with the steps of the method. It should be understood that these figures show only partial schematic views with limited detail, and that in some embodiments, a substrate may include any number of semiconductor sections having aspects as shown in the figures, as well as alternative structural aspects that can still benefit from any of the aspects of the present technology.

[0030]

[0034] The method of flowchart 400 may include forming 402 a first N-type region on a substrate. As shown in FIG. 5A , structure 500 may include a substrate 526. Substrate 526 may have a substantially planar or textured surface in various embodiments. Substrate 526 may be a material such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, a doped or undoped silicon wafer, a patterned or unpatterned wafer, silicon-on-insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. As a non-limiting example, in some embodiments, the substrate may be or include an N+ material such as N+ silicon. Substrate 526 may have various dimensions, such as a 200 mm or 300 mm diameter wafer, as well as a rectangular or square panel. Within the processing region of the semiconductor processing chamber may be disposed a substrate 526. While illustrated as a planar substrate, it should be understood that the substrate 526 is included merely to represent an underlying structure, which may include any number of layers or features on a wafer or other substrate, upon which structures, such as those described below, may be formed.

[0031]

[0035] Above the substrate 526, the structure 500 may include a first N-type material. The first N-type material may be disposed along at least a portion or all of the substrate 526. The first N-type silicon-containing material may be N-type silicon and may be doped with phosphorus, arsenic, or a combination of both, or other similar materials. The first N-type material may form the first N-type region 508, although the mesa or pillar of the first N-type region 508 (and potentially other N-type regions 516) may not be apparent until after trenches are etched in a subsequent step. The height of the first N-type material and subsequent first N-type region 508 may be 40 μm or greater, between about 40 μm and about 50 μm, between about 50 μm and about 60 μm, between about 60 μm and about 70 μm, between about 70 μm and about 80 μm, about 80 μm or greater, etc. For example, a device with a breakdown voltage of 1300 V may have a first N-type region 508 that is approximately 80 μm high. For devices with a breakdown voltage of greater than 650 V, the height of the first N-type region 508 may be approximately 50 μm or greater, approximately 60 μm or greater, approximately 70 μm or greater, and / or approximately 80 μm or greater. Other embodiments may include a first N-type region 508 that is less than approximately 40 μm, which can be used to form superjunction devices with smaller overall widths. Other embodiments may also include a first N-type region that is approximately 90 μm or greater, approximately 100 μm or greater, etc., depending on the desired voltage characteristics of the superjunction device.

[0032]

[0036] In some embodiments, a hard mask, photoresist, or any other mask material may be disposed along the first N-type material to facilitate patterning of the first N-type material. For example, a first mask may be formed over the first N-type material, and a second mask may be formed over the first mask. In some embodiments, either or both masks may be any number of materials to facilitate structure formation, such as oxide, nitride, carbide, or some combination of materials. For example, the first mask may be or include silicon nitride, and the second mask may be or include silicon oxide, or some other mask material. A single mask may be provided over the first N-type material, and it is contemplated that the embodiment shown in FIG. 5A is merely one example structure 500.

[0033]

[0037] The method of flowchart 400 may also include etching 404 a trench 533 in the first N-type material. As shown in FIG. 5A , a pattern may be etched or formed through the first mask and / or the second mask to form a feature such as trench 533. The trench 533 may be etched through the first mask and / or the second mask using any etch process and any etch reactant. In some embodiments, the etch may completely remove the second mask when the pattern is transferred into the underlying N-type material.

[0034]

[0038] Etching the first N-type material may form one or more trenches in the material. The trenches 533 may be formed to a depth of about 10 μm or greater, about 15 μm or greater, about 20 μm or greater, about 25 μm or greater, about 30 μm or greater, about 35 μm or greater, about 40 μm or greater, about 45 μm or greater, about 50 μm or greater, about 55 μm or greater, about 60 μm or greater, about 65 μm or greater, about 70 μm or greater, about 75 μm or greater, about 80 μm or greater, about 85 μm or greater, about 90 μm or greater, about 95 μm or greater, about 100 μm or greater, or more. As shown in FIG. 5A , the trenches 533 may extend all the way down to the top surface of the substrate 526. In some embodiments, the trenches 533 may extend below the top surface of the substrate 526 such that the trenches 533 penetrate into the substrate 526. As will be described below, this provides a surface onto which epitaxial silicon may grow from substrate 526 when trench 533 is filled. Thus, the height of trench 533 corresponds to or exceeds any of the heights described above for first N-type region 508. For example, trench 533 may be approximately 80 μm high or slightly higher when extending into substrate 526 for a 1300 V device.

[0035]

[0039] It should be noted that reducing the height 524 of the trench 533 also proportionally reduces the breakdown voltage, since the breakdown voltage is directly related to the height of the device. For example, the height can be reduced to less than 80 μm, corresponding to a breakdown voltage of about 1200 V or more, about 1100 V or more, about 1000 V or more, about 900 V or more, about 800 V or more, about 700 V or more, or about 650 V or more.

[0036]

[0040] The trench 533 may have an aspect ratio, or depth to width ratio, of about 50 or less, about 40 or less, about 30 or less, about 25 or less, about 20 or less, about 15 or less, about 10 or less, or less. Additionally, the trench 533 may be formed to a width of about 1.5 μm or more, about 2.0 μm or more, about 2.5 μm or more, about 3.0 μm or more, about 3.5 μm or more, about 4.0 μm or more, about 4.5 μm or more, about 5.0 μm or more, about 6.0 μm or more, about 7.0 μm or more, about 8.0 μm or more, about 9.0 μm or more, about 10.0 μm or more, or more. The trench 533 can also be formed to a width between about 1.5 μm and about 2.0 μm, between about 2.0 μm and about 2.5 μm, between about 2.5 μm and about 3.0 μm, between about 3.0 μm and about 3.5 μm, between about 3.5 μm and about 4.0 μm, between about 4.0 μm and about 4.5 μm, between about 4.5 μm and about 5.0 μm, between about 4.5 μm and about 6.0 μm, etc.

[0037]

[0041] While conventional methods may have invested in etching higher aspect ratio trenches to allow for narrower, deeper P-type regions to be deposited, forming trenches with higher aspect ratios can make structure formation more difficult. Not only can it be difficult to etch high aspect ratio trenches of consistent diameter, it can also be difficult to uniformly backfill these trenches with P-type material. Instead, the P-type material may have seams and / or voids due to pinch-off at the top of the feature during filling. Conversely, embodiments described herein may counterintuitively relax the width of trench 533, allowing for the fabrication of smaller pitch or higher aspect ratio structures. This may allow for more uniform etching and subsequent backfilling. Furthermore, as the width of trench 533 increases, deeper etching of N-type material may be feasible. As an added benefit of deeper etching, and therefore deeper material structures, the breakdown voltage of power devices fabricated by this technique may be improved compared to conventional methods and techniques. For example, the 650V device 200 shown in Figure 2 may have a trench etched approximately 2 μm wide and 40 μm deep with an aspect ratio of 20. By relaxing the width of the trench 200, the 1300V device may still have a trench etched approximately 4 μm wide and 80 μm deep with an aspect ratio of 20. As explained below, the pitch of the N-type and P-type pillars may be maintained at approximately 4 μm. This allows the overall width of the 1300V device to be approximately the same as the width of the full 650V device 200.

[0038]

[0042] The method of flowchart 400 may include forming 406 a P-type liner 550 on a sidewall portion of first N-type region 508 in trench 533. FIG. 5B illustrates forming P-type liner 550 on a sidewall portion of first N-type region 508 in trench 533, according to some embodiments. The deposition or formation may be performed in any number of ways, and in some embodiments, a material may be formed conformally around the feature. P-type liner 550 may be p-type silicon and may be deposited, for example, by atomic layer deposition, grown epitaxially, or fabricated by any number of other processes, capable of producing conformal coverage around trench 533. By having a trench characterized by a wider width, coverage may be uniform despite the greater depth of trench 533. The P-type liner 550 may be characterized by a thickness of between about 50 nm and about 100 nm, between about 100 nm and about 150 nm, between about 150 nm and about 200 nm, between about 200 nm and about 250 nm, between about 250 nm and about 300 nm, about 300 nm or more, etc. The P-type liner 550 may also be characterized by a thickness of about 200 nm or less, about 150 nm or less, about 100 nm or less, about 90 nm or less, about 80 nm or less, about 70 nm or less, about 60 nm or less, about 50 nm or less, about 40 nm or less, about 30 nm or less, about 20 nm or less, about 10 nm or less, about 5 nm or less, or less. The P-type liner 550 may be a silicon-containing material doped with boron or other similar materials. In some embodiments, the P-type liner 550 may also include germanium.

[0039] P-type liner 550 may substantially cover the sidewall portion of first N-type region 508 in trench 533. In some embodiments, P-type liner 550 may also be formed on the lower portion of trench 533. Based on conformal coverage around the structure, P-type liner 550 may be seam- and / or void-free, even to a depth of several hundred nanometers. This can result in significant improvements in final device performance compared to prior art techniques that may not only have seams or voids, but also reduced or incomplete coverage at greater depths. However, it is anticipated that some pores may be present in P-type liner 550, depending on the formation and thickness.

[0040]

[0043] FIG. 5C illustrates the formation of a passivation layer 552 as part of an optional step that may be added to the method of flowchart 400 in some embodiments. The passivation layer 552 may be formed by providing an oxygen-containing precursor to the processing region. The oxygen-containing precursor may be any number of precursors capable of oxidizing the P-type liner 550. As non-limiting examples, the oxygen-containing precursor may be or include diatomic oxygen, ozone, nitrous oxide, nitric oxide, sulfur dioxide, or any other oxygen-containing precursor, which may be provided with or without plasma enhancement, or may be provided with any other precursor, such as a silicon-containing precursor, to deposit an oxide layer. The passivation layer 552 may be formed using any deposition or growth method. The oxygen-containing material in the passivation layer 552 may oxidize and passivate at least a portion of the P-type liner 550. The passivation layer 552 may serve to protect the P-type liner 550 during a subsequent etching step.

[0041]

[0044] 5D illustrates the results of a directional etch to remove P-type liner 550 from the bottom of trench 533. The portion of P-type liner 550 that is removed may be located in the bottom of trench 533. In addition to the portion of P-type liner 550 that is removed, a portion of passivation layer 552 may also be removed. The portion of passivation layer 552 that is removed may be located in the bottom of trench 533. In some embodiments, removing the portion of P-type liner 550 may include an anisotropic etching process, such as a reactive ion etching process or any other directional dry etching process. For example, the method of flowchart 400 may include applying a bias power to etch passivation layer 552 and / or the bottom of P-type liner 550. Etching of passivation layer 552 may be by sputtering oxide within passivation layer 552, while more chemical removal may occur through p-type silicon, or vice versa. The anisotropy of the etch may cause the bottom of passivation layer 552 to be sputtered and removed at a faster rate than the sidewalls of passivation layer 552. Thus, this process may remove P-type liner 550 and passivation layer 552 from the bottom of trench 533 while leaving P-type liner 550 (and passivation layer 552 along the sidewall portions of trench 533) in place. This may expose the surface of substrate 526 at the bottom of trench 533.

[0042]

[0045] 5E illustrates removal of the remnants of passivation layer 552, according to some embodiments. The method of flowchart 400 may optionally include removing the remnants of passivation layer 552. The removed portions of passivation layer 552 may be located along the sidewalls of trench 553 and the underlying P-type liner 550. In some embodiments, removing the portions of passivation layer 552 may include, as one non-limiting example, a wet etching step using any wet etch reactant(s), such as a halogen-containing material. However, it is contemplated that other forms of etching, including dry etching processes, may alternatively or additionally be utilized.

[0043]

[0046] The remaining P-type liner 550 may be present on the sidewalls of trench 553. P-type liner 550 may be characterized by an aspect ratio of about 50 or greater, about 100 or greater, about 150 or greater, about 200 or greater, about 250 or greater, about 300 or greater, about 350 or greater, about 400 or greater, or more. Superjunction devices formed using these structures, with taller and narrower features than conventional methods, may be characterized by reduced on-resistance due to the separation distance between N-type regions and improved breakdown voltage due to the depth and uniformity of the formed P-type pillars.

[0044]

[0047] The method of flowchart 400 may include filling 408 the trench 533 with an N-type material to form a second N-type region 512 such that the P-type liner 550 is between the first N-type region 508 and the second N-type region 512. FIG. 5F illustrates the formation of the second N-type region 512 according to some embodiments. The second N-type region 512 may fill the trench 533 by backfilling the interior region of the trench 533 between the sidewalls on which the P-type liner 550 is formed. The second N-type region 512 may fill the trench 533 without any voids and without intermittent etching based on the increased width that may be provided from the initial trench formation (e.g., about 4 μm). The second N-type region 512 may be the same material as the first N-type region 508. Together, N-type region 508 and second N-type region 512 may at least partially surround P-type liner 550. P-type liner 550 may now be referred to as P-type region 551 in the superjunction device. Trench 533 may be filled with N-type material via an epitaxial growth process. For example, exposed substrate 526 may provide a base for epitaxially growing N-type silicon material upward from substrate 526 to fill trench 533.

[0045]

[0048] The ratio of the width of second N-type region 512 to the width of P-type region 551 may be about 15 or greater, and may be about 20 or greater, about 22 or greater, about 24 or greater, about 26 or greater, about 28 or greater, about 30 or greater, or even greater. This ratio between the two materials may lead to reduced on-resistance in subsequent devices fabricated with these structures, as previously described. In other words, width 557 of P-type region 551 may be about 10% or less of the combined width of P-type region 551 and second N-type region 512. Width 557 of P-type region 551 may also be about 9% or less, about 8% or less, about 7% or less, about 6% or less, about 5% or less, etc., of this combined width. For example, P-type region 551 having a width 557 of 200 nm may be formed with second N-type region 512 having a width 554 of 3.8 μm in a trench that is 4.0 μm wide and 80 μm high.

[0046]

[0049] Further steps may include removing a portion of the N-type material and any remaining mask material by planarizing the structure, such as with a chemical-mechanical polishing step. The method may also optionally include forming remaining contact regions for device 500. FIG. 5G shows device 500 with contact regions, according to some embodiments. Device 500 may also include gate region 502 and / or source region 506 to complement the drain region formed by substrate 526. P-type region 551 may be disposed between first N-type region 508 and second N-type region 512, with a significantly thinner width. To maintain proper charge balance, the doping level of P-type region 551 may be increased accordingly. The doping levels of first N-type region 508 and / or second N-type region 512 may remain the same as in the 650V device of FIG. 2. For example, the doping level of first N-type region 508 may be about 1e14 dopant / cm 3 and approximately 1e16 dopant / cm 3 The doping level of P-type region 551 may be about 8 times or more, about 9 times or more, about 10 times or more, etc., the doping level of first N-type region 508.

[0047]

[0050] Although the above description, for purposes of explanation, provides numerous details to facilitate an understanding of various embodiments of the present technology, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details, or with additional details.

[0048]

[0051] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, some well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Therefore, the foregoing description should not be deemed to limit the scope of the technology.

[0049]

[0052] Where a range of values ​​is given, unless the context clearly indicates otherwise, each intervening value between the upper and lower limit of that range is specifically disclosed, to the smallest unit of the lower limit. Any smaller ranges between any stated or unstated intervening value in a stated range, and any other stated or intervening value in that stated range, are also included. The upper and lower limits of such narrower ranges may individually be included or excluded from that range. Each range where either, neither, or both limits are included in this narrower range is also encompassed within the technology, even though there may be specifically excluded limits in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0050]

[0053] As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a pillar" includes a plurality of such pillars, a reference to "the layer" includes a reference to one or more layers and equivalents thereof known to those skilled in the art, and so on.

[0051]

[0054] Additionally, the terms "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including," when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or operations, but do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

[0052]

[0055] The foregoing description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the foregoing description of various embodiments will provide an enabling disclosure for implementing at least one embodiment. It will be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of some embodiments, as set forth in the appended claims.

[0053]

[0056] Specific details are provided in the foregoing description to provide a thorough understanding of the embodiments. However, it will be understood that some embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form so as not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail so as not to obscure the embodiments.

[0054]

[0057] It should also be noted that the particular embodiments may be described as a process that is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. While the flowcharts have described operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Furthermore, the order of operations may be rearranged. A process terminates when an operation is completed, but there may be additional steps not included in the diagram. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination may correspond to the return of the function to the calling function or to the main function.

[0055]

[0058] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media that can store, preserve, or convey one or more instructions and / or data. A code segment or machine-executable instructions may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be connected to another code segment or a hardware circuit by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

[0056]

[0059] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented by software, firmware, middleware, or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine-readable medium. Processor(s) may perform the necessary tasks.

[0057]

[0060] Furthermore, for illustrative purposes, the methods have been described in a particular order. It should be understood that in alternative embodiments, the methods may be performed in an order different from that described. It should also be understood that the methods described above may be performed by hardware components or embodied in sequences of machine-executable instructions, which may be used to cause a machine, such as a general-purpose or special-purpose processor, or a logic circuit programmed with the instructions, to perform the method. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disk, a floppy diskette, ROM, RAM, EPROM, EEPROM, a magnetic or optical card, flash memory, or any other type of machine-readable medium suitable for storing electronic instructions. Alternatively, the methods may be implemented by a combination of hardware and software.

Claims

1. a first N-type region extending vertically upward from a substrate, said substrate forming a first contact region for the device; a second N-type region extending vertically upward from the substrate to a second contact region of the device; and 1. A superjunction device comprising: a P-type region extending vertically upward from the substrate to a third contact region of the device, the P-type region being disposed between the first N-type region and the second N-type region, the width of the P-type region comprising no more than about 10% of the combined width of the P-type region and the second N-type region.

2. The superjunction device of claim 1 , wherein the height of said P-type region is greater than or equal to about 70 μm.

3. The superjunction device of claim 1 , wherein the width of said P-type region is about 200 nm or less.

4. the first contact region includes a drain of a superjunction transistor; the second contact region includes a gate of the superjunction transistor; The superjunction device of claim 1 , wherein the third contact region comprises a source of the superjunction transistor.

5. The superjunction device according to claim 4 , wherein the superjunction transistor has a breakdown voltage of about 1200 V or more.

6. 10. The superjunction device of claim 1, wherein the combined width of the P-type region and the second N-type region is about 4 [mu]m or less.

7. The superjunction device of claim 1 , wherein the doping concentration of the P-type region is higher than the doping concentration of the second N-type region.

8. a silicon substrate forming a drain region for the device; Gate region, Source region, an N-type region extending upward from the silicon substrate to the gate region; and a P-type region extending upward from the silicon substrate to the source region; The device is a superjunction device having a breakdown voltage of about 1000V or more.

9. 9. The superjunction device of claim 8, wherein the height of said N-type region is about 80 μm.

10. 9. The superjunction device of claim 8, wherein an aspect ratio of the area occupied by said N-type region and said P-type region is about 20 or less.

11. 9. The superjunction device of claim 8, wherein the width of the area occupied by the N-type region and the P-type region is about 4 [mu]m or less.

12. 1. A method of forming a superjunction device, comprising: forming a first N-type material on a substrate, the N-type region having a height above the substrate of about 70 μm or more; etching a trench in the first N-type material, the trench extending from a top surface of the first N-type material downward to at least a top surface of the substrate to form a first N-type region; forming a P-type liner on a sidewall portion of the first N-type region in the trench; and filling the trench with an N-type material to form the second N-type region such that the P-type liner is between the first N-type region and the second N-type region.

13. The method of claim 12 , wherein the trench is etched below the top surface of the substrate.

14. The method of claim 12 further comprising forming a passivation layer over the P-type liner.

15. 15. The method of claim 14, further comprising removing the passivation layer before filling the trench.

16. The method of claim 12 , wherein the P-type liner is also formed on a lower portion of the trench.

17. 17. The method of claim 16, further comprising performing a directional etch to remove the P-type liner from the lower portion of the trench while leaving the P-type liner along the sidewall portions of the trench.

18. 13. The method of claim 12, wherein the P-type liner is about 300 nm or less.

19. The doping concentration of the N-type region is about 1e14 dopant / cm 3 and about 1e16 dopant / cm 3 The method of claim 12, wherein

20. 20. The method of claim 19, wherein the doping concentration of the P-type region is greater than about 8 times the doping concentration of the N-type region.

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