Improving mobility in semiconductor devices

Abstract

The present technology includes a semiconductor device with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, and a channel region including at least one channel disposed between the source and drain. The device includes a first gate region having a first self-aligned single diffusion break in an n-MOS region and a second gate region having a second self-aligned single diffusion break in a p-MOS region. The second self-aligned single diffusion break also includes a liner and a compressive stress material, and the stressed metal fill exhibits a compressive stress of about 350 MPa or greater.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 63 / 504,689, filed May 26, 2023, entitled "ENHANCED MOBILITY IN SEMICONDUCTOR DEVICES," and U.S. patent application Ser. No. 63 / 487,501, filed February 28, 2023, entitled "STRESS INCORPORATION IN SEMICONDUCTOR DEVICES," which are incorporated herein by reference in their entireties.

[0002]

[0002] The present technology relates to methods for semiconductor processing. In particular, the present technology relates to methods for incorporating increased stress within doped regions of semiconductor devices. [Background technology]

[0003]

[0003] Integrated circuits have evolved into complex devices that can contain millions of transistors, capacitors, and resistors on a single chip. During the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has generally increased while feature size has decreased. A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, many transistors, as well as capacitors, inductors, resistors, diodes, conductive lines, or other elements, may be formed on a semiconductor device. Integrated circuits incorporate field effect transistors (FETs), which conduct current through a semiconductor channel between a source and a drain in response to a voltage applied to a control gate.

[0004]

[0004] Integrated circuits are made possible by processes that form intricately patterned layers of materials on substrate surfaces. Fabricating patterned materials on substrates requires controlled methods for forming and removing materials. As devices become smaller, film properties can have a greater impact on device performance. As devices become smaller and the industry utilizes more complex patterning schemes, thin film deposition becomes a challenge. Additionally, as material thickness continues to decrease, the as-deposited properties of films can have a greater impact on device performance. These challenges include depositing void-free and stressed films.

[0005]

[0005] Therefore, there is a need for high quality devices and structures with improved mobility, and methods for making such devices. The present technology addresses these and other needs. Summary of the Invention

[0006] The present technology is generally directed to semiconductor devices, systems, and methods of forming such devices and systems. The semiconductor device includes a substrate, a source region, a drain region, and a channel region having at least one channel disposed between the source and drain. The device also includes a first gate region having a first self-aligned single diffusion break in the n-MOS region and a second gate region having a second self-aligned single diffusion break in the p-MOS region. In the device, the second self-aligned single diffusion break includes a compressive stress filler material characterized by a compressive stress of about 350 MPa or greater. In the device, the first self-aligned single diffusion break includes a first liner and a first filler material.

[0007] In some embodiments, the device includes a first fill material that is a neutral stress material or a tensile stress material. In more embodiments, the first fill material, the compressive stress fill material, or both the first fill material and the compressive stress fill material comprise a dielectric fill material. Furthermore, in some embodiments, the device includes a first fill material and a compressive stress fill material that comprise a dielectric fill material. In this case, the first fill material is different from the second fill material. In some embodiments, the dielectric fill material comprises silicon nitride, silicon oxynitride, silicon dioxide, or a combination thereof. Furthermore, in some embodiments, the second self-aligned single diffusion break comprises a second liner. In even more embodiments, the first liner, the second liner, or both the first liner and the second liner comprise a dielectric liner material. In some embodiments, the dielectric liner material comprises silicon nitride, silicon oxynitride, silicon dioxide, or a combination thereof. Additionally or alternatively, in some embodiments, the dielectric liner material of the first liner has an etch rate that is different from the etch rate of the first fill material. In further embodiments, the dielectric liner material of the second material is selected from materials that are the same as or different from the compressive stress filling material. In some embodiments, the second liner comprises silicon nitride, silicon dioxide, or a combination thereof, and the compressive stress filling material comprises silicon dioxide, silicon nitride, or a combination thereof. Furthermore, in some embodiments, the first fill material comprises silicon nitride, silicon dioxide, or a combination thereof. In that case, the second fill material is different from the first fill material. In yet another embodiment, the semiconductor device may be a nanosheet field effect transistor or a complementary field effect transistor, and / or a gate-all-around complementary metal oxide semiconductor.

[0008] The present technology is also generally directed to a semiconductor processing system. The system includes a first processing chamber, a second processing chamber, a third processing chamber, and a system controller. In the system, the controller is configured to pattern a substrate in the first processing chamber. In the system, the controller is configured to etch a first shallow trench isolation in the first gate region and etch a second shallow trench isolation in the second gate region in the second processing chamber. In this case, the first gate region is an n-MOS region and the second gate region is a p-MOS region. In the system, the controller is configured to, in the third processing chamber, line the first shallow trench isolation and the second shallow trench isolation with a dielectric liner, fill the first shallow trench isolation and the second shallow trench isolation with a neutral stress material or a tensile stress material, remove the neutral stress material or the tensile stress material from the first shallow trench isolation, and fill the first shallow trench isolation with a compressive stress material.

[0009] The present technology is also generally directed to a method for forming a semiconductor device. The method includes etching a first shallow trench isolation in a first gate region and etching a second shallow trench isolation in a second gate region, where the first gate region is an n-MOS region and the second gate region is a p-MOS region. In some methods, the semiconductor device includes a substrate, a source region, a drain region, and a channel region including at least one channel disposed between the source and drain. In some methods, the semiconductor device includes lining the first shallow trench isolation and the second shallow trench isolation with a liner. In some methods, the lined first shallow trench isolation and the second shallow trench isolation include filling the lined first shallow trench isolation and the second shallow trench isolation with a neutral stress or tensile stress material. In some methods, the neutral stress or tensile stress material is etched from the gate region. In some methods, the etched second shallow trench isolation includes filling the etched second shallow trench isolation with a compressive stress material.

[0010] In embodiments, methods do not include a polishing step between filling the lined first shallow trench isolation with a neutral or tensile stress material and filling the etched second shallow trench isolation with a compressive stress material. In more embodiments, methods include etching the neutral or tensile stress material by a wet or dry etching process. In still further embodiments, methods include a liner comprising a dielectric liner material having an etch rate different from the etch rate of the neutral or tensile stress material. In embodiments, methods include a liner comprising silicon nitride, silicon oxynitride, silicon dioxide, or a combination thereof. In embodiments, the compressive stress material comprises silicon nitride, and the neutral or tensile stress material comprises silicon nitride or silicon dioxide.

[0011]

[0011] Such techniques may offer many advantages over conventional techniques. For example, embodiments of the present technique generate a desired level of stress in the channel region of a semiconductor transistor without modifying the composition of the adjacent source and drain regions. In addition, the present technique generates stress in the channel region from existing diffusion breaks, thus allowing more compact devices to be formed with improved stress. The present technique may therefore provide improved stress without requiring additional channels or diffusion breaks with increased size. These and other embodiments, along with their many advantages and features, are described in more detail below and in the accompanying drawings.

[0012]

[0012] The nature and advantages of the techniques of the present disclosure may be further understood by reference to the remainder of this specification and the following drawings. [Brief explanation of the drawings]

[0013] [Figure 1]

[0013] A top view of an exemplary processing chamber is shown, in accordance with some embodiments of the present technique. [Figure 2]

[0014] 1 illustrates selected steps in a fabrication method, according to some embodiments of the present technique. [Figure 3A]

[0015] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. [Figure 3B] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. [Figure 3C] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. [Figure 3D] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. [Figure 3E] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. [Figure 3F] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. [Figure 3G] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. [Figure 3H] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. [Figure 4]

[0016] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. DETAILED DESCRIPTION OF THE INVENTION

[0014]

[0017] Some of the drawings are included as schematics. It is understood that the figures are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematics, the figures are provided to aid in understanding and may not include all aspects or information compared to realistic depictions and may include material that is emphasized for illustrative purposes.

[0015]

[0018] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished according to the reference numeral, with a letter distinguishing between the similar components. When only a first reference numeral is used herein, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letter.

[0016]

[0019] The present technology includes electronic devices having one or more self-aligned single diffusion breaks and methods for forming such devices. Such electronic devices may include semiconductor transistors, such as n-channel and p-channel MOSFETs, FinFETs, gate-all-around FETs, and nanosheet FETs, among other transistors, as well as products having such channel regions. In conventional processing methods, the stress level in a transistor channel can be controlled by varying the composition of the semiconductor material in the channel and the composition of the material in the adjacent source and drain regions. In many cases, varying the composition of these doped regions of a transistor to impart a desired amount of stress to the channel region can result in otherwise less desirable transistor performance, such as a lower thermal budget and / or increased resistance at the interface between the contact and the doped region. Controlling the stress in the channel region by varying the composition of the doped region also limits the types of materials that can be used in the doped region. For example, modern PMOS transistors often use doped silicon-germanium (SiGe) semiconductors in the doped region of the transistor. If the Ge-Si ratio becomes too high, defects can occur in the material due to lattice mismatch, reducing the stress in the channel region below acceptable levels.

[0017]

[0020] Another conventional method for increasing stress in a transistor's channel region involves depositing a stressed conductive material in a contact trench above the channel region. The stress from the conductive material is transferred downward to impart the desired stress in the doped material of the channel region. These conventional methods require careful selection and deposition of the conductive material in the contact trench to meet the stress requirements, as well as electrical conductivity, chemical reactivity, hermeticity, thermal budget, and other requirements for the material. In many cases, meeting the stress requirements requires a compromise: selecting a conductive material with less-than-ideal properties in some respects. Altering the deposition method or composition of the stressed material creates additional stress that can degrade the material's performance in other respects, such as electrical conductivity.

[0018]

[0021] Nevertheless, conventional methods have proven increasingly ineffective due to increasingly complex gate and channel surface orientations. That is, gate orientations in multichannel semiconductor nanostructures, such as gate-all-around, complementary FET, nanosheet, and nanowire orientations, to name just a few, hinder the effectiveness of conventional stress application. For example, conventional methods for increasing stress may be able to apply sufficient stress to the top and / or bottom gates, but they are unable to provide the necessary stress to the gate disposed therebetween. Furthermore, due at least in part to poor stress matching in addition to unfavorable surface orientations, multichannel semiconductor nanostructures also exhibit unfavorable hole and / or electron mobilities. Such hole mobility deficiencies are particularly evident compared to conventional gate and favorable channel orientations, such as fin field effect transistors (FinFETs).

[0019]

[0022] Efforts to improve channel strain in multichannel semiconductor nanostructures, particularly those involving source and drain regions formed via epitaxial growth processes, have been underway. However, due to their complex geometries and surface orientations, epitaxial merging consistently suffers from dislocations during and after formation. These dislocations can pull the epitaxially grown material away from the gate and create dislocation seams, leading to channel stress relaxation over time. This has proven problematic, particularly for hole mobility, such as in p-type metal oxide semiconductor (PMOS) regions. Methods to improve epitaxial merging defects have been explored as a way to impart consistent channel stress. However, none of the existing methods have proven sufficient to provide consistent stress, improve electron and hole mobility, or achieve a combination of both.

[0020]

[0023] The present technology overcomes these and other challenges by providing a consistent stressed channel with improved hole and / or electron mobility. By utilizing a self-aligned single diffusion break with a liner filled with one or more fill materials based on the location of the self-aligned single diffusion break within a p-MOS or n-MOS region, the stressed channel region can be imparted with a desired stress. Additionally, by utilizing a unique combination of liner and tailored fill materials, the formation of a self-aligned diffusion break can be achieved in both p-MOS and n-MOS regions without requiring an intermediate polishing step. In embodiments of the present technology, stress can be generated by depositing a stressed material within one or more self-aligned single diffusion breaks adjacent to one or more doped regions of a transistor, such as a channel region. The stressed material can initially impart stress to the one or more self-aligned single diffusion breaks, which can then transfer a portion of that stress to the channel region of the transistor.

[0021]

[0024] While the remainder of the disclosure will routinely identify particular metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductors (CMOS), and their components, it will be readily understood that the devices and methods are equally applicable to other field-effect transistors, their configurations, and processes for forming such devices. Accordingly, the present technology should not be considered limited to use solely with these particular devices or methods. This disclosure will describe one possible semiconductor device, which may include one or more components utilizing one or more self-aligned single diffusion breaks in accordance with embodiments of the present technology, before further variations and modifications to this device in accordance with embodiments of the present technology are described.

[0022]

[0025] FIG. 1 illustrates a top view of a multi-chamber processing system 100 that may be specifically configured to implement aspects or operations according to some embodiments of the present technology. The multi-chamber processing system 100 may be configured to perform one or more manufacturing processes on individual substrates, such as any number of semiconductor substrates, to form semiconductor devices. The multi-chamber processing system 100 may include some or all of the following: a transfer chamber 106, a buffer chamber 108, single-wafer load locks 110 and 112 (or dual load locks may be included), processing chambers 114, 116, 118, 120, 122, and 124, preheat chambers 123 and 125, and robots 126 and 128. The single-wafer load locks 110 and 112 may include a heating element 113 and may be attached to the buffer chamber 108. The processing chambers 114, 116, 118, and 120 may be attached to the transfer chamber 106. The processing chambers 122 and 124 may be attached to the buffer chamber 108. Two substrate transfer platforms 102 and 104 may be positioned between the transfer chamber 106 and the buffer chamber 108 to facilitate transfer between the robots 126 and 128. The platforms 102, 104 may be open to the transfer and buffer chambers, or the platforms may be selectively isolated or sealed from the chambers so that different operating pressures are maintained between the transfer chamber 106 and the buffer chamber 108. The transfer platforms 102 and 104 may each include one or more tools 105, such as for orientation or measurement operations.

[0023]

[0026] The operation of the multi-chamber processing system 100 may be controlled by a computer system 130. The computer system 130 may include any device or combination of devices configured to perform the operations described below. Accordingly, the computer system 130 may be a general-purpose computer configured with a controller or an array of controllers and / or software stored on a non-transitory computer-readable medium that, when executed, can perform the operations described in connection with methods according to embodiments of the present technology. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more processing steps in the fabrication of semiconductor structures. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform numerous substrate processing steps, including dry etching processes, cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, pre-cleaning, degassing, and orientation, among any number of other substrate processes.

[0024]

[0027] 2 illustrates exemplary steps in a method 200 according to some embodiments of the present technique. The method may be performed in a variety of processing chambers, including the processing chamber 100 described above. Method 200 may include several optional steps that may or may not be specifically associated with some embodiments of methods according to the present technique. For example, many of the steps are described to provide a broader range of structure formations, but are not critical to the technique or may be performed by alternative methods as may be readily understood.

[0025]

[0028] Method 200 may include additional steps prior to the initiation of the recited steps. For example, additional processing steps may include forming structures on a semiconductor substrate, including both the formation and removal of materials. Prior processing steps may be performed in the chamber in which method 200 is performed, or processing may be performed in one or more other processing chambers before transferring the substrate to the semiconductor processing chamber in which method 200 is performed. In either case, method 200 may optionally include providing a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 100 described above, or another chamber that may include the components described above. The substrate may be disposed on a substrate support / transfer platform, which may be a pedestal, such as substrate support 104, and which may be mounted within the processing region of a chamber, such as processing region 120 described above. Method 200 describes steps shown generally in FIGS. 3A through 3H, examples of which are described in conjunction with the steps of method 200. 3A-3H show partial schematic views only, and it will be understood that the semiconductor substrate may be of any size or configuration that further includes components as illustrated in the figures, as well as alternative components, and still benefit from aspects of the present technology. For example, FIGS. 3A-3H show a first region 307 adjacent to a second region 309. Regions 307, 309 are shown with a gap between them to indicate that first region 307 may be immediately adjacent to second region 309 or may be spaced apart from second region 309 (e.g., have one or more intermediate regions therebetween).

[0026]

[0029] Method 200 may or may not include optional steps for developing a semiconductor structure into a specific manufacturing process. It should be understood that method 200 may be performed on any number of semiconductor structures or substrates 302, including exemplary structures upon which selective deposition materials may be formed, as shown in FIGS. 3A-3H. As shown in FIG. 3A, substrate 302 may have several layers of material deposited thereon. Substrate 302 may be any number of materials, such as a base wafer or substrate made of silicon, silicon-containing materials, germanium, other substrate materials, and one or more materials that may be formed thereon during semiconductor processing.

[0027]

[0030] Structure 300 may, in embodiments, illustrate a partial view of a substrate that may be used in n-channel and p-channel MOSFETs, FinFETs, gate-all-around FETs, complementary metal-oxide semiconductors, and nanosheet FETs, among other types of semiconductor transistor structures. The layers of material may be fabricated by any number of methods, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (TECVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), or any other formation technique. In embodiments, plasma-enhanced chemical vapor deposition may be performed in a processing chamber, such as processing chamber 100 described above. The substrate layers may include silicon oxide and silicon nitride, silicon oxide and silicon, silicon nitride and silicon, silicon and doped silicon, or any number of other materials.

[0028]

[0031] As shown in FIG. 3A , a structure 300 is provided that includes a substrate 302 that has already undergone source / drain 304 formation. In some embodiments, the source / drain 304 formation may include epitaxial growth of a doped silicon material, such as silicon-germanium. However, it should be understood that the source / drain regions 304 may be formed from any suitable deposition and patterning process, as the present disclosure does not require rigorous source / drain 304 formation (e.g., attempting to heal epitaxial growth defects) to maintain hole or electron mobility. Additionally, the structure 300 includes multiple gate regions 306 and interlayer dielectric / dummy gate regions 308, which may be formed as known in the art and described above.

[0029]

[0032] In some embodiments, the structure 300 may be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate where the entire substrate is composed of a semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor substrate 300 may comprise one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In several embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 300 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 300 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although some examples of materials from which the substrate may be formed are described herein, any material that can serve as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) may be constructed is within the spirit and scope of the present disclosure.

[0030]

[0033] In embodiments, the semiconductor material may be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor made by doping an intrinsic semiconductor with an electron-donating element during fabrication. The term n-type comes from the negative charge carried by electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the wells (or holes). Relative to n-type semiconductors, p-type semiconductors have a higher hole concentration than the electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. As discussed above, in embodiments, the present technology may provide improved mobility in both p- and n-type semiconductors. However, in embodiments, p-type semiconductors may experience further hole mobility enhancement.

[0031]

[0034] Nevertheless, in step 201, method 200 may include patterning one or more mask layers 310 deposited on top surfaces of source / drain regions 304 and portions of gate regions 306 on substrate 302. For example, in some embodiments, substrate 302 is loaded into load locks 110, 112 and transferred via robots 126, 128 to a process chamber (such as process chamber 114) where a mask deposition process occurs. That is, as shown, one or more mask layers 310 are patterned over five of the seven illustrated gate regions 306, leaving two gate regions 306 exposed. However, as will be explained in more detail below, it should be understood that the patterned mask layer 310 may be positioned or spaced over one or more gate regions 306 as needed to provide the necessary stress to the channel region 316 (as shown more clearly in FIG. 4 ).

[0032]

[0035] 3B, in step 202, method 200 may include etching structure 300. In some embodiments, such step may include transferring substrate 302 to second process chamber 116 configured for an etching process. For example, in one embodiment, one or more of inductively coupled plasma (ICP) etching, reactive ion etching (RIE), or capacitively coupled plasma (CCP) etching are used to form shallow trench isolation or via 312. Furthermore, because mask layer 310 is aligned with gate region 306, shallow trench isolation 312 may be formed within and self-aligned to the gate region and may therefore be considered a self-aligned shallow trench isolation or self-aligned single diffusion break. Furthermore, in some embodiments, the first gate region 307, which may be an n-MOS region, includes a first self-aligned diffusion break 301 (which may be a pair of breaks 301 in some embodiments), and the second gate region 309, which may be a p-MOS region, includes a second self-aligned diffusion break 303 (or a pair of breaks 303 in some embodiments), or vice versa, although other configurations may be utilized. However, it will be apparent that the semiconductor substrate may include more than two diffusion breaks (or more than two pairs of diffusion breaks) based on the size of the structure. Additionally, while the self-aligned diffusion breaks are illustrated as being in separate regions, as is known in the art, it will be apparent that other arrangements, including adjacent ones within the same region, are contemplated, since the methods provided by the present technology enable the formation of different materials within adjacent or spaced apart self-aligned diffusion breaks.

[0033]

[0036] After etching the structure 300 in step 202, the method 200 may include an optional passivation and / or oxidation process after removal of the mask layer(s) 310, as shown in FIG. 3C. Nevertheless, the etched substrate 302 may be transferred to a third process chamber 118 configured for a deposition and / or fill process, including a chamber for chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), etc. For example, within such process chamber 118, as shown in FIG. 3C, in step 203, a liner 328 may be formed within the first self-aligned diffusion break 301 and the second self-aligned diffusion break 303 along the perimeter 330 (or outer wall) of each respective self-aligned diffusion break 301, 303.

[0034]

[0037] In embodiments, the liner 328 may be formed from any dielectric material having an etch rate different from that of the second fill material, as known in the art, as will be described in more detail below. For example, exemplary liner materials include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide, silicon dioxide, aluminum oxide, and carbon-containing organic materials, and combinations thereof, among other types of dielectric materials. Nevertheless, in embodiments, the liner may be a dielectric material such as silicon nitride, silicon oxynitride, silicon dioxide, or other similar materials. In embodiments, the liner 328 may be referred to as a first liner (e.g., a portion of the liner disposed within the first self-aligned diffusion break) and a second liner (e.g., a portion of the liner disposed within the second self-aligned diffusion break), because the liner 328 may not be continuous between each diffusion break. However, in some embodiments, the first liner and the second liner may be formed from the same or different materials, and may be formed from any one or more of the materials listed above.

[0035]

[0038] In some embodiments, the liner 328 can be characterized by a thickness of about 0.5 nm or more, e.g., about 1 nm or more, about 1.5 nm or more, about 2 nm or more, about 2.5 nm or more, about 3 nm or more, about 3.5 nm or more, about 4 nm or more, about 4.5 nm or more, about 5 nm or more, or more. Furthermore, the liner 328 can be characterized by a thickness of about 8 nm or less, e.g., about 7 nm or less, about 6 nm or less, about 5 nm or less, about 4.5 nm or less, or less, or any range or value therebetween. By utilizing a liner thickness within the above range, degradation of breakdown voltage can be avoided while imparting significant stress to the channel region. That is, the liner thickness transfers less stress from the respective fill material to the channel region. Therefore, it is important to balance a liner thickness sufficient to prevent degradation of breakdown voltage without losing the desired stress.

[0036]

[0039] After forming liners in the first self-aligned diffusion break 301 and the second self-aligned diffusion break 303 in step 203, method 200 may include a filling step 204, in which a first fill material 314 is provided in both the first self-aligned diffusion break and the second self-aligned diffusion break. Filling step 204 may occur within the same deposition chamber 218, or the substrate 302 may be transferred to an additional process chamber. In embodiments, filling with first fill material 314 may occur via chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), or the like. In embodiments, first fill material 314 may be filled via plasma-enhanced atomic layer deposition.

[0037]

[0040] In embodiments, the fill may be performed with a stressed material, such as a tensile stress material, or may include an unstressed material (e.g., a neutral stress material). However, the tensile stress material may be filled as an unstressed material and then configured to provide the necessary stress. For example, when an unstressed material is used, but an overall tensile stress is desired, further processing can be utilized to impart the necessary stress to the filled material. In embodiments, the first fill material may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide, silicon dioxide, aluminum oxide, and carbon-containing organic materials, and combinations thereof, among other types of dielectric materials. In embodiments, the first fill material may include silicon dioxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0038]

[0041] Furthermore, as described above, the first fill material can be a neutral stress material or a tensile stress material. Thus, in some embodiments, a tensile stress material may be utilized (or a tensile stress may be induced in the stressed dielectric material). For example, a high-oxygen deposition environment or UV curing may be utilized, and may be utilized in conjunction with any one or more of the first fill materials described above, by way of example only. Nevertheless, the present technique has discovered that deposition of a tensile stress dielectric material within a single self-aligned diffusion break in the n-MOS region can further improve electron mobility and n-MOS current drive characteristics without adversely affecting hole mobility and p-MOS current drive characteristics as described herein.

[0039]

[0042] In embodiments, the first fill may be characterized by a neutral stress of about 0 MPa (e.g., about -10 to about 10 MPa, e.g., about -7.5 MPa to about 7.5 MPa, e.g., about -5 MPa to about 5 MPa, e.g., about -2.5 MPa to about 2.5 MPa, e.g., about -1 MPa to about 1 MPa, or any range or value therebetween), or a tensile stress of about 250 MPa or greater, e.g., about 350 MPa or greater, e.g., about 400 MPa or greater, about 500 MPa or greater, about 600 MPa or greater, about 700 MPa or greater, about 800 MPa or greater, about 900 MPa or greater, about 1 GPa or greater, or greater, or any range or value therebetween. For purposes of this disclosure, a higher stress material is characterized by an absolute value of stress, whether positive or negative, that is greater than the absolute value of a lower stress material. In the convention used herein, positive stress is characterized by tensile stress, negative stress is characterized as compressive stress, and zero stress (i.e., 0 GPa) is characterized as neutral stress. Positive (i.e., tensile) stress may be characterized by an outward extrusive force that may be generated by the expansion of a material. Negative (i.e., compressive) stress may be characterized by an inward pulling force that may be generated by the contraction of a material. Thus, as used herein, a "compressive stress" value may refer to a negative absolute value (e.g., a compressive stress of 250 MPa may also be read as -250 MPa), and as used herein, a "tensile stress" value may refer to a positive absolute value (e.g., a tensile stress of 250 MPa refers to 250 MPa).

[0040]

[0043] Thus, in addition to the improvements described herein with respect to improving hole mobility in the p-MOS region, increased stress in the channel region is believed to enhance the mobility of charge carriers in the channel, thereby increasing the drive current through the n-MOS channel region. In some examples, the increased stress generated in the channel region by embodiments of the present technology may increase the drive current through the transistor channel by about 1% or more, e.g., about 5% or more, about 10% or more, about 15% or more, about 20% or more, about 25% or more, about 30% or more, about 35% or more, about 40% or more, about 45% or more, about 50% or more, about 55% or more, or more, or any range or value therebetween. The increase in drive current and hole mobility through the channel region may improve transistor performance in several ways, including, but not limited to, improved switching speed and / or reduced power consumption.

[0041]

[0044] Nevertheless, in some embodiments, the first fill material may be selected to have an etch rate that is different from the etch rate of the liner 328. For example, in some embodiments, both the liner 328 and the first fill material may be dielectric materials, and both may be independently selected from silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide, silicon dioxide, aluminum oxide, and carbon-containing organic materials, and combinations thereof (e.g., in some embodiments, silicon nitride, silicon oxide, silicon oxynitride), among other types of dielectric materials. However, in some embodiments, the first fill material is selected to be a material that is different from the liner material. Nevertheless, as shown, the liner 328 forms a barrier between the first fill material 314 and the adjacent source-drain regions 304.

[0042]

[0045] In some embodiments, the first fill material may be filled into the lined 328 self-aligned diffusion breaks 301, 303 using a void-free, stressed deposition process as known in the art. For example, chemical vapor deposition (CVD) and ALD (including PEALD) deposition of these materials may include using any suitable precursor. For example, CVD and ALD, as well as other fill processes such as those described above known in the art, may be suitable for deposition utilizing any suitable precursor of the first and / or second fill material.

[0043]

[0046] Nevertheless, in embodiments, deposition of the first fill material 314 may occur at a temperature of about 150° C. or greater, e.g., about 200° C. or greater, about 250° C. or greater, about 300° C. or greater, about 350° C. or greater, about 400° C. or greater, or greater. Additionally, deposition of the first fill material may be performed at a temperature of about 500° C. or less, e.g., about 450° C. or less, or any range or value therebetween.

[0044]

[0047] After the first fill step 204, a second patterning step 205 is performed. As shown in FIG. 3E, in step 205, one or more mask layers 340 are patterned / deposited over the top surfaces of the source / drain regions 304 and portions of the gate regions 306 on the substrate 302. However, unlike step 201, as shown in FIG. 3E, one or more mask layers 340 (which may be formed from the same or different material as mask layer 310) are patterned over five of the seven shown gate regions 306, as well as the first self-aligned diffusion break 301, leaving the second self-aligned diffusion break 303 (e.g., in the p-MOS region) exposed. In some embodiments, the mask 340 may leave more than one self-aligned diffusion break exposed, such as a portion or each of the self-aligned diffusion breaks in the p-MOS region, while covering a portion or each of the self-aligned diffusion breaks in the n-MOS region.

[0045]

[0048] As shown in FIG. 3F , in step 206, the method 200 may include etching the structure 300 having the first fill material disposed within the first and second self-aligned diffusion breaks 301, 303. In some embodiments, such a step may include transferring the substrate 302 back to the second process chamber 116 or to an additional process chamber configured for an etching process. For example, in one embodiment, one or more of an inductively coupled plasma (ICP) etch, a reactive ion etch (RIE), or a capacitively coupled plasma (CCP) etch are used to remove the first fill material 314 from the second self-aligned diffusion break. In embodiments, the etching process may be a wet or dry etching process using hydrofluoric acid, phosphoric acid, or the like, as well as other etchants known in the art, or based on the first fill material and liner material utilized.

[0046]

[0049] That is, as described above, in some embodiments, the first fill material and the liner can be selected to have different etch rates. In this manner, the first fill material can be effectively removed from the lined second self-aligned diffusion break without damaging the surrounding structure. For example, the liner 328 can remain in place while the first fill material 314 can be selectively etched, protecting the sides and underside of the second self-aligned diffusion break. Furthermore, such a process also allows different materials to be deposited and filled into the first and second self-aligned diffusion breaks without an intermediate polishing step (e.g., between the first and second material fills, as described below). Thus, the present technique provides a structure that reduces surface loss and improves the electrical properties of the semiconductor structure because, in some embodiments, the semiconductor structure does not undergo an intermediate polishing step.

[0047]

[0050] After removing the first fill material 314 from the second self-aligned diffusion break in step 206, the second self-aligned diffusion break 303 (e.g., located in the p-MOS region) may be filled with a compressive stress material 342. The compressive stress material may be filled into the lined second self-aligned diffusion break 303 using atomic layer deposition, plasma-enhanced atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, among other types of deposition techniques as described above. In embodiments, the second fill material 342 may be a dielectric material, such as any one or more of the dielectric materials described above. However, unlike the first fill material 314, the second fill material (compressive stress material) 342 need not be different from the liner 328. Thus, in embodiments, the compressive stress material may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide, silicon dioxide, aluminum oxide, and carbon-containing organic materials, and combinations thereof, among other types of dielectric materials. They may be the same material as the liner 328 material or may be a different material. In some embodiments, the compressive stress material may be silicon nitride, silicon oxynitride, silicon dioxide, or a combination thereof. In some embodiments, the compressive stress material may be selected to be a different material than the first fill material.

[0048]

[0051] Nevertheless, to deposit a compressive stress material, deposition of the compressive stress material may be performed by utilizing increased RF power, higher deposition temperatures, higher kinetic energy plasma levels, or combinations thereof. Thus, in embodiments, the deposition process may be performed at a deposition temperature of about 150°C or higher, e.g., about 200°C or higher, e.g., about 250°C or higher, e.g., about 300°C or higher, e.g., about 350°C or higher, e.g., about 400°C or higher, e.g., about 450°C or higher, e.g., about 500°C or higher, e.g., about 550°C or higher, e.g., about 600°C or higher, e.g., up to about 700°C, e.g., up to about 650°C, or any range or value therebetween.

[0049]

[0052] In embodiments, the compressive stress material may be characterized by a stress of about 250 MPa or more, such as about 350 MPa or more, for example, about 500 MPa or more, for example, about 1 GPa or more, for example, about 1.5 GPa or more, for example, about 2 GPa or more, such as about 2.25 GPa or more, for example, about 2.5 GPa or more, for example, about 2.75 GPa or more, for example, about 3 GPa or more, or a range or value therebetween.

[0050]

[0053] However, in some embodiments, the second self-aligned diffusion break 303 is filled with a compressive stress material and / or the first self-aligned diffusion break 301 is filled with a neutral or tensile stress material. It should be understood that the volume defined by each self-aligned diffusion break may be filled with the respective material at about 90% by volume or more, e.g., about 92% by volume or more, about 94% by volume or more, about 96% by volume or more, about 98% by volume or more, about 99% by volume or more, or any range or value therebetween. In some embodiments, the volume defined by the self-aligned diffusion break may be completely filled with the respective material, and no voids or seams may be present. That is, current technology has found that even small voids within a self-aligned diffusion break can result in a dramatic reduction in channel stress. For example, a void or seam characterized by a size of about 3 nm or less, e.g., about 2 nm or less, or about 1 nm or less, may result in a reduction in average channel stress of more than 60%.

[0051]

[0054] Thus, in some embodiments, to obtain a high volume percentage and reduce voids and seams, the fill steps 204 and / or 207 may simply involve forming a thin layer of the respective fill material, etching back a portion of the fill material, then filling with another thin layer of the respective fill material, and repeating in a cyclic in-situ manner until a self-aligned diffusion break is completed. Such a process may be particularly useful for high aspect ratio diffusion breaks, as the cyclic process avoids pinch-off, allows for smaller volume voids and seams, and allows for a higher volume occupation of the stressed dielectric material.

[0052]

[0055] As described above, the present technology has discovered that even thin layers of compressive stress material and / or tensile stress material (when utilized) can be effective for imparting stress when utilized within each self-aligned diffusion break. Accordingly, the thicknesses described above may represent the overall width of the self-aligned diffusion break. In such cases, each self-aligned diffusion break may define a channel length L, defined as the distance between the source and drain regions, as shown in FIG. 4 . The channel length L may be characterized by a length of about 35 nm or less, e.g., about 30 nm or less, about 25 nm or less, about 20 nm or less, or any range or value therebetween. In embodiments, the self-aligned diffusion break may be considered to be characterized by a high aspect ratio due to the small channel length and large diffusion break depth. Additionally, in embodiments, only a single self-aligned diffusion break is utilized within structure 300, and not a double diffusion break, yet still imparting the necessary stress, thus allowing for a reduced size while maintaining effectiveness.

[0053]

[0056] Nevertheless, after formation of the liner 328, first fill material 314, and second fill material 342, the substrate 302 may be transferred to a fourth process chamber 120, such as a process chamber configured for polishing, including chemical-mechanical polishing. Accordingly, in step 205, the method 200 may include polishing the structure 300 (e.g., chemical-mechanical polishing the top surface 332 of the structure 300 (FIG. 3G)). A further view of FIG. 3G is shown in FIG. 3H, where the interlayer dielectric 308 and gate region 306 have been removed for clarity. Additionally, FIG. 4 shows a cross-sectional view of an exemplary embodiment, such as along line A-A' in FIG. 3H. FIG. 4 may more clearly show the source / drain regions 304, the gate region 306, and the channel region 316. As shown, in some embodiments, the structure 300 may have a horizontal gate-all-around orientation, with multiple horizontally extending channels 326 within the channel region 316. For example, in some embodiments, the channel 326 may be generally parallel to the top surface 336 of the substrate 302 .

[0054]

[0057] That is, the present technology has surprisingly discovered that by utilizing a liner 328 around the perimeter 330 of the first and second self-aligned diffusion breaks 301, 303, and then filling the first self-aligned diffusion break 301 with a first fill material 314 of a tensile or neutral stress material and filling the second self-aligned diffusion break 303 with a compressive stress material 342, excellent electron and / or hole mobility can be achieved without imparting surface losses to the semiconductor structure. The same is true even for structures with unfavorable surface orientations. Furthermore, by utilizing a combination of fill material and liner within the self-aligned diffusion breaks as described herein, the present technology can transfer compressive stress from the stressed compressive stress material to the adjacent channel region, either alone or in some embodiments in combination with tensile stress from the first fill material, without suffering relaxation of the channel stress as demonstrated in known technology.

[0055]

[0058] For example, in the present technology, one or more channel regions 316 (FIG. 3H, shown more clearly in FIG. 4) are increased from a lower stress (a first stress amount prior to incorporating a filler material) to a higher stress (a second stress amount after forming one or more stressed diffusion breaks). In embodiments, the change in percentage of stress in the channel region 316 from the first stress amount to the second stress amount can be about 0.1% or more, e.g., about 1% or more, about 2% or more, about 5% or more, about 10% or more, about 25% or more, about 50% or more, about 75% or more, about 100% or more, or more, or any range or value therebetween. In further embodiments, the first stress amount in the channel region 316 can be about 10 MPa or less, e.g., about 5 MPa or less, about 1 MPa or less, or less. In further embodiments, the second amount of stress in the channel region 316 can be about 100 MPa or more, e.g., about 200 MPa or more, about 300 MPa or more, about 400 MPa or more, about 500 MPa or more, about 600 MPa or more, or any range or value therebetween.

[0056]

[0059] Additionally, in embodiments, the present technology has found that such stress can be evenly distributed throughout the channel region 316. As mentioned above, previous attempts have utilized stressed materials above and below the channel region. However, conventional techniques may limit stress improvements to the upper side 318 of the channel region 316 and / or the lower side 320 of the channel region 316. Thus, conventional techniques have failed to provide consistent stress throughout the channel. Conversely, it should be understood that in embodiments, the present technology can have a first channel stress at a first location 322 within the channel region 316 (illustrated adjacent the lower portion 320 of the channel 316 for illustrative purposes only; the first location 322 can be anywhere within the channel region 316) and a second channel stress at a second location 324 within the channel region 316. As shown, the first location 322 can be vertically spaced from the second location 324 for illustrative purposes. However, in some embodiments, the regions may be spaced apart horizontally, or may be spaced apart both vertically and horizontally. Nevertheless, the stress in the first channel may vary from the stress in the second channel by about 30% or less, e.g., about 27.5% or less, about 25% or less, about 22.5% or less, about 20% or less, about 17.5% or less, about 15% or less, about 12.5% ​​or less, about 10% or less, or any range or value therebetween.

[0057]

[0060] Furthermore, as described above, increased stress in the channel region is believed to improve the mobility of charge carriers in the channel, which may also increase the drive current through the channel region. In particular, the increased stress generated in the channel region in embodiments of the present technology may enhance the drive current, such as the p-MOS drive current and / or the n-MOS drive current, through the transistor channel by about 1% or more, e.g., about 5% or more, about 10% or more, about 15% or more, about 20% or more, about 25% or more, about 30% or more, about 35% or more, about 40% or more, about 45% or more, about 50% or more, about 55% or more, or any range or value therebetween. In embodiments, increased stress in the channel region can lead to further improvements in hole mobility, such as by about 10% or more, about 20% or more, about 30% or more, about 40% or more, about 50% or more, about 60% or more, about 70% or more, about 80% or more, about 90% or more, about 100% or more, about 110% or more, about 120% or more, about 130% or more, about 140% or more, about 150% or more, or any range or value therebetween. Increased drive current and hole mobility through the channel region can improve transistor performance in several ways, including, but not limited to, improved switching speed and / or reduced power consumption. Embodiments of the present technology can achieve these improvements in semiconductor devices without imposing limitations on the types of materials used in the devices, which may create new processing challenges or otherwise compromise device performance.

[0058]

[0061] In some embodiments, the self-aligned diffusion break may define a channel length L, defined as the distance between the source and drain regions, as shown in FIG. 4 . The channel length L may be characterized by a length of about 35 nm or less, e.g., about 30 nm or less, about 25 nm or less, about 20 nm or less, or any range or value therebetween. The self-aligned diffusion break may be characterized by a high aspect ratio due to the small channel length and large diffusion break depth. Additionally, in some embodiments, only a single self-aligned diffusion break is utilized in structure 300, and not a double diffusion break, yet still imparts the necessary stress, thus allowing for a reduced size while maintaining effectiveness.

[0059]

[0062] Furthermore, although the illustrated embodiments include two single self-aligned diffusion breaks 301, 303 on either side of three gate regions 306 in Figures 3A-3H and two single self-aligned diffusion breaks 301, 303 on either side of a single gate region 306 in Figure 4, it should be understood that the self-aligned diffusion breaks may be positioned with any number of gate regions 306 between the pair of diffusion breaks. For example, one gate region 306, e.g., two gate regions, three gate regions, e.g., four gate regions, e.g., five gate regions, e.g., six gate regions, e.g., seven gate regions, or more gate regions may be positioned between the pair of diffusion breaks depending on the desired stress on the channel region 316 in the structure 300. For example, the number of channel regions 304 disposed between the opposing self-aligned diffusion breaks 312 may be selected to maintain a channel stress of about 350 MPa or more, e.g., about 400 MPa or more, about 450 MPa or more, about 500 MPa or more, about 550 MPa or more, e.g., about 650 MPa or more, e.g., 750 MPa or more, e.g., about 850 MPa or more, e.g., about 950 MPa or more, e.g., about 1000 MPa or more, or more, or any range or value therebetween.

[0060]

[0063] As described above, in some embodiments, the stress imparted by the compressive stress material can significantly improve mobility and drive current. Furthermore, in some desirable embodiments, the tensile-stressed first fill material can also improve the mobility and drive current of the n-MOS region. Thus, in addition to the improvements described above, increased stress in the channel region can improve the mobility of charge carriers in the channel, which can also increase the drive current through the n-MOS region. In some embodiments, the increased stress created in the channel region by embodiments of the present technology increases the drive current through the transistor channel (in the n-MOS region, in the p-MOS region, or in both the n-MOS and p-MOS regions) by about 1% or more, e.g., about 5% or more, about 10% or more, about 15% or more, about 20% or more, about 25% or more, about 30% or more, about 35% or more, about 40% or more, about 45% or more, about 50% or more, about 55% or more, or more, or any range or value therebetween. Increasing the drive current and hole mobility through the channel region may improve the performance of the transistor in several ways, including, but not limited to, improved switching speed and / or reduced power consumption.

[0061]

[0064] In the above description, for purposes of explanation, numerous details are presented in order to facilitate an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details, or with additional details.

[0062]

[0065] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, some well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Therefore, the foregoing description should not be deemed to limit the scope of the technology.

[0063]

[0066] Where a range of values ​​is given, unless the context clearly indicates otherwise, each intervening value between the upper and lower limit of that range is specifically disclosed, to the smallest unit of the lower limit. Any smaller ranges between any stated or unstated intervening value in a stated range, and any other stated or intervening value in that stated range, are also included. The upper and lower limits of such narrower ranges may individually be included or excluded from that range. Each range where either, neither, or both limits are included in this narrower range is also encompassed within the technology, even though there may be specifically excluded limits in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0064]

[0067] As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a dielectric material" includes a plurality of such materials, a reference to "a gate region" includes reference to one or more gate regions, and equivalents thereof known to those skilled in the art, and so forth.

[0065]

[0068] Additionally, the terms "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including," when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or operations, but do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. substrate, Source region, Drain region, a channel region including at least one channel disposed between the source and the drain; a first gate region including a first self-aligned single diffusion break in the n-MOS region, the first self-aligned single diffusion break including a first liner and a first fill material; and 1. A semiconductor device comprising: a second gate region including a second self-aligned single diffusion break within a p-MOS region, the second self-aligned single diffusion break comprising a compressive stress-filling material, the compressive stress-filling material being characterized by a compressive stress of greater than or equal to about 350 MPa.

2. The semiconductor device of claim 1 , wherein the first fill material is a neutral stress material or a tensile stress material.

3. 3. The semiconductor device of claim 2, wherein the first fill material, the compressive stress fill material, or both the first fill material and the compressive stress fill material comprise a dielectric fill material.

4. 4. The semiconductor device of claim 3, wherein both the first fill material and the compressive stress fill material comprise a dielectric fill material, and the first fill material is different from the compressive stress fill material.

5. The semiconductor device of claim 3 , wherein the dielectric fill material comprises silicon nitride, silicon oxynitride, silicon dioxide, or a combination thereof.

6. The semiconductor device of claim 1 , wherein the second self-aligned single diffusion break comprises a second liner.

7. The semiconductor device of claim 6 , wherein the first liner, the second liner, or both the first liner and the second liner comprise a dielectric liner material.

8. The semiconductor device of claim 7 , wherein the dielectric liner material comprises silicon nitride, silicon oxynitride, silicon dioxide, or a combination thereof.

9. The semiconductor device of claim 7 , wherein the dielectric liner material of the first liner has an etch rate that is different from an etch rate of the first fill material.

10. The semiconductor device of claim 7 , wherein the dielectric liner material of the second liner is selected from the same material or a different material than the compressive stress-filling material.

11. The semiconductor device of claim 7 , wherein the second liner comprises silicon nitride, silicon dioxide, or a combination thereof, and the compressive stress-filling material comprises silicon dioxide, silicon nitride, or a combination thereof.

12. 12. The semiconductor device of claim 11, wherein the first fill material comprises silicon nitride, silicon dioxide, or a combination thereof, and the compressive stress fill material is different from the first fill material.

13. 10. The semiconductor device of claim 1, wherein the semiconductor device is a nanosheet field effect transistor or a complementary field effect transistor, and / or the semiconductor device is a gate-all-around complementary metal oxide semiconductor.

14. 1. A semiconductor processing system comprising: a first processing chamber; a second processing chamber; a third processing chamber; and a system controller, the system controller comprising: patterning a substrate in the first processing chamber; in the second processing chamber, etching a first shallow trench isolation in a first gate region of a semiconductor device and etching a second shallow trench isolation in a second gate region of the semiconductor device, wherein the first gate region is an n-MOS region and the second gate region is a p-MOS region; and and, in the third processing chamber, lining the first shallow trench isolation and the second shallow trench isolation with a dielectric liner, filling the first shallow trench isolation and the second shallow trench isolation with a neutral stress material or a tensile stress material, removing the neutral stress material or the tensile stress material from the first shallow trench isolation, and filling the first shallow trench isolation with a compressive stress material.

15. 1. A method of forming a semiconductor device, comprising: etching a first shallow trench isolation in a first gate region of the semiconductor device and etching a second shallow trench isolation in a second gate region of the semiconductor device, the first gate region being an n-MOS region and the second gate region being a p-MOS region, the semiconductor device including a substrate, a source region, a drain region, and a channel region including at least one channel disposed between the source and the drain; lining the first shallow trench isolation and the second shallow trench isolation with a liner; filling the lined first shallow trench isolation and the lined second shallow trench isolation with a neutral stress material or a tensile stress material; Etching the neutral stress material or the tensile stress material from the second shallow trench isolation; and filling the etched second shallow trench isolation with a compressive stress material.

16. 16. The method of claim 15, wherein no polishing step is performed between filling the lined first shallow trench isolation with the neutral stress material or the tensile stress material and filling the etched second shallow trench isolation with the compressive stress material.

17. 16. The method of claim 15, wherein etching the neutral stress material or the tensile stress material is a wet etching process or a dry etching process.

18. 20. The method of claim 17, wherein the liner comprises a dielectric liner material having an etch rate different from an etch rate of the neutral stress material or the tensile stress material.

19. The method of claim 18 , wherein the liner comprises silicon nitride, silicon oxynitride, silicon dioxide, or a combination thereof.

20. 20. The method of claim 19, wherein the compressive stress material comprises silicon nitride and the neutral stress material or the tensile stress material comprises silicon nitride or silicon dioxide.

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