Overlay correction for photolithography

The lithography system addresses alignment challenges in semiconductor packaging by measuring and compensating for positional variations in die placement, ensuring accurate electrical connections and improved performance through compensated mask patterns.

JP2026506895APending Publication Date: 2026-02-27APPLIED MATERIALS INC
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Patent Information

Application Number
JP2025546019
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Priority Date
2023-02-13
Filing Date
2024-02-13
Publication Date
2026-02-27

AI Technical Summary

Technical Problem

The increasing integration density of electronic components in semiconductor devices necessitates smaller semiconductor dies and more ingenious packaging techniques, but existing lithography systems struggle to accurately align and connect components due to shifts, rotations, and expansions caused by processes like die pick-and-place, leading to reduced I/O density, increased power consumption, and degraded chip performance.

Method used

A lithography system and method that measures element and package marks, determines variations, generates compensated patterns for masks, and performs lithography processes to form aligned and connected semiconductor elements, using a single or multiple masks to correct for shifts, rotations, and expansions, ensuring proper electrical connections.

Benefits of technology

The system effectively aligns and connects semiconductor elements, maintaining electrical connections and improving I/O density while reducing power consumption and enhancing chip performance by accounting for positional variations in the packaging process.

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Abstract

FIELD OF THE INVENTION [0002] Embodiments of the present disclosure generally relate to lithography systems. In particular, embodiments of the present disclosure relate to lithography systems, software applications, and methods for semiconductor packaging. The packaging method and application implemented by the system includes measuring positions of one or more element marks and one or more package marks for a plurality of packages, each package having one or more first elements, at least one package corresponding to a respective field area of ​​a mask, determining variations between each of the element marks and element positions for the first mask pattern and between each of the package marks and package positions for the first mask pattern, generating a compensated pattern for at least one mask having a second pattern of a second element, and performing a lithography process using the at least one mask for the plurality of field areas to form the second pattern of the second element.
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