Solar cell and its manufacturing method, solar module

Abstract

The present application discloses a solar cell, a manufacturing method thereof, and a solar module, the solar cell comprising: a semiconductor substrate having opposite first and second surfaces; a doped semiconductor layer provided on the first surface of the semiconductor substrate; a dielectric layer provided on the side of the doped semiconductor layer opposite the semiconductor substrate and including a plurality of openings exposing a partial region of the doped semiconductor layer, the dielectric layer having a plurality of holes formed on the side of the doped semiconductor layer opposite the semiconductor substrate of the portion of the doped semiconductor layer exposed in the opening; and an electrode provided on the side of the dielectric layer away from the semiconductor substrate and electrically connected to the doped semiconductor layer through the opening in the dielectric layer. The present application reduces the risk of the electrode becoming detached from the doped semiconductor layer and improves the structural reliability of the solar cell.

Description

[Technical Field]

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a manufacturing method thereof, and a solar module.

[0002] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to Chinese Patent Application No. 202410160240.1 filed on February 4, 2024, Chinese Patent Application No. 202510082596.2 filed on January 17, 2025, Chinese Patent Application No. 202510081229.0 filed on January 17, 2025, Chinese Patent Application No. 202510080848.8 filed on January 17, 2025, and Chinese Patent Application No. 202510081825.9 filed on January 17, 2025, the entire contents of which are incorporated herein by reference. [Background technology]

[0003] Currently, solar cells have been widely used as a new alternative energy source. Photovoltaic solar cells are devices that convert solar light energy into electrical energy. Specifically, solar cells use the photovoltaic principle to generate carriers, and then extract the carriers through electrodes, thereby contributing to the efficient use of electrical energy.

[0004] In conventional high-temperature metallization processes, high-temperature silver paste is sintered at high temperatures onto a dielectric layer such as silicon nitride, allowing the paste to form good metal contact with the underlying doped semiconductor layer through the silicon nitride interface. However, due to the high cost of high-temperature silver paste, the industry has been actively researching other metallization processes in recent years. Summary of the Invention [Problem to be solved by the invention]

[0005] The present application aims to provide a solar cell, a manufacturing method thereof, and a solar module, which can reduce the cost of the metallization process, increase the bonding strength between the electrode and the doped semiconductor layer on the semiconductor substrate, reduce the risk of the electrode detaching from the doped semiconductor layer, and improve the structural stability of the solar cell. [Means for solving the problem]

[0006] According to a first aspect of the present application, there is provided a solar cell comprising: a semiconductor substrate having opposite first and second surfaces; a doped semiconductor layer provided on the first surface of the semiconductor substrate; a dielectric layer provided on the side of the doped semiconductor layer opposite the semiconductor substrate and including a plurality of openings exposing a partial region of the doped semiconductor layer, wherein a plurality of holes are formed in the dielectric layer on the side of the doped semiconductor layer opposite the semiconductor substrate of the portion exposed in the opening; and an electrode provided on the side of the dielectric layer away from the semiconductor substrate and electrically connected to the doped semiconductor layer through the opening in the dielectric layer.

[0007] According to a second aspect, there is provided a solar module including a plurality of cell strings each including a plurality of solar cells and a plurality of connection members for connecting the plurality of solar cells in series, wherein the solar cells are the solar cells described in any one of the claims of the present application.

[0008] According to a third aspect, there is provided a method for manufacturing a solar cell, comprising the steps of: providing a semiconductor substrate having opposite first and second surfaces; forming a doped semiconductor layer on the first surface and / or the second surface; forming a dielectric layer on the side of the doped semiconductor layer opposite the semiconductor substrate; forming a through opening in the dielectric layer so that at least a portion of the doped semiconductor layer is exposed, and forming a plurality of holes on the side of the doped semiconductor layer opposite the semiconductor substrate of the portion exposed in the opening; and forming an electrode in the opening and electrically connecting the electrode to the doped semiconductor layer. [Brief explanation of the drawings]

[0009] The drawings described herein are intended to further the understanding of the present application and constitute a part of the present application, and the illustrative embodiments and descriptions thereof are intended to interpret the present application and are not intended to unduly limit the present application.

[0010] [Figure 1] 1 is a cross-sectional schematic diagram of a first structure of a solar cell provided in an example of the present application. [Figure 2] FIG. 2 is a cross-sectional schematic diagram of a second structure of a solar cell provided in an example of the present application. [Figure 3] FIG. 1 is a schematic diagram of a solar cell provided in an example of the present application after laser patterning. [Figure 4] 1 is a cross-sectional schematic diagram of a first structure of a back-contact solar cell provided in an example of the present application. [Figure 5] FIG. 2 is a cross-sectional schematic diagram of a second structure of a back-contact solar cell provided in an embodiment of the present application. [Figure 6] FIG. 2 is a cross-sectional schematic diagram of a third structure of a back-contact solar cell provided in an embodiment of the present application. [Figure 7] FIG. 2 is a cross-sectional schematic diagram of a fourth structure of a back-contact solar cell provided in an embodiment of the present application. [Figure 8-1] 1 is an SEM image of the open surface of a solar cell provided in an example of the present application. [Figure 8-2] FIG. 2 is a scanning electron microscope topography view of a solar cell provided in an example of the present application, viewed from above an opening. [Figure 8-3] FIG. 2 is a scanning electron microscope topography view of an N-type doped semiconductor layer of a solar cell provided in an example of the present application, viewed from above an opening. [Figure 8-4] FIG. 2 is a scanning electron microscope topography view of a P-type doped semiconductor layer of a solar cell provided in an example of the present application, viewed from above an opening. [Figure 8-5] FIG. 2 is a scanning electron microscope topography view of an opening in an N-type doped semiconductor layer of a solar cell provided in an example of the present application. [Figure 8-6]FIG. 2 is a scanning electron microscope topography view of an opening in a P-type doped semiconductor layer of a solar cell provided in an example of the present application. [Figure 8-7] FIG. 2 is a scanning electron microscope topography view of an opening in an N-type doped semiconductor layer of another solar cell provided in an example of the present application. [Figure 8-8] FIG. 2 is a scanning electron microscope topography view of an opening in a P-type doped semiconductor layer of another solar cell provided in an example of the present application. [Figure 8-9] FIG. 2 is a diagram showing the doping concentration distribution ECV measurement in the thickness direction of an N-type doped semiconductor layer provided in an example of the present application. [Figure 8-10] FIG. 2 is a diagram showing the doping concentration distribution ECV measurement in the thickness direction of a P-type doped semiconductor layer provided in an example of the present application. [Figure 8-11] 1 is a cross-sectional structural view of a solar cell provided in an embodiment of the present application. [Figure 8-12] FIG. 8-4 is a partial enlarged view of a portion A in the edge region of the opening shown in FIG. 8-3. [Figure 8-13] FIG. 2 is an oxygen elemental scan of the surface of a solar cell provided in an example of the present application after laser patterning. [Figure 9-1] FIG. 2 is a cross-sectional schematic diagram of a third structure of a solar cell provided in an embodiment of the present application. [Figure 9-2] FIG. 1 is a cross-sectional schematic diagram of a fifth structure of a back-contact solar cell provided in an embodiment of the present application. [Figure 10] 1 is a structural schematic diagram 1 of a solar cell in a manufacturing process according to an embodiment of the present invention; [Figure 11] 2 is a structural schematic diagram 2 of the solar cell in the manufacturing process according to the embodiment of the present invention; [Figure 12] 3 is a structural schematic diagram 3 of the solar cell in the manufacturing process according to the embodiment of the present invention; [Figure 13] 4 is a structural schematic diagram 4 of the solar cell in the manufacturing process according to the embodiment of the present invention. [Figure 14] 5 is a structural schematic diagram 5 of the solar cell in the manufacturing process according to the embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present application will be described with reference to the drawings. However, it should be understood that these descriptions are merely illustrative and do not limit the scope of the present application. In the following description, descriptions of known structures and techniques will be omitted to avoid unnecessary confusion with the concept of the present application.

[0012] The drawings show various structural schematic diagrams according to the embodiments of the present application. These drawings are not drawn to scale, and some details may be enlarged and some details may be omitted for clarity. The shapes of various regions and layers shown in the drawings, as well as the relative sizes and positional relationships between them, are merely exemplary, and may vary in practice due to manufacturing tolerances and technical limitations. Furthermore, those skilled in the art can separately design regions / layers having different shapes, sizes, and relative positions according to actual needs.

[0013] In the context of the present application, when a layer / element is described as being "on" another layer / element, the layer / element may be directly on top of the other layer / element, or an intermediate layer / element may exist between them. Also, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "under" the other layer / element when the orientation is changed. In order to make the technical problems, technical solutions, and beneficial effects that the present application aims to solve more clear, the present application will be described in more detail below in combination with figures and examples. It should be understood that the specific examples described herein are merely for the purpose of interpreting the present application, and are not intended to limit the present application.

[0014] Additionally, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or the quantity of the technical features indicated. Thus, a feature qualified as "first" or "second" may expressly or imply the inclusion of one or more of that feature. In the description of this application, unless expressly and specifically limited, "plurality" means two or more than two. Unless expressly and specifically limited, "some" means one or more than one.

[0015] In the description of this application, as should be explained, unless otherwise clearly defined or limited, the terms "attach," "couple," and "connect" should be understood in a broad sense. For example, they may refer to fixed connection, detachable connection, integral connection, mechanical connection, electrical connection, direct connection, indirect connection via an intermediate medium, internal communication between two elements, or an interaction between two elements. Those skilled in the art may understand the specific meaning of the above terms in this application according to specific circumstances.

[0016] Conventional solar cells generally include a semiconductor substrate, a doped semiconductor layer, a dielectric layer, and an electrode. The doped semiconductor layer is formed on the light-receiving and / or non-light-receiving surfaces of the semiconductor substrate. A dielectric layer is formed on the doped semiconductor layer opposite the semiconductor substrate to serve as a surface passivation layer and / or reflection-reduction layer. The surface passivation layer passivates surface defects on the doped semiconductor layer opposite the semiconductor substrate, reducing the carrier recombination efficiency of the doped semiconductor layer. The reflection-reduction layer reduces the reflection of incident light and improves the light absorption rate of the semiconductor substrate. An electrode extends at least partially through the dielectric layer and makes electrical contact with the doped semiconductor layer to remove carriers collected in the doped semiconductor layer and generate photocurrent.

[0017] In practical application, the electrodes can be formed by processes such as screen printing, electroplating, or physical vapor deposition. Currently, the electrodes are generally formed by a screen printing process, and high-temperature silver paste is used as the electrode manufacturing material. However, the high-temperature silver paste is very expensive, and the overall manufacturing cost of a solar cell is very high, in addition to the cost of the semiconductor substrate itself. Therefore, reducing the electrode manufacturing cost is currently an issue that the industry must urgently solve.

[0018] To address this issue, the industry has adopted a method of patterning the interface of a dielectric layer, such as silicon nitride, to remove a portion of the dielectric layer, forming a contact window for the exposed doped semiconductor layer, and then fabricating the electrode using a low-temperature metallization process, for example, by using a low-temperature paste instead of a high-temperature silver paste, or by using an electroplating process to form the electrode. However, the bonding strength of the electrode formed by the low-temperature metallization process with the doped semiconductor layer is currently weaker than that provided by the synthetic crystal formed by baking the internal glass body of the silver paste with the silicon interface in an electrode made with a high-temperature silver paste, resulting in a high risk of the electrode detaching from the doped semiconductor layer and reducing the structural reliability of the solar cell.

[0019] To solve the above technical problems, an embodiment of the present application provides a solar cell. In terms of the type of cell, the solar cell provided in one embodiment of the present application includes, but is not limited to, any one of the following photovoltaic cells that can convert light energy into electrical energy. For example, the solar cell provided in the embodiment of the present application may be any one of a tunnel oxide passivation contact cell (Topcon), a doped polycrystalline silicon all-back contact cell (TBC), a hybrid passivation back contact cell (HPBC), a bifacial hybrid cell, etc.

[0020] In terms of the electrode formation positions, the solar cell provided in one embodiment of the present application may be a back-contact type cell, in which the positive and negative electrodes of the solar cell are all formed on the non-light-receiving side of the semiconductor substrate, as shown in Figure 1. Alternatively, the solar cell provided in one embodiment of the present application may be a double-sided contact type cell, in which the positive and negative electrodes of the solar cell are respectively formed on the light-receiving side and non-light-receiving side of the semiconductor substrate, as shown in Figure 2.

[0021] 1 to 3, one embodiment of the present application provides a solar cell comprising a semiconductor substrate 11, a doped semiconductor layer 12, a dielectric layer 13 and an electrode 17. In the embodiment of FIG.

[0022] Here, the semiconductor substrate 11 has opposite first and second surfaces. The first surface of the semiconductor substrate 11 may correspond to the non-light-receiving surface of the solar cell, and in this case, the second surface of the semiconductor substrate 11 corresponds to the light-receiving surface of the solar cell. The embodiments of the present application do not specifically limit the surface morphology of the first and second surfaces of the semiconductor substrate 11. For example, as shown in FIG. 2, the first and second surfaces of the semiconductor substrate 11 are both flat. For further example, as shown in FIG. 1, the second surface of the semiconductor substrate 11 may be a textured surface, and at least a portion of the first surface of the semiconductor substrate 11 is flat. For further example, the first and second surfaces of the semiconductor substrate 11 are both textured surfaces.

[0023] In one embodiment, the semiconductor substrate 11 may be a silicon substrate. The conductivity type of the semiconductor substrate 11 may be N-type or P-type, or the semiconductor substrate 11 may be of a near-intrinsic conductivity type, and the crystal type thereof may be single crystal or polycrystalline, etc.

[0024] The doped semiconductor layer 12 may be disposed on a first side of the semiconductor substrate 11. It is understood that the doped semiconductor layer 12 may be disposed on a second side of the semiconductor substrate 11, or, as shown in Figure 2, the doped semiconductor layer 12 may be disposed on both the first and second sides of the semiconductor substrate 11. In this application, the doped semiconductor layer 12 may also be referred to as a conductively doped layer.

[0025] The position where the doped semiconductor layer 12 is formed on the semiconductor substrate 11 can be determined depending on the type of solar cell. It should be noted that the doped semiconductor layer 12 in the embodiments of the present application refers to a doped semiconductor layer in which a hole is formed on the side of the opening in the dielectric layer opposite the semiconductor substrate, and may be referred to as a first doped semiconductor layer. In some examples, the doped semiconductor layer 12 in the embodiments of the present application refers to a semiconductor layer in which a hole is formed on the side of the opening in the dielectric layer opposite the semiconductor substrate, and an annular protrusion is formed around the edge of the hole. The third doped semiconductor layer described below is different from the doped semiconductor layer (i.e., the first doped semiconductor layer) and refers to a semiconductor layer in which no hole is formed.

[0026] For example, when the solar cell provided in the embodiments of the present application is a double-sided contact type cell, the doped semiconductor layer 12 may be formed only on the first surface side or the second surface side of the semiconductor substrate 11. In this case, the conductivity type of the doped semiconductor layer 12 may be opposite to that of the semiconductor substrate 11, and the solar cell may further include a third doped semiconductor layer formed on the side of the semiconductor substrate 11 opposite to the doped semiconductor layer 12 and having the same conductivity type as the semiconductor substrate. Alternatively, when the doped semiconductor layer is formed only on the first surface side or the second surface side of the semiconductor substrate 11, the conductivity type of the doped semiconductor layer may be the same as that of the semiconductor substrate 11, and the solar cell may further include a third doped semiconductor layer formed on the side of the semiconductor substrate opposite to the doped semiconductor layer, and the third doped semiconductor layer has the opposite conductivity type to that of the semiconductor substrate. Of course, when the solar cell provided in the embodiments of the present application is a double-sided contact type cell, the solar cell does not necessarily include the third doped semiconductor layer.

[0027] Alternatively, the doped semiconductor layers 12 may be formed on the first and second surfaces of the semiconductor substrate 11, in which case the two doped semiconductor layers 12 located on the first and second surfaces of the semiconductor substrate 11, respectively, have opposite conductivity types.

[0028] When the solar cell provided in the examples of the present application is a double-sided contact type cell, the doped semiconductor layer 12 may be provided on the entire first surface and / or the second surface of the semiconductor substrate 11, or may be provided on a partial region of the first surface and / or the second surface of the semiconductor substrate 11.

[0029] For example, if the solar cell provided in the embodiments of the present application is a back-contact type cell, the doped semiconductor layer 12 is formed on the first surface of the semiconductor substrate 11. Here, the doped semiconductor layer 12 may have the same conductivity type as the semiconductor substrate 11. In this case, the solar cell further includes a third doped semiconductor layer formed on the first surface of the semiconductor substrate 11 and interleaved with the doped semiconductor layer 12, the third doped semiconductor layer having the opposite conductivity type to that of the semiconductor substrate 11. Alternatively, the doped semiconductor layer 12 may have the opposite conductivity type to that of the semiconductor substrate 11. In this case, the solar cell may include a third doped semiconductor layer formed on the first surface of the semiconductor substrate 11 and interleaved with the doped semiconductor layer 12, the third doped semiconductor layer having the same conductivity type as that of the semiconductor substrate 11. Of course, if the solar cell provided in the embodiments of the present application is a back-contact type cell, the solar cell does not necessarily include the third doped semiconductor layer. Alternatively, the doped semiconductor layers 12 located in different regions on the first surface side of the semiconductor substrate 11 have opposite conductivity types, and the differently doped semiconductor layers 12 having opposite conductivity types are distributed alternately.

[0030] When the solar cell further includes a third doped semiconductor layer, the conductivity type of the third doped semiconductor layer can be determined according to actual needs, as long as it is ensured that the conductivity types of the doped semiconductor layer 12 and the third doped semiconductor layer are opposite to each other. For example, the materials of the doped semiconductor layer 12 and the third doped semiconductor layer may be semiconductor materials such as silicon, germanium, silicon carbide, or gallium arsenide, and in terms of the internal arrangement form of the material, may be amorphous, microcrystalline, single crystalline, nanocrystalline, polycrystalline, etc. The materials of the doped semiconductor layer 12 and the third doped semiconductor layer may be the same or different.

[0031] Dielectric layer 13 is provided on the side of doped semiconductor layer 12 opposite semiconductor substrate 11. A plurality of openings 14 are provided through dielectric layer 13, and in this application openings 14 may be referred to as conductive windows. Openings 14 expose at least a partial region of doped semiconductor layer 12. A plurality of holes 15 are formed in portions of doped semiconductor layer 12 exposed through openings 14 on the side opposite semiconductor substrate 11.

[0032] It should be noted that in the examples of the present application, the holes do not penetrate through the doped semiconductor layer but are blind holes.

[0033] The dielectric layer 13 can passivate the surface of the doped semiconductor layer 12 and reduce the carrier recombination rate. Because the dielectric layer 13 is a non-conductive insulating layer, an opening 14 is formed through the dielectric layer 13. The opening 14 in this application may have other shapes, such as a circular, rectangular, or elliptical shape. The opening 14 exposes at least a portion of the doped semiconductor layer 12. A plurality of holes 15 are formed on the side of the doped semiconductor layer 12 exposed through the opening 14, opposite the semiconductor substrate 11. This approach allows electrodes to be formed on the openings 14 using a low-temperature metallization process, thereby reducing the cost of the metallization process. Furthermore, because the plurality of holes 15 are formed on the side of the doped semiconductor layer 12 exposed through the opening 14, opposite the semiconductor substrate 11, the side of the doped semiconductor layer 12 exposed through the opening 14 opposite the semiconductor substrate 11 has uneven, non-flat surface features, which contributes to increasing the surface roughness and specific surface area of ​​the doped semiconductor layer 12 located at the openings. Therefore, compared to conventional solar cells in which electrode 17 is formed on a doped semiconductor layer with a flat surface, in the solar cell provided in the examples of the present application, when electrode 17 is formed on doped semiconductor layer 12 whose surface is uneven and not flat, the contact area between electrode 17 and the portion of doped semiconductor layer 12 exposed through opening 14 is large, which increases the bonding force between electrode 17 and doped semiconductor layer 12, strengthens the connection strength between them, reduces the risk of electrode 17 detaching from doped semiconductor layer 12, and contributes to improving the structural reliability of the solar cell. At the same time, the large contact area also reduces the contact resistance between electrode 17 and doped semiconductor layer 12, improves contact characteristics, and further improves the photoelectric conversion efficiency of the solar cell.

[0034] The dielectric layer 13 may have a single-layer structure or a multi-layer structure. In some examples, the dielectric layer 13 may include a surface passivation layer, other possible layers such as a reflection reduction layer, or a stacked surface passivation layer and a reflection reduction layer. The structure of the dielectric layer 13 is not specifically limited in the examples of this application and can be configured according to the needs of the solar cell. For example, in a TBC cell, the dielectric layer 13 on the non-light-receiving surface may include a stacked surface passivation layer and a reflection reduction layer. In a Topcon cell, the dielectric layer 13 on the non-light-receiving surface may include a reflection reduction layer, a surface passivation layer, or a stacked surface passivation layer and a reflection reduction layer. The dielectric layers on the light-receiving surfaces of both the TBC cell and the Topcon cell may include a stacked surface passivation layer and a reflection reduction layer.

[0035] The material of the dielectric layer 13 is an insulating material. In some examples, when the dielectric layer includes a surface passivation layer, the material of the dielectric layer 13 may include at least one of silicon nitride, silicon oxynitride, silicon carbide, and aluminum oxide. In some examples, when the dielectric layer includes a surface passivation layer and a reflection reduction layer that are stacked together, the material of the surface passivation layer may include one or more of aluminum oxide, silicon oxide, and intrinsic amorphous silicon, and the material of the reflection reduction layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride. In some examples, the material of the dielectric layer 13 includes silicon nitride. In this case, silicon nitride has high resistivity, which contributes to improving the insulating properties of the dielectric layer 13 and has a good passivation effect. Therefore, the dielectric layer 13 containing silicon nitride as a material passivates the surface of the doped semiconductor layer 12 and contributes to reducing the carrier recombination rate. Furthermore, silicon nitride also has a good reflection reduction effect, which can improve the photoelectric conversion efficiency of the solar cell.

[0036] In some embodiments, the solar cell may further include a first passivation layer 20 located between the semiconductor substrate 11 and the doped semiconductor layer 12. The first passivation layer 20 passivates at least the corresponding surfaces of the semiconductor substrate 11 and the doped semiconductor layer 12, thereby reducing the rate of carrier recombination at the surface of the semiconductor substrate 11. In addition, the doped semiconductor layer 12 formed on the first passivation layer 20 selectively collects carriers of the corresponding conductivity type in the semiconductor substrate 11, thereby further improving the photoelectric conversion efficiency of the solar cell provided in the embodiments of the present application.

[0037] The first passivation layer 20 may be a single layer or multiple layers, or may be composed of different materials in different regions. The material of the first passivation layer 20 can be determined according to the material of the doped semiconductor layer 12. For example, when the material of the doped semiconductor layer 12 includes one or more of doped amorphous silicon, doped microcrystalline silicon, or doped nanocrystalline silicon, the first passivation layer 20 may be an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon layer, or a mixture of at least two of these three. In this case, the doped semiconductor layer 12 and the first passivation layer 20 can form a heterocontact structure.

[0038] Furthermore, for example, when the doped semiconductor layer 12 is a doped polycrystalline silicon layer, the first passivation layer 20 may be a tunnel passivation layer. In this case, the doped semiconductor layer 12 and the first passivation layer 20 can form a tunnel passivation contact structure. The material of the tunnel passivation layer may include any dielectric material that has a tunnel passivation function. For example, the material of the tunnel passivation layer may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium carbonitride.

[0039] In some embodiments, the doped semiconductor layer 12 is formed only on the first surface side or the second surface side of the semiconductor substrate 11, and the solar cell may further include a second passivation layer 19 formed on the side of the semiconductor substrate 11 opposite the doped semiconductor layer 12, which passivates the side of the semiconductor substrate 11 opposite the doped semiconductor layer 12, thereby reducing the rate of carrier recombination at the surface of the semiconductor substrate 11 and further improving the photoelectric conversion efficiency of the solar cell. Specifically, the embodiments of the present application do not specifically limit the material and thickness of the second passivation layer 19, and reference may be made to the material of the dielectric layer described above. For example, the material of the second passivation layer 19 may include any one or more insulating materials such as silicon oxide, aluminum oxide, silicon nitride, etc.

[0040] 4 to 7, in some embodiments of the present application, the solar cell is a back-contact type cell, and the solar cell provided in these embodiments includes a semiconductor substrate 11, a first doped semiconductor layer 12-1, a second doped semiconductor layer 12-2, a dielectric layer 13, a first electrode 17A, and a second electrode 17B. It should be noted that FIGS. 4 and 5 are merely illustrative of the structure of the solar cell and do not limit the thickness or surface morphology of each layer. FIGS. 6 and 7 are merely illustrative of the structure of the solar cell and the placement of the openings in the dielectric layer and do not limit the surface morphology of the area exposed through the openings in the doped semiconductor layer; specific surface morphology characteristics will be described in detail below.

[0041] In this embodiment, only the parts that are different from the above embodiment will be described, and for the parts that are the same, the above embodiment can be referred to. For example, for the features of the semiconductor substrate 11 in this embodiment, the features of the semiconductor substrate 11 in the above embodiment can be referred to, and detailed explanations will be omitted here.

[0042] For example, the first doped semiconductor layer 12-1 may be an N-type doped semiconductor layer, and the second doped semiconductor layer 12-2 may be a P-type doped semiconductor layer. In this application, the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2 may be referred to as a first conductive doped layer or a second conductive doped layer.

[0043] The solar cell provided in this embodiment is a back-contact type cell, in which first doped semiconductor layers 12-1 and second doped semiconductor layers 12-2 are alternately disposed on the first surface side of a semiconductor substrate 11. Here, the conductivity type of the first doped semiconductor layer 12-1 may be the same as the conductivity type of the semiconductor substrate 11, and the conductivity type of the second doped semiconductor layer 12-2 may be opposite to the conductivity type of the semiconductor substrate 11. Alternatively, the conductivity type of the first doped semiconductor layer 12-1 may be opposite to the conductivity type of the semiconductor substrate 11, and the conductivity type of the second doped semiconductor layer 12-2 may be the same as the conductivity type of the semiconductor substrate 11.

[0044] The materials of the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2 can be referenced to the materials of the doped semiconductor layers in the above examples, and detailed descriptions are omitted here. The materials of the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2 may be the same or different.

[0045] In some examples, an isolation region is formed between the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2, and the isolation region may be, for example, an isolation trench; in other examples, there is no isolation region between the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2, i.e., the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2 are provided in contact with each other, or there is an overlap region between the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2.

[0046] The dielectric layer 13 is provided on the side of the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2 opposite the semiconductor substrate 11. The dielectric layer 13 includes a plurality of first openings 14-1 and a plurality of second openings 14-2, where the first openings 14-1 expose a partial region of the first doped semiconductor layer 12-1 and the second openings 14-2 expose a partial region of the second doped semiconductor layer 12-2. The first openings 14-1 and the second openings 14-2 may also be referred to as first and second conductive windows.

[0047] The structural features of the dielectric layer 13 can be referred to the dielectric layer 13 in the above embodiment, and detailed description thereof will be omitted here.

[0048] 7, the solar cell may further include a first passivation layer 20 located between the semiconductor substrate 11 and the doped semiconductor layers (i.e., the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2). The first passivation layer 20 passivates at least the corresponding surfaces of the semiconductor substrate 11 and the doped semiconductor layers, thereby reducing the rate of carrier recombination at the surface of the semiconductor substrate 11. The first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2 each selectively collect carriers of the corresponding conductivity type in the semiconductor substrate 11, thereby further improving the photoelectric conversion efficiency of the solar cell provided in the embodiments of the present application. In some embodiments, the first passivation layer 20 formed between the semiconductor substrate 11 and the first doped semiconductor layer 12-1 and the first passivation layer 20 formed between the semiconductor substrate 11 and the second doped semiconductor layer 12-2 may be formed simultaneously or in different process steps. When formed in different process steps, the first passivation layer 20 formed between the semiconductor substrate 11 and the first doped semiconductor layer 12-1 and the first passivation layer 20 formed between the semiconductor substrate 11 and the second doped semiconductor layer 12-2 may be the same or different in material, thickness, etc.

[0049] The first passivation layer 20 may be a single layer, a multilayer, or may be composed of different materials in different regions. The material of the first passivation layer 20 can be determined according to the material of the doped semiconductor layer. For example, when the first doped semiconductor layer and the second doped semiconductor layer are both doped polycrystalline silicon layers, the first passivation layer 20 may be a tunnel passivation layer. In this case, the first doped semiconductor layer and the first passivation layer 20 may form a tunnel passivation contact structure, and the second doped semiconductor layer and the first passivation layer may form a tunnel passivation contact structure. The material of the tunnel passivation layer may include any dielectric material that has a tunnel passivation function. For example, the above description of the material of the tunnel passivation layer can be referred to, and a detailed description will be omitted here.

[0050] In some embodiments, the solar cell of the examples of the present application may further include a surface passivation layer and a reflection reduction layer formed on the side opposite to the doped semiconductor layer of the semiconductor substrate 11, i.e., on the second surface. The materials and functions of the surface passivation layer and the reflection reduction layer can be referenced above, and detailed descriptions thereof will be omitted here.

[0051] In any of the embodiments of the present application, the surface morphology (e.g., roughness, contact area between the electrode and the doped semiconductor layer, etc.) of the portion of the doped semiconductor layer exposed through the opening on the side opposite the semiconductor substrate directly affects the stability of the electrode structure, so reasonable morphology characteristics can solve or at least alleviate the problem of the electrode easily detaching from the doped semiconductor layer, thereby ensuring the structural reliability of the solar cell.

[0052] It should be noted that the surface morphology of the portion of the doped semiconductor layer exposed through the opening on the side opposite to the semiconductor substrate can be controlled by controlling laser parameters such as laser energy, laser spot size, laser spot overlap rate, laser irradiation area, laser energy at different positions, etc. Of course, the surface morphology of the portion of the doped semiconductor layer exposed through the opening on the side opposite to the semiconductor substrate can also be controlled by adjusting the etching conditions such as the components of the etching solution, temperature, and time.

[0053] For the sake of convenience, the doped semiconductor layer in the following examples of the present application may include one type of doped semiconductor layer, or may include at least one of a first doped semiconductor layer 12-1 and a second doped semiconductor layer 12-2, and the characteristics of at least one of the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2 are the same as the characteristics of the doped semiconductor layer described below. The opening in the following examples of the present application may include one type of opening, or may include at least one of a first opening 14-1 and a second opening 14-2, and the characteristics of at least one of the first opening 14-1 and the second opening 14-2 are the same as the characteristics of the opening described below. The hole in the following examples of the present application may include one type of hole, or may include at least one of a first hole 15-1 and a second hole 15-2, and the characteristics of at least one of the first hole 15-1 and the second hole 15-2 are the same as the characteristics of the hole described below. The annular protrusion in the following examples of the present application may include one type of annular protrusion, or may include at least one of the annular protrusion 16-1 of the first hole and the annular protrusion 16-2 of the second hole, and the characteristics of at least one of the annular protrusion 16-1 of the first hole and the annular protrusion 16-2 of the second hole are the same as the characteristics of the annular protrusion described below.

[0054] Referring to Figures 8-1 to 8-13, in any embodiment of the present application, the portion of the doped semiconductor layer exposed in the opening opposite the semiconductor substrate may have one or more of the following morphological features:

[0055] For example, in the solar cell provided in the present application, a plurality of holes 15 are formed on the side of the doped semiconductor layer opposite the semiconductor substrate, in the portion exposed to the opening. The effect of forming a plurality of holes 15 on the side of the doped semiconductor layer opposite the semiconductor substrate, in the portion exposed to the opening, is described in the above examples, and a detailed description will be omitted here. In some examples, for example, when the doped semiconductor layer is a P-type polycrystalline silicon layer, the contact resistance between the electrode and the doped semiconductor layer can be reduced to an average of 0.8 mΩ*cm2. For example, when the doped semiconductor layer is an N-type polycrystalline silicon layer, the contact resistance between the electrode and the doped semiconductor layer 12 can be reduced to an average of 0.35 mΩ*cm2.

[0056] It can be understood that the shape, size, number and form of the holes 15 affect the surface roughness of the exposed portion of the doped semiconductor layer on the side opposite to the semiconductor substrate, and therefore the above-mentioned related information of the holes can be adjusted and controlled to suit the actual use case.

[0057] For example, the hole 15 is an approximately hemispherical hole. The approximately hemispherical hole may be a hemispherical hole in the strict sense, or may be a hole similar to a hemisphere, i.e., it may vary slightly from a hemispherical hole, for example, within a tolerance range (e.g., 5% or 10%). When the hole 15 is an approximately hemispherical hole, the cross-sectional dimension of the hole opening is largest in the depth direction of the hole 15, which makes it easier to fill the hole 15 with a conductive material for manufacturing an electrode, contributes to improving the connection strength and contact characteristics between the electrode and the doped semiconductor layer, and ensures a strong bond strength and good contact characteristics between the electrode and the doped semiconductor layer.

[0058] In some examples, the maximum radial dimension of the holes 15 is nanoscale. In this case, the small maximum radial dimension of the holes helps prevent the thickness of the remaining portion of the doped semiconductor layer exposed through the opening from becoming thin after the hole-distributed surface is formed on the opposite side of the semiconductor substrate, ensuring high carrier shunting ability in the doped semiconductor layer, reducing the carrier recombination rate, and further improving the photoelectric conversion efficiency of the solar cell.

[0059] In yet another example, the maximum radial dimension of the holes 15 is greater than 0 μm and less than or equal to 3 μm.

[0060] If the maximum radial dimension of the holes 15 is too large, for example, 4 μm, 5 μm, or 10 μm, or if it is larger, the number of holes 15 will be reduced, thereby reducing the specific surface area of ​​the portion of the doped semiconductor layer exposed to the opening, and further reducing the contact area between the doped semiconductor layer and the electrode, thereby reducing the bonding strength between the electrode and the doped semiconductor layer.Taking this into consideration, the maximum radial dimension of the holes 15 in this application is set to 3 μm or less.

[0061] Furthermore, if the maximum radial dimension of the holes 15 is too small, the surface roughness of the doped semiconductor layer will be reduced, and when forming an electrode on the doped semiconductor layer, it will be difficult to fill the small holes 15 with a conductive material for manufacturing the electrode, and the connection strength and contact characteristics between the electrode and the doped semiconductor layer will not be ensured. Considering this, in some examples, the maximum radial dimension of the holes is 0.02 μm or more. Optionally, the maximum radial dimension of the holes is 0.02 μm or more and 0.1 μm or less.

[0062] The maximum radial dimension of the holes 15 may be, for example, 0.02 μm, 0.03 μm, 0.04 μm, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm, 0.4 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 1.5 μm, 2 μm, or 3 μm.

[0063] By adopting the above-mentioned maximum radial dimension range of the holes 15, the present application increases the surface roughness of the doped semiconductor layer, increases the contact area between the electrode and the doped semiconductor layer, increases the bonding force between the electrode and the doped semiconductor layer, strengthens the connection strength between them, contributes to reducing the risk of the electrode detaching from the doped semiconductor layer, and further contributes to improving the structural reliability of the solar cell.

[0064] For example, an annular protrusion 16 is formed around the edge of the hole 15. The circular (or approximately circular) area surrounded by a light circle in FIG. 8-2 is the hole 15, and the light circle is the annular protrusion 16 formed around the edge of the hole 15. In some examples, the annular protrusion 16 can be formed by melting and then solidifying the material of the doped semiconductor layer, and has a shape similar to an annular crater, and the annular protrusion 16 protrudes relative to the inner and / or outer regions of the hole 15.

[0065] It can be understood that the annular protrusion 16 is formed by melting and then solidifying a doped semiconductor layer, and therefore, when the doped semiconductor layer is a doped polycrystalline silicon layer, the material of the annular protrusion 16 includes silicon.

[0066] By adopting the above technical solution, the annular protrusion 16 can further enhance the formation of uneven surface features on the side of the doped semiconductor layer exposed through the opening, opposite the semiconductor substrate, contributing to further increasing the surface roughness and specific surface area of ​​the side of the doped semiconductor layer exposed through the opening, opposite the semiconductor substrate. Therefore, since the electrode of the solar cell provided herein is formed on a doped semiconductor layer having an uneven surface, the contact area between the electrode and the exposed portion of the doped semiconductor layer through the opening is increased, thereby increasing the bonding force between the electrode and the doped semiconductor layer, strengthening the connection strength between them, reducing the risk of the electrode detaching from the doped semiconductor layer, and contributing to improving the structural reliability of the solar cell. Furthermore, the increased contact area between the electrode and the exposed portion of the doped semiconductor layer through the opening reduces the contact resistance between the doped semiconductor layer and the electrode, improving contact characteristics and further improving the photoelectric conversion efficiency of the solar cell.

[0067] For example, the width of the annular protrusion 16 is greater than 0 μm and not greater than 0.3 μm. If the width of the annular protrusion 16 is too large, for example, 0.4 μm, 0.7 μm, or 1 μm, or if it is larger, the increase in the specific surface area of ​​the doped semiconductor layer will not be significant, the surface roughness of the doped semiconductor layer will be small, and it will also be disadvantageous in increasing the contact area between the electrode and the doped semiconductor layer. Considering this, the present application specifies the width of the annular protrusion 16 to be not greater than 0.3 μm.

[0068] Furthermore, if the width of the annular protrusion 16 is too small, the annular protrusion is prone to breakage, is ineffective in increasing the contact area between the electrode and the doped semiconductor layer, and the silicon in the annular protrusion 16 (i.e., the silicon in the doped semiconductor layer) is prone to being pulled by the electrode, which is disadvantageous in increasing the adhesive strength between the electrode and the doped semiconductor layer. Considering these factors, in some examples, the width of the annular protrusion 16 is set to 0.05 μm or more.

[0069] The width of the annular protrusion 16 may be, for example, 0.05 μm, 0.07 μm, 0.09 μm, 0.1 μm, 0.15 μm, 0.2 μm, or 0.3 μm.

[0070] The width range of the annular protrusion 16 contributes to increasing the surface roughness of the doped semiconductor layer, thereby increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, strengthening the connection strength between them, reducing the risk of the electrode detaching from the doped semiconductor layer, and contributing to improving the structural reliability of the solar cell.

[0071] For example, the height of the annular protrusion 16 is greater than 0 μm and not greater than 0.5 μm. If the height of the annular protrusion 16 is too high, for example, 0.6 μm, 0.8 μm, 1 μm, or greater, the annular protrusion 16 will be easily broken, which will not be effective in increasing the contact area between the electrode and the doped semiconductor layer. In addition, the annular protrusion 16 will be easily broken by the electrode, which will reduce the tensile force between the electrode and the doped semiconductor layer, which is unfavorable for increasing the adhesive strength between the electrode and the doped semiconductor layer. Considering these factors, the present application specifies the height of the annular protrusion 16 to be not greater than 0.5 μm.

[0072] Furthermore, if the height of the annular protrusion 16 is too low, it is disadvantageous in increasing the surface roughness of the doped semiconductor layer, so in some examples, the height of the annular protrusion 16 is set to 0.001 μm or more.

[0073] The height of the annular protrusion 16 may be, for example, 0.001 μm, 0.005 μm, 0.008 μm, 0.01 μm, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm, 0.2 μm, 0.3 μm, or 0.5 μm.

[0074] The above height range of the annular protrusion 16 contributes to increasing the surface roughness of the doped semiconductor layer, thereby increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, strengthening the connection strength between them, reducing the risk of the electrode detaching from the doped semiconductor layer, and contributing to improving the structural reliability of the solar cell.

[0075] For example, the range of the ratio of the maximum radial dimension of the holes 15 to the width of the annular protrusion is 60 or less. If this ratio is too large, for example, 80, 90, or 100, or even larger, that is, if the maximum radial dimension of the holes 15 is large and the width of the annular protrusion 16 is small, the number of holes 15 will be reduced due to the large maximum radial dimension of the holes 15, and the narrow width of the annular protrusion 16 will reduce the specific surface area of ​​the doped semiconductor layer at the openings, further reducing the surface roughness of the doped semiconductor layer at the openings, which is also disadvantageous in increasing the contact area between the electrode and the doped semiconductor layer. Taking this into consideration, the present application specifies the range of the ratio of the maximum radial dimension of the holes 15 to the width of the annular protrusion 16 as 60 or less.

[0076] Furthermore, if this ratio is too small, i.e., if the width of the annular protrusion 16 is large and the maximum radial dimension of the hole 15 is small, the specific surface area of ​​the doped semiconductor layer will be small and the surface roughness of the doped semiconductor layer may also be reduced, which is disadvantageous in increasing the contact area between the electrode and the doped semiconductor layer. Furthermore, since the maximum radial dimension of the hole 15 is small, the surface roughness of the doped semiconductor layer will be reduced, and when forming an electrode on the doped semiconductor layer, it will be difficult to fill the small-sized hole 15 with a conductive material for manufacturing the electrode, and the connection strength and contact characteristics between the electrode and the doped semiconductor layer will not be ensured. Taking this into consideration, in some examples, the ratio of the maximum radial dimension of the hole to the width of the annular protrusion is set to 0.06 or more.

[0077] The range of the ratio of the maximum radial dimension of the hole 15 to the width of the annular protrusion 16 may be, for example, 0.06, 0.08, 0.1, 0.2, 0.3, 1, 10, 15, 18, 20, 30, 35, 40, or 60.

[0078] The above range of the ratio of the maximum radial dimension of the hole 15 to the width of the annular protrusion 16 increases the surface roughness of the doped semiconductor layer, increases the contact area between the electrode and the doped semiconductor layer, increases the bonding force between the electrode and the doped semiconductor layer, strengthens the connection strength between them, contributes to reducing the risk of the electrode detaching from the doped semiconductor layer, and further contributes to improving the structural reliability of the solar cell.

[0079] For example, the doped semiconductor layer located in the opening has a doping concentration on a side away from the semiconductor substrate that is greater than the doping concentration on a side closer to the semiconductor substrate.

[0080] By adopting the above technical solution, the doped semiconductor layer has a relatively high doping concentration away from the semiconductor substrate, i.e., the doped semiconductor layer has a higher doping concentration on the side closer to the electrode, which reduces the contact resistance between the doped semiconductor layer and the electrode and improves the photoelectric conversion efficiency of the solar cell. Furthermore, compared to when the doped semiconductor layer has the same doping concentration on the side closer to the electrode and the side closer to the semiconductor substrate, the doped semiconductor layer has a higher doping concentration on the side closer to the electrode, which allows the thickness of the doped semiconductor layer to be appropriately reduced, thereby not only saving costs but also improving the manufacturing efficiency of the solar cell.

[0081] For example, the portion of the doped semiconductor layer exposed in the opening opposite the semiconductor substrate has a fifth surface roughness, and the portion of the doped semiconductor layer not exposed in the opening opposite the semiconductor substrate has a sixth surface roughness, the fifth surface roughness being greater than the sixth surface roughness. The large surface roughness of the portion of the doped semiconductor layer exposed in the opening can increase the contact area between the doped semiconductor layer and the electrode, contributing to a reduction in the contact resistance between the electrode and the doped semiconductor layer, and increasing the bonding force between the electrode and the doped semiconductor layer, strengthening the connection strength therebetween, reducing the risk of the electrode detaching from the doped semiconductor layer and contributing to improving the structural reliability of the solar cell. The small sixth surface roughness can ensure good film formation quality of the formed doped semiconductor layer.

[0082] For example, the fifth surface roughness is in the range of 0 to 0.5 μm, and optionally the fifth surface roughness is in the range of 0.3 μm to 0.5 μm, for example, the fifth surface roughness may be 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, or 0.5 μm. The sixth surface roughness is in the range of 0 to 100 nm. In this case, by having the fifth surface roughness in the above range, a contact area between the electrode and the side of the doped semiconductor layer exposed through the opening opposite the semiconductor substrate can be ensured, and high connection strength and good contact characteristics can be ensured between the electrode and the doped semiconductor layer.

[0083] For example, the portion of the doped semiconductor layer exposed in the opening has a fifth surface roughness on the side opposite the semiconductor substrate, and the unexposed portion of the doped semiconductor layer not exposed in the opening includes a first unexposed portion at the edge of the opening in the dielectric layer and the remaining unexposed portions other than the first unexposed portion, the side of the first unexposed portion opposite the semiconductor substrate has a seventh surface roughness, and the side of the remaining unexposed portion opposite the semiconductor substrate has an eighth surface roughness, where the fifth surface roughness > the seventh surface roughness > the eighth surface roughness. The large surface roughness of the portion of the doped semiconductor layer exposed in the opening can increase the contact area between the doped semiconductor layer and the electrode, contributing to lowering the contact resistance between the electrode and the doped semiconductor layer and increasing the bonding force between the electrode and the doped semiconductor layer, strengthening the connection strength between them, reducing the risk of the electrode detaching from the doped semiconductor layer, and contributing to improving the structural reliability of the solar cell. In addition, when forming an electrode, the electrode material can be formed on the first unexposed portion, and since the seventh surface roughness of the first unexposed portion is greater than the eighth surface roughness, the bonding strength between the electrode and the doped semiconductor layer can be further strengthened, reducing the risk of the electrode detaching from the doped semiconductor layer and further contributing to improving the structural stability of the solar cell.

[0084] In the examples of the present application, surface roughness may refer to the arithmetic mean deviation Ra of the profile of the target surface, specifically the arithmetic mean value of the absolute values ​​of the peaks and valleys (relative to the mean line) of the profile of the target surface within a sampling length Lr of the target surface. In actual measurements, the more measurement points there are, the more accurate Ra will be. Alternatively, surface roughness may refer to the maximum height Rz of the profile of the target surface, specifically the distance between the peak line and the valley line of the profile of the target surface. It should be understood that the same roughness evaluation criteria are used for the roughness of different surface regions, for example, the first surface roughness, the second surface roughness, the third surface roughness, and the fourth surface roughness.

[0085] For example, a plurality of discontinuous protrusions 21 are further formed on the side of the doped semiconductor layer exposed through the opening, opposite to the semiconductor substrate. The discontinuous protrusions 21 may include at least one of dot-like protrusions (bright dots within circles in FIG. 8-2) and linear protrusions (white curves within square frames in FIG. 8-2). The linear protrusions may be straight protrusions, curved linear protrusions, annular unclosed protrusions, etc.

[0086] Here, the discontinuous protrusions 21 may be distributed at any position on the side of the doped semiconductor layer exposed through the opening, opposite the semiconductor substrate. The discontinuous protrusions 21 also contribute to increasing the surface roughness of the doped semiconductor layer located in the opening, thereby further increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, strengthening the connection strength between them, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0087] In the embodiments of the present application, the number of discontinuous protrusions per unit area located in the edge region of the opening may be greater than the number of discontinuous protrusions per unit area located in the middle region of the opening, or the number of discontinuous protrusions per unit area located in the edge region of the opening may be less than the number of discontinuous protrusions per unit area located in the middle region of the opening. The openings in the present application may be other shapes, such as circular, rectangular, or elliptical, and the shape enclosed by the boundary of the corresponding middle region of the opening is the same as the shape enclosed by the boundary of the opening, and the distance from the boundary of the middle region to the boundary of the opening is equal or nearly equal. For example, if the opening is circular, the middle region is a circular or approximately circular region around the center of the opening, and the distance from the boundary of the middle region to the outer boundary of the opening in the radial direction passing through the center of the opening is the same or nearly the same (i.e., equal within a tolerance range). The area within the opening other than the middle region is the edge region of the opening. An approximately circular shape may vary slightly from a circular shape, for example, within a tolerance range (e.g., 5% or 10%). As shown in FIG. 8-2, the areas surrounded by large red circles in the figure are the middle areas of the openings, and the remaining areas are the edge areas of the openings.

[0088] For example, if the doped semiconductor layer is a P-type doped semiconductor layer, the number of discontinuous protrusions per unit area located in the edge region of the opening is greater than the number of discontinuous protrusions per unit area located in the middle region of the opening, as shown in Figure 8-4. Generally, P-type doped semiconductor layers have a low doping concentration and a high number of holes and a low number of electrons, making them unsuitable for forming electrodes on P-type doped semiconductor layers. It is understandable that, when forming electrodes of the same thickness, it is more difficult to form electrodes on P-type doped semiconductor layers than on N-type doped semiconductor layers. Furthermore, for the same opening, it is more difficult to form electrodes on the edge region of the opening than on the middle region of the opening. According to this, in some embodiments of the present application, the number of discontinuous protrusions per unit area located in the edge region of the opening of the P-type doped semiconductor layer is made larger than the number of discontinuous protrusions per unit area in the middle region of the opening, thereby improving the effect of electrode fabrication in the edge region of the opening and further ensuring the quality of the electrode formed in the edge region of the opening, so that the quality of the electrode formed in the edge region and the middle region of the opening is consistent, which contributes to improving the carrier transport effect in the electrode.

[0089] For example, if the doped semiconductor layer is an N-type doped semiconductor layer, the number of discontinuous protrusions per unit area located in the middle region of the opening is greater than the number of discontinuous protrusions per unit area located in the edge region of the opening, as shown in Figure 8-3. Generally, an N-type doped semiconductor layer has a high doping concentration, which means that it has many electrons and few holes, making it suitable for forming an electrode on the N-type doped semiconductor layer. It is understandable that, when forming an electrode of the same thickness, it is less difficult to form an electrode on an N-type doped semiconductor layer than on a P-type doped semiconductor layer. Furthermore, for the same opening, it is less difficult to form an electrode on the middle region of the opening than on the edge region of the opening. In other words, because it is less difficult to form an electrode on the middle region of the N-type doped semiconductor layer, the speed of forming an electrode on the middle region of the N-type doped semiconductor layer is faster. However, since an electrode fabrication speed that is too fast is detrimental to improving adhesion, in some embodiments of the present application, the number of discontinuous protrusions per unit area located in the middle region of the N-type doped semiconductor layer opening is made greater than the number of discontinuous protrusions per unit area located in the edge region of the opening, thereby increasing the specific surface area of ​​the middle region of the N-type doped semiconductor layer and further contributing to improving the bonding strength between the electrode and the N-type doped semiconductor layer in the middle region.

[0090] For example, the height of the discontinuous protrusion is greater than 0 μm and less than or equal to 0.5 μm. If the height of the discontinuous protrusion is too high, the discontinuous protrusion is likely to break, and the tensile force between the electrode and the doped semiconductor layer is reduced. Therefore, the present application specifies the height of the discontinuous protrusion to be less than or equal to 0.5 μm.

[0091] Furthermore, considering that if the height of the discontinuous protrusions is too small, the effect of increasing the surface roughness of the doped semiconductor layer is not significant, in some examples the height of the discontinuous protrusions is set to 0.001 μm or more.

[0092] The height of the discontinuous protrusions may be, for example, 0.001 μm, 0.003 μm, 0.006 μm, 0.009 μm, 0.01 μm, 0.05 μm, 0.07 μm, 0.1 μm, 0.2 μm, 0.3 μm, or 0.5 μm.

[0093] The height range of the discontinuous protrusions of the present application contributes to increasing the surface roughness of the doped semiconductor layer, thereby increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength therebetween, and avoiding the problem of low tensile force between the electrode and the doped semiconductor layer due to an excessively large height.

[0094] In the back-contact type batteries of Figures 4 to 7, the P-type doped semiconductor layer and the N-type doped semiconductor layer are made of different materials, doping concentrations, conductivities, etc., and therefore the contact resistance and adhesion between the P-type doped semiconductor layer and the first electrode and between the N-type doped semiconductor layer and the second electrode are also different. Currently, it is difficult to achieve the required contact resistance and adhesion between the P-type doped semiconductor layer and the first electrode and between the N-type doped semiconductor layer and the second electrode, making it difficult to achieve a good match between the electrical properties and tensile strength of the P region and the N region.

[0095] The embodiments of the present application provide solutions to the above problems. Referring to Figures 8-2 to 8-10, in the back-contact solar cell of this embodiment, the dielectric layer includes a plurality of first openings and a plurality of second openings, the first openings exposing a portion of the first doped semiconductor layer, and the second openings exposing a portion of the second doped semiconductor layer. The first doped semiconductor layer exposed in the first openings has a first surface roughness, and the second doped semiconductor layer exposed in the second openings has a second surface roughness, the first surface roughness and the second surface roughness being different.

[0096] Taking the first surface roughness as an example, the first surface roughness of the region of the first doped semiconductor layer exposed to the first opening affects the contact area between the first electrode formed in the region of the first opening and the first doped semiconductor layer, which in turn affects the contact resistance between the first electrode and the first doped semiconductor layer, the bonding strength between the first electrode and the first doped semiconductor layer, and the film formation quality of the first electrode. The contact resistance between the first electrode and the first doped semiconductor layer and the bonding strength between the first electrode and the first doped semiconductor layer further affect the number of first openings. Therefore, by adjusting and controlling the first surface roughness, it is possible to adjust the contact resistance between the first electrode and the first doped semiconductor layer, the bonding strength, the film formation quality of the first electrode, the number of first openings, etc.

[0097] By adopting the above technical solution, the region of the first doped semiconductor layer exposed through the first opening has a first surface roughness, which can increase the contact area between the first electrode and the first doped semiconductor layer, thereby increasing the bonding strength between the first electrode and the first doped semiconductor layer and reducing the contact resistance between the first electrode and the second doped semiconductor layer. The region of the second doped semiconductor layer exposed through the second opening has a second surface roughness, which has the same technical effect as the first surface roughness and will not be described in detail here. In addition, since the first surface roughness of the region exposed to the first opening of the first doped semiconductor layer is different from the second surface roughness of the region exposed to the second opening of the second doped semiconductor layer, by adjusting and controlling the first surface roughness and the second surface roughness, the film formation quality of the first electrode and the second electrode, the contact resistance between the first electrode and the first doped semiconductor layer and between the second electrode and the second doped semiconductor layer, the bonding strength, the number of the first openings and the second openings, etc. can be adjusted to prevent the difference in material, doping concentration, and conductivity between the first doped semiconductor layer and the second doped semiconductor layer from occurring. This reduces problems such as the film formation quality, contact resistance and adhesion between the first electrode and the first doped semiconductor layer and between the second electrode and the second doped semiconductor layer, and mismatches in the number of first and second openings. Therefore, the contact resistance, adhesion, and number of first and second openings between the first electrode and the first doped semiconductor layer and between the second electrode and the second doped semiconductor layer all meet the solar cell design requirements. This contributes to ensuring that the film formation quality of the first and second electrodes also meets the solar cell design requirements, and further contributes to improving the structural stability of the solar cell. Furthermore, during the solar cell fabrication process, the different surface roughnesses can effectively distinguish the P and N regions of the solar cell. Furthermore, compared to forming electrodes directly using a high-temperature sintering process, this application allows electrodes to be formed in the openings using a low-temperature metallization process, thereby reducing the cost of the metallization process.

[0098] For example, the first surface roughness is greater than the second surface roughness. Figure 8-5 shows the surface of the region of the first doped semiconductor layer exposed to the first opening, which has a first surface roughness, and Figure 8-6 shows the surface of the region of the second doped semiconductor layer exposed to the second opening, which has a second surface roughness. As can be seen by comparing Figures 8-5 and 8-6, the first surface roughness is greater than the second surface roughness.

[0099] When the above technical solution is adopted, the first surface roughness is the surface roughness of the region of the first doped semiconductor layer exposed by the first opening, i.e., the surface roughness of the region of the N-type doped semiconductor layer exposed by the first opening. In the embodiments of the present application, the first surface roughness is relatively large, thereby relatively increasing the contact area between the N-type doped semiconductor layer and the electrode, reducing the contact resistance between the N-type doped semiconductor layer and the electrode, and improving the bonding strength between the N-type doped semiconductor layer and the electrode. In some examples, the contact resistance between the N-type doped semiconductor layer and the electrode is low, and the bonding strength between the N-type doped semiconductor layer and the electrode is high. Therefore, while satisfying the bonding strength and contact resistance, the number of first openings in the N region corresponding to the N-type doped semiconductor layer can be reduced, i.e., the number of first openings can be made less than the number of second openings. This reduces the number of first openings, improves the efficiency of forming the first openings in the dielectric layer, reduces damage to the N-type doped semiconductor layer caused by laser patterning, and contributes to ensuring the passivation effect of the N region.

[0100] In some embodiments, for example, the first surface roughness is less than the second surface roughness, and Figure 8-7 shows the surface of the region of the first doped semiconductor layer exposed to the first opening, the surface having a first surface roughness, and Figure 8-8 shows the surface of the region of the second doped semiconductor layer exposed to the second opening, the surface having a second surface roughness, and as can be seen by comparing Figure 8-7 and Figure 8-8, the first surface roughness is less than the second surface roughness.

[0101] The second surface roughness is the surface roughness of the region of the second doped semiconductor layer (i.e., the P-type doped semiconductor layer in this embodiment) exposed through the second opening. The conductivity of the P-type doped semiconductor layer is greater than that of the N-type doped semiconductor layer, i.e., the high conductivity of the P-type doped semiconductor layer results in a high contact resistance between the P-type doped semiconductor layer and the second electrode. In the embodiment of the present application, by relatively increasing the second surface roughness corresponding to the P-type doped semiconductor layer, the contact area between the P-type doped semiconductor layer and the second electrode can be relatively increased, thereby reducing the contact resistance between the P-type doped semiconductor layer and the second electrode, contributing to improving the photoelectric conversion efficiency of the solar cell. Furthermore, the adhesion strength of the contact between the P-type doped semiconductor layer and the electrode can be increased, further increasing the connection strength between them, reducing the risk of the electrode peeling off from the P-type doped semiconductor layer, and improving the structural reliability of the solar cell.

[0102] It should be noted that the first surface roughness and the second surface roughness can be controlled by controlling laser parameters such as laser energy, laser spot size, laser spot overlap rate, laser irradiation area, laser energy at different positions, etc., or by controlling the components, concentration, time, etc. of the etching solution.

[0103] For example, the region of the first doped semiconductor layer covered by the dielectric layer has a third surface roughness, the first surface roughness being greater than the third surface roughness.

[0104] The embodiments of the present application adopt the above technical solution, and by relatively increasing the surface roughness of the portion of the first doped semiconductor layer exposed through the opening, the contact area between the first doped semiconductor layer and the first electrode can be relatively increased, which contributes to reducing the contact resistance between the first electrode and the first doped semiconductor layer, increasing the bonding force between the first electrode and the first doped semiconductor layer, strengthening the connection strength therebetween, reducing the risk of the first electrode detaching from the first doped semiconductor layer, and improving the structural reliability of the solar cell.In addition, by reducing the third surface roughness of the region of the first doped semiconductor layer covered by the dielectric layer, it is possible to ensure good film formation quality of the dielectric layer formed on the first doped semiconductor layer and improve the passivation effect of the dielectric layer on the first doped semiconductor layer.

[0105] For example, the region of the second doped semiconductor layer covered by the dielectric layer has a fourth surface roughness, and the second surface roughness is greater than the fourth surface roughness. The technical effect can refer to the technical effect corresponding to the case where the first surface roughness is greater than the third surface roughness.

[0106] For example, the region of the first doped semiconductor layer covered by the dielectric layer has a third surface roughness, and the region of the second doped semiconductor layer covered by the dielectric layer has a fourth surface roughness, the third surface roughness being less than the fourth surface roughness.

[0107] The third surface roughness is the surface roughness of the region of the first doped semiconductor layer (i.e., the N-type doped semiconductor layer in this embodiment) covered by the dielectric layer, and the fourth surface roughness is the surface roughness of the region of the second doped semiconductor layer (i.e., the P-type doped semiconductor layer in this embodiment) covered by the dielectric layer. It can be understood that, generally, the doping concentration of the P-type doped semiconductor layer is lower than that of the N-type doped semiconductor layer, i.e., the doping concentration of the second doped semiconductor layer is lower than that of the first doped semiconductor layer, so the conductivity of the P-type doped semiconductor layer is higher than that of the N-type doped semiconductor layer. When the third surface roughness and the fourth surface roughness are the same, the contact resistance between the P-type doped semiconductor layer and the second electrode is higher than the contact resistance between the N-type doped semiconductor layer and the first electrode. In order to provide the solar cell with good photoelectric conversion efficiency by making the contact resistance of the P region and the N region the same or similar, the fourth surface roughness is made larger than the third surface roughness, thereby increasing the contact area between the second doped semiconductor layer and the second electrode and reducing the contact resistance between the P-type doped semiconductor layer and the second electrode.

[0108] For example, the means for making the first surface roughness and the second surface roughness different includes forming a plurality of first holes 15-1 in the region of the first doped semiconductor layer exposed to the first opening, forming a plurality of second holes 15-2 in the region of the second doped semiconductor layer exposed to the second opening, forming annular protrusions around the edges of the first holes 15-1 and the second holes 15-2, and making the average height of the annular protrusions 16-1 of the first holes and the average height of the annular protrusions 16-2 of the second holes different. The circular (or approximately circular) area surrounded by a bright circle in FIG. 8-3 is the first hole 15-1, and the bright circle is the annular protrusion 16-1 formed around the edge of the first hole 15-1. The circular (or approximately circular) area surrounded by a bright circle in FIG. 8-4 is the second hole 15-2, and the bright circle is the annular protrusion 16-2 formed around the edge of the second hole 15-2.

[0109] The features of the first hole 15-1, the second hole 15-2, the annular protrusion 16-1 of the first hole, and the annular protrusion 16-2 of the second hole are the same as those described in the above embodiment, and detailed description thereof will be omitted here.

[0110] It should be noted that in the embodiment of the present application, the first hole 15-1 does not penetrate the first doped semiconductor layer 12-1 but is a blind hole, and similarly, the second hole 15-2 does not penetrate the second doped semiconductor layer 12-2 but is a blind hole.

[0111] The embodiments of the present application employ the above technical solution, whereby the holes and annular protrusions can adjust the surface roughness of the opening regions (including the first and second opening regions) and form uneven, textured surface features on the side of the doped semiconductor layer exposed through the openings, opposite the semiconductor substrate, thereby contributing to increased surface roughness and specific surface area. Therefore, when the electrodes (including the first and second electrodes) of the solar cell provided in the present application are formed on an uneven, textured doped semiconductor layer, the increased contact area between the electrode and the exposed portion of the doped semiconductor layer through the openings increases the bonding strength between the electrode and the doped semiconductor layer, strengthening the connection between them and reducing the risk of the electrode detaching from the doped semiconductor layer, thereby improving the structural reliability of the solar cell. Furthermore, the increased contact area between the electrode and the exposed portion of the doped semiconductor layer through the openings reduces the contact resistance between the electrode and the doped semiconductor layer, contributing to improving the photoelectric conversion efficiency of the solar cell. Furthermore, since the surface roughness of the first opening region and the second opening region differs due to the difference in average height of the annular protrusion, the first surface roughness and the second surface roughness can be adjusted by adjusting and controlling the average height of the annular protrusion, thereby achieving the technical effect that is obtained when the first surface roughness and the second surface roughness are different as described above. For this, please refer to the above explanation, and a detailed explanation will be omitted here.

[0112] For example, the average height of the annular protrusions can be measured in the following manner: The same number of annular protrusions are taken at the same or nearly the same positions in the first opening region and the second opening region, and the average height is calculated to obtain the average height of the annular protrusions of the first opening and the second opening. For example, if the distance from one position in the first opening region to the center of the first opening region is equal to the distance from one position in the second opening region to the center of the second opening region, then the position in the first opening region and the position in the second opening region are considered to be the same positions in the first opening region and the second opening region, respectively. If the difference between the distance from one position in the first opening region to the center of the first opening region and the distance from one position in the second opening region to the center of the second opening region is smaller than a certain distance value or tolerance, then the position in the first opening region and the position in the second opening region are considered to be nearly the same positions in the first opening region and the second opening region, respectively.

[0113] For example, the average height of the annular protrusion 16-1 of the first hole is greater than the average height of the annular protrusion 16-2 of the second hole.

[0114]

[0033] By adopting the above technical solution, the average height of the annular protrusion 16-1 of the first hole can be relatively increased, thereby relatively increasing the surface roughness of the region of the N-type doped semiconductor layer exposed to the first opening corresponding to the first hole, relatively increasing the contact area between the N-type doped semiconductor layer and the first electrode, reducing the contact resistance between the N-type doped semiconductor layer and the first electrode, and improving the bonding strength between the N-type doped semiconductor layer and the first electrode. In some examples, because the contact resistance between the N-type doped semiconductor layer and the first electrode is low and the bonding strength between the N-type doped semiconductor layer and the first electrode is high, the number of first openings in the N region corresponding to the N-type doped semiconductor layer can be reduced while satisfying the bonding strength and contact resistance, i.e., the number of first openings can be made less than the number of second openings. This reduces the number of first openings, which can reduce damage to the N-type doped semiconductor layer caused by laser patterning and contributes to ensuring the passivation effect of the N region.

[0115] For example, the average height of the annular protrusion 16-2 of the second hole is greater than the average height of the annular protrusion 16-1 of the first hole.

[0116] When the above technical solution is adopted, the average height of the annular protrusions 16-2 of the second holes is greater than the average height of the annular protrusions 16-1 of the first holes. Therefore, the second surface roughness of the region of the P-type doped semiconductor layer exposed through the second opening corresponding to the second hole is greater than the first surface roughness of the region of the N-type doped semiconductor layer exposed through the first opening corresponding to the first hole. The conductivity of the P-type doped semiconductor layer is greater than that of the N-type doped semiconductor layer, i.e., the higher conductivity of the P-type doped semiconductor layer results in a higher contact resistance between the P-type doped semiconductor layer and the second electrode. In the embodiments of the present application, the second surface roughness corresponding to the P-type doped semiconductor layer is relatively increased, thereby increasing the contact area between the P-type doped semiconductor layer and the second electrode and reducing the contact resistance between the P-type doped semiconductor layer and the second electrode, thereby contributing to improving the photoelectric conversion efficiency of the solar cell. Furthermore, the adhesive strength of the contact between the P-type doped semiconductor layer and the electrode can be increased, the connection strength between them can be further increased, the risk of the electrode peeling off from the P-type doped semiconductor layer can be reduced, and the structural reliability of the solar cell can be improved.

[0117] For example, a plurality of first holes 15-1 are formed in the region of the first doped semiconductor layer exposed to the first opening 14-1, and a plurality of second holes 15-2 are formed in the region of the second doped semiconductor layer exposed to the second opening 14-2, where the number of second holes 15-2 per unit area located in the intermediate region of the second opening 14-2 is greater than the number of first holes 15-1 per unit area located in the intermediate region of the first opening 14-1.

[0118] For example, as shown in Figures 8-3 and 8-4, the areas surrounded by large red circles in the two figures are the middle area of ​​the first opening 14-1 and the middle area of ​​the second opening 14-2, respectively, and the remaining areas are the edge areas of the openings. As can be seen from the two figures, the number of second holes 15-2 per unit area in the middle area of ​​the second opening 14-2 is greater than the number of first holes 15-1 per unit area in the middle area of ​​the first opening 14-1.

[0119] Because the conductivity of the P-type doped semiconductor layer is higher than that of the N-type doped semiconductor layer, the contact resistance between the P-type doped semiconductor layer and the second electrode is high. Furthermore, when the electrode contacts the doped semiconductor layer in the opening, the main point of application of the tensile force is concentrated in the middle region of the opening. The large number of holes per unit area in the middle region of the second opening contributes to an increase in the roughness of the middle region of the second opening. This further increases the contact area between the second electrode and the second doped semiconductor layer in the middle region of the second opening, contributing to a decrease in the contact resistance between the P-type doped semiconductor layer and the second electrode, thereby improving the photoelectric conversion efficiency of the solar cell. Furthermore, the adhesion strength between the second electrode and the second doped semiconductor layer is increased, increasing the connection strength between them, reducing the risk of the electrode peeling off from the P-type doped semiconductor layer and improving the structural reliability of the solar cell.

[0120] It can be understood that in different embodiments, for example under different laser conditions, the number of first holes per unit area located in the intermediate region of the first opening may be greater than the number of second holes per unit area located in the intermediate region of the second opening.

[0121] For example, a plurality of first holes 15-1 are formed in the region of the first doped semiconductor layer exposed by the first opening 14-1, and a plurality of second holes 15-2 are formed in the region of the second doped semiconductor layer exposed by the second opening 14-2. Here, the average maximum radial dimension of the holes located in the central region of the second opening 14-2 is larger than the average maximum radial dimension of the holes located in the central region of the first opening 14-1. For example, the average maximum radial dimension can be measured in the following manner: The same number of first holes and second holes are taken at the same or approximately the same positions in the first hole region and the second hole region, respectively, and the average maximum radial dimensions of these holes are calculated to obtain the average maximum radial dimension of the first holes and second holes.

[0122] Still referring to Figures 8-3 and 8-4, as can be seen, the average maximum radial dimension of the holes located in the intermediate region of the second opening 14-2 is greater than the average maximum radial dimension of the holes located in the intermediate region of the first opening 14-1.

[0123] The conductivity of the P-type doped semiconductor layer is higher than that of the N-type doped semiconductor layer, i.e., the high conductivity of the P-type doped semiconductor layer results in a high contact resistance between the P-type doped semiconductor layer and the second electrode. In the embodiments of the present application, by increasing the average maximum radial dimension of the holes in the intermediate region of the second opening corresponding to the P-type doped semiconductor layer, the corresponding second surface roughness is relatively increased, thereby relatively increasing the contact area between the P-type doped semiconductor layer and the second electrode, reducing the contact resistance between the P-type doped semiconductor layer and the second electrode, and contributing to improving the photoelectric conversion efficiency of the solar cell. Furthermore, the adhesive strength of the contact between the P-type doped semiconductor layer and the electrode is strengthened, further increasing the connection strength between them, reducing the risk of the electrode peeling off from the P-type doped semiconductor layer, and improving the structural reliability of the solar cell.

[0124] It can be appreciated that in different embodiments, for example under different laser conditions, the average maximum radial dimension of the holes located in the intermediate region of the first opening may be greater than the average maximum radial dimension of the holes located in the intermediate region of the second opening.

[0125] For example, the doping concentration of the first doped semiconductor layer located in the first opening 14-1 on the side farther from the semiconductor substrate is higher than the doping concentration of the side closer to the semiconductor substrate. And / or the doping concentration of the second doped semiconductor layer located in the second opening 14-2 on the side farther from the semiconductor substrate is higher than the doping concentration of the side closer to the semiconductor substrate. For the effect of this example, refer to the effect when the doping concentration of the doped semiconductor layer located in the opening on the side farther from the semiconductor substrate is higher than the doping concentration of the side closer to the semiconductor substrate, and a detailed description thereof will be omitted here.

[0126] 8-9 and 8-10, the difference between the doping concentration of the first doped semiconductor layer located at the first opening 14-1 on the side away from the semiconductor substrate and the doping concentration of the second doped semiconductor layer located at the second opening 14-2 on the side close to the semiconductor substrate is a first difference, and the difference between the doping concentration of the second doped semiconductor layer located at the side away from the semiconductor substrate and the side close to the semiconductor substrate is a second difference, and the first difference is greater than the second difference. The abscissa in FIG. 8-9 represents the depth of the first doped semiconductor layer in the direction from the surface of the first doped semiconductor layer close to the first electrode to the surface of the first doped semiconductor layer close to the semiconductor substrate, and the ordinate represents the doping concentration of the first doped semiconductor layer. The abscissa in FIG. 8-10 represents the depth of the second doped semiconductor layer in the direction from the surface of the second doped semiconductor layer close to the second electrode to the surface of the second doped semiconductor layer close to the semiconductor substrate, and the ordinate represents the doping concentration of the second doped semiconductor layer. As can be seen by comparing FIG. 8-9 and FIG. 8-10, the first difference between the doping concentration on the side of the N-type doped semiconductor layer away from the semiconductor substrate and the doping concentration on the side close to the semiconductor substrate is larger.

[0127] The above technical solution has a large first difference, which contributes to improving the electron transport speed in the first doped semiconductor, i.e., contributing to the rapid transport of electrons from the first doped semiconductor layer to the first electrode, and thus allows the number of first openings to be appropriately reduced, which contributes to reducing damage to the first doped semiconductor layer. Furthermore, the large first difference, i.e., the doping concentration on the side of the first doped semiconductor layer located at the first opening, away from the semiconductor substrate, is higher than the doping concentration on the side closer to the semiconductor substrate, which reduces the contact resistance between the first electrode and the first doped semiconductor layer and further reduces the thickness of the first doped semiconductor layer, which not only saves costs but also improves the manufacturing efficiency of solar cells.

[0128] It can be appreciated that in different embodiments, for example under different laser conditions, the second difference may be greater than the first difference.

[0129] For example, a plurality of discontinuous protrusions 21 are formed on the side of the first doped semiconductor layer exposed through the first opening 14-1 opposite to the semiconductor substrate, and / or a plurality of discontinuous protrusions 21 are formed on the side of the second doped semiconductor layer exposed through the second opening 14-2 opposite to the semiconductor substrate. The characteristics and effects of the discontinuous protrusions in this embodiment are the same as those described in the above embodiments, and detailed description thereof will be omitted here.

[0130] For example, the number of discontinuous protrusions per unit area of ​​the edge region of the second opening 14-2 is greater than the number of discontinuous protrusions per unit area of ​​the edge region of the first opening 14-1.

[0131] When the above technical solution is adopted, the P-type doped semiconductor layer corresponding to the second opening 14-2 generally has a low doping concentration and has the properties of many holes and few electrons, which makes it difficult to form a second electrode on the P-type doped semiconductor layer. It can be understood that, when forming electrodes of the same thickness, it is more difficult to form a second electrode on the P-type doped semiconductor layer than it is to form a first electrode on the N-type doped semiconductor layer corresponding to the first opening 14-1. Furthermore, for the same opening, it is more difficult to form an electrode on the edge region of the opening than it is to form an electrode in the middle region of the opening. Therefore, in some embodiments of the present application, the number of discontinuous protrusions per unit area located in the edge region of the second opening 14-2 in the P-type doped semiconductor layer is made greater than the number of discontinuous protrusions per unit area located in the edge region of the first opening 14-1 in the N-type doped semiconductor layer, thereby improving the effect of electrode fabrication in the edge region of the second opening 14-2 and ensuring the quality of the electrode formed in the edge region of the second opening, so that the quality of the electrode formed in the edge region and the middle region of the second opening 14-2 is consistent, which contributes to improving the carrier transport effect in the second electrode.

[0132] It can be understood that in different embodiments, for example under different laser conditions, the number of discontinuous protrusions per unit area in the edge region of the first opening 14-1 is greater than the number of discontinuous protrusions per unit area in the edge region of the second opening 14-2.

[0133] For example, the number of discontinuous protrusions per unit area in the intermediate region of the first opening 14-1 is greater than the number of discontinuous protrusions per unit area in the intermediate region of the second opening 14-2.

[0134] When the above technical solution is adopted, the N-type doped semiconductor layer corresponding to the first opening 14-1 generally has a high doping concentration, with many electrons and few holes, which is conducive to forming an electrode on the N-type doped semiconductor layer. It can be understood that, when forming an electrode of the same thickness, it is less difficult to form an electrode on the N-type doped semiconductor layer than it is to form an electrode on the P-type doped semiconductor layer corresponding to the second opening 14-2. Furthermore, for the same opening, it is less difficult to form an electrode on the middle region of the opening than on the edge region of the opening. That is, since it is less difficult to form an electrode on the middle region of the N-type doped semiconductor layer, the speed of forming an electrode on the middle region of the N-type doped semiconductor layer is faster. However, since an electrode fabrication speed that is too fast is detrimental to improving adhesion, in some embodiments of the present application, the number of discontinuous protrusions per unit area located in the intermediate region of the first opening of the N-type doped semiconductor layer is made greater than the number of discontinuous protrusions per unit area located in the intermediate region of the second opening, thereby increasing the specific surface area of ​​the intermediate region of the N-type doped semiconductor layer and further contributing to improving the bonding strength between the electrode and the N-type doped semiconductor layer in the intermediate region.

[0135] It can be understood that in different embodiments, for example under different laser conditions, the number of discontinuous protrusions per unit area in the intermediate region of the second opening 14-2 is greater than the number of discontinuous protrusions per unit area in the intermediate region of the first opening 14-1.

[0136] For the sake of convenience, the doped semiconductor layer in the following examples of the present application may include one type of doped semiconductor layer, or may include at least one of the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2. The opening in the following examples of the present application may include one type of opening, or may include at least one of the first opening 14-1 and the second opening 14-2. The hole in the following examples of the present application may include one type of hole, or may include at least one of the first hole 15-1 and the second hole 15-2. The annular protrusion in the following examples of the present application may include one type of annular protrusion, or may include at least one of the annular protrusion 16-1 of the first hole and the annular protrusion 16-2 of the second hole.

[0137] For example, referring to Figures 1 and 2, a trench 18 is formed on the side of the doped semiconductor layer exposed in the opening opposite the semiconductor substrate, and a plurality of holes are formed in the surface of the trench 18 facing away from the semiconductor substrate.

[0138] It can be understood that the greater the depth of the grooves 18, the smaller the thickness of the portions of the doped semiconductor layer exposed at the openings. When the solar cell is in operation, the doped semiconductor layer can effectively shunt and collect photogenerated carriers of the opposite conductivity type. The thickness of the doped semiconductor layer determines the magnitude of its shunting effect on the photogenerated carriers. Therefore, the depth of the grooves 18 and the minimum thickness of the portions of the doped semiconductor layer located below the grooves 18 can be determined depending on the shunting ability of the portions of the doped semiconductor layer located below the grooves 18 required for actual use cases.

[0139] 3, the doped semiconductor layer has a first thickness d1 at the openings and a second thickness d2 at the non-openings, where the first thickness d1 is smaller than the second thickness d2. Because the thickness of the doped semiconductor layer at the openings is smaller than the thickness at the non-openings, the distance carriers must travel from the semiconductor substrate to the electrode is shorter, resulting in lower longitudinal transport resistance. This allows the thickness of the doped semiconductor layer to be reduced, particularly for non-sintered electrodes, thereby reducing the longitudinal transport resistance, ensuring high carrier shunting capability in the doped semiconductor layer, slowing down the carrier recombination rate, and further improving the photoelectric conversion efficiency of the solar cell.

[0140] The specific shape of the groove 18 can be determined according to the actual manufacturing process. For example, the side surface of the groove 18 may be a plane perpendicular to the surface of the semiconductor substrate, or may be a plane inclined relative to the surface of the semiconductor substrate, or may have an arc-shaped surface concave on both sides. When configured in this manner, the side surface of the groove 18 having an arc-shaped surface concave on both sides has a larger surface area than when the side surface of the groove 18 is flat, assuming other factors are the same. This further increases the contact area between the electrode and the doped semiconductor layer, further reduces the risk of the electrode detaching from the doped semiconductor layer, and improves the contact characteristics of the electrode.

[0141] For example, the longitudinal cross section of the groove 18 may be bowl-shaped. In this case, the side surfaces of the groove 18 are recessed on both sides, thereby increasing the surface area of ​​the side surfaces of the groove 18, further reducing the risk of the electrode detaching from the doped semiconductor layer and improving the contact characteristics of the electrode. Furthermore, when the longitudinal cross section of the groove 18 is bowl-shaped, the groove 18 has a regular shape, which prevents defects such as gaps from occurring during the process of filling the groove 18 with a conductive material for manufacturing an electrode, ensuring a high yield of solar cells.

[0142] For example, the doped semiconductor layer has a first thickness at the opening, and the unexposed portion of the doped semiconductor layer not exposed in the opening includes a first unexposed portion at the edge of the opening in the dielectric layer and a remaining unexposed portion other than the first unexposed portion, the first unexposed portion has a third thickness, and the remaining unexposed portion has a fourth thickness, where the fourth thickness > the third thickness > the first thickness.

[0143] For example, the first thickness range of the doped semiconductor layer at the opening in the thickness direction of the semiconductor substrate may be 20 nm or more. For example, the first thickness of the doped semiconductor layer at the opening may be 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, or 150 nm. In this case, by setting the minimum thickness of the portion of the doped semiconductor layer located below the opening within the above range, it is possible to prevent the thickness of the remaining portion of the doped semiconductor layer from becoming small after a surface with distributed pores is formed in the portion of the doped semiconductor layer exposed through the opening, thereby ensuring high carrier shunting ability in the doped semiconductor layer, reducing the carrier recombination rate, and further improving the photoelectric conversion efficiency of the solar cell.

[0144] For example, the number of holes per unit area located in the middle region of the opening is greater than the number of holes per unit area located in the edge region of the opening. For example, as shown in FIG. 8-2, the number of holes 15 per unit area in the middle region of the opening is greater than the number of holes 15 per unit area in the edge region of the opening, i.e., the holes 15 in the middle region of the opening are more densely packed than the holes 15 in the edge region.

[0145] For example, the intermediate region occupies 70% to 80% of the area of ​​the opening. For example, the intermediate region occupies 70%, 71%, 72%, 72.5%, 73%, 74%, 75%, 75.5%, 76%, 77%, 78%, 79%, and 80% of the area of ​​the opening.

[0146] It can be understood that when the metal material of the electrode contacts the doped semiconductor layer in the opening, the main point of application of the tensile force is concentrated in the middle region of the opening, and the number of holes in the middle region is greater than the number of holes in the edge region. Increasing the number of holes in the middle region contributes to increasing the contact area between the electrode and the doped semiconductor layer in the middle region, so the proportion of the middle region to the area of ​​the opening directly affects the stability of the electrode structure. At the same time, the large number of holes in the middle region can cause severe recombination in the middle region. Therefore, if the middle region is too large, severe recombination will occur at the corresponding opening in the dielectric layer, reducing the photoelectric conversion efficiency. If the middle region is too small, it will not effectively increase the adhesive strength of the contact between the electrode and the doped semiconductor layer. Therefore, the above-mentioned range of the middle region proportion effectively increases the contact area between the electrode and the doped semiconductor layer, strengthening the adhesive strength of the contact between the electrode and the doped semiconductor layer, further increasing the connection strength between them, without causing excessive recombination.

[0147] For example, the average maximum radial dimension of the holes located in the middle region of the opening is larger than the average maximum radial dimension of the holes located in the edge region of the opening. For example, the average maximum radial dimension of the holes in the middle region and the edge region can be obtained by measuring the maximum radial dimensions of the holes within the same area in each of the middle region and the edge region, or by measuring the maximum radial dimensions of the same number of holes and calculating the average value. When the metal material of the electrode contacts the doped semiconductor layer in the opening, the main point of application of the tensile force is concentrated in the middle region of the opening. A larger average maximum radial dimension of the holes in the middle region contributes to the deposition of more metal in the holes, which further increases the contact area between the electrode and the doped semiconductor layer, strengthens the adhesive strength of the contact between the electrode and the doped semiconductor layer, further strengthens the connection strength between them, reduces the risk of the electrode peeling off from the doped semiconductor layer, and improves the structural reliability of the solar cell.

[0148] When the above technical solution is adopted, when the metal material of the electrode contacts the doped semiconductor layer in the opening, the main point of application of the tensile force is concentrated in the middle region of the opening, and since the number of holes per unit area in the middle region is large in this application, this contributes to increasing the roughness of the middle region of the opening, and further contributes to increasing the contact area between the electrode and the doped semiconductor layer in the middle region of the opening, thereby strengthening the adhesive force of the contact between the electrode and the doped semiconductor layer, further strengthening the connection strength between them, reducing the risk of the electrode peeling off from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0149] For example, at least two holes 15 are in contact with each other. In this way, when forming an electrode on the doped semiconductor layer, the conductive materials for manufacturing the electrode formed in two or more holes that are in contact with each other are electrically connected, which can increase the bonding force between the electrode and the doped semiconductor layer, strengthen the connection strength therebetween, reduce the risk of the electrode detaching from the doped semiconductor layer, and improve the structural reliability of the solar cell.

[0150] By way of example, the doped semiconductor layer may include a doped polycrystalline silicon layer and may further include amorphous silicon disposed on the side of the doped polycrystalline silicon layer opposite the semiconductor substrate from the portion exposed in the opening.

[0151] When the above technical solution is adopted, after the opening is formed in the dielectric layer, it is necessary to remove the residue by etching with an etchant. Since amorphous silicon has good corrosion resistance, by distributing amorphous silicon on the side of the doped semiconductor layer exposed through the opening opposite the semiconductor substrate, the amorphous silicon can protect the doped polycrystalline silicon layer underneath and prevent the doped polycrystalline silicon layer underneath the amorphous silicon from being corroded by the etchant and severely damaged, resulting in serious recombination. In addition, amorphous silicon has good passivation effect, which helps reduce recombination caused by direct contact between the doped polycrystalline silicon layer and the electrode.

[0152] Optionally, when the doped semiconductor layer is a doped polycrystalline silicon layer, the doped semiconductor layer exposed in the opening on the opposite side of the semiconductor substrate may further include at least one of microcrystalline silicon and nanocrystalline silicon.The beneficial effects of including microcrystalline silicon and / or nanocrystalline silicon therein are similar to the beneficial effects of the amorphous silicon described above, so the above description can be referred to and detailed description will be omitted here.

[0153] By way of example, the doped semiconductor layer may include a doped polycrystalline silicon layer, and the doped semiconductor layer may further include amorphous silicon located at an edge of the opening in the dielectric layer, located below the dielectric layer, and on an opposite side of the doped polycrystalline silicon layer from the semiconductor substrate.

[0154] When the above technical solution is adopted, after forming the opening in the dielectric layer, it is necessary to etch it with an etchant to remove the residue. When etched with an etchant to remove the residue, side etching also occurs in the portion of the dielectric layer that is located at the edge of the opening and located below the dielectric layer. In this case, since amorphous silicon has good corrosion resistance, by distributing amorphous silicon at the edge of the opening in the dielectric layer and below the dielectric layer on the side of the doped polycrystalline silicon layer opposite the semiconductor substrate, the amorphous silicon can protect the doped polycrystalline silicon layer underneath and prevent the doped polycrystalline silicon layer underneath the amorphous silicon layer from being corroded by the etchant and severely damaged, resulting in serious recombination. In addition, amorphous silicon has a good passivation effect, which helps to reduce recombination loss caused by direct contact between the doped polycrystalline silicon layer and the electrode.

[0155] For example, the length of the amorphous silicon distributed in the direction parallel to the semiconductor substrate from the edge of the opening in the dielectric layer is greater than 0 μm and less than 6 μm. Here, the length of the amorphous silicon distributed is calculated as the length from the edge of the opening in the dielectric layer to the farthest amorphous silicon along a direction parallel to the semiconductor substrate and away from the opening edge. Here, the direction parallel to the semiconductor substrate is perpendicular to the thickness direction of the semiconductor substrate.

[0156] As can be seen from the above-described function of amorphous silicon, if the length range of the amorphous silicon distribution is very large, amorphous silicon has a higher lateral transport resistance than polycrystalline silicon, which is unfavorable for lateral carrier transport and reduces the photoelectric conversion efficiency of the solar cell. Furthermore, if the length range of the amorphous silicon distribution is large, a large amount of heat is required when forming an opening in the dielectric layer. If the heat is large, excessive damage to the doped semiconductor layer occurs when forming the opening in the dielectric layer, resulting in a reduced passivation effect of the doped semiconductor layer. Therefore, in this application, the length of the amorphous silicon distribution in the direction parallel to the semiconductor substrate from the edge of the opening in the dielectric layer is set to 6 μm or less.

[0157] Furthermore, if the length range of the amorphous silicon distribution is very small, in cases where side etching is severe, the corrosion prevention effect cannot be effectively achieved and the passivation effect is not significant. Therefore, in some examples, the length of the amorphous silicon distribution in the direction parallel to the semiconductor substrate from the edge of the opening in the dielectric layer is set to 0.001 μm or more.

[0158] The distributed length of the amorphous silicon may be, for example, 0.001 μm, 0.007 μm, 0.01 μm, 0.07 μm, 0.09 μm, 0.1 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 2 μm, 3 μm, 5 μm, or 6 μm.

[0159] For example, the depth range of the amorphous silicon in the thickness direction of the semiconductor substrate is greater than 0 nm and less than or equal to 350 nm.

[0160] In some embodiments, the depth of the amorphous silicon at a location where protrusions (e.g., annular protrusions, discontinuous protrusions) are distributed on the side of the doped semiconductor layer exposed through the opening opposite the semiconductor substrate is greater than the depth of the amorphous silicon at a location where no protrusions are present. For example, the depth range of the amorphous silicon corresponding to the location where protrusions are distributed on the side of the doped semiconductor layer exposed through the opening opposite the semiconductor substrate is greater than 0 nm and less than 350 nm, and the depth range of the amorphous silicon corresponding to the location where no protrusions are present is greater than 0 nm and less than 50 nm. In most cases, when the protrusions are formed by melting and then solidifying the material of the doped semiconductor layer, and the doped semiconductor layer is a doped polycrystalline silicon layer, the material of the protrusions is primarily amorphous silicon, and therefore the amorphous silicon depth of the protrusions is greater than the amorphous silicon depth of the non-protrusions.

[0161] When adopting the above technical solution, if the depth of the amorphous silicon is too large, the carrier transport resistance will increase, which will further affect the electrical characteristics of the solar cell. Therefore, the amorphous silicon depth is set to 350 nm or less.

[0162] Furthermore, if the depth range of the amorphous silicon is too small, it will not only fail to protect the underlying doped semiconductor layer and prevent it from being damaged by the etchant, but also fail to effectively passivate the surface of the doped polycrystalline silicon. Therefore, in some examples, the depth of the amorphous silicon is set to 0.001 nm or more.

[0163] The depth of the amorphous silicon in the thickness direction of the semiconductor substrate may be, for example, 0.001 nm, 0.005 nm, 0.009 nm, 0.01 nm, 0.05 nm, 0.1 nm, 0.8 nm, 1 nm, 6 nm, 10 nm, 50 nm, 100 nm, 200 nm, or 350 nm.

[0164] 8-11, for example, at the edge of the opening in the dielectric layer 13, gaps 22 are formed between the dielectric layer 13 and the underlying doped semiconductor layer 12. Here, the size and distribution number of the gaps 22 are not limited.

[0165] During the formation of a dielectric layer, elemental hydrogen is typically formed in the dielectric layer. For example, when the dielectric layer contains aluminum oxide, excess hydrogen is generated due to the reaction with water during the aluminum oxide deposition process. Furthermore, when silicon nitride is deposited, nitrogen-hydrogen bonds remain, and at high temperatures, these nitrogen-hydrogen bonds break and recombine to generate hydrogen gas. Because the dielectric layer contains elemental hydrogen, hydrogen escapes from the dielectric layer due to thermal effects during laser patterning. During this process, film breakdown occurs in some non-opened regions of the dielectric layer, damaging the dielectric layer and the doped semiconductor layer and further affecting the passivation effect of the solar cell.

[0166] In this embodiment, the gap 22 can provide a space for hydrogen to escape during the laser patterning process, which helps to mitigate or avoid film breakdown in the dielectric layer in the non-aperture area due to laser patterning, and helps to accurately control the size of the aperture area and reduce damage to the doped semiconductor layer in the non-aperture area due to laser patterning, thereby effectively ensuring the passivation effect of the solar cell.

[0167] For example, the distribution length of the gaps 22 in the direction parallel to the semiconductor substrate from the edge of the opening in the dielectric layer is greater than 0 μm and less than 5 μm. For example, the distribution length of the gaps 22 is calculated by measuring the length from the edge of the opening in the dielectric layer to the farthest gap along a direction parallel to the semiconductor substrate away from the opening edge. Here, the direction parallel to the semiconductor substrate is perpendicular to the thickness direction of the semiconductor substrate. Considering that if the distribution length of the gaps 22 is very large, for example, 10 μm, 20 μm, or 30 μm, or even larger, the dielectric layer is prone to cracking and peeling, which can affect the passivation effect of the solar cell and further increase recombination loss in the doped semiconductor layer, the embodiment of the present application specifies the distribution length of the gaps in the direction parallel to the semiconductor substrate to be less than 5 μm.

[0168] Furthermore, if the distribution length of the gaps 22 is very small, hydrogen will escape during the laser patterning process, and there will be insufficient space for the hydrogen to escape, so there is still a risk of film breakdown occurring in the dielectric layer in the non-opening areas. Therefore, in some examples, the distribution length of the gaps in the direction parallel to the semiconductor substrate from the edge of the opening in the dielectric layer is set to 0.01 μm or more.

[0169] The distributed length of the gap in the direction parallel to the semiconductor substrate from the edge of the opening in the dielectric layer may be, for example, 0.01 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 2 μm, 3 μm, or 5 μm.

[0170] The above-mentioned gap distribution length range provided in the present application can provide a reasonable space for hydrogen in the dielectric layer to escape during the laser patterning process, effectively mitigate or avoid film breakdown in the dielectric layer in the non-aperture areas due to laser patterning, accurately control the size of the aperture areas, contribute to reducing damage to the doped semiconductor layer in the non-aperture areas due to laser patterning, and prevent the dielectric layer from cracking and peeling off due to the gap distribution length being too large, contribute to avoiding the dielectric layer cracking and peeling off from affecting the passivation effect of the solar cell, thereby reducing damage caused by laser patterning and contributing to ensuring the passivation effect of the solar cell.

[0171] For example, the length of the amorphous silicon distributed from the edge of the opening in the dielectric layer 13 in a direction parallel to the semiconductor substrate layer is greater than the length of the gap 22. After turning the dielectric layer, it is necessary to remove the residue using an etchant. During the process of removing the residue using the etchant, the etchant is likely to remain in the gap and is difficult to flow out. Therefore, to prevent the etchant from corroding and damaging the doped polycrystalline silicon in the gap, in some embodiments of the present application, amorphous silicon is formed at the edge of the opening in the dielectric layer and below the dielectric layer on the side of the doped polycrystalline silicon layer opposite the semiconductor substrate, and the length of the amorphous silicon distributed is greater than the length of the gap.

[0172] For example, gap 22 contains at least one of the metallic materials in the electrode.

[0173] The present application adopts the above solution, and by allowing the gap 22 to contain at least one of the metal materials in the electrode, the contact area between the electrode and the doped semiconductor layer can be increased, thereby reducing the contact resistance between the electrode and the doped semiconductor layer, increasing the bonding strength between the electrode and the doped semiconductor layer, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0174] By way of example, the metallic material may include one or more of nickel, copper, silver or tin.

[0175] The present application adopts the above solution, and by filling the gaps with these metal materials, the contact area between the electrode and the doped semiconductor layer is increased, the contact resistance between the electrode and the doped semiconductor layer is reduced, and the bonding force between the electrode and the doped semiconductor layer is increased, strengthening the connection strength between them, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell. Furthermore, these metals can also stop deep level impurities or other metals from diffusing into the doped semiconductor layer and the semiconductor substrate, reducing recombination in the doped semiconductor layer and the semiconductor substrate, and reducing recombination loss.

[0176] For example, the portion of the dielectric layer adjacent to the opening is warped away from the doped semiconductor layer at the position indicated by the arrow in Figures 8-13. Because the portion of the dielectric layer adjacent to the opening is warped away from the doped semiconductor layer, a space is formed between the dielectric layer and the underlying doped semiconductor layer at the portion adjacent to the opening. This provides a space for hydrogen generated by the laser action of the dielectric layer during the laser patterning process to escape, thereby mitigating or avoiding film breakdown, reducing damage caused by laser patterning, and preventing the dielectric layer from cracking and peeling off, which may affect the passivation effect of the solar cell, thereby ensuring the passivation effect of the solar cell.

[0177] For example, the angle at which the portion of the dielectric layer adjacent to the opening is warped away from the doped semiconductor layer ranges from greater than 0° to 20° or less. The angle is, for example, angle α shown in FIG. 4 . For example, this angle is the angle formed by the surface of the portion of the dielectric layer adjacent to the opening facing the doped semiconductor layer with respect to the first surface of the semiconductor substrate, with one side of this angle corresponding to a direction parallel to the first surface of the semiconductor substrate and the other side corresponding to the surface of the portion of the dielectric layer adjacent to the opening facing the doped semiconductor layer. Considering that if the angle at which the portion of the dielectric layer adjacent to the opening is warped away from the doped semiconductor layer is very large, for example, 30°, 40°, or other larger angles, the dielectric layer is likely to crack and peel off, affecting the passivation effect of the solar cell and causing loss due to recombination in the doped semiconductor layer, in the embodiments of the present application, the angle at which the portion of the dielectric layer adjacent to the opening is warped away from the doped semiconductor layer is 20° or less.

[0178] Furthermore, if the angle at which the portion of the dielectric layer adjacent to the opening is warped away from the doped semiconductor layer is very small, this is disadvantageous in providing a space for hydrogen to escape during the laser patterning process, and there is a risk of film breakdown occurring in the dielectric layer in the non-laser opening region. Considering this, in some examples, the angle at which the portion of the dielectric layer adjacent to the opening is warped away from the doped semiconductor layer is set to 0.001° or more.

[0179] The angle at which the portion of the dielectric layer adjacent to the opening is curved away from the doped semiconductor layer may be, for example, 0.001°, 0.005°, 0.01°, 0.05°, 0.09°, 1°, 6°, 9°, 10°, 12°, 15°, 18°, or 20°.

[0180] The range of the angle at which the portion of the dielectric layer adjacent to the opening is warped away from the doped semiconductor layer provided in the examples of the present application can provide a reasonable space for hydrogen in the dielectric layer to escape during the laser patterning process, can mitigate or avoid film breakdown in the dielectric layer in the non-opening region due to laser patterning, can reduce damage to the doped semiconductor layer in the non-opening region due to laser patterning, and can prevent the dielectric layer from cracking and peeling off due to an excessively large warping angle. Therefore, the above angle range can ensure the passivation effect of the solar cell, reduce damage caused by laser patterning, and prevent the dielectric layer from cracking and affecting the passivation effect of the solar cell.

[0181] For example, as shown in Figure 8-12, a depression 23 is formed in the edge region of the opening. Figure 8-12 is a partially enlarged schematic diagram of point A in Figure 8-3. The maximum radial dimension of the depression 23 is much smaller than the maximum radial dimension of the hole, and there is no annular protrusion around the depression 23 (as shown in the figure, there is no bright white circle around the depression 23). The depression 23 is mainly distributed in the edge region of the opening. The depression increases the surface roughness and specific surface area of ​​the opening edge region, increasing the bonding force between the electrode and the doped semiconductor layer and strengthening the connection strength between them, reducing the risk of the electrode detaching from the doped semiconductor layer, and contributing to improving the structural reliability of the solar cell.

[0182] For example, when the doped semiconductor layer comprises an N-type doped semiconductor layer, the recesses 23 are distributed in the edge region of the opening in the N-type doped semiconductor layer.

[0183] Generally, N-type doped semiconductor layers have a high doping concentration and have the property of having many electrons and few holes, which is conducive to the formation of an electrode on the N-type doped semiconductor layer. It can be understood that when forming an electrode of the same thickness, the difficulty of forming an electrode on an N-type doped semiconductor layer is less than the difficulty of forming an electrode on a P-type doped semiconductor layer, which means that the speed of forming an electrode on an N-type doped semiconductor layer is higher, which reduces the adhesion between the electrode and the N-type doped semiconductor layer. Furthermore, for the same opening, it is more difficult to fabricate an electrode in the edge region of the opening than in the middle region of the opening. Therefore, in some embodiments of the present application, the depressions 23 are distributed in the edge region of the opening in the N-type doped semiconductor layer, which increases the specific surface area of ​​the edge region of the opening in the N-type doped semiconductor layer, reduces the difficulty of fabricating an electrode in the edge region, and further ensures the quality of the electrode formed in the edge region of the opening. This increases the contact area between the electrode and the N-type doped semiconductor layer located in the edge region of the opening, improves the bonding strength between the electrode and the N-type doped semiconductor layer located in the edge region of the opening, and reduces the contact resistance between the electrode and the N-type doped semiconductor layer located in the edge region of the opening.

[0184] For example, referring to FIG. 8-2, a crack 24 is formed at the edge of the dielectric layer 13 adjacent to the opening. When an electrode is formed at a position corresponding to the opening in the dielectric layer, the crack 24 formed at the edge of the dielectric layer adjacent to the opening allows the electrode-forming material to fill the crack 24 and electrically connect to the doped semiconductor layer through the crack 24, thereby further improving the bonding strength between the electrode and the doped semiconductor layer. In addition, when patterning the dielectric layer, the crack formed at the edge of the opening in the dielectric layer helps hydrogen escape, reducing the risk of film breakdown and allowing for accurate control of the dimensions of the opening made in the dielectric layer, thereby helping to avoid damage to the doped semiconductor layer below the non-opening region, which would lead to serious recombination.

[0185] For example, referring to Figures 8-13, silicon oxide is formed on the side of the doped semiconductor layer exposed through the opening, opposite the semiconductor substrate. In one embodiment, the silicon oxide formed on the annular protrusion is thick, and the silicon oxide is concentrated in the peripheral region of the annular protrusion (the opposite side of the opening), and the silicon oxide in the peripheral region of the annular protrusion is thicker than the silicon oxide in the opening 15. It can be understood that after forming the opening in the dielectric layer, it is necessary to remove the residue by etching with an etchant. When removing the residue using an etchant, since the silicon oxide is located above the doped semiconductor layer, the etchant reacts preferentially with the silicon oxide, thereby reducing the corrosion of the underlying doped semiconductor layer and further reducing damage caused by patterning. In addition, silicon oxide has a good passivation effect, which can passivate the surface of the doped semiconductor layer and contribute to reducing recombination loss that occurs when the doped semiconductor layer directly contacts an electrode.

[0186] It should be noted that in some examples, it is necessary to remove silicon oxide formed on the side of the doped semiconductor layer opposite the semiconductor substrate from the portion exposed through the opening. In other examples, it is not necessary to remove silicon oxide formed on the side of the doped semiconductor layer opposite the semiconductor substrate from the portion exposed through the opening, because a plurality of holes are formed on the side of the doped semiconductor layer opposite the semiconductor substrate from the portion exposed through the opening, and the holes can increase the contact area between the electrode and the doped semiconductor layer, improve bonding strength, and reduce contact resistance.

[0187] For example, when the dielectric layer contains aluminum oxide, aluminum is contained on the side of the doped semiconductor layer opposite the semiconductor substrate from the portion exposed through the opening. Because aluminum is a metallic element, if aluminum remains on the side of the doped semiconductor layer opposite the semiconductor substrate from the portion exposed through the opening, it can reduce the contact resistance between the electrode and the doped semiconductor layer, and further contribute to carrier shunting, reducing the carrier recombination rate and further improving the photoelectric conversion efficiency of the solar cell.

[0188] By way of example, the portion of the doped semiconductor layer exposed in the opening may have a via hole through the doped semiconductor layer, where the via hole through the doped semiconductor layer may have nanoscale dimensions.

[0189] In some examples, a through-hole penetrating the doped semiconductor layer is formed in the hole. When the portion of the doped semiconductor layer exposed to the opening includes a through-hole penetrating the doped semiconductor layer, in some examples, when forming an electrode, the electrode-forming material can directly contact the semiconductor substrate through the through-hole, and thus a small amount of carriers generated in the semiconductor substrate can be directly transported to the electrode, reducing resistance and improving the carrier shunting ability, further contributing to improving the photoelectric conversion rate of the solar cell.

[0190] In this embodiment, the electrode 17 may be a single-layer structure, for example, as shown in Figures 1, 2, 4 and 5, or a laminated multi-layer structure. For example, as shown in Figures 9-1 and 9-2, the electrode includes a laminated two-layer structure, which is a laminated conductive contact layer 17-2 and a connecting electrode 17-1, respectively.

[0191] In the back-contact solar cell shown in Figures 4 to 7, the electrodes include a first electrode 17A and a second electrode 17B, which are disposed on the side of the dielectric layer 13 away from the semiconductor substrate 11. The first electrode 17A is electrically connected to the first doped semiconductor layer 12-1 through the first opening 14-1, and the second electrode 17B is electrically connected to the second doped semiconductor layer 12-2 through the second opening 14-2. In this application, electrical connection may also be referred to as electrical coupling or electrical contact. At least one of the first electrode 17A and the second electrode 17B includes a laminated conductive contact layer 17-2 and a connecting electrode 17-1.

[0192] For convenience of explanation, the electrodes in the following examples of the present application may include one type of electrode, or may include at least one of the first electrode 17A and the second electrode 17B, and the characteristics of at least one of the first electrode 17A and the second electrode 17B are the same as the characteristics of the electrodes described below.

[0193] The conductive contact layer 17-2 is located on the side of the electrode closest to the doped semiconductor layer 12, and the connecting electrode 17-1 is electrically connected to the doped semiconductor layer 12 via the conductive contact layer 17-2.

[0194] When the electrode has a single layer structure, the electrode can be formed by a method such as screen printing, chemical plating, electroplating, deposition and etching, etc. When the electrode has a laminated multilayer structure, each film layer can be formed by a method such as electroplating, chemical plating, screen printing, deposition and etching, etc.

[0195] The electrode material may be a metal material such as Ag, Cu, Al, Ni, Au, Zn, Sn, or Pb; a metal oxide including various TCOs such as ITO, AZO, or IWO; a metal nitride such as TiN; a metal carbide such as TiC; a metal sulfide; or other conductive connection materials such as graphene; or various combinations of the above materials. The material of the conductive contact layer 17-2 and the connection electrode 17-1 may be any one of the above electrode materials or a suitable combination thereof.

[0196] It should be noted that when the electrode includes a conductive contact layer 17-2 and a connecting electrode 17-1, the material of the conductive contact layer 17-2 and the material of the connecting electrode 17-1 may be the same or different. The material and thickness of the conductive contact layer 17-2 can be determined according to the conductivity type of the doped semiconductor layer and the actual use case, and are not specifically limited here. In one possible implementation, the conductive contact layer 17-2 is formed by electroplating or chemical plating and may be made of one or more of Ag, Ni, and Sn, for example, while the connecting electrode 17-1 is formed by screen printing and may be made of silver paste, copper paste, or silver-coated copper paste, for example.

[0197] It can be understood that when the electrode has a multi-layer structure, the bottommost conductive contact layer 17-2 is formed on the surface of the doped semiconductor layer having an uneven surface, thereby increasing the bonding strength between the conductive contact layer 17-2 and the doped semiconductor layer and reducing the risk of the conductive contact layer 17-2 becoming detached from the doped semiconductor layer, i.e., reducing the risk of the electrode becoming detached from the doped semiconductor layer, thereby contributing to improving the structural reliability of the solar cell. Here, when the conductive contact layer 17-2 is formed on the surface of the doped semiconductor layer having an uneven surface, the surface of the conductive contact layer 17-2 opposite the semiconductor substrate may be flat or uneven. When the surface of conductive contact layer 17-2 opposite the semiconductor substrate also has uneven surface features, forming connecting electrode 17-1 increases the contact area between conductive contact layer 17-2 and connecting electrode 17-1, improving the bonding strength between conductive contact layer 17-2 and connecting electrode 17-1, i.e., further increasing the bonding strength between the electrode and the doped semiconductor layer, and contributing to further reducing the risk of the electrode becoming detached from the doped semiconductor layer.When the electrode has a single-layer structure, the electrode is formed on the surface of the doped semiconductor layer, which has an uneven surface, increasing the bonding strength between the electrode and the doped semiconductor layer, reducing the risk of the electrode becoming detached from the doped semiconductor layer, and contributing to improving the structural reliability of the solar cell.

[0198] An embodiment of the present application further provides a solar module including a plurality of cell strings that can be connected in series and / or parallel. Each cell string includes a plurality of solar cells and a plurality of connecting members for connecting the plurality of solar cells in series. It is understood that the connecting members are electrically connected to the electrodes of the plurality of solar cells, thereby connecting the plurality of solar cells in series. Here, the solar cells include the solar cells of any of the above embodiments.

[0199] The connecting member may be, for example, a ribbon, a metal wire, a conductive tape, or the like.

[0200] In the technology of forming electrodes using a low-temperature metallization process, a prerequisite for smooth low-temperature metallization is ensuring good contact between the electrode material and the surface of the doped semiconductor layer. Poor contact can make low-temperature metallization difficult or even impossible. Conventional electrode manufacturing methods require pretreatment of the doped semiconductor layer surface to improve the contact characteristics between the electrode and the doped semiconductor layer after forming an opening in the dielectric layer using a process such as laser etching. However, after the pretreatment, the surface of the doped semiconductor layer exposed through the opening is flat, resulting in a weak bond between the electrode and the doped semiconductor layer, increasing the risk of the electrode detaching from the doped semiconductor layer and reducing the structural reliability of the solar cell.

[0201] In order to solve the above problems, the embodiments of the present application provide a method for manufacturing a solar cell. 4 The manufacturing process is described with the cross-sectional views of the operations shown in Figure 1. Specifically, the manufacturing method of the solar cell includes the following steps:

[0202] First, a semiconductor substrate having opposite first and second surfaces is provided, and the conductivity type and surface morphology of the semiconductor substrate can be referred to above, and detailed description thereof will be omitted here.

[0203] In practical application, when the first surface of the semiconductor substrate included in the solar cell is the light-receiving surface and the first surface is a textured surface, the semiconductor substrate can be first cleaned to remove impurities from the surface of the semiconductor substrate, and then a texturing solution such as an alkaline solution can be used to perform a one-sided texturing process on the first surface of the semiconductor substrate to improve the light absorption of the semiconductor substrate.

[0204] Next, a doped semiconductor layer is formed on the first surface and / or the second surface. The above can be referenced for information on the material, conductivity type, formation position, thickness, etc., of the doped semiconductor layer. The specific formation process of the doped semiconductor layer can be determined according to the position where the doped semiconductor layer is to be formed on the semiconductor substrate.

[0205] For example, if the solar cell being fabricated is a double-sided contact solar cell, an intrinsic semiconductor layer can be formed on the first and / or second surfaces by a process such as chemical vapor deposition. The intrinsic semiconductor layer can then be doped by a process such as diffusion or ion implantation to form a doped semiconductor layer, as shown in FIG.

[0206] For example, if the solar cell being fabricated is a back-contact solar cell, a doped semiconductor layer can first be formed over the entire first and / or second surfaces using a deposition and doping process, and then at least a portion of the doped semiconductor layer is selectively removed using a process such as laser etching.

[0207] 11, a dielectric layer 13 is formed on the side of the doped semiconductor layer 12 opposite to the semiconductor substrate 11. Specifically, the dielectric layer 13 can be formed by processes such as chemical vapor deposition and physical vapor deposition. The material and thickness of the dielectric layer 13 can be determined as described above.

[0208] Next, as shown in FIGS. 11 and 12, an opening 14 is formed through the dielectric layer 13 so as to expose at least a portion of the doped semiconductor layer 12.

[0209] The embodiments of the present invention do not specifically limit the method for forming the openings. For example, the openings can be formed by a laser etching process and / or a wet etching process. When forming the openings by a laser etching process and a wet etching process, the openings can be formed first by a laser etching process and then by a wet etching process. Alternatively, the openings can be formed by a process such as wet etching or dry etching using the masking effect of a corresponding mask layer.

[0210] It should be noted that because the laser etching process has high etching accuracy, when an opening in a dielectric layer is formed using the laser etching process, the accuracy of the opening can be improved, which in turn can improve the accuracy of the electrode formation and thereby improve the yield of the manufactured solar cell. As shown in FIG. 11 , the specific etching depth corresponding to the formation of opening 14 can be equal to the thickness of dielectric layer 13. In this case, dielectric layer 13 is etched just through, thereby reducing damage caused by the etching process to the portion of doped semiconductor layer 12 exposed through opening 14. Alternatively, as shown in FIG. 12 , the etching depth can be slightly greater than the thickness of dielectric layer 13. In this case, the portion of doped semiconductor layer 12 exposed through opening 14 is etched only to a certain depth, thereby ensuring that dielectric layer 13 is etched through and that the electrode can penetrate dielectric layer 13 to electrically connect to doped semiconductor layer 12. However, since the etching depth is required to be equal to the thickness of dielectric layer 13, strict control of etching accuracy is not required, thereby reducing the difficulty of etching. Here, if the specific etching depth corresponding to the formation of opening 14 is slightly greater than the thickness of dielectric layer 13, silicon residues are likely to remain on the surface of the portion of doped semiconductor layer 12 exposed to opening 14.

[0211] 13, a plurality of holes are formed in the exposed portion of doped semiconductor layer 12 in opening 14, opposite semiconductor substrate 11. It will be appreciated that the openings and holes may be formed in the same process step or in different process steps, e.g., the openings may be formed before the holes are formed.

[0212] For example, a groove 18 is formed on the side of the doped semiconductor layer 12 opposite to the semiconductor substrate 11 in the portion exposed in the opening 14, and a plurality of holes are formed in the surface of the groove 18.

[0213] In another example, a hole is directly formed on the side of the doped semiconductor layer 12 exposed through the opening 14 opposite to the semiconductor substrate 11 without forming a groove 18 .

[0214] For example, a wet etching process can be used to form a groove on the side of the doped semiconductor layer opposite the semiconductor substrate at the portion exposed by the opening, forming some pores on the surface of the groove. Specifically, the etchant can contain ammonium bifluoride and / or ammonium fluoride, which can remove silicon residue remaining on the semiconductor substrate after the opening is formed and, optionally, further remove oxide formed on the portion of the doped semiconductor layer exposed by the opening after etching, thereby ensuring good contact characteristics between the electrode formed in the groove and the doped semiconductor layer. Furthermore, the etching of the portion of the doped semiconductor layer exposed by the opening with the etchant also forms a groove with distributed pores on its surface. In actual applications, the material of the dielectric layer generally includes silicon nitride. Compared to a hydrogen fluoride solution, the ammonium bifluoride solution and the ammonium fluoride solution are more acidic. Specifically, when the etching solution contains ammonium hydrogen fluoride and / or ammonium fluoride, the etching solution can dissolve the oxides and silicon residues, and grooves with holes on the surface of the doped semiconductor layer are formed, without significantly affecting the dielectric layer containing silicon nitride as a material, and the dielectric layer is prevented from being excessively corroded by the etching solution during the groove formation process, ensuring good passivation effect for the dielectric layer and ensuring precision in the formation of the openings and electrodes.

[0215] In actual application, the concentration of the etching solution and the specific process conditions for wet etching can be determined according to the type of etching solution, the size of the grooves to be formed, and the size and number of holes distributed on the groove surface, and are not specifically limited herein.

[0216] For example, when the etching solution contains ammonium hydrogen fluoride and / or ammonium fluoride, the fluorine ion concentration in the etching solution may be 2 g / L or more and 13 g / L or less. For example, the fluorine ion concentration in the etching solution may be 2 g / L, 5 g / L, 7 g / L, 10 g / L, or 12 g / L. In this case, the removal of oxide and silicon residue and the formation of grooves are achieved by forming silicon tetrafluoride mainly through the reaction of fluorine ions with silicon ions in the oxide or fluorine ions with silicon atoms in the etching solution. Therefore, by keeping the fluorine ion concentration within the above range, the etching solution can prevent the etching effect of the silicon residue and oxide from being reduced due to a low fluorine ion concentration, ensuring good contact characteristics between the electrode and the doped semiconductor layer, and at the same time, preventing a slow etching rate of the etching solution to form grooves and holes, thereby contributing to improved manufacturing efficiency. Furthermore, it is possible to prevent the formation rate of the trenches and holes from being high, which is caused by the high concentration of fluorine ions, making it difficult to adjust and control the etching completion time, and ensure that the shapes of the trenches and holes meet operational requirements. At the same time, it is possible to prevent the etching solution from having a significant impact on the dielectric layer during the formation of the trenches and holes, and ensure that the dielectric layer has a good passivation effect and high opening formation precision.

[0217] Specifically, when the etching solution contains ammonium hydrogen fluoride and / or ammonium fluoride, the concentration of ammonium hydrogen fluoride and / or ammonium fluoride in the etching solution can be determined according to the concentration of fluorine ions in the etching solution. For example, when the etching solution contains ammonium hydrogen fluoride but does not contain ammonium fluoride, the concentration of ammonium hydrogen fluoride in the etching solution may be 5 g / L or more and 20 g / L or less.

[0218] For example, the etching time corresponding to the wet etching process may be 10 seconds or more and 60 seconds or less. For example, the etching time may be 10 seconds, 20 seconds, 30 seconds, 40 seconds, 50 seconds, or 60 seconds. In this case, since the etching time corresponding to the wet etching process is directly proportional to the dimensions of the grooves and holes formed within a certain range, by keeping the etching time within the above range, it is possible to prevent the groove depth and hole diameter from being small, which would result in low groove surface roughness, and to ensure a large contact area between the electrode and the portion of the doped semiconductor layer corresponding to the groove. Furthermore, it is possible to prevent the groove depth and hole diameter from being large, which would result in a small thickness of the portion of the doped semiconductor layer remaining below the groove, which would result in a long etching time, and it is possible to ensure good carrier shunting ability in the doped semiconductor layer and good operating performance of the solar cell.

[0219] For example, the process temperature corresponding to the wet etching process may be 15° C. or more and 30° C. or less. For example, the process temperature may be 15° C., 18° C., 20° C., 22° C., 24° C., 26° C., 28° C., or 30° C. The beneficial effects in this case are similar to those in the case where the etching time corresponding to the wet etching process is 10 s. or more and 60 s. Therefore, detailed description thereof will be omitted here.

[0220] In practical application, the etching solution may contain additives to reduce the corrosion rate of the etching solution to an extremely low probability during the groove formation process, further improve the passivation effect of the dielectric layer on the doped semiconductor layer, and further improve the formation precision of the openings and electrodes.

[0221] The type of additive and the concentration of the additive in the etching solution can be determined according to the type of etching solution and the actual use case, and any additive may be used as long as it can inhibit the corrosion of the dielectric layer by the etching solution.

[0222] For example, the additive may include at least one of 3-ethylbutoxypropylamine, phenylacetic acid, sodium benzoate, and sodium acetate. For example, the additive may be only 3-ethylbutoxypropylamine, phenylacetic acid, sodium benzoate, or sodium acetate. For example, the additive may include any two of 3-ethylbutoxypropylamine, phenylacetic acid, sodium benzoate, and sodium acetate. For example, the additive may include any three of 3-ethylbutoxypropylamine, phenylacetic acid, sodium benzoate, and sodium acetate. For example, the additive may include 3-ethylbutoxypropylamine, phenylacetic acid, sodium benzoate, and sodium acetate. In this case, 3-ethylbutoxypropylamine, phenylacetic acid, sodium benzoate, and sodium acetate have good solubility and dispersibility in the etching solution, and are likely to form steric hindrance on the surface of the dielectric layer that inhibits contact between ammonium bifluoride and / or ammonium fluoride and the dielectric layer. This results in an extremely low corrosion rate of the etching solution on the dielectric layer during the groove formation process, further improving the passivation effect of the dielectric layer on the doped semiconductor layer and further improving the forming precision of the openings and electrodes.

[0223] For example, the concentration of the additive in the etching solution may be 0.5 ml / L or more and 5 ml / L or less. For example, the concentration of the additive may be 0.5 ml / L, 1 ml / L, 2 ml / L, 3 ml / L, 4 ml / L, or 5 ml / L. In this case, by keeping the concentration of the additive in the etching solution within the above range, it is possible to prevent a low additive concentration from weakening the steric hindrance formed by the additive on the surface of the dielectric layer, thereby ensuring a low corrosion efficiency of the etching solution on the dielectric layer. It is also possible to prevent a high additive concentration from reducing the corrosion effect of silicon residues and oxides by the etching solution, which would affect the formation of grooves and holes, thereby ensuring high connection strength and contact characteristics between the electrode and the doped semiconductor layer.

[0224] Next, when an electrode is subsequently formed using an electroplating process, the etching solution may contain a surfactant, which reduces the surface tension of the electroplating pretreatment solution and provides strong wetting ability to the small-sized holes formed on the groove surface, thus contributing to the filling of the holes with the metal material for electrode fabrication and ensuring a large contact area between the electrode and the doped semiconductor layer. For example, the etching solution may contain a surfactant.

[0225] The type of surfactant and the concentration of the surfactant in the etching solution can be determined depending on the type of etching solution and the actual use case, and any surfactant can be used as long as it can reduce the surface tension of the electroplating pretreatment solution.

[0226] For example, the surfactant may include at least one of perfluorotriethylamine, perfluorohexylsulfonamide, and perfluorohexylsulfuryl fluoride. For example, the surfactant may be perfluorotriethylamine, perfluorohexylsulfonamide, or perfluorohexylsulfuryl fluoride. For example, the surfactant may include any two of perfluorotriethylamine, perfluorohexylsulfonamide, and perfluorohexylsulfuryl fluoride. For example, the surfactant may include perfluorotriethylamine, perfluorohexylsulfonamide, and perfluorohexylsulfuryl fluoride. In this case, the perfluorotriethylamine, perfluorohexylsulfonamide, and perfluorohexylsulfuryl fluoride all have good wettability, ensuring that the electroplating pretreatment solution has strong infiltration into the pores on the groove surface.

[0227] For example, the surfactant concentration in the etching solution may be 0.01 ml / L or more and 0.2 ml / L or less. For example, the surfactant concentration may be 0.01 ml / L, 0.04 ml / L, 0.08 ml / L, 0.12 ml / L, 0.16 ml / L, or 0.2 ml / L. In this case, by keeping the surfactant concentration within the above range, it is possible to prevent a situation in which a low surfactant concentration results in poor wettability of the pre-electroplating solution to the pores on the groove surface, resulting in the electrode material not being filled or the pores not being filled sufficiently during electroplating. This also ensures that there are no gaps between the electrode and the doped semiconductor layer, ensuring a large contact area between the electrode and the doped semiconductor layer. Furthermore, it is also possible to prevent a situation in which a high surfactant concentration results in some surface-active molecules not being able to contact water, resulting in the surfactant not functioning at all. This improves surfactant utilization and reduces surfactant consumption.

[0228] Next, as shown in FIG. 14, an electrode 17 is formed in the opening, and the electrode 17 is electrically connected to the doped semiconductor layer 12.

[0229] In practical application, the electrode can be formed in the opening by a process such as electroplating or physical vapor deposition, and the electrode can be electrically connected to the doped semiconductor layer. The material of the electrode can be referred to above, and a detailed description thereof will be omitted here.

[0230] Here, when the electrode further includes a conductive contact layer, the conductive contact layer can be formed on at least a portion of the surface of the opening by a process such as deposition and etching, electroplating, chemical plating, screen printing, etc. The material and thickness of the conductive contact layer can be referred to above, and a detailed description thereof will be omitted here. 9-1 As shown in FIG. 1, the above means can be used to form a connection electrode 17-1 on the conductive contact layer 17-2.

[0231] For the beneficial effects of the method for fabricating a solar cell in the embodiment of the present invention, reference can be made to the analysis of the beneficial effects of various implementations of the solar cell above, and detailed description thereof will be omitted here.

[0232] The above description does not provide a detailed description of the technical details of each layer, such as the structure and etching of each layer. However, those skilled in the art should understand that layers, regions, etc. of desired shapes can be formed using various technical means. Furthermore, those skilled in the art can design methods that are not completely identical to the methods described above to form the same structure. Furthermore, although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used together.

[0233] The above describes the embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is limited by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all of these substitutions and modifications are intended to fall within the scope of the present disclosure. [Explanation of symbols]

[0234] 11 Semiconductor substrate 12 doped semiconductor layer 12-1 First doped semiconductor layer 12-2 Second doped semiconductor layer 13 Dielectric layer 14 Aperture 14-1 First opening 14-2 Second opening 15 holes 15-1 Hole 1 15-2 2nd hole 16 Annular protrusion 16-1 Annular protrusion of the first hole 16-2 Annular protrusion of second hole 17 electrodes 17A 1st electrode 17B 2nd electrode 17-1 Connecting electrode 17-2 Conductive Contact Layer 18 groove 19 Second passivation layer 20 First passivation layer 21 Non-continuous protrusions 22 Gap 23 Depression 24 Crack

Claims

1. a semiconductor substrate having opposing first and second surfaces; a doped semiconductor layer disposed on the first surface of the semiconductor substrate; a dielectric layer provided on the opposite side of the doped semiconductor layer from the semiconductor substrate, the dielectric layer including a plurality of openings exposing a partial region of the doped semiconductor layer, wherein a plurality of holes are formed on the opposite side of the semiconductor substrate from the portion of the doped semiconductor layer exposed in the opening; an electrode disposed on a side of the dielectric layer remote from the semiconductor substrate, the electrode being electrically connected to the doped semiconductor layer through an opening in the dielectric layer.

2. The solar cell according to claim 1 , wherein an annular protrusion is formed around the edge of the hole.

3. The width of the annular protrusion is greater than 0 μm and less than or equal to 0.3 μm, and / or The height of the annular protrusion is greater than 0 μm and less than or equal to 0.5 μm, and / or The solar cell according to claim 2 , wherein the ratio of the maximum radial dimension of the hole to the width of the annular protrusion is in the range of 60 or less.

4. the holes are approximately hemispherical holes; and / or the maximum radial dimension of the pores is nanoscale, or greater than 0 μm and less than or equal to 3 μm.

5. 2. The solar cell according to claim 1, wherein a groove is formed on a side of the doped semiconductor layer opposite the semiconductor substrate from the portion exposed in the opening, and the plurality of holes are formed on a surface of the groove away from the semiconductor substrate.

6. The solar cell of claim 1 , wherein the number of holes per unit area located in the middle region of the opening is greater than the number of holes per unit area located in the edge region of the opening.

7. The solar cell according to claim 6 , wherein the intermediate region occupies 70% to 80% of the area of ​​the opening.

8. The solar cell according to claim 1 , further comprising a plurality of discontinuous protrusions formed on the side of the doped semiconductor layer opposite to the semiconductor substrate from the portion exposed in the opening.

9. The doped semiconductor layer is a P-type doped semiconductor layer, and the number of discontinuous protrusions per unit area located at the edge region of the opening is greater than the number of discontinuous protrusions per unit area located at the middle region of the opening; or 9. The solar cell of claim 8, wherein the doped semiconductor layer is an N-type doped semiconductor layer, and the number of discontinuous protrusions per unit area located in a middle region of the opening is greater than the number of discontinuous protrusions per unit area located in an edge region of the opening.

10. 10. The solar cell according to claim 8, wherein the height of the discontinuous protrusions is greater than 0 μm and not more than 0.5 μm.

11. 2. The solar cell of claim 1, wherein a portion of the doped semiconductor layer opposite the semiconductor substrate from the portion exposed to the opening has a fifth surface roughness, and a portion of the doped semiconductor layer opposite the semiconductor substrate from the portion not exposed to the opening has a sixth surface roughness, the fifth surface roughness being greater than the sixth surface roughness.

12. the doped semiconductor layer includes a first doped semiconductor layer and a second doped semiconductor layer, the first doped semiconductor layer and the second doped semiconductor layer are alternately provided on the first surface of the semiconductor substrate, the first doped semiconductor layer is an N-type doped semiconductor layer, and the second doped semiconductor layer is a P-type doped semiconductor layer; 2. The solar cell of claim 1, wherein the plurality of openings includes a plurality of first openings and a plurality of second openings, the first openings exposing a partial region of the first doped semiconductor layer, the second openings exposing a partial region of the second doped semiconductor layer, the regions of the first doped semiconductor layer exposed in the first openings having a first surface roughness, and the regions of the second doped semiconductor layer exposed in the second openings having a second surface roughness, the first surface roughness and the second surface roughness being different.

13. a region of the first doped semiconductor layer covered by the dielectric layer having a third surface roughness, and a region of the second doped semiconductor layer covered by the dielectric layer having a fourth surface roughness; The solar cell of claim 12 , wherein the third surface roughness is less than the fourth surface roughness.

14. 13. The solar cell of claim 12, wherein a plurality of first holes are formed in a region of the first doped semiconductor layer exposed to the first opening, a plurality of second holes are formed in a region of the second doped semiconductor layer exposed to the second opening, an annular protrusion is formed around the edge of each of the first holes and the edge of each of the second holes, and the average height of the annular protrusion of each of the first holes is different from the average height of the annular protrusion of each of the second holes.

15. 13. The solar cell of claim 12, wherein a plurality of first holes are formed in the first doped semiconductor layer in a region exposed to the first opening, and a plurality of second holes are formed in the second doped semiconductor layer in a region exposed to the second opening, and the number of second holes per unit area located in intermediate regions of the second openings is greater than the number of first holes per unit area located in intermediate regions of the first openings.

16. 13. The solar cell of claim 12, wherein a plurality of first holes are formed in the first doped semiconductor layer in a region exposed to the first opening, and a plurality of second holes are formed in the second doped semiconductor layer in a region exposed to the second opening, and an average maximum radial dimension of the holes located in intermediate regions of the second openings is greater than an average maximum radial dimension of the holes located in intermediate regions of the first openings.

17. The solar cell according to claim 1 , wherein the doped semiconductor layer located in the opening has a doping concentration on a side away from the semiconductor substrate that is greater than a doping concentration on a side closer to the semiconductor substrate.

18. the first doped semiconductor layer located in the first opening has a first difference between a doping concentration on a side away from the semiconductor substrate and a doping concentration on a side close to the semiconductor substrate; the second doped semiconductor layer located in the second opening has a second difference between a doping concentration on a side away from the semiconductor substrate and a doping concentration on a side close to the semiconductor substrate; The solar cell of claim 12 , wherein the first difference is greater than the second difference.

19. a plurality of discontinuous protrusions are formed on a side of the first doped semiconductor layer opposite to the semiconductor substrate in a portion exposed in the first opening, and a plurality of discontinuous protrusions are formed on a side of the second doped semiconductor layer opposite to the semiconductor substrate in a portion exposed in the second opening, the number of discontinuous protrusions per unit area of ​​the edge region of the first opening is less than the number of discontinuous protrusions per unit area of ​​the edge region of the second opening; And / or the number of discontinuous protrusions per unit area in the intermediate region of the first opening is greater than the number of discontinuous protrusions per unit area in the intermediate region of the second opening.

20. 2. The solar cell of claim 1, wherein the doped semiconductor layer includes a doped polycrystalline silicon layer, and the doped semiconductor layer further includes amorphous silicon provided on the side of the doped polycrystalline silicon layer opposite the semiconductor substrate from the portion exposed in the opening.

21. 2. The solar cell of claim 1, wherein the doped semiconductor layer comprises a doped polycrystalline silicon layer, the doped semiconductor layer further comprising amorphous silicon located at an edge of the opening in the dielectric layer, located below the dielectric layer, and on an opposite side of the doped polycrystalline silicon layer from the semiconductor substrate.

22. The solar cell of claim 1 , wherein a gap is formed between the dielectric layer and the underlying doped semiconductor layer at the edge of the opening in the dielectric layer.

23. the doped semiconductor layer includes a doped polycrystalline silicon layer, the doped semiconductor layer further includes amorphous silicon located at an edge of the opening in the dielectric layer, located below the dielectric layer, and on an opposite side of the doped polycrystalline silicon layer from the semiconductor substrate; 23. The solar cell of claim 22, wherein a distribution length of the amorphous silicon below the dielectric layer in a direction parallel to the semiconductor substrate layer from an edge of the opening in the dielectric layer is greater than a distribution length of the gap.

24. 23. The solar cell of claim 22, wherein the gap contains at least one of the metallic materials in the electrode.

25. 24. The solar cell of claim 1 or claim 23, wherein a portion of the dielectric layer adjacent the opening is bowed away from the doped semiconductor layer.

26. The solar cell according to claim 1 , wherein a recess is formed in an edge region of the opening.

27. 27. The solar cell of claim 26, wherein the doped semiconductor layer is an N-type doped semiconductor layer, and the recesses are distributed in the edge region of the opening in the N-type doped semiconductor layer.

28. The solar cell of claim 1 , wherein the dielectric layer has cracks formed at the edges adjacent to the openings.

29. The solar cell according to claim 1 , wherein silicon oxide is formed on the side of the doped semiconductor layer opposite to the semiconductor substrate in the portion exposed in the opening.

30. 2. The solar cell of claim 1, wherein the dielectric layer comprises aluminum oxide, and the doped semiconductor layer comprises aluminum on the side opposite the semiconductor substrate from the portion exposed in the opening.

31. The solar cell of claim 1 , wherein the portion of the doped semiconductor layer exposed in the opening has a through hole penetrating the doped semiconductor layer.

32. a plurality of battery strings including a plurality of solar cells and a plurality of connection members for connecting the plurality of solar cells in series; A solar module, wherein the solar cell is a solar cell according to any one of claims 1 to 31.

33. providing a semiconductor substrate having opposing first and second surfaces; forming a doped semiconductor layer on the first surface and / or the second surface; forming a dielectric layer on the doped semiconductor layer opposite the semiconductor substrate; forming an opening through the dielectric layer to expose at least a portion of the doped semiconductor layer, and forming a plurality of holes on a side of the doped semiconductor layer opposite the semiconductor substrate from the exposed portion of the opening; forming an electrode in the opening and electrically connecting the electrode to the doped semiconductor layer.

34. 34. The method of claim 33, wherein the opening is formed by a laser etching process.

35. 35. The method for manufacturing a solar cell according to claim 33 or claim 34, wherein a plurality of holes are formed on a side of the doped semiconductor layer opposite to the semiconductor substrate in the portion exposed in the opening by a laser etching process and / or a wet etching process, and an etchant for the wet etching process contains ammonium hydrogen fluoride and / or ammonium fluoride.

36. the etching solution contains an additive, the additive including at least one of 3-ethylbutoxypropylamine, phenylacetic acid, sodium benzoate, and sodium acetate; and / or The etching solution contains a surfactant, and the surfactant includes at least one of perfluorotriethylamine, perfluorohexylsulfonamide, and perfluorohexylsulfuryl fluoride; and / or In the etching solution, the concentration of fluorine ions is 2 g / L or more and 13 g / L or less, and / or The etching time corresponding to the wet etching process is between 10 seconds and 60 seconds, and / or The method for manufacturing a solar cell according to claim 35, wherein a process temperature corresponding to the wet etching process is 15°C or more and 30°C or less.

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