Power Semiconductor Package

Abstract

A power semiconductor package is provided. In one example, the power semiconductor package may include a power semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposite the first side. The power semiconductor package may include one or more electrical leads extending from the first side. The power semiconductor package may include one or more leadless surface mount (SMT) connection structures on the second side.

Description

Detailed Description of the Invention

[0001] [Priority Claim] This application is based on and claims the benefit of priority to U.S. Patent Application No. 18 / 179,036, filed March 6, 2023. This application claims priority to and the benefit of the cited applications, the contents of which are incorporated by reference in their entireties.

[0002] [Field] The present disclosure relates generally to semiconductor packages.

[0003] [background] Semiconductor devices such as transistors and diodes are ubiquitous in modern electronic devices. Wide bandgap semiconductor material systems such as gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC) are increasingly utilized in semiconductor devices to push the limits of device performance in areas such as switching speed, power handling capability, and thermal conductivity. Exemplary power semiconductor devices may include metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), Schottky barrier diodes, PiN diodes, thyristors, and high-electron-mobility transistors (HEMTs). Packaging technology can play a major role in the performance of power semiconductor devices.

[0004] [overview] Aspects and advantages of embodiments of the present disclosure will be set forth in part in the description that follows, or may be learned from the description, or may be learned through practice of the embodiments.

[0005] One exemplary aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package may include a power semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposite the first side. The power semiconductor package may include one or more electrical leads extending from the first side. The power semiconductor package may include one or more leadless surface mount (SMT) connection structures on the second side.

[0006] Another exemplary aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package may include a semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposite the first side. The power semiconductor package may include one or more electrical leads extending from the first side. The power semiconductor package may include one or more SMT connection structures on the second side. Each of the one or more SMT connection structures may have a connection surface area greater than a connection surface area of ​​the one or more electrical leads.

[0007] Another exemplary aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package may include a semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposite the first side. The housing has a first surface extending between the first side and the second side and a second surface opposite the first surface. The power semiconductor package may include a thermal pad. The power semiconductor package may include a staircase structure on the first surface of the housing. The staircase structure may be defined in the housing such that a first portion of the housing at the first side has a first thickness and a second portion of the housing at the thermal pad has a second thickness. The second thickness may be greater than the first thickness.

[0008] Another exemplary aspect of the present disclosure is directed to a method. The method may include providing a first power semiconductor package. The first power semiconductor package may include a first housing having a first side and a second side opposite the first side. The first power semiconductor package may include one or more first electrical leads extending from the first side and one or more first leadless surface mount (SMT) connection structures on the second side. The method may include providing a second power semiconductor package. The second power semiconductor package may include a second housing having a third side and a fourth side opposite the third side. The second power semiconductor package may include one or more second electrical leads extending from the third side and one or more second leadless SMT connection structures on the fourth side. The second side of the first power semiconductor package may be aligned with the fourth side of the second power semiconductor package.

[0009] Another exemplary aspect of the present disclosure is directed to a power semiconductor assembly. The power semiconductor assembly may include a first power semiconductor package. The first power semiconductor package may include a first housing having a first side and a second side opposite the first side. The first power semiconductor package may include one or more first electrical leads extending from the first side and one or more first leadless surface mount (SMT) connection structures on the second side. The power semiconductor package assembly may include a second power semiconductor package. The second power semiconductor package may include a second housing having a third side and a fourth side opposite the third side. The second power semiconductor package may include one or more second electrical leads extending from the third side and one or more second leadless SMT connection structures on the fourth side. The second side of the first power semiconductor package may be aligned with the fourth side of the second power semiconductor package.

[0010] These and other features, aspects, and advantages of various embodiments will become better understood with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the detailed description, explain associated principles.

[0011] A detailed discussion of embodiments directed to those skilled in the art is set forth herein, which refers to the accompanying drawings. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a top perspective view of a semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 2] FIG. 2 is a bottom perspective view of a semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 3] 1 is a bottom perspective view of a semiconductor package in which a portion of the semiconductor package is transparent, according to an exemplary embodiment of the present disclosure. FIG. [Figure 4] FIG. 1 is a top perspective view of a semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 5] FIG. 2 is a bottom perspective view of a semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 6] 1 is a side view of a semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 7] 1 is a bottom perspective view of a semiconductor package in which a portion of the semiconductor package is transparent, according to an exemplary embodiment of the present disclosure. FIG. [Figure 8] FIG. 1 is a top perspective view of a semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 9] FIG. 1 is a top perspective view of a semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 10] FIG. 1 is a top perspective view of a semiconductor package according to an exemplary embodiment of the present disclosure. [Figure 11] 1 is a top perspective view of a semiconductor package in which a portion of the semiconductor package is transparent, according to an exemplary embodiment of the present disclosure. FIG. [Figure 12] FIG. 1 is a top perspective view of an exemplary semiconductor package assembly according to an exemplary embodiment of the present disclosure. [Figure 13] FIG. 2 is a bottom perspective view of an exemplary semiconductor package assembly according to an exemplary embodiment of the present disclosure. [Figure 14] 1 is a flowchart of an exemplary method according to an exemplary embodiment of the present disclosure. [Figure 15] 1A-1C illustrate an exemplary separation of an exemplary semiconductor package assembly according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] [Detailed explanation] Reference will now be made in detail to the embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation of an embodiment, not as a limitation of the disclosure. Indeed, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments without departing from the scope or spirit of the disclosure. For example, features illustrated or described as part of one embodiment may be used with another embodiment to yield still a further embodiment. Accordingly, it is intended that aspects of the disclosure encompass such modifications and variations.

[0014] Discrete semiconductor packages containing semiconductor dies, such as MOSFETs or Schottky diodes, have been developed. Such semiconductor packages with MOSFETs can be utilized in a variety of applications to enable higher switching frequencies with associated reduced losses, higher blocking voltages, and improved avalanche capabilities. Exemplary applications can include high-performance industrial power supplies, server / telecom power supplies, electric vehicle charging systems, energy storage systems, uninterruptible power supplies, high-voltage DC / DC converters, electric vehicles, and battery management systems. Discrete semiconductor packages with Schottky diodes can be utilized in many of the same high-performance power supply applications described above for MOSFETs, and in some cases in systems that also include MOSFET discrete power packages.

[0015] Packaging technology for semiconductor devices plays an important role in determining the performance of the semiconductor device. For example, the packaging of a power semiconductor die can constrain the semiconductor die's ability to dissipate heat, conduct current, or even switch at a particular speed (e.g., due to parasitic inductance). Ineffective heat dissipation can create problems for semiconductor devices (e.g., small form factor semiconductor devices) or in situations where the semiconductor device is in close contact with a housing. Excessive heat can adversely affect the operation of the semiconductor device itself, as well as the operation of an electronic system that uses the semiconductor device.

[0016] Exemplary aspects of the present disclosure are directed to a semiconductor package incorporating surface mount technology (SMT) construction. The semiconductor package may offer increased flexibility and various pinout options for electrical leads. In some embodiments, the semiconductor package may include a thermal pad for topside cooling, which may enable direct bonding to a heat sink (e.g., with an electrical insulator) to improve thermal performance. The semiconductor package may offer increased current and voltage handling capabilities compared to other semiconductor packages with smaller form factors.

[0017] In some embodiments, the power semiconductor package may include a semiconductor die. The semiconductor die may be based on a wide bandgap semiconductor material. The wide bandgap semiconductor has a bandgap greater than about 1.40 eV, such as silicon carbide and / or a Group III nitride (e.g., gallium nitride). In some examples, the semiconductor die may include a semiconductor device such as a transistor, a diode, and / or a thyristor. For example, in some examples, the power semiconductor die may include a silicon carbide-based MOSFET located between source and drain contacts, e.g., to form a vertically structured power semiconductor device.

[0018] Aspects of the present disclosure are discussed with reference to silicon carbide-based MOSFET devices for purposes of illustration and discussion. Those skilled in the art will understand, using the disclosure provided herein, that the power semiconductor die may include other power semiconductor devices, such as diodes (e.g., Schottky diodes, PiN diodes, etc.), insulated gate bipolar transistors, high electron mobility transistors, or other devices, without departing from the scope of the present disclosure.

[0019] In some examples, a power semiconductor package may include a housing having a first side and a second side opposite the first side. The power semiconductor package may include one or more electrical leads extending from the first side. The power semiconductor package may include one or more surface mount type (SMT) connection structures on the second side. The SMT connection structures may have a size larger than the one or more electrical leads. For example, the SMT connection structures may have a larger connection surface area than each of the one or more electrical leads. More specifically, the SMT connection structures may each have a connection surface area larger than the connection surface area of ​​each of the one or more electrical leads, e.g., at least two times larger, e.g., at least 2.5 times larger, e.g., at least three times larger.

[0020] In some examples, due to the smaller size of the electrical leads compared to the SMT connection structures, the first side may have a larger number of electrical leads compared to the number of SMT connection structures on the second side. For example, in some examples, a power semiconductor package may have two SMT connection structures on the second side and two to fourteen electrical leads on the first side. In this way, the power semiconductor package may accommodate high power ratings (e.g., high voltage ratings) through the use of SMT connection structures with large connection surface areas, while allowing flexibility in providing other connections (e.g., gate, source, Kelvin, sensor) through smaller electrical leads.

[0021] In some examples, one or more SMT connection structures may be leadless SMT connection structures. For example, the SMT connection structures may be wettable flank connection structures. In these examples, the SMT connection structures may be partially encapsulated in the housing such that connection surfaces of the wettable flank connection structures are exposed through the mounting surface of the housing. The wettable flank connection structures may also be exposed through at least one side surface of the housing. This may facilitate connection of the power semiconductor package to another structure (e.g., a circuit board) and may facilitate efficient design of a lead frame (e.g., a conductive lead frame) for the power semiconductor package.

[0022] In some examples, the one or more SMT connection structures may be SMT connection tabs. The one or more SMT connection tabs may extend from the second side of the housing. The one or more SMT connection tabs may extend from the second side of the housing at a position below a top surface of the housing (e.g., the surface opposite the mounting surface).

[0023] In some examples, the power semiconductor package may include a thermal pad. The thermal pad may provide cooling (e.g., top-side cooling) for the semiconductor package. In some examples, the power semiconductor package may include a creepage extension structure between the thermal pad and a first side of the power semiconductor package. The creepage extension structure may increase the current and voltage handling capability of the power semiconductor package. More specifically, the creepage extension structure may increase voltage isolation between one or more electrical leads on the first side of the housing and an SMT connection structure on the second side of the housing. The creepage extension structure may substantially increase a surface distance (e.g., a creepage distance) along the housing of the power semiconductor package between one or more electrical leads on the first side of the housing and an SMT connection structure on the second side of the housing.

[0024] In some examples, the creepage distance extension structure may include a stepped structure between one or more electrical leads and the thermal pad. Alternatively or additionally, the creepage distance extension structure may include a stepped structure between the thermal pad and one or more SMT connection structures. The stepped structure may have a depth of about 0.5 mm to about 2.0 mm.

[0025] In some examples, the creepage distance extension structure may include one or more grooves defined in the housing. The one or more grooves may be defined between the step structure and one or more electrical leads extending from the first side of the housing. The one or more grooves may extend at least partially along the periphery of the housing on the first side of the housing. The one or more grooves may have a depth of about 0.5 mm to about 2.0 mm and a length of about 5 mm to about 10 mm. The creepage distance extension structure may provide a creepage distance of about 5 mm to about 20 mm between the one or more electrical leads and the SMT connection structure.

[0026] In some embodiments, the power semiconductor package may provide electrical isolation between the thermal pad and one or more SMT connection structures. For example, the thermal pad may be on a first side of an insulating layer of a mounting substrate of the semiconductor die. The SMT connection structure and / or a conductive lead frame coupled to the SMT connection structure may be coupled to one or more conductive pads on a second side of the insulating layer of the mounting substrate such that an insulating layer is provided between the SMT connection structure and the thermal pad. In some examples, the mounting substrate may be, for example, a direct bonded copper (DBC) substrate or an active metal brazed (AMB) structure.

[0027] Aspects of the present disclosure provide several technical effects and benefits. For example, the power semiconductor package may provide efficient heat dissipation through the thermal pad. The power semiconductor package may provide multiple pin options for electrical leads extending from the power semiconductor package, making the power semiconductor package suitable for use with multiple device groups. The power semiconductor package may have a high voltage rating and / or a high current rating due to the use of large SMT connection structures (e.g., for source and / or drain connections) and due to, for example, creepage extension structures. The power semiconductor package may provide a small form factor. The power semiconductor package may provide electrical isolation between the thermal pad and the SMT connection structures (e.g., drain connection).

[0028] Terms such as first, second, and third may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be termed a second element, and similarly, a second element may be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning consistent with their meaning in the context of the present specification and related art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0031] When an element, such as a layer, region, or substrate, is referred to as being "in contact with" or extending "in contact with" another element, it will be understood that it may be in direct contact with or extending into direct contact with the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "in direct contact with" or extending "in direct contact with" another element, no intervening elements are present, except for adhesive materials in some instances (e.g., die attach materials, solder, pastes, adhesives, sintered materials, or other materials). When an element is referred to as being "connected" or "coupled" to another element, it will also be understood that it may be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening elements are present, except for adhesive materials in some instances (e.g., die attach materials, solder, pastes, adhesives, sintered materials, or other materials).

[0032] Relative terms such as "below" or "up" or "above" or "below" or "horizontal" or "lateral" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0033] Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments of the present disclosure. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or errors, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. Similarly, it will be understood that variations in dimensions are to be expected based on standard deviations in manufacturing procedures. As used herein, "generally" or "about" includes values ​​within 10% of the nominal value.

[0034] Like numbers refer to like elements throughout. Thus, the same or similar numbers may be described with reference to other drawings even if they are not mentioned or described in the corresponding drawing. Elements not designated by a reference number may also be described with reference to other drawings.

[0035] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions characterized as having a conductivity type, such as n-type or p-type, where conductivity type refers to the concentration of majority carriers in the layer and / or region. Thus, an N-type material has a majority equilibrium concentration of negatively charged electrons, and a P-type material has a majority equilibrium concentration of positively charged holes. Some materials may be designated with a "+" or "-" (such as N+, N-, P+, P-, N++, N--, P++, P--, etc.) to indicate a relatively high ("+") or low ("-") concentration of majority carriers compared to another layer or region. However, such designations do not imply the presence of a particular concentration of majority or minority carriers in the layer or region.

[0036] Aspects of the present disclosure are discussed with reference to silicon carbide-based semiconductor structures, such as silicon carbide-based MOSFETs. Using the disclosure provided herein, those skilled in the art will understand that power semiconductor packages according to exemplary embodiments of the present disclosure can be used with any semiconductor material, such as other wide bandgap semiconductor materials, without departing from the scope of the present disclosure. Exemplary wide bandgap semiconductor materials include silicon carbide (e.g., alpha silicon carbide has a bandgap of 2.996 eV at room temperature) and Group III nitrides (e.g., gallium nitride has a bandgap of 3.36 eV at room temperature).

[0037] In the drawings and specification, exemplary embodiments are disclosed and specific terms are employed, but they are used in a generic and descriptive sense only and not for the purpose of limiting the scope as set forth in the following claims.

[0038] FIG. 1 illustrates a top perspective view of an exemplary semiconductor package 100 in accordance with an exemplary embodiment of the present disclosure. FIG. 2 illustrates a bottom perspective view of the exemplary semiconductor package 100. With reference to FIGS. 1 and 2, the semiconductor package 100 includes a housing 102. The semiconductor package 100 may be arranged to house and provide external electrical connections to a semiconductor die located within the housing 102, such as a semiconductor die having a MOSFET or a Schottky diode.

[0039] The housing 102 may include a first side 102′ and an opposite second side 102″. The housing 102 may include a first surface 102A (e.g., a top surface) extending between the first side 102′ and the second side 102″. The housing 102 may include a second surface 102B (e.g., a bottom surface or mounting surface) extending between the first side 102′ and the second side 102″. The housing 102 may also include side surfaces 102C, 102D, 102E, and 102F. The side surface 102C may be located on the first side 102C′. The side surface 102D may be located on the second side 102″. The housing 102 may include different arrangements of surfaces without departing from the scope of the present disclosure. For example, one or more notches or recesses may be formed in any of the surfaces 102A-102F without departing from the scope of the present disclosure.

[0040] The power semiconductor package 100 may be arranged as a surface mount technology (SMT) package with a first side 102A (e.g., a top side) opposite an external surface, such as a printed circuit board (PCB), on which the power semiconductor package 100 is mounted. A second side 102B (e.g., a bottom or mounting side) forms the mounting side of the power semiconductor package 100 that is mounted to the external surface, such as a PCB.

[0041] The housing 102 may be formed by a molding process. The housing 102 may include a material capable of high temperature operation, such as at a temperature of about 200° C. An exemplary material for the housing 102 may include an epoxy material or an epoxy mold compound (EMC).

[0042] The power semiconductor package 100 includes one or more electrical leads 110 extending from a first side 102′ of the housing 102. The electrical leads 110 may be SMT connection structures having connection surfaces 112. The connection surfaces 112 of the electrical leads 110 may be used to connect internal components of the power semiconductor package 100 to external electrical connections. The electrical leads 110 have the form of electrical connection pins.

[0043] The power semiconductor package 100 includes a leadless SMT connection structure 120 on a second side 102'' of the housing 102. The leadless SMT connection structure 120 has a connection surface 122. The surface area of ​​the connection surface 122 of the leadless SMT connection structure 120 may be larger than the surface area of ​​the connection surface 112 of the electrical lead 110 (e.g., an electrical connection pin), e.g., about two times larger, e.g., about 2.5 times larger, e.g., about three times larger.

[0044] 1 and 2 , the leadless SMT connection structures 120 are wettable flank connection structures. More specifically, the leadless SMT connection structures 120 are partially enclosed by the housing 102 such that connection surfaces 122 of the leadless SMT connection structures 120 are exposed through the second face 102B (e.g., mounting face) of the power semiconductor package 100. In some examples, the connection surface 122 of each leadless SMT connection structure 120 is flush with the second face 102B (e.g., mounting face). In some examples, a portion 124 of each leadless SMT connection structure 120 is exposed through a side face 102D, 102E, or a side face 102D, 102F of the housing 102.

[0045] As shown, the number of electrical leads 110 extending from the first side 102′ of the housing 102 may be greater than the number of leadless SMT connection structures 120 on the second side 102″ of the housing 102. For example, the power semiconductor package 100 includes seven electrical leads 110 and two leadless SMT connection structures 120. More or fewer electrical leads 110 may be included in the power semiconductor package 100 without departing from the scope of the present disclosure. More or fewer leadless SMT connection structures 120 may be included in the power semiconductor package 100 without departing from the scope of the present disclosure.

[0046] 1 and 2 , the first surface 102A (e.g., the top surface) of the housing 102 may include a thermal pad 130. The thermal pad 130 may include a thermally conductive material such as a metal. The thermal pad 130 may be coupled to an external heat sink (e.g., an electrical insulator) to provide top-side cooling for the power semiconductor package 100.

[0047] The first surface 102A of the housing 102 may also include creepage distance extension structures 140.1 and 140.2. The creepage distance extension structures 140.1 and 140.2 may increase the creepage distance between the electrical leads 110 and the leadless SMT connection structure 120. In the example of FIGS. 1 and 2, the creepage distance extension structure 140.1 includes a first step structure 142.1 between the thermal pad 130 and the electrical leads 110 extending from the first side 102′ of the housing 102. The first step structure 142.1 may be defined such that the housing 102 has a first thickness T1 at the first side 102′ of the housing 102 and a second thickness T2 at the thermal pad 130. The second thickness T2 is greater than the first thickness T1. For example, the staircase structure may have a depth ranging from about 0.5 mm to about 2.0 mm such that T2 exceeds T1 by about 0.5 mm to about 2.0 mm.

[0048] The creepage distance extension structure 140.2 includes a second staircase structure 142.2 between the thermal pad 130 and the leadless SMT connection structure 120 on the second side 102″ of the housing 102. The second staircase structure 142.2 can be defined such that the housing 102 has a third thickness T3 at the second side 102″ of the housing 102 and a second thickness T2 at the thermal pad 130. The second thickness T2 is greater than the third thickness T3. For example, the second staircase structure can have a depth ranging from about 0.1 mm to about 2.5 mm such that T2 exceeds T3 by about 0.1 mm to about 2.5 mm. The third thickness T3 can be the same as or different from the first thickness T1. The second staircase structure 142.2 can have a depth that is the same as or different from the depth of the first staircase structure 142.1.

[0049] The housing 102 of the power semiconductor package 100 may have other creepage distance extension features without departing from the scope of the present disclosure. For example, the first creepage distance extension structure 140.1 may include a groove 144 defined along the periphery of the housing 102 on the first side 102' of the housing 102 between the electrical leads 110 and the thermal pad 130. The groove 144 may have a depth ranging from 0.5 mm to approximately 2.0 mm, for example. The total creepage distance between the electrical leads 110 and the leadless SMT connection structure 120 may be in the range of approximately 5 mm to approximately 20 mm, for example.

[0050] 3 shows a bottom perspective view of a power semiconductor package 100 in which the housing 102 is transparent, according to an exemplary embodiment of the present disclosure. As shown, a semiconductor die 160 may be mounted to a mounting substrate 150 (e.g., a conductive lead frame) for the power semiconductor package. The mounting substrate 150 may be coupled to or integral with the thermal pad 130. The semiconductor die 160 may be attached to the mounting substrate 150 using, for example, a die attach material.

[0051] The semiconductor die 160 may include one or more semiconductor devices, such as a MOSFET device, a Schottky diode, or other devices. In some examples, the semiconductor die 160 may be based on a wide bandgap semiconductor, such as silicon carbide and / or a Group III nitride (e.g., gallium nitride). For example, in some examples, the power semiconductor die 160 may include a silicon carbide-based MOSFET located between source and drain contacts, e.g., to form a vertically structured power semiconductor device. Aspects of the present disclosure are discussed with respect to a silicon carbide-based MOSFET device for purposes of illustration and discussion. Those skilled in the art will understand, using the disclosure provided herein, that the power semiconductor die may include other semiconductor devices, such as a diode (e.g., a Schottky diode, a PiN diode, etc.), an insulated gate bipolar transistor, a high electron mobility transistor, or other devices, without departing from the scope of the present disclosure.

[0052] Semiconductor die 160 may be, for example, a 7 mm by 7 mm semiconductor die, however, aspects of the present disclosure are applicable to many different semiconductor die sizes, such as 1 mm by 1 mm semiconductor die to 7 mm by 9 mm semiconductor die, as some examples.

[0053] In the example of a semiconductor die 160 including a silicon carbide-based MOSFET device, the electrical leads 110 may include a first lead 110.1, a second lead 110.2, and a third lead 110.3. The first lead 110.1 may include a plurality of integral electrical connection pins. The first lead 110.1 may be coupled to a source of a MOSFET device on the semiconductor die 160 using, for example, a wire bond 172. The first lead 110.1 may be used to connect the source of the MOSFET device on the semiconductor die 160 to one or more external connections (e.g., on a PCB).

[0054] Second lead 110.2 may include an electrical connection pin (e.g., a single electrical connection pin). Second lead 110.2 may be coupled to the gate of a MOSFET device on semiconductor die 160, for example, using wirebond 174. Second lead 110.2 may be used to connect the gate of the MOSFET device on semiconductor die 160 to one or more external connections (e.g., on a PCB).

[0055] Third lead 110.3 may include an electrical connection pin (e.g., a single electrical connection pin). Third lead 110.3 may be coupled to another contact associated with a MOSFET device on semiconductor die 160, such as a source Kelvin contact and / or a sensor contact. Third lead 110.3 may be coupled to a gate of a MOSFET device on semiconductor die 160, for example, using wirebond 176. Third lead 110.3 may be used to connect contacts associated with a MOSFET device on semiconductor die 160 to one or more external connections (e.g., on a PCB).

[0056] SMT connection structure 120 may be connected to a drain of a MOSFET device on semiconductor die 160. More specifically, the drain of the MOSFET device may be electrically coupled to mounting substrate 150 (e.g., through a die attach material). SMT connection structure 120 may be electrically coupled to mounting substrate 150. For example, SMT connection structure 120 may be electrically coupled to mounting substrate 150 through connection elbow 126. In some embodiments, connection elbow 126 and / or SMT connection structure 120 may be integral with mounting substrate 150.

[0057] As discussed above, power semiconductor package 100 may include semiconductor die 160 with other types of semiconductor devices without departing from the scope of this disclosure. For example, in some examples, semiconductor die 160 may include a Schottky diode. In this example, one or more of electrical leads 110 may be coupled to a first contact of the Schottky diode on semiconductor die 160, for example, using a wire bond. SMT connection structure 120 may be connected to a second contact of the Schottky diode, for example, through mounting substrate 150 (e.g., through connection elbow 126 and mounting substrate 150).

[0058] Figure 4 is a top perspective view of an exemplary semiconductor package 200 in accordance with an exemplary embodiment of the present disclosure. Figure 5 is a bottom perspective view of the exemplary semiconductor package 200. With reference to Figures 4 and 5, the semiconductor package 200 includes a housing 202. The semiconductor package 200 may be arranged to house and provide external electrical connections to a semiconductor die located within the housing 202, such as a semiconductor die having a MOSFET or a Schottky diode.

[0059] The housing 202 may include a first side 202′ and an opposite second side 202″. The housing 202 may include a first surface 202A (e.g., a top surface) extending between the first side 202′ and the second side 202″. The housing 202 may include a second surface 202B (e.g., a bottom surface or mounting surface) extending between the first side 202′ and the second side 202″. The housing 202 may also include side surfaces 202C, 202D, 202E, and 202F. The side surface 202C may be located on the first side 202′. The side surface 202D may be located on the second side 202″. The housing 202 may include different arrangements of surfaces without departing from the scope of the present disclosure. For example, one or more notches or recesses may be formed in any of the surfaces 202A-202F without departing from the scope of the present disclosure.

[0060] The power semiconductor package 200 may be arranged as a surface mount technology (SMT) package with a first side 202A (e.g., a top side) opposite an external surface, such as a printed circuit board (PCB), on which the power semiconductor package 200 is mounted. A second side 202B (e.g., a bottom or mounting side) forms the mounting side of the power semiconductor package 200 that is mounted to the external surface, such as a PCB.

[0061] The housing 202 may be formed by a molding process. The housing 202 may include a material capable of high temperature operation, such as at a temperature of about 200° C. An exemplary material for the housing 202 may include an epoxy material or epoxy molding compound (EMC).

[0062] The power semiconductor package 200 includes one or more electrical leads 210 extending from a first side 202′ of the housing 202. The electrical leads 210 may be SMT connection structures having connection surfaces 212. The connection surfaces 212 of the electrical leads 210 may be used to connect internal components of the power semiconductor package 200 to external electrical connections. The electrical leads 210 have the form of electrical connection pins.

[0063] The power semiconductor package 200 includes an SMT connection structure 220 on the second side 102'' of the housing 102. The SMT connection structure 220 has a connection surface 222. The surface area of ​​the connection surface 222 of the SMT connection structure 220 may be larger than the surface area of ​​the connection surface 212 of the electrical lead 210 (e.g., an electrical connection pin), e.g., about 2 times larger, e.g., about 2.5 times larger, e.g., about 3 times larger.

[0064] 3 and 4, the SMT connection structures 220 are SMT connection tabs 220. The SMT connection tabs 220 extend from the second side 202'' of the housing 202 (e.g., extend from the side surface 202). The SMT connection tabs 220 each include a connection surface 222 and a connection elbow 226. The connection elbow 226 may be integral with the connection surface 222. The housing 202 does not enclose at least a portion of the connection elbow 226 such that the connection elbow 226 is exposed.

[0065] In some examples, the SMT connection tabs 220 extend from the second side 202" of the housing 202 at a location below the top surface 202A of the housing 202. For example, FIG. 6 illustrates a side view of an exemplary power semiconductor package 200 in accordance with an exemplary embodiment of the present disclosure. As shown, the SMT connection tabs 220 extend from a side surface 202D on the second side 202" of the housing 202 at a location below the top surface 202A of the housing 202, such as a depth D1 below the top surface 202A of the housing 202. The depth D1 may be in the range of 0.5 mm to approximately 2.0 mm, for example. In some examples, the connection surface 222 of each of the SMT connection tabs 220 may be flush with the bottom surface 202B of the housing 202 of the power semiconductor package 200.

[0066] 4 and 5 , the number of electrical leads 210 extending from the first side 202′ of the housing 202 may be greater than the number of SMT connection structures 220 extending from the second side 202″ of the housing 202. For example, the power semiconductor package 200 includes seven electrical leads 210 and two SMT connection structures 220. More or fewer electrical leads 210 may be included in the power semiconductor package 200 without departing from the scope of the present disclosure. More or fewer SMT connection structures 220 may be included in the power semiconductor package 200 without departing from the scope of the present disclosure.

[0067] 4 and 5, the first surface 202A (e.g., the top surface) of the housing 202 may include a thermal pad 230. The thermal pad 230 may include a thermally conductive material such as a metal. The thermal pad 230 may be coupled to an external heat sink (e.g., with an electrical insulator) to provide top-side cooling for the power semiconductor package 300.

[0068] The first surface 202A of the housing 202 may also include a creepage distance extension structure 240. The creepage distance extension structure 240 may increase the creepage distance between the electrical leads 210 and the SMT connection structure 220. In the example of FIGS. 4 and 5 , the creepage distance extension structure 240 includes a step structure 242 between the thermal pad 230 and the electrical leads 210 extending from the first side 202′ of the housing 202. The step structure 242 may be defined such that the housing 202 has a first thickness T1 at the first side 202′ of the housing 202 and a second thickness T2 at the second side 202″ of the housing 202. The second thickness T2 is greater than the first thickness T1. For example, the step structure may have a depth ranging from approximately 0.5 mm to approximately 2.0 mm such that T2 exceeds T1 by approximately 0.5 mm to approximately 2.0 mm. The housing 202 of the power semiconductor package 200 may have other creepage distance enhancing features without departing from the scope of this disclosure.

[0069] 7 illustrates a bottom perspective view of a power semiconductor package 200 in which the housing 202 is transparent, according to an exemplary embodiment of the present disclosure. As shown, a semiconductor die 260 may be mounted to a mounting substrate 250 (e.g., a conductive lead frame) for the power semiconductor package. The mounting substrate 250 may be bonded to or integral with the thermal pad 230. The semiconductor die 260 may be attached to the mounting substrate 250 using, for example, a die attach material.

[0070] The semiconductor die 260 may include one or more semiconductor devices, such as a MOSFET device, a Schottky diode, or other devices. In some examples, the semiconductor die 260 may be based on a wide bandgap semiconductor, such as silicon carbide and / or a Group III nitride (e.g., gallium nitride). For example, in some examples, the power semiconductor die 260 may include a silicon carbide-based MOSFET located between source and drain contacts, e.g., to form a vertically structured power semiconductor device. Aspects of the present disclosure are discussed with respect to a silicon carbide-based MOSFET for purposes of illustration and discussion. Those skilled in the art will understand, using the disclosure provided herein, that the power semiconductor die may include other power semiconductor devices, such as a diode (e.g., a Schottky diode, a PiN diode, etc.), an insulated gate bipolar transistor, a high electron mobility transistor, or other devices, without departing from the scope of the present disclosure.

[0071] Semiconductor die 260 may be, for example, a 7 mm by 7 mm semiconductor die, however, aspects of the present disclosure are applicable to many different semiconductor die sizes, such as 1 mm by 1 mm semiconductor die to 7 mm by 9 mm semiconductor die, as some examples.

[0072] In the example of a semiconductor die 260 including a silicon carbide-based MOSFET device, the electrical leads 210 may include a first lead 210.1, a second lead 210.2, and a third lead 210.3. The first lead 210.1 may include a plurality of integral electrical connection pins. The first lead 210.1 may be coupled to the source of the MOSFET device on the semiconductor die 260 using, for example, a wire bond 272. The first lead 210.1 may be used to connect the source of the MOSFET device on the semiconductor die 260 to one or more external connections (e.g., on a PCB).

[0073] The second lead 210.2 may include an electrical connection pin (e.g., a single electrical connection pin). The second lead 210.2 may be coupled to the gate of a MOSFET device on the semiconductor die 260 using, for example, wirebond 274. The second lead 210.2 may be used to connect the gate of the MOSFET device on the semiconductor die 260 to one or more external connections (e.g., on a PCB).

[0074] Third lead 210.3 may include an electrical connection pin (e.g., a single electrical connection pin). Third lead 210.3 may be coupled to another contact associated with a MOSFET device on semiconductor die 260, such as a source Kelvin contact and / or a sensor contact. Third lead 210.3 may be coupled to a gate of a MOSFET device on semiconductor die 260, for example, using wirebond 276. Third lead 210.3 may be used to connect contacts associated with a MOSFET device on semiconductor die 260 to one or more external connections (e.g., on a PCB).

[0075] SMT connection structure 220 may be connected to a drain of a MOSFET device on semiconductor die 260. More specifically, the drain of the MOSFET device may be electrically coupled to mounting substrate 250 (e.g., through a die attach material). SMT connection structure 220 may be electrically coupled to mounting substrate 250. For example, SMT connection structure 220 may be electrically coupled to mounting substrate 250 through connection elbow 226. In some embodiments, connection elbow 226 and / or SMT connection structure 120 may be integral with mounting substrate 250.

[0076] As discussed above, power semiconductor package 200 may include semiconductor die 260 with other types of semiconductor devices without departing from the scope of this disclosure. For example, in some examples, semiconductor die 260 may include a Schottky diode. In this example, one or more of electrical leads 210 may be coupled to a first contact of the Schottky diode on semiconductor die 260 using, for example, a wire bond. SMT connection structure 220 may be connected to a second contact of the Schottky diode, for example, through mounting substrate 250 (e.g., through connection elbow 126 and mounting substrate 250).

[0077] Variations and modifications may be made to the example power semiconductor devices described herein without departing from the scope of the present disclosure. For example, the power semiconductor devices may include electrical leads extending from a first side of the power semiconductor die of various sizes and shapes.

[0078] For example, FIG. 8 illustrates the exemplary power semiconductor package 200 of FIGS. 4 and 5 with a different arrangement of the electrical leads 210 according to an exemplary embodiment of the present disclosure. The exemplary power semiconductor package 200 of FIG. 8 includes four electrical leads 210: a first lead 210.1, a second lead 210.2, a third lead 210.3, and a fourth lead 210.4. The first lead 210.1 may have a larger size than the second lead 210.2, the third lead 210.3, and the fourth lead 210.4. Additionally, in the example of FIG. 8, the power semiconductor device 200 may include a groove 244 as part of the creepage extension structure 240 of the power semiconductor package 200. The groove 244 may be defined along a periphery of the housing 202 on a first side 202′ of the housing 202 between the electrical leads 210 and the thermal pad 230. The grooves 244 may have a depth ranging from, for example, 0.5 mm to about 2.0 mm.

[0079] 9 illustrates the exemplary power semiconductor package 200 of FIGS. 4 and 5 with another arrangement of the electrical leads 210 in accordance with an exemplary embodiment of the present disclosure. The exemplary power semiconductor package 200 of FIG. 9 includes five electrical leads 210: a first lead 210.1, a second lead 210.2, a third lead 210.3, a fourth lead 210.4, and a fifth lead 210.5. The first lead 210.1 may have a larger size than the second lead 210.2, the third lead 210.3, the fourth lead 210.4, and the fifth lead 210.5. Additionally, in the example of FIG. 9, the power semiconductor device 200 may include a groove 244 as part of the creepage extension structure 240 of the power semiconductor package 200. Groove 244 may be defined along the periphery of housing 202 on first side 202′ of housing 202 between electrical lead 210 and thermal pad 230. Groove 244 may have a depth in the range of, for example, 0.5 mm to about 2.0 mm.

[0080] 8 and 9, power semiconductor packages according to exemplary embodiments of the present disclosure may have a variety of different electrical lead options for the electrical leads. In this manner, power semiconductor packages according to aspects of the present disclosure are suitable for a variety of different types of semiconductor devices.

[0081] Figures 10 and 11 show a power semiconductor package 100 similar to the power semiconductor package 100 of Figures 1 and 2. In the example of Figures 10 and 11, the power semiconductor package 100 includes a different arrangement of electrical leads 110 relative to the power semiconductor package 100 of Figure 1. The exemplary power semiconductor package 100 of Figures 10 and 11 includes three electrical leads 110: a first lead 110.1, a second lead 110.2, and a third lead 110.3. The first lead 110.1 may have a larger size compared to the second lead 110.2 and the third lead 110.3.

[0082] 10 and 11, the thermal pad 130 is electrically isolated from the SMT connection structure 120. More specifically, FIG. 11 illustrates a top perspective view of the power semiconductor package 100 of FIG. 10 in which the housing 102 is transparent, according to an exemplary embodiment of the present disclosure. As shown, the power semiconductor package 100 includes a mounting substrate 150 with an insulating layer 152.

[0083] 11 provides a cross-sectional view of the mounting substrate 150 taken along line A-A'. The thermal pad 130 is on an insulating layer 152. The insulating layer 152 may be formed of an insulating material, such as a ceramic material or other insulating material. The insulating substrate 152 may have a conductive layer 154 on a surface opposite the thermal pad 130. The conductive layer 154 may be electrically coupled to the SMT connection structure 120. The insulating layer 152 may provide electrical insulation between the thermal pad 130 and the SMT connection structure 120. In some examples, the mounting substrate 150 may be, for example, a direct-bonded copper (DBC) substrate or an active metal bond (AMB) substrate.

[0084] 12 illustrates a top perspective view of a power semiconductor package assembly 450 according to an exemplary embodiment of the present disclosure. FIG. 13 illustrates a bottom perspective view of a power semiconductor package assembly 450 according to an exemplary embodiment of the present disclosure. The power semiconductor package assembly 450 includes a first power semiconductor package 300 and a second power semiconductor package 400. Each of the first power semiconductor package 300 and the second power semiconductor package 400 may resemble any of the power semiconductor packages described herein, such as the power semiconductor package 100 of FIG. 1 .

[0085] For example, the first power semiconductor package 300 may include a first housing 302 having a first side 302′ and a second side 302″ opposite the first side 302′. The first power semiconductor package 300 may include one or more first electrical leads 310 extending from the first side 302′. The first power semiconductor package 300 may include one or more first SMT connection structures 320 on the second side 302″. For example, the first power semiconductor package 300 may include one or more first leadless SMT connection structures 320. The first leadless SMT connection structures 320 may be wettable flank connection structures. The first power semiconductor package 300 may include a first thermal pad 330. The first power semiconductor package 300 may include one or more first creepage extension structures 340. The one or more first creepage distance extension structures 340 may include a stepped structure and / or a groove. The power semiconductor package 300 may house a semiconductor die having one or more semiconductor devices, such as a MOSFET (e.g., a silicon carbide-based MOSFET) or a Schottky diode (e.g., a silicon carbide-based Schottky diode).

[0086] The second power semiconductor package 400 may include a first housing 402 having a third side 402′ and a fourth side 402″ opposite the third side 402′. The second power semiconductor package 400 may include one or more second electrical leads 410 extending from the third side 402′. The second power semiconductor package 400 may include one or more second SMT connection structures 420 on the fourth side 402″. For example, the second power semiconductor package 400 may include one or more second leadless SMT connection structures 420. The second leadless SMT connection structures 420 may be wettable flank connection structures. The second power semiconductor package 400 may include a second thermal pad. The second power semiconductor package 400 may include one or more second creepage extension structures 440. The one or more second creepage extension structures 440 may include a step structure and / or a groove. The power semiconductor package 400 may house a semiconductor die having one or more semiconductor devices, such as a MOSFET (e.g., a silicon carbide-based MOSFET) or a Schottky diode (e.g., a silicon carbide-based Schottky diode).

[0087] 12 and 13 , the second side 302″ of the first power semiconductor package 300 is aligned with the fourth side 402″ of the second power semiconductor package 400. In this manner, the one or more first leadless SMT connection structures 320 of the first power semiconductor package 300 are aligned with the one or more second leadless SMT connection structures 420 of the second power semiconductor package 400. The one or more first electrical leads 310 extend in a first direction C. The one or more second electrical leads 410 extend in a second direction D. The first direction C is opposite the second direction D. The power semiconductor package assembly 450 of FIGS. 12 and 13 may facilitate manufacturing of a power semiconductor package according to an exemplary embodiment of the present disclosure.

[0088] For example, Figure 14 shows a flow diagram of an exemplary method 500 according to an exemplary embodiment of the present disclosure. Figure 14 shows exemplary process steps for purposes of illustration and discussion. Those skilled in the art will understand, using the disclosure provided herein, that the process steps of any of the methods described in this disclosure may be adapted, modified, or may include steps not shown, omitted, and / or reordered without departing from the scope of the present disclosure.

[0089] At 502, the method 500 may include providing a first power semiconductor package. For example, the method may include providing the first power semiconductor package 300 of FIGS. 12 and 13. The first power semiconductor package 300 may include a first housing 302 having a first side 302′ and a second side 302″ opposite the first side 302′. The first power semiconductor package 300 may include one or more first electrical leads 310 extending from the first side 302′. The first power semiconductor package 300 may include one or more first SMT connection structures 320 on the second side 302″. For example, the first power semiconductor package 300 may include one or more first leadless SMT connection structures 320. The first leadless SMT connection structures 320 may be wettable flank connection structures. The first power semiconductor package 300 may include a first thermal pad 330. The first power semiconductor package 300 may include one or more first creepage distance extension structures 340. The one or more first creepage distance extension structures 340 may include a step structure and / or a groove.

[0090] At 504 of FIG. 14 , the method 500 may include providing a second power semiconductor package. The second power semiconductor package may include providing the second power semiconductor package 400 of FIGS. 12 and 13 . The second power semiconductor package 400 may include a first housing 402 having a third side 402′ and a fourth side 402″ opposite the third side 402′. The second power semiconductor package 400 may include one or more second electrical leads 410 extending from the third side 402′. The second power semiconductor package 400 may include one or more second SMT connection structures 420 on the fourth side 402″. For example, the second power semiconductor package 400 may include one or more second leadless SMT connection structures 420. The second leadless SMT connection structures 420 may be wettable flank connection structures. The second power semiconductor package 400 may include a second thermal pad. The second semiconductor package 400 may include one or more second creepage distance extension structures 440. The one or more second creepage distance extension structures 440 may include a step structure and / or a groove.

[0091] In some examples, the second side of the first semiconductor package may be aligned with the fourth side of the second power semiconductor package. For example, as shown in FIGS. 12 and 13 , the second side 302″ of the first semiconductor package 300 is aligned with the fourth side 402″ of the second power semiconductor package 400. In this manner, the one or more first leadless SMT connection structures 320 of the first power semiconductor package 300 are aligned with the one or more second leadless SMT connection structures 420 of the second power semiconductor package 400. The one or more first electrical leads 310 extend in a first direction C. The one or more second electrical leads 410 extend in a second direction D. The first direction C is opposite to the second direction D.

[0092] At 506 of Figure 14, the method may include separating the first power semiconductor package from the second power semiconductor package. For example, as shown in Figure 15, the first power semiconductor package 300 may be separated from the second power semiconductor package 400, as indicated by the arrow representing operation 506 of Figure 14. In this manner, power semiconductor packages according to exemplary embodiments of the present disclosure may be assembled back-to-back to provide a power semiconductor assembly. The power semiconductor packages may then be separated to provide individual power semiconductor packages.

[0093] Exemplary aspects of the present disclosure are described below. Any of the following features or examples may be used in combination with any of the embodiments or features provided in this disclosure.

[0094] One exemplary aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package may include a power semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposite the first side. The power semiconductor package may include one or more electrical leads extending from the first side. The power semiconductor package may include one or more leadless surface mount (SMT) connection structures on the second side.

[0095] In some examples, the one or more leadless SMT connection structures each include a wettable flank connection structure. In some examples, the wettable flank connection structure is partially encapsulated by the housing such that a connection surface of the wettable flank connection structure is exposed through a mounting surface of the housing. In some examples, the wettable flank connection structure is exposed through at least one side surface of the housing.

[0096] In some examples, each of the one or more leadless SMT connection structures has a larger connection surface area than each of the one or more electrical leads. In some examples, the power semiconductor package has a larger number of electrical leads on the first side than the number of leadless SMT connection structures on the second side. In some examples, the one or more electrical leads comprise a first lead and a second lead, and the first lead has a size larger than the size of the second lead.

[0097] In some examples, the housing includes a first surface defined between a first side and a second side and a second surface opposite the first surface, the first surface including at least one creepage extension structure, the at least one creepage extension structure including a stepped structure. In some examples, the at least one creepage extension structure includes a first stepped structure between the thermal pad and the first side of the housing and a second stepped structure between the thermal pad and the second side of the housing. In some examples, the stepped structure has a depth of about 0.5 mm to about 2.0 mm. In some examples, the at least one creepage extension structure includes a groove defined between the stepped structure and one or more electrical leads.

[0098] In some examples, the power semiconductor package includes a thermal pad that is electrically isolated from one or more leadless SMT connection structures. In some examples, the thermal pad is on an insulating layer of a mounting substrate for the semiconductor die.

[0099] In some examples, the semiconductor die comprises a wide bandgap semiconductor. In some examples, the semiconductor die comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), where a first lead of the one or more electrical leads is connected to a gate of the MOSFET and a second lead of the one or more electrical leads is connected to a source of the MOSFET. In some examples, the one or more leadless SMT connection structures are connected to a drain of the MOSFET. In some examples, a third lead of the one or more electrical leads is connected to a source Kelvin contact of the MOSFET or a sensor contact of the MOSFET. In some examples, the MOSFET comprises a silicon carbide-based MOSFET.

[0100] In some examples, the semiconductor die includes a Schottky diode. In some examples, one or more electrical leads are coupled to a first contact for the Schottky diode and one or more SMT connection structures are coupled to a second contact for the Schottky diode. In some examples, the Schottky diode is a silicon carbide-based Schottky diode.

[0101] Another exemplary aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package may include a semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposite the first side. The power semiconductor package may include one or more electrical leads extending from the first side. The power semiconductor package may include one or more SMT connection structures on the second side. Each of the one or more SMT connection structures may have a connection surface area greater than a connection surface area of ​​the one or more electrical leads.

[0102] In some examples, the connection surface area of ​​each of the SMT connection structures is at least two times greater than the connection surface area of ​​each of the one or more electrical leads.

[0103] In some examples, the one or more SMT connection structures each comprise a wettable flank connection structure, hi some examples, the wettable flank connection structure is partially enclosed by the housing such that a connection surface of the wettable flank connection structure is exposed through the mounting surface of the housing and such that the wettable flank connection structure is exposed through at least one side surface of the housing.

[0104] In some examples, each of the one or more SMT connection structures includes an SMT connection tab extending from the second side of the housing, hi some examples, each SMT connection tab extends from a side surface on the second side of the housing at a position below the top surface of the housing.

[0105] In some examples, the power semiconductor package has a greater number of electrical leads on the first side compared to the number of SMT connection structures on the second side, hi some examples, the one or more electrical leads comprise a first lead and a second lead, the first lead having a size greater than the size of the second lead.

[0106] In some examples, the semiconductor die comprises a metal oxide semiconductor field effect transistor (MOSFET), a first lead of the one or more electrical leads connected to a gate of the MOSFET, a second lead of the one or more electrical leads connected to a source of the MOSFET, and one or more SMT connection structures connected to a drain of the MOSFET. In some examples, the MOSFET comprises a silicon carbide-based MOSFET.

[0107] In some examples, the semiconductor die includes a Schottky diode. In some examples, one or more electrical leads are coupled to a first contact for the Schottky diode and one or more SMT connection structures are coupled to a second contact for the Schottky diode. In some examples, the Schottky diode is a silicon carbide-based Schottky diode.

[0108] Another exemplary aspect of the present disclosure is directed to a power semiconductor package. The power semiconductor package may include a semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposite the first side. The housing has a first surface extending between the first side and the second side and a second surface opposite the first surface. The power semiconductor package may include a thermal pad. The power semiconductor package may include a staircase structure on the first surface of the housing. The staircase structure may be defined in the housing such that a first portion of the housing at the first side has a first thickness and a second portion of the housing at the thermal pad has a second thickness. The second thickness may be greater than the first thickness.

[0109] In some examples, the staircase structure is disposed between the thermal pad and the first side of the housing. In some examples, the first surface further comprises a groove defined between the staircase structure and the first side of the housing. In some examples, the staircase structure has a depth of about 0.5 mm to about 2.0 mm.

[0110] In some examples, the power semiconductor package includes one or more electrical leads extending from a first side of the housing and one or more surface mount (SMT) connection structures on a second side of the housing.

[0111] In some examples, the one or more SMT connection structures each include an SMT connection tab extending from the second side of the housing.

[0112] In some examples, the one or more SMT connection structures each comprise a wettable flank connection structure.

[0113] In some examples, the thermal pad is electrically isolated from one or more SMT connection structures.

[0114] In some examples, the semiconductor die comprises a wide bandgap semiconductor. In some examples, the semiconductor die comprises a metal oxide semiconductor field effect transistor (MOSFET). In some examples, the MOSFET is a silicon carbide-based MOSFET.

[0115] In some examples, the semiconductor die comprises a Schottky diode. In some examples, the Schottky diode is a silicon carbide-based Schottky diode.

[0116] Another exemplary aspect of the present disclosure is directed to a method. The method may include providing a first power semiconductor package. The first power semiconductor package may include a first housing having a first side and a second side opposite the first side. The first power semiconductor package may include one or more first electrical leads extending from the first side and one or more first leadless surface mount (SMT) connection structures on the second side. The method may include providing a second power semiconductor package. The second power semiconductor package may include a second housing having a third side and a fourth side opposite the third side. The second power semiconductor package may include one or more second electrical leads extending from the third side and one or more second leadless SMT connection structures on the fourth side. The second side of the first power semiconductor package may be aligned with the fourth side of the second power semiconductor package.

[0117] In some examples, the method further comprises separating the first power semiconductor package and the second power semiconductor package.

[0118] In some examples, the one or more first leadless SMT connection structures of the first power semiconductor package are aligned with the one or more second leadless SMT connection structures of the second power semiconductor package, and in some examples, the one or more first SMT connection structures each comprise a wettable flank connection structure and the one or more second SMT connection structures each comprise a wettable flank connection structure.

[0119] In some examples, the one or more first electrical leads extend in a first direction and the one or more second electrical leads extend in a second direction, the first direction being opposite the second direction.

[0120] In some examples, the first power semiconductor package includes a first thermal pad and the second power semiconductor package includes a second thermal pad.

[0121] In some examples, the first power semiconductor package includes a first creepage extension structure that is part of the first housing, the first creepage extension structure including a first step structure, the second power semiconductor package includes a second creepage extension structure that is part of the second housing, the second creepage extension structure including a second step structure, and in some examples, the first creepage extension structure includes a first groove and the second creepage extension structure defines a second groove.

[0122] In some examples, the first power semiconductor package and the second power semiconductor package each comprise a wide bandgap semiconductor die.

[0123] In some examples, the semiconductor die comprises a metal oxide semiconductor field effect transistor (MOSFET). In some examples, the MOSFET is a silicon carbide-based MOSFET.

[0124] In some examples, the semiconductor die comprises a Schottky diode. In some examples, the Schottky diode is a silicon carbide-based Schottky diode.

[0125] Another exemplary aspect of the present disclosure is directed to a power semiconductor package assembly. The power semiconductor package assembly may include a first power semiconductor package. The first power semiconductor package may include a first housing having a first side and a second side opposite the first side. The first power semiconductor package may include one or more first electrical leads extending from the first side and one or more first leadless surface mount (SMT) connection structures on the second side. The power semiconductor package assembly may include a second power semiconductor package. The second power semiconductor package may include a second housing having a third side and a fourth side opposite the third side. The second power semiconductor package may include one or more first electrical leads extending from the third side and one or more second leadless SMT connection structures on the fourth side. The second side of the first power semiconductor package may be aligned with the fourth side of the second power semiconductor package.

[0126] In some examples, the one or more first leadless SMT connection structures of the first power semiconductor package are aligned with the one or more second leadless SMT connection structures of the second power semiconductor package, hi some examples, the one or more first leadless SMT connection structures each comprise a wettable flank connection structure, and the one or more second leadless SMT connection structures each comprise a wettable flank connection structure.

[0127] In some examples, the one or more first electrical leads extend in a first direction and the one or more second electrical leads extend in a second direction, the first direction being opposite the second direction.

[0128] In some examples, the first power semiconductor package includes a first thermal pad and the second power semiconductor package includes a second thermal pad.

[0129] In some examples, the first power semiconductor package includes a first creepage extension structure that is part of the first housing, the first creepage extension structure comprising a first step structure, the second power semiconductor package includes a second creepage extension structure that is part of the second housing, the second creepage extension structure comprising a second step structure, and in some examples, the first creepage extension structure comprises a first groove and the second creepage extension structure defines a second groove.

[0130] In some examples, each of the first power semiconductor package and the second power semiconductor package comprises a wide bandgap semiconductor die.

[0131] In some examples, the semiconductor die comprises a metal oxide semiconductor field effect transistor (MOSFET). In some examples, the MOSFET is a silicon carbide-based MOSFET.

[0132] In some examples, the semiconductor die comprises a Schottky diode. In some examples, the Schottky diode is a silicon carbide-based Schottky diode.

[0133] While the present subject matter has been described in detail with reference to specific exemplary embodiments thereof, it will be appreciated that those skilled in the art, once they have achieved the above understanding, may readily produce modifications to, variations on, and equivalents of, such embodiments. Accordingly, the scope of the present disclosure is intended to be illustrative rather than limiting, and the disclosure of the present subject matter does not exclude the inclusion of such modifications, variations, and / or additions to the present subject matter as would be readily apparent to those skilled in the art.

Claims

1. a semiconductor die; a housing having a first side and a second side opposite the first side; one or more electrical leads extending from the first side; one or more leadless surface mount (SMT) connection structures on the second side; and A power semiconductor package comprising:

2. 10. The power semiconductor package of claim 1, wherein the one or more leadless SMT connection structures each comprise a wettable flank connection structure.

3. The power semiconductor package of claim 2 , wherein the wettable flank connection structure is partially encapsulated by the housing such that a connection surface of the wettable flank connection structure is exposed through a mounting surface of the housing.

4. The power semiconductor package of claim 3 , wherein the wettable flank connection structure is exposed through at least one side surface of the housing.

5. 2. The power semiconductor package of claim 1, wherein each of the one or more leadless SMT connection structures has a larger connection surface area than each of the one or more electrical leads.

6. 10. The power semiconductor package of claim 1, wherein the power semiconductor package has a greater number of electrical leads on the first side compared to a number of leadless SMT connection structures on the second side.

7. 10. The power semiconductor package of claim 1, wherein the one or more electrical leads comprise a first lead and a second lead, the first lead having a size larger than a size of the second lead.

8. 2. The power semiconductor package of claim 1, wherein the housing comprises a first surface defined between the first side and the second side and a second surface opposite the first surface, the first surface comprising at least one creepage distance extension structure, and the at least one creepage distance extension structure comprising a stair structure.

9. 9. The power semiconductor package of claim 8, wherein the at least one creepage distance extension structure comprises a first staircase structure between a thermal pad and the first side of the housing, and a second staircase structure between the thermal pad and the second side of the housing.

10. The power semiconductor package of claim 8 , wherein the staircase structure has a depth of about 0.5 mm to about 2.0 mm.

11. 10. The power semiconductor package of claim 8, wherein the at least one creepage extension structure comprises a groove defined between the step structure and the one or more electrical leads.

12. 10. The power semiconductor package of claim 1, further comprising a thermal pad electrically isolated from the one or more leadless SMT connection structures.

13. 13. The power semiconductor package of claim 12, wherein the thermal pad is on an insulating layer of a mounting substrate for the semiconductor die.

14. 10. The power semiconductor package of claim 1, wherein the semiconductor die comprises a wide bandgap semiconductor.

15. 10. The power semiconductor package of claim 1, wherein the semiconductor die comprises a metal oxide semiconductor field effect transistor (MOSFET), a first lead of the one or more electrical leads connected to a gate of the MOSFET, and a second lead of the one or more electrical leads connected to a source of the MOSFET.

16. 16. The power semiconductor package of claim 15, wherein the one or more leadless SMT connection structures are connected to a drain of the MOSFET.

17. 16. The power semiconductor package of claim 15, wherein a third lead of the one or more electrical leads is connected to a source Kelvin contact of the MOSFET or a sensor contact of the MOSFET.

18. 16. The power semiconductor package of claim 15, wherein the MOSFET comprises a silicon carbide-based MOSFET.

19. 10. The power semiconductor package of claim 1, wherein the semiconductor die comprises a Schottky diode.

20. 20. The power semiconductor package of claim 19, wherein the one or more electrical leads are coupled to a first contact for the Schottky diode and the one or more SMT connection structures are coupled to a second contact for the Schottky diode.

21. 20. The power semiconductor package of claim 19, wherein the Schottky diode is a silicon carbide based Schottky diode.

22. a semiconductor die; a housing having a first side and a second side opposite the first side; one or more electrical leads extending from the first side; one or more surface mount (SMT) connection structures on the second side; Equipped with 10. A power semiconductor package, wherein each of the one or more SMT connection structures has a connection surface area greater than a connection surface area of ​​each of the one or more electrical leads.

23. 23. The power semiconductor package of claim 22, wherein the connection surface area of ​​each of the SMT connection structures is at least two times greater than the connection surface area of ​​each of the one or more electrical leads.

24. 23. The power semiconductor package of claim 22, wherein the one or more SMT connection structures each comprise a wettable flank connection structure.

25. 25. The power semiconductor package of claim 24, wherein the wettable flank connection structure is partially encapsulated by the housing such that a connection surface of the wettable flank connection structure is exposed through a mounting surface of the housing and such that the wettable flank connection structure is exposed through at least one side surface of the housing.

26. 23. The power semiconductor package of claim 22, wherein each of the one or more SMT connection structures comprises an SMT connection tab extending from the second side of the housing.

27. 23. The power semiconductor package of claim 22, wherein each SMT connection tab extends from a side surface on the second side of the housing at a location below a top surface of the housing.

28. 23. The power semiconductor package of claim 22, wherein the power semiconductor package has a greater number of electrical leads on the first side compared to a number of SMT connection structures on the second side.

29. 10. The power semiconductor package of claim 1, wherein the one or more electrical leads comprise a first lead and a second lead, the first lead having a size larger than a size of the second lead.

30. 23. The power semiconductor package of claim 22, wherein the semiconductor die comprises a metal oxide semiconductor field effect transistor (MOSFET), a first lead of the one or more electrical leads connected to a gate of the MOSFET, a second lead of the one or more electrical leads connected to a source of the MOSFET, and the one or more SMT connection structures connected to a drain of the MOSFET.

31. 31. The power semiconductor package of claim 30, wherein the MOSFET comprises a silicon carbide-based MOSFET.

32. a semiconductor die; a housing having a first side and a second side opposite the first side, the housing having a first surface extending between the first side and the second side and a second surface opposite the first surface; a thermal pad on the first surface; a staircase structure on the first surface of the housing, the staircase structure being defined on the housing such that a first portion of the housing at the first side has a first thickness and a second portion of the housing at the thermal pad has a second thickness, the second thickness being greater than the first thickness; A power semiconductor package comprising:

33. 33. The power semiconductor package of claim 32, wherein the stair structure is disposed between the thermal pad and the first side of the housing.

34. 33. The power semiconductor package of claim 32, wherein the first surface further comprises a groove defined between the stair structure and the first side of the housing.

35. 33. The power semiconductor package of claim 32, wherein the staircase structure has a depth of about 0.5 mm to about 2.0 mm.

36. 33. The power semiconductor package of claim 32, wherein the power semiconductor package comprises one or more electrical leads extending from the first side of the housing and one or more surface mount (SMT) connection structures on the second side of the housing.

37. 37. The power semiconductor package of claim 36, wherein the one or more SMT connection structures each comprise an SMT connection tab extending from the second side of the housing.

38. 37. The power semiconductor package of claim 36, wherein the one or more SMT connection structures each comprise a wettable flank connection structure.

39. 33. The power semiconductor package of claim 32, wherein the thermal pad is electrically isolated from the one or more SMT connection structures.

40. 33. The power semiconductor package of claim 32, wherein the semiconductor die comprises a wide bandgap semiconductor.

41. 33. The power semiconductor package of claim 32, wherein the semiconductor die comprises a metal oxide semiconductor field effect transistor (MOSFET).

42. 42. The power semiconductor package of claim 41, wherein the MOSFET is a silicon carbide based MOSFET.

43. 33. The power semiconductor package of claim 32, wherein the semiconductor die comprises a Schottky diode.

44. 44. The power semiconductor package of claim 43, wherein said Schottky diode is a silicon carbide based Schottky diode.

45. providing a first power semiconductor package, the first power semiconductor package comprising a first housing having a first side and a second side opposite the first side, the first power semiconductor package comprising one or more first electrical leads extending from the first side and one or more first leadless surface mount (SMT) connection structures on the second side; providing a second power semiconductor package, the second power semiconductor package comprising a second housing having a third side and a fourth side opposite the third side, the second power semiconductor package comprising one or more second electrical leads extending from the third side and one or more second leadless SMT connection structures on the fourth side; Equipped with The method, wherein the second side of the first power semiconductor package is aligned with the fourth side of the second power semiconductor package.

46. 46. ​​The method of claim 45, wherein the method further comprises separating the first power semiconductor package and the second power semiconductor package.

47. 46. ​​The method of claim 45, wherein the one or more first leadless SMT connection structures of the first power semiconductor package are aligned with the one or more second leadless SMT connection structures of the second power semiconductor package.

48. 46. ​​The method of claim 45, wherein the one or more first SMT connection structures each comprise a wettable flank connection structure, and the one or more second SMT connection structures each comprise a wettable flank connection structure.

49. 46. ​​The method of claim 45, wherein the one or more first electrical leads extend in a first direction and the one or more second electrical leads extend in a second direction, the first direction being opposite the second direction.

50. 46. ​​The method of claim 45, wherein the first power semiconductor package comprises a first thermal pad and the second power semiconductor package comprises a second thermal pad.

51. 46. ​​The method of claim 45, wherein the first power semiconductor package comprises a first creepage distance extension structure that is part of the first housing, the first creepage distance extension structure comprising a first staircase structure, and the second power semiconductor package comprises a second creepage distance extension structure that is part of the second housing, the second creepage distance extension structure comprising a second staircase structure.

52. 52. The method of claim 51, wherein the first creepage extension structure comprises a first groove and the second creepage extension structure defines a second groove.

53. 46. ​​The method of claim 45, wherein the first power semiconductor package and the second power semiconductor package each comprise a wide bandgap semiconductor die.

54. 54. The method of claim 53, wherein the wide bandgap semiconductor die comprises a metal oxide semiconductor field effect transistor (MOSFET).

55. 55. The method of claim 54, wherein the MOSFET is a silicon carbide-based MOSFET.

56. 54. The method of claim 53, wherein the wide bandgap semiconductor die comprises a Schottky diode.

57. 57. The method of claim 56, wherein the Schottky diode is a silicon carbide-based Schottky diode.

58. 1. A power semiconductor package assembly, comprising: a first power semiconductor package comprising a first housing having a first side and a second side opposite the first side, the first power semiconductor package comprising one or more first electrical leads extending from the first side and one or more first leadless surface mount (SMT) connection structures on the second side; a second power semiconductor package comprising a second housing having a third side and a fourth side opposite the third side, the second power semiconductor package comprising one or more second electrical leads extending from the third side and one or more second leadless SMT connection structures on the fourth side; Equipped with a power semiconductor package assembly, wherein the second side of the first power semiconductor package is aligned with the fourth side of the second power semiconductor package;

59. 59. The power semiconductor package assembly of claim 58, wherein the one or more first leadless SMT connection structures of the first power semiconductor package are aligned with the one or more second leadless SMT connection structures of the second power semiconductor package.

60. 59. The power semiconductor package assembly of claim 58, wherein the one or more first leadless SMT connection structures each comprise a wettable flank connection structure, and the one or more second leadless SMT connection structures each comprise a wettable flank connection structure.

61. 59. The power semiconductor package assembly of claim 58, wherein the one or more first electrical leads extend in a first direction and the one or more second electrical leads extend in a second direction, the first direction being opposite the second direction.

62. 60. The power semiconductor package assembly of claim 58, wherein the first power semiconductor package comprises a first thermal pad and the second power semiconductor package comprises a second thermal pad.

63. 59. The power semiconductor package assembly of claim 58, wherein the first power semiconductor package comprises a first creepage distance extension structure that is part of the first housing, the first creepage distance extension structure comprising a first staircase structure, and the second power semiconductor package comprises a second creepage distance extension structure that is part of the second housing, the second creepage distance extension structure comprising a second staircase structure.

64. 64. The power semiconductor package assembly of claim 63, wherein the first creepage extension structure comprises a first groove and the second creepage extension structure defines a second groove.

65. 60. The power semiconductor package assembly of claim 58, wherein the first power semiconductor package and the second power semiconductor package each comprise a wide bandgap semiconductor die.

66. 66. The power semiconductor package assembly of claim 65, wherein the wide bandgap semiconductor die comprises a metal oxide semiconductor field effect transistor (MOSFET).

67. 67. The power semiconductor package assembly of claim 66, wherein the MOSFET is a silicon carbide based MOSFET.

68. 68. The power semiconductor package assembly of claim 67, wherein the wide bandgap semiconductor die comprises a Schottky diode.

69. 69. The power semiconductor package assembly of claim 68, wherein said Schottky diode is a silicon carbide based Schottky diode.

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