Integrated micro- and nanoscale metal-assisted chemical etch process with uniform and clean etch front

Abstract

A method for metal-assisted chemical etching is described in which a catalyst layer is patterned on the surface of a semiconductor material, the catalyst layer including a pattern of sub-100 nm or smaller features adjacent to features greater than 1 μm in size. Furthermore, the catalyst layer is multi-layered. The patterned catalyst layer is then exposed to an etching solution, which causes etching of the semiconductor material to form nanostructures. Etch non-uniformity is sub-50 nm per μm etch, made possible by the multi-layer catalyst. In this manner, simultaneous micro- and nano-scale silicon etching can be performed without nanowire-like defects.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to U.S. Provisional Patent Application No. 63 / 450,829, entitled "Integrated Micro-Nano MACE," filed March 8, 2023, which is incorporated herein by reference in its entirety.

[0002] [Government Interests] This invention was made with government support under Grant No. EEC1160494 awarded by the National Science Foundation. The government has certain rights in this invention.

[0003] [Technical field] The present disclosure relates generally to metal-assisted chemical etching, and more particularly to an integrated micro- and nanoscale metal-assisted chemical etch process with a uniform and clean etch front. [Background technology]

[0004] Metal-assisted chemical etching (also known as MACE, but referred to herein as "MacEtch") is a process of wet chemical etching of semiconductors (mainly silicon) that involves the use of a metal catalyst, usually deposited in the form of a thin film or nanoparticles on the surface of the semiconductor. The metal-covered semiconductor is then immersed in an etching solution containing an oxidizing agent and hydrofluoric acid. The metal on the surface catalyzes the reduction of the oxidizing agent and, therefore, the dissolution of the silicon. This phenomenon of increased dissolution rate is also spatially restricted, increasing in close proximity to the metal particles on the surface. Ultimately, this leads to the formation of linear pores that are etched into the semiconductor. This means that predefined patterns of metal on the surface can be directly transferred to semiconductor substrates.

[0005] Simultaneous micro- and nanoscale etching of silicon at the wafer scale is currently performed using plasma etching techniques. However, these plasma techniques suffer from low throughput due to aspect ratio dependent etch (ARDE) rates, etch lag due to feature size variations, loading effects due to increased etch area, and undesirable surface characteristics such as sidewall taper and scalloping, which are particularly problematic at the nanoscale level and can affect etch uniformity. In addition, the hardware required for plasma etching can be very expensive. A potential alternative that addresses the above challenges with plasma etching is metal-assisted chemical etching ("MacEtch"). Summary of the Invention [Problem to be solved by the invention]

[0006] Unfortunately, MacEtch processes, especially integrated micro- and nanoscale MacEtch processes, currently suffer from nanowire-like defects in the microscale regime. As a result, current integrated micro- and nanoscale MacEtch processes do not possess a uniform and clean etch front. [Means for solving the problem]

[0007] In one embodiment of the present disclosure, a method for metal-assisted chemical etching includes patterning a catalyst layer on a surface of a semiconductor material, the catalyst layer including a pattern of sub-100 nm or smaller features adjacent to features greater than 1 μm in size, and the catalyst layer being multi-layered. The method further includes exposing the patterned catalyst layer to an etchant, causing the patterned catalyst layer to etch the semiconductor material to form nanostructures. Furthermore, the etch non-uniformity is sub-50 nm per μm etch, the non-uniformity being enabled by the multi-layer catalyst.

[0008] In another embodiment of the present disclosure, a method for metal-assisted chemical etching includes patterning a substrate with lithographic structures, exposing a surface of the substrate in areas free of the lithographic structures, wherein patterning the substrate with the lithographic structures results in sub-100 nm features on the substrate adjacent to features greater than 1 μm in size. The method further includes depositing a catalyst on the exposed substrate surface, wherein the catalyst is a multi-layer catalyst. The method additionally includes exposing the deposited catalyst layer to an etchant, wherein the deposited catalyst layer causes etching of the semiconductor material of the substrate to form nanostructures. Furthermore, the etch non-uniformity is sub-50 nm per μm etch, the non-uniformity being enabled by the multi-layer catalyst.

[0009] The foregoing has outlined rather broadly the features and technical advantages of one or more embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described below which may form the subject of the claims of the invention.

[0010] A better understanding of the present invention can be obtained when the following detailed description is considered in conjunction with the following drawings. [Brief explanation of the drawings]

[0011] [Figure 1A] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 1B] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 1C]FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 1D] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 1E] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 1F] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 1G] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 1H] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 1I]FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 2A] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 2B] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 2C] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 2D] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 2E] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 2F]FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 2G] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 2H] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 2I] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where photoresist lift-off was performed immediately before etching according to an embodiment of the present disclosure. [Figure 3A] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 3B] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 3C]FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 3D] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 3E] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 3F] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 3G] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 3H] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 3I]FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 12.5 / 1 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 4A] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 4B] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 4C] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 4D] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 4E] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 4F]FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 4G] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 4H] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 4I] FIG. 1 illustrates microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5 M / M, where no photoresist lift-off was performed prior to etching according to an embodiment of the present disclosure. [Figure 5A] FIG. 1 illustrates nanoscale etching on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack, in accordance with an embodiment of the present disclosure. [Figure 5B] FIG. 1 illustrates nanoscale etching on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack, in accordance with an embodiment of the present disclosure. [Figure 5C] FIG. 1 illustrates nanoscale etching on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack, in accordance with an embodiment of the present disclosure. [Figure 5D]FIG. 1 illustrates nanoscale etching on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack, in accordance with an embodiment of the present disclosure. [Figure 5E] FIG. 1 illustrates nanoscale etching on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack, in accordance with an embodiment of the present disclosure. [Figure 5F] FIG. 1 illustrates nanoscale etching on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack, in accordance with an embodiment of the present disclosure. [Figure 6A] FIG. 1 illustrates integrated micro- and nanoscale MacEtch results on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 05 M / M, in accordance with an embodiment of the present disclosure. [Figure 6B] FIG. 1 illustrates integrated micro- and nanoscale MacEtch results on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 05 M / M, in accordance with an embodiment of the present disclosure. [Figure 6C] FIG. 1 illustrates integrated micro- and nanoscale MacEtch results on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 05 M / M, in accordance with an embodiment of the present disclosure. [Figure 6D] FIG. 1 illustrates integrated micro- and nanoscale MacEtch results on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 05 M / M, in accordance with an embodiment of the present disclosure. [Figure 6E] FIG. 1 illustrates integrated micro- and nanoscale MacEtch results on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 05 M / M, in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] As mentioned above, metal-assisted chemical etching (also known as MACE, but referred to herein as "MacEtch") is a process of wet chemical etching of semiconductors (mainly silicon) that involves the use of a metal catalyst, usually deposited in the form of a thin film or nanoparticles on the surface of the semiconductor. The metal-covered semiconductor is then immersed in an etching solution containing an oxidizing agent and hydrofluoric acid. The metal on the surface catalyzes the reduction of the oxidizing agent and, therefore, the dissolution of the silicon. This phenomenon of increased dissolution rate is also spatially restricted, increasing in close proximity to the metal particles on the surface. Ultimately, this leads to the formation of linear pores that are etched into the semiconductor. This means that predefined patterns of metal on the surface can be directly transferred to a semiconductor substrate.

[0013] Simultaneous micro- and nanoscale etching of silicon at the wafer scale is currently performed using plasma etching techniques. However, these plasma techniques suffer from low throughput due to aspect ratio dependent etch (ARDE) rates, etch lag due to feature size variations, loading effects due to increased etch area, and undesirable surface characteristics such as sidewall taper and scalloping, which are particularly problematic at the nanoscale level and can affect etch uniformity. In addition, the hardware required for plasma etching can be very expensive. A potential alternative that addresses the above challenges with plasma etching is metal-assisted chemical etching ("MacEtch").

[0014] Unfortunately, MacEtch processes, especially integrated micro- and nanoscale MacEtch processes, currently suffer from nanowire-like defects in the microscale regime. As a result, current integrated micro- and nanoscale MacEtch processes do not possess a uniform and clean etch front.

[0015] As discussed herein, the principles of the present disclosure provide a viable process flow for defect-free simultaneous micro- and nanoscale silicon etching of nanowires, which is referred to herein as "Integrated Micro- and Nanoscale MacEtch" (IMN-MacEtch). Successful etching of silicon features ranging from 100 nm to 100 μm was achieved in a single step using embodiments of the present disclosure as discussed herein at an etch rate of approximately 1.8 μm / min, achieving features with an aspect ratio (AR) of approximately 18:1. As a result, embodiments of the present disclosure provide a viable alternative to current dry etch methods for patterning feature sizes across three orders of magnitude.

[0016] In one embodiment, a catalyst layer is patterned on the surface of the semiconductor material, the catalyst layer comprising a pattern of sub-100 nm or smaller (e.g., 50 nm) features adjacent to features greater than 1 μm in size, including features greater than 10 μm, 100 μm, etc.

[0017] Furthermore, in one embodiment, such a catalyst layer is a multi-layer catalyst. In one embodiment, such a catalyst comprises a bilayer of silver and gold. In one embodiment, the silver is approximately 3 nm thick and the gold is approximately 11 nm thick.

[0018] Additionally, in one embodiment, the catalyst layer comprises a pattern of adjacent features that differ in size by three orders of magnitude.

[0019] Further, in one embodiment, the patterned catalyst layer is exposed to an etching solution. In one embodiment, the etching solution comprises HF at a concentration between 5 and 10 M and HO at a concentration between 0.4 and 0.6 M. In one embodiment, the etching solution comprises HF at a concentration of 8.4 M and HO at a concentration of 0.5 M.

[0020] In one embodiment, the substrate is patterned with lithographic structures, leaving the surface of the substrate exposed in areas free of the lithographic structures, hi one embodiment, patterning the substrate with lithographic structures results in sub-100 nm features on the substrate adjacent to features greater than 1 μm in size.

[0021] In one embodiment, a catalyst is deposited on the exposed substrate surface, the catalyst being a multi-layer catalyst, hi one embodiment, the deposited catalyst layer is exposed to an etchant, and the deposited catalyst layer causes etching of the semiconductor material of the substrate to form nanostructures.

[0022] In one embodiment, the etch non-uniformity is sub-50 nm per μm of etch, and the non-uniformity is made possible by a multi-layer catalyst.

[0023] A brief discussion of MacEtch is provided below.

[0024] Similar to dry plasma etch techniques, MacEtch is suitable for etching at both the micro- and nanoscales. At the nanoscale, MacEtch has been used to create nanopillars, pores, and trenches, with local etch rates of approximately 8.6 μm / min. Etch rates between about 1 μm / min and about 4 μm / min have been achievable in some cases, although etch rates below 1 μm / min are also possible. Wafer-scale nanopatterned substrates are also compatible with light-scattering-based metrology, which was previously developed for plasma-etched silicon substrates. At the microscale, etch rates of about 2.8 μm / min for hole formation have been reported with the use of an applied electrical bias to assist the etch process, which is faster than the etch rates obtained for hole formation using the BOSCH™ process. However, catalyst instability limits etch quality as far as pillar formation is concerned, and etch rates below 0.5 μm / min using MacEtch do not even perform better than Cryo-RIE, with micropillars being etched at approximately 0.96 μm / min. An alternative implementation of MacEtch relies on the use of gaseous HF, but also has an etch rate below 1 μm / min.

[0025] Currently, MacEtch is primarily utilized to etch features at a single scale. As discussed above, there is currently no integration of micro- and nanoscale MacEtch without the generation of nanowire-type defects in the microscale domain, where these multiscale features are an intrinsic part of the device, as is the case with microfluidic devices for nanoparticle separation or zone plates.

[0026] One example of a current multiscale etch process uses an HF vapor-based process for zone plate fabrication. While such processes achieve high (82:1) multiscale AR and ultra-high (10,000:1) nanoscale AR, their etch quality at the multiscale is adversely affected by the presence of extensive nanowire-type defects due to the porosity of the metal layer required for sufficient large-scale etching. In addition, such processes suffer from very slow etch rates (approximately 0.4 μm / min). Finally, this etch technique requires proper temperature control to prevent condensation and high-temperature annealing to improve catalyst stability, adding both complexity and sample handling requirements to the process.

[0027] Embodiments of the present disclosure address such deficiencies by developing a feasible approach for scalable integrated micro-to-nanoscale MacEtch at room temperature and in liquid solution, referred to herein as "IMN-MacEtch." For example, certain embodiments of the present disclosure utilize jet and flash imprint lithography (J-FIL) and an Ag / Au catalytic bilayer, which enable simultaneous etching of 100 nm (200 nm pitch) nanopillars and 50 μm to 100 μm streets at a rate of approximately 1.8 μm / min, roughly five times faster than current technology, without extensive nanowhisker defects in the microscale etched region. Samples using the disclosed technique achieve an AR of approximately 18:1 without significant catalytic instability. Therefore, embodiments of the present disclosure provide a viable option for high-throughput fabrication of silicon devices. A discussion of the materials used by embodiments of the present disclosure to achieve scalable integrated micro-to-nanoscale MacEtch is provided below.

[0028] In one embodiment, single crystal, 100 mm, P-type, lightly doped (1-10 Ωcm), supplied by Nova Electronic Materials for nanopatterning and thermal oxide experiments, University Wafer for micropatterning experiments, and Pure Wafer for integrated micro-nano experiments. <100> The experiments were performed using a substrate that was a 500 μm thick silicon wafer. The adhesion layer (TranSpin) used to coat the wafer prior to micro- and nanopatterning was provided by Canon® Nanotechnologies Inc. Nanopatterning and integrated micro- to nanoscale patterning were performed using a proprietary polymer provided by Canon® Nanotechnologies Inc. Micropatterning experiments were performed using AZ-5209E positive tone photoresist and AZ 1:1 developer (MicroChemicals).

[0029] For substrate preparation, a solution consisting of a 2:1 mixture of 96% v / v sulfuric acid (H2SO4) and 30% v / v hydrogen peroxide (H2O2), prepared in a quartz bath for 10 minutes, was used. Unless otherwise noted, the substrate was then immersed in 49% v / v hydrofluoric acid (HF) for 30 seconds to remove surface oxides. A TranSpin adhesion layer was then spin-coated at 4000 RPM for 60 seconds and baked on a hotplate at 165 °C for 70 seconds. The wafer was air-cooled with a nitrogen gun and patterned. For micropatterning, a 900 nm layer of photoresist was deposited using a spin-coater at 4000 RPM for 60 seconds and baked at 90 °C for 2 minutes.

[0030] For substrate patterning, an Impreo 1100 Jet and Flash Nanoimprint Lithography (J-FIL) tool (Molecular Imprints, Inc.) was used to pattern 1 × 1 mm nanoimprints separated by 100 μm trenches. 2Nanopatterning was performed with an imprint template consisting of 100 nm pillars with a 200 nm pitch in a block of 100 μm. Micropatterning, on the other hand, consisted of hard-contact lithography based on a repeating grid of micropillars with diameters ranging from 10 μm to 50 μm and gaps of 20 μm, using acrylic clamps fabricated in-house and a Mylar photomask provided by CAD / Art Services Inc.

[0031] The UV exposure was carried out for 12 seconds inside an IntelliRay 400W UV flood lamp, followed by a 40 second development step and water quench before being thoroughly rinsed in a spin-rinse-dry (SRD) tool.

[0032] After both micro- and nanopatterning, residual layers from the imprint resist, photoresist, and adhesion layer remained between the pillars, thereby preventing the silicon substrate from being exposed. This residual layer was removed using a reactive ion etch tool (Oxford Instruments®) with a plasma-based polymer etch recipe consisting of a 5 sccm O2 and 70 sccm Ar gas flow mix with 65 W plasma in a chamber at 15 mTorr pressure for 55 seconds for J-FIL-defined patterns and 3 minutes for photolithographically-defined patterns. An optional photoresist lift-off step was performed after metal deposition on some micropatterned samples before the silicon wet etch.

[0033] For metal layer deposition, metal catalyst deposition was performed using a physical vapor deposition electron beam evaporator (CHA Industries®) under high vacuum (5×10 -6 The deposition was carried out under a pressure of 1000 Torr. The deposition rates for each metal were 0.2 Å / sec for Ag and 0.4 Å / sec for Au. In an attempt, Ti was deposited at a rate of 0.2 Å / sec.

[0034] Below, the process for performing a metal-assisted chemical etch is discussed.

[0035] After metal catalyst deposition or lift-off (if applicable), the substrates were placed in a solution consisting of HF, HO, and DI water. Two different etchant chemistries were tested: a 12.5 / 1 M / M ([HF] / [HO]) solution (4:1:4 HF:HO:HO volume ratio) and an 8.44 / 0.5 M / M solution (6:1:13 HF:HO:HO volume ratio). Etch times were 30 s in the 12.5 / 1 M / M solution and 60 s in the 8.44 / 0.4 M / M solution for nanopatterned samples, and 10 min for micropatterned samples, regardless of etchant chemistry. After etching, all samples were quenched in a DI HO bath, thoroughly rinsed, and dried using clean, dry air (CDA).

[0036] The results obtained by performing the experiments discussed above are divided into three subsets: micropillar etching, nanopillar etching, and micro- to nanoscale etching. The first two subsets were performed as part of a larger experimental space exploration to identify feasible process parameters for multiscale etching, some of which are repeated here. Briefly, the micro- and nanoscale etching results originate from a set of 54 individual experiments aimed at identifying sufficient metal stacks, substrate surface oxide thicknesses, and etching solution compositions. Micro- to nanoscale etching conditions were implemented by further optimizing the metal stack and selecting the substrate conditions and etching solution concentrations identified as the best possible for micro- and nanoscale patterning. A summary of the results presented here is shown in Table 1. For all experiments, the etching solution is presented as the ratio of HF to HO molar concentration ([HF] / [HO]M / M).

[0037] [Table 1]

[0038] The micropillar etching results are divided into two conditions: (i) a "metal break" process, where the metal catalyst breaks around the photoresist cap, similar to the J-FIL MacEtch process, and (ii) a photoresist lift-off process.

[0039] Below, lift-off micropillar etching is discussed.

[0040] Results obtained using a 12.5 / 1M / M solution are presented in Figures 1A-1I. Figures 1A-1I illustrate microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and a 12.5 / 1M / M etchant, with photoresist lift-off performed immediately prior to etching according to certain embodiments of the present disclosure. Figure 1A illustrates 10 μm pillars. Figure 1B illustrates 15 μm pillars. Figure 1C illustrates 20 μm pillars. Figure 1D illustrates 25 μm pillars. Figure 1E illustrates 30 μm pillars. Figure 1F illustrates 35 μm pillars. Figure 1G illustrates 40 μm pillars. Figure 1H illustrates 45 μm pillars. Figure 1I illustrates 50 μm pillars.

[0041] Metal catalyst cracking and fin formation could be observed between the pillars, with some widening of the features as the etch progressed, and some collapsed nanowires, likely resulting from porosity in the catalyst. The pillar height and etch rate across the sample were found to be 12.069 (0.994) μm and 1.207 (0.099) μm / min, respectively. The range between the highest and lowest pillars was found to be approximately 4.9 μm.

[0042] Using an 8.44 / 0.5M / M etchant instead resulted in a significant reduction in etch, including a slower hole injection rate into silicon and slower oxide removal. The resulting micropillars are shown in Figures 2A-2I. Figures 2A-2I illustrate microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an 8.44 / 0.5M / M etchant, with photoresist lift-off performed immediately before etching according to certain embodiments of the present disclosure. Figure 2A illustrates 10 μm pillars, Figure 2B illustrates 15 μm pillars, Figure 2C illustrates 20 μm pillars, Figure 2D illustrates 25 μm pillars, Figure 2E illustrates 30 μm pillars, Figure 2F illustrates 35 μm pillars, and Figure 2G illustrates 40 μm pillars. Figure 2H illustrates 45 μm pillars, and Figure 2I illustrates 50 μm pillars.

[0043] Catalyst stability appears to have improved, as no large fins were visible, although some catalyst fractures were still observed (e.g., Figures 2A and 2F). The measured etch depth was 3.458 (0.347) μm for an etch rate of 0.346 (0.035) μm / min. The pillar height range was found to be approximately 1.4 μm.

[0044] Metal break micropillar etching is discussed below.

[0045] 3A-3I, which illustrate microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and a 12.5 / 1M / M etchant, with no photoresist lift-off performed prior to etching according to certain embodiments of the present disclosure. FIG. 3A illustrates 10 μm pillars. FIG. 3B illustrates 15 μm pillars. FIG. 3C illustrates 20 μm pillars. FIG. 3D illustrates 25 μm pillars. FIG. 3E illustrates 30 μm pillars. FIG. 3F illustrates 35 μm pillars. FIG. 3G illustrates 40 μm pillars. FIG. 3H illustrates 45 μm pillars. FIG. 3I illustrates 50 μm pillars.

[0046] Figures 3A-3I show the results obtained using a 12.5 / 1M / M etchant on a metal fracture specimen. The etch depth achieved across all nine sections was 14.925 (0.991) μm, an etch rate of 1.493 (0.099) μm / min, or nearly five times faster than the results obtained with a similar metal stack but a different etchant solution. Non-vertical sidewalls can be observed for the larger fins and especially for the thinner pillars, resulting from catalytic instability (e.g., Figure 3A). Etch non-uniformity can sometimes be observed at the bottom of the etched region, showing irregular topography; some porosity at the top of the features was also evident. The height range for pillars across the specimen was approximately 6 μm.

[0047] The tapering and catalyst fracture issues seen in Figures 3A-3I were addressed by reducing the etchant concentration to an 8.44 / 0.5M / M etchant, and the improved etch quality is shown in Figures 4A-4I.

[0048] 4A-4I illustrate microscale MacEtch on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 0.5M / M, where no photoresist lift-off was performed prior to etching according to certain embodiments of the present disclosure. FIG. 4A illustrates 10 μm pillars. FIG. 4B illustrates 15 μm pillars. FIG. 4C illustrates 20 μm pillars. FIG. 4D illustrates 25 μm pillars. FIG. 4E illustrates 30 μm pillars. FIG. 4F illustrates 35 μm pillars. FIG. 4G illustrates 40 μm pillars. FIG. 4H illustrates 45 μm pillars. FIG. 4I illustrates 50 μm pillars.

[0049] The etch depth was measured to be 7.562 (0.560) μm under very similar etch conditions for an etch rate of 0.756 (0.056) μm / min, which is about 2.5 times faster than the prior art. Etch uniformity was also improved, as evidenced by a smoother-appearing surface at the base of the pillars. The pillar height range was about 2.1 μm.

[0050] The nanopillar etch results for both etchant concentrations are shown in Figures 5A-5F.

[0051] 5A-5F illustrate nanoscale etching on an oxide-free silicon substrate using a 3 nm Ag and 15 nm Au catalyst stack according to an embodiment of the present disclosure. 5A-5C illustrate etching in a 12.5 / 1 M / M solution. 5D-5F illustrate etching in an 8.44 / 0.5 M / M solution.

[0052] Some uneven etching was observed, particularly in Figures 5A and 5D, with localized etch non-uniformity shown in Figures 5B and 5E. The source of this uneven etching may be due to incomplete residual layer removal, as discussed further below. Evidence of collapse is seen in Figure 5C. The completed pillar heights were 1.459 (0.199) μm and 1.112 (0.261) μm for the 12.5 / 1 M / M and 8.44 / 0.5 M / M etchants, corresponding to etch rates of 2.918 (0.398) μm / min and 1.112 (0.261) μm / min, and ARs of approximately 12:1 and approximately 9:1, respectively. The pillar height range was approximately 0.9 μm for the 12.5 / 1 M / M etchant and approximately 1 μm for the 8.44 / 0.5 M / M etchant.

[0053] In the following, integrated micro-to-nanoscale etching (IMN-MacEtch) is discussed.

[0054] Based on the results presented above, integrated micro- and nanoscale etching was performed using an 8.44 / 0.5M / M etchant and an optimized metal stack, as described below. The results for multiscale etching are shown in Figures 6A-6E.

[0055] 6A-6E illustrate integrated micro- and nanoscale MacEtch results on oxide-free silicon substrates using a 3 nm Ag and 15 nm Au catalyst stack and an etchant of 8.44 / 05 M / M, according to certain embodiments of the present disclosure. FIG. 6A illustrates a 10 μm nanopillar array. FIGS. 6B-6C illustrate a 1 μm nanopillar array. FIGS. 6D-6E illustrate a 2 μm nanopillar array. Evidence of etch non-uniformity at the edges of the nanopillar array is shown in FIG. 6E.

[0056] Instead of the 15 nm of Au used in the results presented so far, the optimal metal stack was found to be 3 nm of Ag and 11 nm of Au. For this multiscale etch, a pillar height of 1.793 (0.127) μm was obtained at an etch rate of 1.793 (0.127) μm / min.

[0057] Some areas of localized etch non-uniformity occurred, as shown in Figure 6E, which was explained by the calculation of the standard deviation in height. Other areas appeared to be dominated by pinholes, or localized metal layer defects that caused islands to form in microscale regions, rather than uniform etching.

[0058] The reason for these defects may be due to uneven residual layer removal or uneven catalyst thickness. Because these defects can be optimized and reduced, areas with pinhole etching were not considered when measuring pillar height. However, large areas were observed to be defect-free, lending credence to the conclusion that a uniform multiscale etch was first achieved when simultaneously etching 100-nm diameter pillars with a 200-nm pitch and 50-μm to 100-μm trenches in microscale features.

[0059] Catalyst selection is a valuable step in developing a viable MacEtch process. The catalyst needs to be selected so that the correct potential difference exists between the metal and silicon surfaces to ensure the reaction can proceed. Furthermore, it is important to consider that different catalysts will exhibit different catalytic activity, that catalytic bilayers may exhibit improved catalytic activity over single metal layers, and that different bilayers will lead to differences in etch quality. As discussed herein, three catalyst compositions were considered: Ti / Au, Ti / Ag / Au, and Ag / Au.

[0060] Regarding the use of a Ti / Au catalyst bilayer, in one embodiment, implementation of the Ti / Au catalyst involved using a thick Au layer (approximately 40 nm) and low-temperature etching, which resulted in very slow etching (approximately 0.1 μm / min). This low etch rate would be undesirable for high-throughput etching. Experiments performed on substrates similar to those used for individual micro- and nanopatterning experiments showed that using 0.5 nm of Ti and 15 nm of Au catalyst resulted in uniform etching at the nanoscale for both etchants, but failed to produce micropillars, regardless of etch pretreatment of the sample.

[0061] For the Ti / Ag / Au triple layer, a stack consisting of 0.5 nm Ti, 3 nm Ag, and 15 nm Au was tested, which failed to produce high-quality etch results at both the micro- and nanoscales.

[0062] The failure was somewhat unexpected since the Ti was only used as an adhesion layer in MacEtch to act as an etch retarder that needed to be overcome before the etch could proceed. However, the use of a metal trilayer was discarded as a viable catalyst for these substrates.

[0063] Finally, we utilized thin Ag and thick Au catalysts to produce successful etching at both the micro- and nanoscales, as previously discussed. Furthermore, the etch rates for Ag / Au-MacEtch at the nanoscale were higher than those obtained with the Ti / Au catalyst for either etchant concentration. The etch rates for the Ag / Au catalyst were 2.918 (0.398) μm / min and 1.112 (0.261) μm / min, respectively, whereas the etch rates for the Ti / Au catalyst were 1.573 (0.075) μm / min and 0.673 (0.0085) μm / min for the 12.5 / 1 M / M and 8.44 / 0.5 M / M etchants, respectively, as shown in Table 2 below.

[0064] [Table 2]

[0065] These differences in etch rates appear to be statistically significant for the 12.1 / 1M / M etchant but not for the 8.44 / 0.5M / M case, because the 3-σ confidence interval (CI) for the former is [1.724, 4.112] μm / min, which does not include the mean etch rate for the Ti / Au case, while the 3-σ CI for the latter is [0.329, 1.895] μm / min, which does include the mean etch rate for the 8.44 / 0.5M / M Ti / Au case. However, it should be noted that the occurrence of defects for the Ag / Au-catalyzed case shown in Figures 5A-5F led to a large standard deviation in the etch rate for this case compared to the more uniform etch obtained with the Ti / Au catalyst.

[0066] These defects are hypothesized to be due to incomplete residual layer removal and surface defects, contaminants, or variations in metal thickness that cause regional localization of conformal metal layer formation. Any of these defects would locally inhibit MacEtch. Localized incomplete residual layer removal or contaminants affecting pattern definition and imprint resist spreading and thickness are likely reasons for the nonuniform etch, since there is no readily observable reason for metal thickness variations considering the equipment used for metal deposition. In both cases, these issues arise from external factors that cannot be easily controlled and attributed to nonreproducible errors. Regarding incomplete residual layer removal, a potential cause could be plasma nonuniformity in the etch chamber, while surface contamination could result from manual handling and transport of the sample or contaminants present on the nanoimprint template. The residual layer can also be affected by issues with inkjet dispensing imprint resist onto the substrate for J-FIL, which can cause thickness variations in the residual layer. These challenges are non-reproducible and difficult to predict, but several steps can be taken to resolve or mitigate them. First, residual layer removal can be improved by increasing the plasma etch time before metal deposition, but there is a limit beyond which polymer features will be adversely affected. Second, repeated cleaning of the imprint template and careful handling of the template and sample can reduce the occurrence of surface contaminants, but particle contamination can never be completely prevented in a laboratory setting involving human intervention.

[0067] A final but important finding regarding catalyst selection is the observed Ag instability in MacEtch, which can lead to silver dissolution and redeposition, causing defects. This dissolution and redeposition behavior has been shown to depend on the etchant concentration ratio. Ag instability would not have been expected for the catalyst concentrations used. However, silicon corrosion is observed, particularly on the top of micropillars etched in the 12.5 / 1M / M solution using the metal-breaking approach to etching. This dissolution may have been mitigated by the addition of a layer of Au on top. The addition of HCl may also help ameliorate the silver instability issue.

[0068] A discussion regarding substrate processing is provided below.

[0069] As mentioned above, the samples used to obtain the results discussed herein were pretreated with HF to remove any surface oxide present prior to photopatterning or J-FIL. It should be noted that silicon surfaces begin to oxidize immediately upon exposure to air at room temperature. Therefore, these samples were not truly oxide-free; instead, they had a surface oxide thickness less than that of the native silicon oxide. To compare etch results using different oxide conditions, native oxide and 25 nm thermal oxide substrates were also etched using an Ag / Au catalyst. For the native oxide samples, nanopillar etching with an 8.44 / 0.5 M / M etchant and metal-breaking micropillar etching with a 12.5 / 1 M / M etchant were the only cases that produced potentially useful results.

[0070] At the microscale, metal break etching for 10 minutes using a 12.5 / 1M / M etchant on a native oxide substrate produced good results. No significant defects were observed at the etch front. Furthermore, some bowing and erosion of the pillar tops were observed.

[0071] However, incompatible etchants meant that further exploration was ignored. At the nanoscale, only the thermal oxide samples produced satisfactory results, but similar challenges with etch uniformity existed as in the oxide-free case.

[0072] Microscale etching using the Ag / Au catalyst could not be achieved in the 25 nm oxide sample, and it is not easy to see why the oxide layer would cause different results.

[0073] For the 25 nm thermal oxide samples, catalyst delamination can be observed for the 12.5 / 1M / M sample, and photoresist lift-off can be observed for both etchant concentrations. Catalyst delamination can be caused by the underlying oxide being completely etched away, leading to large gaps with the metal, so that the attraction to the silicon was too low to re-establish contact. Photoresist lift-off can also be caused by removal of the oxide layer.

[0074] A potential reason for the oxide effect may be that the HF first removes any oxide present before the catalyst comes into contact with the silicon, providing a uniform starting point for the etch reaction. Because the catalyst must soak in, this may improve metal breakage around the polymer pattern cap by breaking the catalyst in areas where the layer would otherwise be conformal. This may be more pronounced with thick thermal oxides rather than native oxides, which tend to be less than 5 nm thick. Furthermore, thermal oxides may have a more uniform surface topology than native oxides.

[0075] A discussion regarding etchant concentration is provided below.

[0076] The concentration of chemical species in the etchant has an effect on the etch rate and feature quality of silicon micro- and nanostructures, potentially affecting stress generation in metal films. While increasing peroxide has been shown to increase etch rate, too much peroxide can cause hole injection to exceed the rate of oxide consumption, leading to hole diffusion, which subsequently causes porosity and lateral etching. Lateral etching and porosity formation can be problematic when attempting to etch deep vertical trenches or microscale features. Increasing peroxide concentration can also lead to uncontrolled dissolution of silver, which can significantly affect etch quality given the Ag / Au catalytic bilayer. Too much HF can lead to stress accumulation in the film but can be used to address porosity and sidewall tapering. In addition, the relative concentrations of chemical species can affect the etch regime and therefore the results.

[0077] The experimental results discussed herein indicate that increasing the etch rate results in higher concentrations of chemical species, and that slowing the etch rate always results in better etch quality. The etch rate reductions between the 12.5 / 1 and 8.44 / 0.5 M / M solutions were approximately 71%, 49%, and 62% for the lift-off microscale, metal-break microscale, and nanoscale etched samples, respectively. For the microscale samples presented in Figures 1A-I, 2A-I, 3A-I, and 4A-I, the reduced etch rate led to successful prevention of catalyst failure, which would result in protruding fin formation (see Figures 1A-I and 3A-I), although some instability was still occasionally observed with the weaker etchants. However, in the case of the lift-off samples (see Figures 2A-I), some of the catalyst damage may have been induced by the ultrasonic treatment step for resist removal. The improved catalyst stability at slower etch rates can be attributed to a slower hole injection that better matches the oxide removal rate, and to a slower overall reaction that allows for more uniform removal of material across the etch area, even at large lateral dimensions. With more uniform material removal, strain accumulation in the film will not reach a critical magnitude that allows crack formation and propagation.

[0078] A discussion of lift-off versus metal break is provided below.

[0079] Comparing the lift-off versus metal-fracture approaches, lift-off clearly offers several advantages. In particular, the 12.5 / 1 M / M etch results after lift-off reveal approximately 90° angles with no visible corrosion or porosity at the top of the micropillar features (see Figures 1A-1I), whereas metal-fracture samples etched under the same conditions result in visible porosity and rounding at the top of the silicon features, as well as scalloping and sidewall tapering, the latter of which is clearly visible in the smaller micropillars (e.g., Figures 3A-3B). While this tapering and scalloping were not observed in the lift-off cases, some pillars exhibited what appeared to be a step change in width after certain etch depths (e.g., Figures 1G and 1I). In the metal-fracture cases, the scalloping appears visually similar to the scalloping effect of DRIE, but the reason for its presence in MacEtch is not readily apparent. The tapering and broadening of the features at the base of the etch front can be caused by lateral shrinkage of the catalyst. These defects were successfully addressed by reducing the etchant concentration to 8.44 / 0.5M / M.

[0080] Regarding the corrosion and porosity formation at the top of the pillars, which was observed for metal fracture but not for lift-off, it is hypothesized that this may be due to excess hole accumulation and the surface area available for unintended etching. When excess holes diffuse to the top of the pillars, they cause delocalized silicon oxidation, which the HF species can remove. In the case of metal fracture, the polymer blocks are present on the top surface of the silicon feature, preventing holes that accumulate on that surface from participating in silicon oxidation and removal; therefore, only holes that cause oxidation near the sidewalls are etched away. The top of the feature exhibits more prominent defectivity and porosity because the unprotected top of the sidewalls is exposed to the etchant solution for a longer period of time. In the case of lift-off, the entire top region of the micropillar is exposed to the etchant; therefore, any diffusing holes can be more evenly distributed and etched away from the entire top surface, thereby mitigating the effects of sidewall etching and resulting in a form of electropolishing or uniform surface etching by HF alone. The improvement observed when reducing the etchant concentration for the metal break case may be due to a reduction in the number of holes injected into the silicon, thus reducing porosity formation. Another possible source of porosity may be due to increased availability of silver in the metal break case due to prolonged exposure of the metal catalyst located on top of the photoresist to the etchant.

[0081] However, metal breakage has advantages over liftoff. First, performing liftoff after metal deposition raises concerns that the released metal can redeposit elsewhere on the sample, leading to unintended etching and yield-affecting defect rates. Furthermore, sonicating the sample for resist removal potentially damages the metal catalyst and causes defects. These risks are eliminated with the metal breakage process because the metal in contact with the polymer resist is not released into solution, and the sample is not subjected to sonication or other mechanical perturbations. Additionally, liftoff requires the resist to have an undercut profile for metal deposition. While this can be achieved in some forms of lithography, achieving an undercut profile may not be possible with nanoimprinting. Therefore, if any metal adheres to the sidewalls of the imprint resist, liftoff can result in a metal tear or delamination. While there are techniques for creating oxide undercut for nanoimprint-defined features, even this approach was presented as a means to improve metal breakage rather than to enable liftoff. Finally, by relying on metal breaking, fewer process steps are required to pattern silicon, which may require fewer manipulations and reduce the risk of contaminants settling on the sample, thus improving yield.

[0082] Finally, as observed in the results presented herein, metal fracture led to an increase in etch rate for both etchant concentrations. In the 12.5 / 1 M / M solution, the etch rate increased from 1.207 (0.099) μm / min for lift-off to 1.493 (0.099) μm / min for metal fracture. On the other hand, in the 8.44 / 0.5 M / M solution, the etch rate increased from 0.346 (0.035) μm / min to 0.756 (0.056) μm / min between lift-off and metal fracture. Looking at the 3-σ CI for the metal fracture samples etched using the 12.5 / 1 M / M solution, the average etch rate for the lift-off samples was contained within the CI: [1.196, 1.790] μm / min; therefore, the difference may not be statistically significant. This is not the case for the sample etched with the 8.44 / 0.5M / M solution, where the 3-σCI is [0.588, 0.924] μm / min.

[0083] A discussion regarding multi-scale etching is provided below, and in particular, a discussion regarding metal break etch processes is provided below.

[0084] For a given catalyst thickness, increasing the lateral etch dimension leads to a decrease in etch rate and can also cause non-uniform etching across the lateral dimension. Non-uniformity in etching can lead to catalyst bending and strain accumulation, which can cause catalyst fracture, as seen in Figures 3A-3I. Decreasing the etchant concentration addressed the catalyst stability issue (see Figures 4A-4I), consistent with the observation that slower etches reduce defectivity. While differences in etch rates between scales remained, using an 8.44 / 0.5M / M etchant resulted in a microscale average etch rate of 0.756 μm / min and a nanoscale average etch rate of 1.112 μm / min. Note that the 3-σ CI for the etch rate of the nanoscale sample is [0.329, 1.895] μm / min, which encompasses the average etch rate of the microscale sample. This indicates that the differences in etch rates may not be statistically significant, although this conclusion comes with the caveat that, as mentioned previously, nanoscale etch rates had large standard deviations due to residual layer removal challenges. Furthermore, in one embodiment, smaller features etch slower, even when the process is optimized. This "inverse" ARDE (aspect ratio dependent etch) effect can be explained by the etch mechanism for MacEtch, where increasing lateral dimensions result in a slowdown of diffusion-driven processes due to mass transport. In addition to the difference in average etch rates for the micro- and nanoscale etch results, the nanoscale samples exhibited little or no etch in the microscale streets between the nanopillar arrays.

[0085] In one embodiment, further process improvements were utilized to achieve uniform etch rates for the micro- and nanoscale regions such that the nanopillar arrays and microscale streets were etched simultaneously.

[0086] In one embodiment, such process intervention involves optimizing catalyst thickness. The lateral penetration of species for mass transport in MacEtch appears to be at most approximately 700 nm. Therefore, catalysts with small pores spaced less than 700 nm could result in uniform etching of large lateral dimensions. While the 3 nm Ag and 15 nm Au catalyst stacks may have had pores at that spatial frequency, these may have been too small to allow sufficient mass transport at the microscale compared to the approximately 100 nm lateral spacing present in the nanopillar region. While gold is expected to remain porous until it reaches approximately 40 nm, the sharp etch rate decrease observed between 10 and 40 nm catalyst thicknesses indicates that pore size plays an important role in mass transport. Furthermore, a 3 nm Ag layer is not expected to form a continuous film. Thus, in one embodiment, optimization of the catalyst thickness focuses on varying the thickness of the gold layer so that reaction can occur through the membrane pores rather than at the edges of the defined pattern, and so that transport through these pores occurs at a rate similar to that of the nanopillar array to achieve a non-uniform etch at the micro- and nanoscale. At 12 nm, the microscale streets etched more slowly than the nanopillar areas, whereas reducing it to 10 nm caused the streets to form abundant nanowhiskers that pointed to the large pores on the catalyst.

[0087] However, using an 11 nm Au layer resulted in a uniform etch across the nanopillar array and microscale streets, although some defects were still present in some areas of the sample (see Figure 6E). In addition, a longer plasma etch was attempted using 3 nm Ag and 11 nm Au layers, but no significant improvement was observed and defects were still present.

[0088] As a result, in one embodiment, a shorter plasma etch time of 55 seconds was utilized, which was the same amount of time used in the individual nanoscale experiments.

[0089] Overall, the optimized catalyst thickness and lower concentration etchant produced good etch uniformity over large areas with low defectivity at both the micro- and nanoscale simultaneously, with an average etch rate of 1.793 μm / min, which exceeded the average etch rates of individual experiments at both the micro- and nanoscales (0.756 μm / min at the microscale and 1.112 μm / min at the nanoscale). This increase in etch rate can be attributed to the reduced metal thickness, which improved mass transport during the etch. The results achieved an aspect ratio of approximately 18:1 without a substantial amount of collapse.

[0090] In one embodiment, metal-assisted chemical etching is performed where the etched patterns have feature sizes of sub-10 μm, sub-1 μm, sub-750 nm, sub-500 nm, sub-300 nm, sub-200 nm, sub-100 nm, sub-50 nm, sub-30 nm, sub-20 nm, or sub-10 nm. In one embodiment, the etched patterns are adjacent to a second set of etched patterns with feature sizes greater than 100 nm, greater than 200 nm, greater than 500 nm, greater than 750 nm, greater than 1 μm, greater than 5 μm, greater than 10 μm, greater than 20 μm, greater than 30 μm, greater than 40 μm, greater than 50 μm, or greater than 100 μm. In separate embodiments, there is only a single set of etched patterns, and the feature sizes in the patterns are greater than 100 nm, greater than 200 nm, greater than 500 nm, greater than 750 nm, greater than 1 μm, greater than 5 μm, greater than 10 μm, greater than 20 μm, greater than 30 μm, greater than 40 μm, greater than 50 μm, or greater than 100 μm. In one embodiment, one or two sets of etched patterns are etched in a single etching step, and have an etch non-uniformity of less than sub-50 nm per micrometer etch, sub-25 nm per micrometer etch, sub-10 nm per micrometer etch, sub-5 nm per micrometer etch, sub-1 nm per micrometer etch, or sub-100 nm per micrometer etch. In one embodiment, the etch uniformity specification is enabled by the multi-layer catalyst utilized in MacEtch.

[0091] As a result of the above, MacEtch has, for the first time, enabled micro- and nanoscale etching of silicon with feature size variations from 100 nm to 100 μm. Simultaneous micro- and nanoscale etching is demonstrated by using a catalytic bilayer consisting of 3 nm of Ag and 11 nm of Au with an etchant bath containing 8.44 M HF and 0.5 M HO. Based on the measurements obtained, pillars had an average AR of 18:1 and were etched at a rate of approximately 1.8 μm / min. This is the first demonstration of multiscale MacEtch over a three-order of magnitude feature size variation without any ARDE effect, significant etch lag with scale change, or the formation of nanowhisker-type defects in the microscale etched region. Furthermore, the multiscale etching results discussed herein demonstrate an etch rate five times greater than multiscale MacEtch results from other techniques, but at a lower aspect ratio. Furthermore, in one embodiment, decreasing the gold layer thickness leads to porosity-induced defects in the microscale region, while increasing the gold thickness causes an etch rate disparity between the nanoscale and microscale regions. Additionally, the dependence of etchant concentration on etch quality is clearly demonstrated at the microscale, and the need for a slower etch to complete higher quality features is experimentally verified, regardless of sample pre-etch treatment (i.e., metal break or lift-off).

[0092] While descriptions of various embodiments of the present disclosure have been presented for illustrative purposes, they are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of embodiments, practical applications, or technological improvements beyond those found in the art, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method for metal-assisted chemical etching, the method comprising: patterning a catalyst layer on a surface of a semiconductor material, said catalyst layer comprising a pattern of sub-100 nm or less features adjacent to features greater than 1 μm in size, said catalyst layer being multilayer; exposing the patterned catalyst layer to an etchant, causing the patterned catalyst layer to etch the semiconductor material to form nanostructures; Including, The method, wherein the etch non-uniformity is sub-50 nm per μm of etch, and wherein the non-uniformity is enabled by the multi-layer catalyst.

2. 10. The method of claim 1, wherein the catalyst layer comprises a pattern of sub-100 nm features adjacent to features greater than 10 μm in size.

3. 10. The method of claim 1, wherein the catalyst layer comprises a pattern of sub-100 nm features adjacent to features greater than 100 μm in size.

4. 10. The method of claim 1, wherein the catalyst layer comprises a pattern of sub-50 nm features adjacent to features greater than 1 μm in size.

5. 10. The method of claim 1, wherein the catalyst layer comprises a pattern of sub-50 nm features adjacent to features greater than 10 μm in size.

6. 10. The method of claim 1, wherein the catalyst layer comprises a pattern of sub-50 nm features adjacent to features greater than 100 μm in size.

7. The method of claim 1 , wherein the catalyst layer comprises a pattern of adjacent features whose sizes differ by three orders of magnitude.

8. The method of claim 1 , wherein the catalyst layer comprises a bilayer of silver and gold.

9. 9. The method of claim 8, wherein the silver has a thickness of about 3 nm and the gold has a thickness of about 11 nm.

10. The etching solution contains HF at a concentration between 5M and 10M, and the etching solution contains H at a concentration between 0.4M and 0.6M. ２ O ２ The method of claim 1 further comprising:

11. The etching solution contains HF at a concentration of 8.4M, and the etching solution contains H at a concentration of 0.5M. ２ O ２ The method of claim 1 further comprising:

12. 1. A method for metal-assisted chemical etching, the method comprising: patterning a substrate with lithographic structures, wherein a surface of the substrate is exposed in areas free of the lithographic structures, and wherein the patterning of the substrate with lithographic structures results in sub-100 nm features adjacent to features greater than 1 μm in size on the substrate; depositing a catalyst on the exposed substrate surface, the catalyst being a multi-layer catalyst; exposing the deposited catalyst layer to an etchant, wherein the deposited catalyst layer causes etching of the semiconductor material of the substrate to form nanostructures; The method, wherein the etch non-uniformity is sub-50 nm per μm of etch, and wherein the non-uniformity is enabled by the multi-layer catalyst.

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