Electric field reduction structures for nitrogen-polar III-nitride semiconductor devices

Abstract

An electric field reduction structure for a transistor device having a III-nitride semiconductor structure is provided. In one example, the transistor device includes a nitrogen-polar (N-polar) III-nitride semiconductor structure. The transistor device includes a source contact, a drain contact, and a gate contact. The transistor device includes the electric field reduction structure operable to reduce an electric field in a region between the gate contact and the drain contact in the N-polar III-nitride semiconductor structure.

Description

Detailed Description of the Invention

[0001] [Priority claim] This application is based on and claims the benefit of priority to U.S. Patent Application No. 2018 / 179070, filed March 6, 2023. This application claims priority to and the benefit of the entire contents of this cited application, which is incorporated by reference in its entirety.

[0002] [Field] The present disclosure relates generally to semiconductor devices.

[0003] [background] Power semiconductor devices are widely used to carry large currents, handle high voltages, and / or operate at high frequencies, such as radio frequencies. A wide variety of power semiconductor devices are available for a variety of applications, including, for example, power switching devices and power amplifiers. Many power semiconductor devices are realized using various types of field-effect transistor (FET) devices, including MOSFETs (metal-oxide-semiconductor field-effect transistors), DMOS (double-diffused metal-oxide-semiconductor) transistors, HEMTs (high-electron-mobility transistors), MESFETs (metal-semiconductor field-effect transistors), LDMOS (latently diffused metal-oxide-semiconductor) transistors, etc.

[0004] Power semiconductor devices can be fabricated from wide-bandgap semiconductor materials (e.g., having a bandgap of 1.40 eV or greater). For example, HEMT power devices can be fabricated from gallium nitride (GaN) or other Group III-nitride-based material systems formed on, for example, silicon carbide (SiC) substrates or other substrates. As used herein, the term "Group III nitride" refers to semiconductor compounds formed between nitrogen and elements in Group III of the periodic table, often aluminum (Al), gallium (Ga), and / or indium (In). These compounds have empirical formulas in which one mole of nitrogen combines with one mole of total Group III elements. For high-power, high-temperature, and / or high-frequency applications, devices formed from wide-bandgap semiconductor materials, such as silicon carbide (e.g., the bandgap of alpha silicon carbide at room temperature is 2.996 eV) and Group III nitrides (e.g., the bandgap of gallium nitride at room temperature is 3.36 eV), can offer higher electric field breakdown strengths and higher electron saturation velocities compared to gallium arsenide (GaAs) and silicon (Si)-based devices.

[0005] [overview] Aspects and advantages of each embodiment of the disclosure will be set forth in part in the description that follows, or may be learned from the description, or may be learned by practice of the embodiments.

[0006] An exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a nitrogen-polar (N-polar) III-nitride semiconductor structure. The transistor device includes a source contact, a drain contact, and a gate contact. The transistor device includes an electric field reduction structure operable to reduce an electric field in a region between the gate contact and the drain contact in the N-polar III-nitride semiconductor structure.

[0007] Another exemplary embodiment of the present disclosure relates to a transistor device, the transistor device including an N-polar III-nitride semiconductor structure, the transistor device including a field plate overlying the N-polar III-nitride semiconductor structure.

[0008] Yet another exemplary aspect of the present disclosure relates to a transistor device. The transistor device includes a nitrogen-polar (N-polar) III-nitride semiconductor structure. The transistor device includes a source contact, a drain contact, and a gate contact. The transistor device includes an implanted region in the III-nitride semiconductor structure between the gate contact and the drain contact.

[0009] Yet another exemplary aspect of the present disclosure relates to a method of forming a transistor device, the method including forming an N-polar III-nitride semiconductor structure, the method including forming a field plate overlying at least a portion of the N-polar III-nitride semiconductor structure.

[0010] Yet another exemplary aspect of the present disclosure relates to a method of forming a transistor device, the method including forming a III-nitride semiconductor structure, the method including implanting a dopant into a region of the III-nitride semiconductor structure to form an implanted region, and forming a gate contact and a drain contact on the III-nitride semiconductor structure, with the implanted region between the gate contact and the drain contact.

[0011] These and other features, aspects, and advantages of various embodiments will become better understood with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, explain associated principles.

[0012] Detailed descriptions of embodiments directed to those skilled in the art are provided herein and refer to the accompanying drawings, in which: [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 shows examples of metal-polar and nitrogen-polar (N-polar) III-nitride crystal structures. [Figure 2] FIG. 2 illustrates an example semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 3] FIG. 3 illustrates an example of a conductive path between a field plate and a source contact according to an exemplary embodiment of the present disclosure. [Figure 4] FIG. 4 illustrates an example of a conductive path between a field plate and a source contact according to an exemplary embodiment of the present disclosure. [Figure 5] FIG. 5 illustrates an example semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 6] FIG. 6 illustrates an example semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 7] FIG. 7 illustrates an example semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 8] FIG. 8 illustrates an example semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 9] FIG. 9 illustrates an example semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 10] FIG. 10 illustrates an example semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 11] FIG. 11 illustrates an example semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 12] FIG. 12 illustrates an example semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 13] FIG. 13 illustrates an example semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 14] FIG. 14 illustrates an example semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 15] FIG. 15 illustrates an example semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 16] FIG. 16 illustrates a flowchart of an example method according to an exemplary embodiment of the present disclosure. [Figure 17] FIG. 17 shows an example flow chart for forming a nitrogen-polar (N-polar) III-nitride semiconductor structure according to an exemplary embodiment of the present disclosure. [Figure 18] FIG. 18 shows a flowchart of an example of forming a field plate overlying an N-polar III-nitride semiconductor structure according to an exemplary embodiment of the present disclosure. [Figure 19] FIG. 19 illustrates a flowchart of an example method according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] [Detailed explanation] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the various drawings. Each example is provided by way of explanation of an embodiment, not to limit the disclosure. Indeed, it will be apparent to those skilled in the art that various modifications and variations may be made to the embodiments without departing from the spirit and scope of the disclosure. For example, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. Accordingly, it is intended that aspects of the disclosure cover such modifications and variations.

[0015] Semiconductor devices can be used in power electronics applications. For example, transistor devices, such as high electron mobility transistors (HEMTs), can be used in power electronics applications. HEMTs fabricated in III-nitride material systems can have the potential to generate large amounts of radio frequency (RF) power because of their combination of material properties, such as high breakdown field, wide band gap, large conduction band offset, and / or high saturated electron drift velocity. Therefore, III-nitride HEMTs can be promising candidates for high frequency and / or high power RF applications (as well as low frequency, high power switching applications) either as discrete transistors or as transistors that interface with other circuit elements, for example, in monolithic microwave integrated circuit (MMIC) devices.

[0016] Transistor devices, such as HEMT devices, are sometimes classified as depletion-mode or enhancement-mode, corresponding to whether the transistor is in an on-state or off-state when the gate-source voltage is zero. In enhancement-mode devices, the device is in an off-state when the gate-source voltage is zero, while in depletion-mode devices, the device is in an on-state when the gate-source voltage is zero. In many cases, high-performance III-nitride HEMT devices can be implemented as depletion-mode (normally on) devices because they are conductive at zero gate-source bias due to polarization-induced charges at the interface between the barrier and channel layers of the device.

[0017] When a HEMT device is in the on-state, a two-dimensional electron gas (2DEG) is created at the heterojunction of two semiconductor materials with different bandgap energies, where the material with the smaller bandgap has a higher electron affinity. The 2DEG is an accumulation layer in the material with the smaller bandgap and can have a very high sheet electron concentration. Furthermore, electrons generated in the semiconductor material with the wider bandgap migrate to the 2DEG layer, allowing for high electron mobility due to reduced ionized impurity scattering. The combination of high carrier concentration and high carrier mobility gives HEMT devices a very large transconductance (which can also refer to the relationship between output current and input voltage), which can provide a strong performance advantage over MOSFETs in high-frequency applications.

[0018] HEMT devices may include metal-polar (e.g., Ga-polar) or nitrogen-polar (e.g., N-polar) III-nitride semiconductor structures. More specifically, the III-nitride semiconductor structures may have a hexagonal wurtzite crystal structure that lacks inversion symmetry along the c-plane of the crystal structure. The lack of inversion symmetry can result in polarization effects. The polarization effects can, for example, induce spontaneous polarization dipoles within the III-nitride semiconductor structure. The associated direction of the spontaneous polarization dipoles can determine whether the III-nitride semiconductor structure is metal-polar or N-polar.

[0019] For example, FIG. 1 illustrates an example of a metal-polar III-nitride semiconductor structure 50 (e.g., Ga-polar GaN) and an example of an N-polar III-nitride semiconductor structure 60 (e.g., N-polar GaN). As illustrated, the metal-polar III-nitride semiconductor structure 50 and the N-polar III-nitride semiconductor structure 60 each have a hexagonal wurtzite crystal structure. In the wurtzite crystal structure, the metal (e.g., gallium) and nitrogen are arranged in separate and distinct layers. The metal-polar (e.g., Ga-polar) III-nitride semiconductor structure 50 has a metal face 52 (e.g., gallium face) in the growth direction of the semiconductor structure 50 relative to the substrate. In the metal-polar III-nitride semiconductor structure 50, the direction of the spontaneous polarization dipole P may be opposite to the growth direction. The N-polar semiconductor structure 60 has a nitrogen face 62 in the growth direction of the semiconductor structure 60 relative to the substrate. In the N-polar III-nitride semiconductor structure 60, the direction of the spontaneous polarization dipole P may be the same as the growth direction.

[0020] HEMT devices having N-polar III-nitride semiconductor structures may include a thick cap layer (e.g., 500 angstroms to about 1000 angstroms). The thick cap layer in a HEMT device having an N-polar III-nitride semiconductor structure may bury the channel layer and 2DEG of the HEMT device deep below the surface of the semiconductor structure. By burying the channel layer and 2DEG deep below the surface of the semiconductor structure, trapping effects and other surface effects on the 2DEG may be mitigated by physically moving the 2DEG farther away from the surface of the semiconductor structure. Furthermore, increasing the thickness of the cap layer may result in increased polarization at the interface between the channel layer and the back barrier layer of the semiconductor structure. The back barrier layer may be tuned to control the charge density in the channel layer regardless of the distance from the gate to the channel layer. A thick cap layer for N-polar III-nitride semiconductor materials may increase the charge at the interface between the channel layer and the first cap layer, which acts as a confinement layer for the channel layer, thereby increasing the carrier concentration and electron mobility of the 2DEG. This can improve the transconductance of the 2DEG and enhance the performance of the transistor device. For example, increased transconductance reduces the on-resistance of the transistor device and enables its use at high frequencies, e.g., frequencies above 40 GHz. As a result, HEMT devices with N-polar group III-nitride structures have recently been shown to exhibit significant performance advantages over HEMT devices with conventional metal-polar group III-nitride structures, especially at operating frequencies in the millimeter-wave frequency band (e.g., above 40 GHz).

[0021] A field plate may be used in a HEMT device with a metal-polar III-nitride semiconductor structure. The field plate can increase the breakdown voltage of the HEMT device and reduce the electric field within the III-nitride semiconductor structure. The field plate can also reduce trapping effects. However, the field plate can degrade radio frequency performance at high frequencies.

[0022] HEMT devices having N-polar III-nitride semiconductor structures may have RF applications in frequency bands below 40 GHz. For example, larger sized HEMT devices (e.g., gate lengths of 100 nm or greater, or, for example, about 150 nm or greater) having N-polar III-nitride semiconductor structures may be used in applications in Ka-band (e.g., frequencies ranging from about 26.5 GHz to about 40 GHz) and / or X-band (e.g., frequencies ranging from about 7 GHz to 12 GHz).

[0023] According to exemplary embodiments of the present disclosure, a transistor device, e.g., a HEMT device having a gate length of about 100 nm or more, may include an electric field reduction structure operable to reduce an electric field within an N-polar III-nitride structure in a region between a gate contact and a drain contact of the semiconductor device. The electric field reduction structure may, for example, reduce the gate-drain capacitance (Cgd) of the transistor device and increase the gain and power-added efficiency (PAE) of the device at high power and frequencies below about 40 GHz, e.g., Ka-band and X-band frequencies.

[0024] In some embodiments, the electric field reduction structure may be a field plate overlying an N-polar III-nitride semiconductor structure. As used herein, a first structure "at least partially overlaps" or "overlies" a second structure if an axis perpendicular to a major surface of the first structure passes through both the first and second structures. The field plate may be a metallic structure (e.g., gold, nickel, platinum). The field plate may be electrically coupled, for example, to a source contact of a transistor device, to a gate contact of a transistor device, and / or to other bias or power sources via separate contacts. In some examples, the field plate may be floating.

[0025] In some examples, the field plate may include a portion that at least partially overlaps the gate contact of the transistor device. However, in some examples, the field plate may not overlap the gate contact. In some examples, there may be a dielectric layer, such as silicon nitride, between the field plate and the N-polar III-nitride semiconductor structure. However, in some examples, the field plate may be directly on top of the N-polar III-nitride semiconductor structure, such that the field plate forms a Schottky contact with the III-nitride semiconductor structure.

[0026] In some examples, the field plate may be at least partially embedded in the N-polar III-nitride semiconductor structure. For example, the field plate may be at least partially embedded in one or more cap layers of the N-polar III-nitride semiconductor structure. This may, in some examples, allow the field plate to be closer to the interface between the channel layer and the barrier layer (e.g., closer to the 2DEG) in transistor devices having a thick cap layer that buries the channel layer deep below the surface of the N-polar III-nitride semiconductor structure.

[0027] In some examples, the electric field reduction structure includes an implanted region in the III-nitride semiconductor structure. The implanted region may be in a region between a gate contact and a drain contact (e.g., a drain access region) in the III-nitride semiconductor structure. The implanted region may be in a cap layer of an N-polar III-nitride semiconductor structure, for example. The implanted region may include an implanted dopant, such as silicon (Si), magnesium (Mg), fluorine (F), iron (Fe), carbon (C), tin (Sn), oxygen (O), or other dopant. The implanted region may be electrically connected to the source contact and / or the drain contact. The implanted region may be used to reduce an electric field in the III-nitride semiconductor structure.

[0028] Aspects of the present disclosure provide numerous technical effects and advantages. For example, electric field reduction structures can affect the gate-drain capacitance (Cgd) of transistor devices, leading to improved performance in RF applications at frequencies below about 40 GHz, e.g., Ka-band and / or X-band frequencies. Electric field reduction structures can increase the breakdown voltage and reduce electron traps that occur due to the presence of electric fields in III-nitride semiconductor structures. The use of electric field reduction structures can increase the gain and power-added efficiency (PAE) of transistor devices in RF applications at operating frequencies below about 40 GHz.

[0029] Although the terms "first," "second," etc. may be used herein to describe various elements, it should be understood that these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the words "comprises," "comprising," and / or "includes," when used herein, specify the presence of stated features, numbers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Furthermore, it will be understood that terms used herein should be interpreted as having a meaning consistent with the meaning in the context of this specification and related art, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such in this specification.

[0032] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it is understood that the element may be directly on or extending directly onto the other element, and that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it is understood that the element may be directly connected or coupled to the other element, and there may be intervening elements present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0033] Relative terms such as "below," "above," "upper," "lower," "horizontal," "lateral," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation of the device depicted in the figures.

[0034] Embodiments of the present disclosure are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations in the shapes of the figures are expected, for example, as a result of manufacturing techniques and / or tolerances. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein, but are intended to include deviations in shapes that result, for example, from manufacturing. Similarly, it is understood that dimensional variations based on standard deviations in manufacturing procedures are expected. As used herein, "approximately" or "about" includes values ​​within 10% of the nominal value.

[0035] Like numbers refer to like elements throughout, and thus, the same or similar numbers may be described with reference to other drawings even if not illustrated or described in the corresponding drawing, and elements not labeled with a reference number may be described with reference to other drawings.

[0036] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions characterized as having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration within the layer and / or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, and p-type material has a majority equilibrium concentration of positively charged holes. Some materials may be designated by a "+" or "-" (e.g., n+, n-, p+, p-, n++, n--, p++, p--, etc.) to indicate a relatively high ("+") or low ("-") concentration of majority carriers compared to other layers or regions. However, such designations do not imply the presence of a particular concentration of majority or minority carriers in a given layer or region.

[0037] Aspects of the present disclosure are described with reference to HEMT transistor devices for purposes of illustration and explanation, but it will be apparent to those skilled in the art, using the disclosure provided herein, that certain aspects of the present disclosure may also be applicable to other semiconductor devices, such as Schottky diodes, without departing from the scope of the present disclosure.

[0038] The drawings and specification disclose exemplary embodiments, and although specific terms are employed, they are used in a generic and descriptive sense only and are not intended to limit the scope of the invention as set forth in the following claims.

[0039] Exemplary embodiments of the present disclosure will now be described with reference to the drawings.

[0040] 2 shows a cross-sectional view of an example HEMT device 100 according to an exemplary embodiment of the present disclosure. FIG. 2 is intended to depict the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The HEMT device 100 may include a semiconductor structure 102. The semiconductor structure 102 may be a III-nitride semiconductor structure, such as an N-polar III-nitride semiconductor structure.

[0041] As used herein, the term "III-nitrides" refers to semiconductor compounds formed between nitrogen (N) and elements from Group III of the periodic table, usually aluminum (Al), gallium (Ga), and / or indium (In). The term also refers to ternary and quaternary (or higher) compounds, such as AlGaN and AlInGaN. As will be appreciated by those skilled in the art, Group III elements can combine with nitrogen to form binary (e.g., GaN), ternary (e.g., AlGaN, AlInN, ScAlN), and quaternary (e.g., AlInGaN) compounds. All of these compounds have an empirical formula where one mole of nitrogen combines with one mole of total Group III elements.

[0042] The semiconductor structure 102 may be on a substrate 104. The substrate 104 may be a semiconductor material. For example, the substrate 104 may be a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, or other suitable substrate. In some embodiments, the substrate 104 may be a semi-insulating SiC substrate, which may be, for example, a 4H polytype of silicon carbide. Other candidate SiC polytypes may include the 3C, 6H, and 15R polytypes. The substrate may be a high-purity semi-insulating (HPSI) substrate, available from Wolfspeed. The term "semi-insulating" is used herein descriptively, rather than in an absolute sense.

[0043] In some embodiments, the SiC bulk crystal of the substrate 104 has a crystallinity of about 1×10 at room temperature. 5 The substrate 104 may have a resistivity of ohm-cm or greater. Exemplary SiC substrates that may be used in some embodiments are manufactured, for example, by Wolfspeed, Inc., and methods for manufacturing such substrates are described, for example, in U.S. Reissue Patent Nos. 34,861, 4,946,547, 5,200,022, and 6,218,680, the disclosures of which are incorporated herein by reference. While SiC may be used as the substrate material, any suitable substrate may be used in embodiments of the present disclosure, such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), etc. The substrate 104 may be a SiC wafer, and the HEMT device 100 may be formed, at least in part, through wafer-level processing, after which the wafer may be diced to obtain a plurality of individual HEMT devices 100. In some embodiments, the substrate 104 of the HEMT device 100 may be a thin substrate 104. In some embodiments, the thickness of the substrate 104 may be about 100 μm or less, such as about 75 μm or less, or for example about 50 μm or less.

[0044] The semiconductor structure 102 may include an optional nucleation layer 106 on the substrate 104. The nucleation layer 106 may be, for example, a GaN and / or AlN layer on the substrate 104, which may create a crystal structure transition between, for example, the SiC substrate 104 and the III-nitride semiconductor structure 102. The nucleation layer 106 may be deposited on the substrate 104 using, for example, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE).

[0045] The semiconductor structure 102 may be an N-polar III-nitride semiconductor structure having an N-face facing outward in a growth direction 108 of the semiconductor structure 102. The semiconductor structure 102 may include several layers. In the example of the HEMT device 100 of FIG. 2, the semiconductor structure includes a buffer layer 110, a back barrier layer 112, a channel layer 114, a first cap layer 116, and a second cap layer 118. However, those skilled in the art will understand, with the aid of the disclosure provided herein, that aspects of the present disclosure may also be applicable to devices having semiconductor structures with different layer arrangements. The semiconductor structure 102 may be formed on the substrate 104 by epitaxial growth. Techniques for epitaxial growth of III-nitrides are described, for example, in U.S. Pat. Nos. 5,210,051, 5,393,993, and 5,523,589, the disclosures of which are incorporated herein by reference.

[0046] The buffer layer 110 is made of an N-polar group III nitride, such as Al v Ga 1-vN (where 0≦v<0.1). In some embodiments, the aluminum mole fraction v is about 0 (e.g., 0.05 or less), indicating that the buffer layer 110 is GaN. The buffer layer 110 may or may not include other III-nitrides, such as InGaN or AlInGaN. The buffer layer 110 may be undoped or may simply be unintentionally doped. In some examples, the buffer layer 110 may be doped with iron to make it semi-insulating. The buffer layer 110 may be grown to a thickness ranging from about 0.5 μm to about 5 μm, for example, about 2 μm. The buffer layer 110 may also have a multilayer structure, such as a superlattice of GaN, AlGaN, etc., or a combination thereof. In some embodiments, the buffer layer 110 may be compressively strained.

[0047] The semiconductor structure 102 may include a back barrier layer 112 on the buffer layer 110. The back barrier layer 112 may be made of an N-polar group III nitride, such as Al w Ga 1-w In some embodiments, the back barrier layer 112 may be ScAlN or ScAlGaN. The back barrier layer 112 may or may not include other III-nitrides, such as InGaN or AlInGaN. The back barrier layer 112 may have a different bandgap than the channel layer 114. The back barrier layer 112 may have a thickness ranging from about 250 angstroms to about 350 angstroms, for example, about 300 angstroms.

[0048] In some embodiments, the back barrier layer 112 may have a multi-layer structure. For example, in one example, the back barrier layer 112 may include a first layer of n+ doped GaN having a thickness of about 100 Angstroms. The back barrier layer 112 may include a graded Al layer on top of the first layer. w.1 Ga 1-w.1A second layer may comprise a layer of N, where w.1 varies from about 0.05 to about 0.4. w Ga 1-w The second layer of N may have a thickness of about 100 Angstroms. The back barrier layer 112 is formed on the second layer of Al w.2 Ga 1-w.2 The back barrier layer 112 may include a third layer of AlN, where w.2 is in the range of 0.3 to 0.4. The thickness of the third layer may be approximately 100 angstroms. The back barrier layer 112 may include a fourth layer of AlN on the third layer. The thickness of the fourth layer may be in the range of approximately 5 angstroms to approximately 15 angstroms, for example, approximately 7 angstroms.

[0049] The semiconductor structure 102 may include a channel layer 114 on a back barrier layer 112. If the energy of the conduction band edge of the channel layer 114 is less than the energy of the conduction band edge of the back barrier layer 112 at the interface between the channel layer 114 and the back barrier layer 112, the channel layer 114 may be an N-polar group III nitride, such as Al x Ga 1-x N (where 0≦x<0.1). The channel layer 114 may have a bandgap different from the bandgap of the back barrier layer 112. In some embodiments, the aluminum mole fraction x is about 0 (e.g., 0.05 or less), indicating that the channel layer 114 is GaN. The channel layer 114 may or may not include other III-nitrides, such as InGaN or AlInGaN. The channel layer 114 may have a thickness ranging from about 75 angstroms to about 125 angstroms, for example, about 100 angstroms.

[0050] A 2DEG 115 may be induced in the channel layer 114 at the interface between the channel layer 114 and the back barrier layer 112. The 2DEG 115 is highly conductive and provides conduction between the source and drain regions of the HEMT device 100. The 2DEG 115 may be controlled such that, upon gate operation, the HEMT device 100 functions as a tunable transistor device.

[0051] The semiconductor structure 102 includes a first cap layer 116 (e.g., an AlGaN cap layer) on the channel layer 114. The first cap layer 116 is made of an N-polar group III nitride, e.g., Al y Ga 1-y y<0.4), indicating that the first cap layer 116 is an AlGaN layer. In some embodiments, the aluminum mole fraction y is in the range of about 0.2 to about 0.3. In some embodiments, the first cap layer 116 may be an ScAlN layer or an ScAlGaN layer. The first cap layer 116 may or may not include other III-nitrides, such as InGaN or AlInGaN. The first cap layer may have a bandgap that is different from the bandgap of the channel layer 114. The first cap layer 116 may have a thickness in the range of about 15 angstroms to about 50 angstroms, for example, about 26 angstroms.

[0052] The semiconductor structure 102 includes a second cap layer 118 on the first cap layer 116. The second cap layer 118 is made of an N-polar Group III nitride, such as Al z Ga 1-z N (where 0≦z<0.1). In some embodiments, the aluminum mole fraction z is about 0 (e.g., 0.05 or less), indicating that the second cap layer 118 is a GaN layer. The second cap layer 118 may or may not include other III-nitrides, such as InGaN or AlInGaN. The second cap layer 118 deeply buries the channel layer 114 below the surface of the semiconductor structure 102, such that the channel layer 114 is a buried layer at a depth of about 275 angstroms or more, e.g., about 500 angstroms or more, e.g., about 275 angstroms to about 1000 angstroms, from the surface of the semiconductor structure 102. The second cap layer 118 may have a thickness in the range of about 250 angstroms to about 1000 angstroms, e.g., about 500 angstroms.

[0053] The semiconductor structure 102 includes implanted regions 120.1 and 120.2. The implanted regions 120.1 and 120.2 include a distribution of implanted dopants (e.g., ions) of a first conductivity type such that the implanted regions 120.1 and 120.2 are n-type regions. The implanted regions 120.1 and 120.2 extend within the semiconductor structure 102 into the channel layer 114.

[0054] HEMT device 100 includes electrodes on implanted regions 120.1 and 120.2. More specifically, HEMT device 100 may include a source contact 122 on implanted region 120.1. HEMT device 100 may include a drain contact 124 on implanted region 120.2. Source contact 122 and drain contact 124 may be laterally spaced apart from one another. In some embodiments, source contact 122 and drain contact 124 may include a metal capable of forming an ohmic contact with a III-nitride semiconductor material. Suitable metals include refractory metals, such as titanium (Ti), tungsten (W), titanium tungsten (TiW), silicon (Si), titanium tungsten nitride (TiWN), tungsten silicide (WSi), rhenium (Re), niobium (Nb), nickel (Ni), gold (Au), aluminum (Al), tantalum (Ta), molybdenum (Mo), nickel silicide (NiSi), and the like. x ), titanium silicide (TiSi), titanium nitride (TiN), tungsten silicide nitride (WSiN), platinum (Pt), etc. In some embodiments, the source contact 122 may be an ohmic contact. The drain contact 124 may be an ohmic contact. In some embodiments, the source contact 122 and / or the drain contact 124 may include multiple layers that constitute an ohmic contact, which may be provided as described, for example, in U.S. Pat. Nos. 8,563,372 and 9,214,352, the disclosures of which are incorporated herein by reference.

[0055] The HEMT device 100 may include a gate contact 126. The gate contact 126 may extend at least partially through a recess (e.g., an ALE-defined recess) in the cap layer 118 such that the gate contact 126 is in close proximity to the first cap layer 116. In some examples, the gate contact 126 has a gate length L in the range of about 100 nm or greater, e.g., about 150 nm or greater. G The gate length is the length of the gate contact 126 adjacent to the first cap layer 116.

[0056] A protective layer 128 may be disposed between the gate contact 126 and the first cap layer 116. The protective layer 128 may be SiN. Other suitable dielectric layers, such as SiO2, MgOx, MgNx, ZnO, SiNx, SiOx, SiON, or other dielectric layers, may also be used as the protective layer 128. The protective layer 128 may be formed, for example, using one or more MOCVD processes, one or more atomic layer deposition (ALD) processes, and / or a sputter deposition process. The protective layer 128 may serve as a gate insulating film. In some examples, the protective layer 128 may have a thickness of, for example, about 5 angstroms to about 100 angstroms, such as about 10 angstroms to about 50 angstroms.

[0057] The gate contact 126 may be a T-gate and / or a gamma-gate, the configurations of which are described, by way of example, in U.S. Patent Nos. 8,049,252, 7,045,404, and 8,120,064, the disclosures of which are incorporated herein by reference. For example, nickel (Ni), platinum (Pt), nickel silicide (NiSi x Materials that can make contact (e.g., Schottky contact) with Group III nitride semiconductor materials, such as copper (Cu), palladium (Pd), chromium (Cr), tungsten (W), and / or tungsten silicide nitride (WSiN), may also be used.

[0058] The HEMT device 100 may include a dielectric layer 130 on the semiconductor structure 102. The dielectric layer 130 may be, for example, a dielectric material such as SiO2, MgOx, MgNx, ZnO, SiNx, SiOx, SiON, alloys or stacks thereof, or the like. In a particular example, the dielectric layer 130 may be silicon nitride. The dielectric layer 130 may be formed using one or more MOCVD processes, one or more ALD processes, one or more sputter deposition processes, or one or more other suitable processes. The dielectric layer 130 may have a thickness ranging from about 0.05 μm to about 2 μm.

[0059] There may be one or more insulating layers (e.g., insulating layers 132, 134) on the HEMT device 100. For example, the HEMT device 100 may be encapsulated in an insulating material without departing from the scope of the present disclosure. The insulating layers 132, 134 may be, for example, a dielectric material such as SiO2, SiON, MgOx, MgNx, ZnO, SiNx, SiOx, alloys or stacks thereof, etc. The dielectric layer 130 may be formed using one or more MOCVD processes, one or more ALD processes, one or more sputter deposition processes, or one or more other suitable processes.

[0060] In some examples, HEMT device 100 may be capable of operating at frequencies less than about 40 GHz. For example, HEMT device 100 may be capable of operating at frequencies in the Ka-band (e.g., frequencies ranging from about 26.5 GHz to about 40 GHz) and / or the X-band (e.g., frequencies ranging from about 7 GHz to 12 GHz). In some examples, HEMT device 100 may have a power density of up to 10 W / mm or more in these frequency bands, for example, a power density ranging from 2.5 W / mm to about 12 W / mm.

[0061] A transistor device cell may be formed by an active region between a source contact 122 and a drain contact 124, controlled by a gate contact 126 that is between the source contact 122 and the drain contact 124. For purposes of illustration, Figure 2 shows a cross-sectional view of one device cell of the HEMT device 100.

[0062] According to an exemplary embodiment of the present disclosure, the HEMT device 100 includes a field plate 136. The field plate 136 may be laterally disposed between the gate contact 126 and the drain contact 124. The field plate 136 may overlie the N-polar III-nitride semiconductor structure 102. In the example of FIG. 2, a dielectric layer 130 may be between the field plate 136 and the N-polar III-nitride semiconductor structure 102. The field plate 136 may be electrically isolated from the channel layer 114 and the gate contact 126.

[0063] The field plate 136 may include a conductive material. In some examples, the field plate 136 may be a metal or a combination of metals deposited using a metallization method. In some examples, the field plate 136 may include titanium, gold, nickel, a gold / titanium combination, a gold / nickel combination, or any other suitable metal or metals.

[0064] In some examples, there may be a space Lgf between the field plate 136 and the gate contact 126. The space Lgf may be wide enough to separate the field plate 136 from the gate contact 126, but short enough to enhance the electric field effect provided by the field plate 136. In some examples, the space Lgf may be in a range of about 1.0 μm or less, for example, in a range of 0.1 μm to about 1.0 μm.

[0065] The field plate may be connected to the source contact 122 through a conductive path. For example, FIG. 3 shows an example of a conductive path that may be used to couple the field plate 136 to the source contact 122. In the example of FIG. 3, a conductive bus 137 extends from the field plate 136 and connects to the source contact 122 across the active region of the HEMT device 100. FIG. 4 shows an example of a conductive path that may be used to couple the field plate 136 to the source contact 122. In the example of FIG. 4, the field plate 136 is connected to the source contact 122 using a conductive path 139 that runs outside the active region of the HEMT device 100. In some examples, the field plate 136 may be connected to a gate contact or other bias or power contact. In some examples, the field plate 136 may be floating.

[0066] 2 , the field plate 136 is not embedded in the N-polar III-nitride semiconductor structure 102. The field plate 136 has a laterally extending portion 138 that overlaps at least a portion of the gate contact 126. An insulating layer 134 may separate the laterally extending portion 138 of the field plate 136 from the gate contact 126, thereby electrically isolating the field plate 136 from the gate contact 126. The field plate 136 may be separated from the channel layer 114 by a distance D1. In some examples, the distance D1 may be in the range of about 0.06 μm to about 0.6 μm.

[0067] FIG. 5 illustrates a cross-sectional view of an example HEMT device 140 according to an exemplary embodiment of the present disclosure. FIG. 5 is intended to depict the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The HEMT device 140 of FIG. 5 is similar to the HEMT device 100 of FIG. 2 , except that the field plate 136 does not include a laterally extending portion 138 that overlaps at least a portion of the gate contact 126. The field plate 136 is not embedded within the N-polar III-nitride semiconductor structure 102. The field plate 136 may be separated from the N-polar III-nitride semiconductor structure 102 by a dielectric layer 130. The field plate 136 may be separated from the channel layer 114 by a distance D1. In some examples, the distance D1 may range from about 0.06 μm to about 0.6 μm. The field plate 136 of FIG. 5 may be connected to the source contact 122 using one or more of the conductive paths described in FIGS. 3 and 4 . In some examples, the field plate 136 may be connected to a gate contact or other bias or power contact, or in some examples, the field plate 136 may be floating.

[0068] FIG. 6 illustrates a cross-sectional view of an example HEMT device 142 according to an exemplary embodiment of the present disclosure. FIG. 6 is intended to depict the structure for identification and explanation purposes, and is not intended to depict the structure to physical scale. The HEMT device 142 of FIG. 6 is similar to the HEMT device 140 of FIG. 5. However, the field plate 136 of the HEMT device 142 of FIG. 6 is directly above the N-polar III-nitride semiconductor structure 102. For example, the field plate 136 is not separated from the N-polar III-nitride semiconductor structure 102 by the dielectric layer 130. Instead, the field plate 136 forms a Schottky contact with the N-polar III-nitride semiconductor structure 102. The material of the field plate 136 in FIG. 6 may be a material suitable for making a Schottky contact with the N-polar III-nitride semiconductor structure 102, such as nickel (Ni), platinum (Pt), nickel silicide (NiSix), copper (Cu), palladium (Pd), chromium (Cr), tungsten (W), and / or tungsten nitride silicide (WSiN). The field plate 136 may be separated from the channel layer 114 by a distance D2. In some examples, the distance D2 may be in the range of about 500 angstroms to about 1250 angstroms. The field plate 136 in FIG. 6 may be connected to the source contact 122 using one or more of the conductive paths described in FIGS. 3 and 4.

[0069] FIG. 7 illustrates a cross-sectional view of an example HEMT device 144 according to an exemplary embodiment of the present disclosure. FIG. 7 is intended to depict the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The HEMT device 144 of FIG. 7 is similar to the HEMT device 142 of FIG. 6 , except that the field plate 136 is embedded within a recess 146 defined in the N-polar III-nitride semiconductor structure 102. In the example of FIG. 7 , the recess 146 may extend at least partially into the second cap layer 118. The recess 146 may have a depth T1 of about 100 angstroms to about 750 angstroms. The recess 146 may allow the field plate 136 to be positioned closer to the channel layer 114. For example, the field plate 136 may be separated from the channel layer 114 by a distance D3. In some examples, the distance D3 may be in the range of about 250 angstroms to about 900 angstroms. 7 may be connected to the source contact 122 using one or more of the conductive paths described in Figures 3 and 4. In some examples, the field plate 136 may be connected to a gate contact or other bias or power contact. In some examples, the field plate 136 may be floating.

[0070] FIG. 8 illustrates a cross-sectional view of an example HEMT device 148 according to an exemplary embodiment of the present disclosure. FIG. 8 is intended to depict the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The HEMT device 148 of FIG. 8 is similar to the HEMT device 144 of FIG. 7. The field plate 136 is embedded within a recess 146 defined in the N-polar III-nitride semiconductor structure 102. The field plate 136 may be separated from the N-polar III-nitride semiconductor structure 102 within the recess 146 by a dielectric layer 131. The dielectric layer 131 may be the same as or different from the dielectric layer 130. The dielectric layer 131 may have a thickness of, for example, about 5 angstroms to about 100 angstroms, e.g., about 10 angstroms to about 50 angstroms. The dielectric layer 131 may be, for example, a dielectric material such as SiO2, MgOx, MgNx, ZnO, SiNx, SiOx, SiON, alloys or stacks thereof, etc. In a particular example, dielectric layer 130 may be silicon nitride. Dielectric layer 131 may be formed using one or more MOCVD processes, one or more ALD processes, one or more sputter deposition processes, or one or more other suitable processes.

[0071] In the example of FIG. 8 , the recess 146 may extend at least partially into the second cap layer 118. The recess 146 may have a depth T1 of about 100 angstroms to about 750 angstroms. The recess 146 may allow the field plate 136 to be positioned closer to the channel layer 114. For example, the field plate 136 may be separated from the channel layer 114 by a distance D4. In some examples, the distance D4 may be in the range of about 260 angstroms to about 1000 angstroms. The field plate 136 of FIG. 8 may be connected to the source contact 122 using one or more of the conductive paths described in FIGS. 3 and 4 . In some examples, the field plate 136 may be connected to a gate contact or other bias or power contact. In some examples, the field plate 136 may be floating.

[0072] FIG. 9 illustrates a cross-sectional view of an example HEMT device 150 according to an exemplary embodiment of the present disclosure. FIG. 9 is intended to depict the structure for identification and explanation purposes, and is not intended to depict the structure to physical scale. The HEMT device 150 of FIG. 9 is similar to the HEMT device 148 of FIG. 8. The field plate 136 is embedded within a recess 146 defined in the N-polar III-nitride semiconductor structure 102. The field plate 136 may be separated from the N-polar III-nitride semiconductor structure 102 within the recess 146 by a dielectric layer 131. The dielectric layer 131 may be the same as or different from the dielectric layer 130. The dielectric layer 131 may have a thickness of, for example, about 5 angstroms to about 100 angstroms, e.g., about 10 angstroms to about 50 angstroms. The dielectric layer 131 may be, for example, a dielectric material such as SiO2, MgOx, MgNx, ZnO, SiNx, SiOx, SiON, alloys or stacks thereof, etc. In a particular example, dielectric layer 130 may be silicon nitride. Dielectric layer 131 may be formed using one or more MOCVD processes, one or more ALD processes, one or more sputter deposition processes, or one or more other suitable processes.

[0073] In the example of FIG. 9, the recess 146 may extend completely through the second cap layer 118. The recess 146 may have a depth T2 of about 500 angstroms to about 1000 angstroms. The recess 146 may allow the field plate 136 to be positioned closer to the channel layer 114. For example, the field plate 136 may be separated from the channel layer 114 by a distance D5. In some examples, the distance D5 may be in the range of about 20 angstroms to about 150 angstroms. The field plate 136 of FIG. 9 may be connected to the source contact 122 using one or more of the conductive paths described in FIGS. 3 and 4. In some examples, the field plate 136 may be connected to a gate contact or other bias or power contact. In some examples, the field plate 136 may be floating.

[0074] FIG. 10 illustrates a cross-sectional view of an example HEMT device 152 according to an exemplary embodiment of the present disclosure. FIG. 10 is intended to depict the structure for identification and explanation purposes, and is not intended to depict the structure to physical scale. The HEMT device 150 of FIG. 10 is similar to the HEMT device 150 of FIG. 9. The field plate 136 is embedded within a recess 146 defined in the N-polar III-nitride semiconductor structure 102. The field plate 136 may be separated from the N-polar III-nitride semiconductor structure 102 within the recess 146 by a dielectric layer 131. The dielectric layer 131 may be the same as or different from the dielectric layer 130. The dielectric layer 131 may have a thickness of, for example, about 5 angstroms to about 100 angstroms, such as about 10 angstroms to about 50 angstroms. Dielectric layer 131 may be, for example, a dielectric material such as SiO2, MgOx, MgNx, ZnO, SiNx, SiOx, SiON, alloys or stacks thereof, etc. In a particular example, dielectric layer 130 may be silicon nitride. Dielectric layer 131 may be formed using one or more MOCVD processes, one or more ALD processes, one or more sputter deposition processes, or one or more other suitable processes.

[0075] In the example of FIG. 10 , the recess 146 may extend completely through the second cap layer 118 and at least a portion of the first cap layer 116. The recess 146 may have a depth T3 of about 510 angstroms to about 1050 angstroms. The recess 146 may allow the field plate 136 to be positioned closer to the channel layer 114. For example, the field plate 136 may be separated from the channel layer 114 by a distance D6. In some examples, the distance D6 may be in the range of about 10 angstroms to about 125 angstroms. The field plate 136 of FIG. 10 may be connected to the source contact 122 using one or more of the conductive paths described in FIGS. 3 and 4 . In some examples, the field plate 136 may be connected to a gate contact or other bias or power contact. In some examples, the field plate 136 may be floating.

[0076] FIG. 11 illustrates a cross-sectional view of an example HEMT device 154 according to an exemplary embodiment of the present disclosure. FIG. 11 is intended to depict the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The HEMT device 154 of FIG. 11 is similar to the HEMT device 152 of FIG. 10. The field plate 136 is embedded within a recess 146 defined in the N-polar III-nitride semiconductor structure 102. The field plate 136 may be separated from the N-polar III-nitride semiconductor structure 102 within the recess 146 by a dielectric layer 131. The dielectric layer 131 may be the same as or different from the dielectric layer 130. The dielectric layer 131 may have a thickness of, for example, about 5 angstroms to about 100 angstroms, such as about 10 angstroms to about 50 angstroms. Dielectric layer 131 may be, for example, a dielectric material such as SiO2, MgOx, MgNx, ZnO, SiNx, SiOx, SiON, alloys or stacks thereof, etc. In a particular example, dielectric layer 130 may be silicon nitride. Dielectric layer 131 may be formed using one or more MOCVD processes, one or more ALD processes, one or more sputter deposition processes, or one or more other suitable processes.

[0077] In the example of FIG. 11 , the recess 146 may extend completely through the second cap layer 118 and completely through the cap layer 118. The recess 146 may have a depth T4 of about 515 angstroms to about 1100 angstroms. The recess 146 may allow the field plate 136 to be positioned closer to the channel layer 114. For example, the field plate 136 may be separated from the channel layer 114 by a distance D7. In some examples, the distance D7 may be in the range of about 5 angstroms to about 100 angstroms, such as about 10 angstroms to about 50 angstroms. The field plate 136 of FIG. 11 may be connected to the source contact 122 using one or more of the conductive paths described in FIGS. 3 and 4 . In some examples, the field plate 136 may be connected to a gate contact or other bias or power contact. In some examples, the field plate 136 may be floating.

[0078] In some examples, a transistor device may include multiple field plates. For example, FIG. 12 illustrates a cross-sectional view of an example HEMT device 155 according to an exemplary embodiment of the present disclosure. FIG. 12 is intended to depict the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The HEMT device 155 of FIG. 12 is similar to the HEMT device 148 of FIG. 8. However, the HEMT device 155 has multiple field plates, including a first field plate 136.1, a second field plate 136.2, a third field plate 136.3, etc. The first field plate 136.1 is embedded within a recess 146 defined in the N-polar III-nitride semiconductor structure 102. The first field plate 136.1 may be separated from the N-polar III-nitride semiconductor structure 102 within the recess 146 by a dielectric layer 131. The dielectric layer 131 may be the same as or different from the dielectric layer 130. Dielectric layer 131 may have a thickness of, for example, about 5 Angstroms to about 100 Angstroms, such as about 10 Angstroms to about 50 Angstroms. Dielectric layer 131 may be, for example, a dielectric material such as SiO2, MgOx, MgNx, ZnO, SiNx, SiOx, SiON, alloys or stacks thereof, etc. In a particular example, dielectric layer 130 may be silicon nitride. Dielectric layer 131 may be formed using one or more MOCVD processes, one or more ALD processes, one or more sputter deposition processes, or one or more other suitable processes.

[0079] In the example of FIG. 12 , the recess 146 may extend at least partially into the second cap layer 118. The recess 146 may have a depth T1 of about 100 angstroms to about 750 angstroms. The recess 146 may allow the first field plate 136.1 to be positioned closer to the channel layer 114. For example, the field plate 136 may be separated from the channel layer 114 by a distance D4. In some examples, the distance D4 may be in the range of about 260 angstroms to about 1000 angstroms. The first field plate 136.1 of FIG. 12 may be connected to the source contact 122 using one or more of the conductive paths described in FIGS. 3 and 4 . In some examples, the first field plate 136.1 may be connected to a gate contact or other bias or power contact. In some examples, the first field plate 136.1 may be floating.

[0080] As shown, the HEMT device 155 may include a second field plate 136.2 disposed overlying the N-polar III-nitride semiconductor structure 102. The second field plate 136.2 may at least partially overlap the first field plate 136.1. A spacer layer 134 (e.g., a dielectric layer 134) may be disposed between the first field plate 136.1 and the second field plate 136.2. The second field plate 136.2 may be the same material as the first field plate 136.1 or may be a different material, such as a different conductive material (e.g., a metal). The second field plate 136.2 of FIG. 12 may be connected to the source contact 122 using one or more of the conductive paths described in FIGS. 3 and 4. In some examples, the second field plate 136.2 may be connected to a gate contact or other bias or power contact. In some examples, the second field plate 136.2 may be floating.

[0081] In some examples, as represented by the dotted lines, the HEMT device 155 may include one or more additional field plates, such as a third field plate 136.3. The third field plate 136.3 may be disposed overlying the N-polar III-nitride semiconductor structure 102. The third field plate 136.3 may at least partially overlap the second field plate 136.2 and / or the first field plate 136.1. The second field plate 136.2 may be within an insulating layer 135.1 (e.g., a dielectric layer). A spacer layer 135.24 (e.g., a dielectric layer 134) may be disposed between the second field plate 136.2 and the third field plate 136.3. The insulating layer 135.1 and the spacer layer 135.2 may be, for example, a dielectric material such as SiO2, MgOx, MgNx, ZnO, SiNx, SiOx, SiON, alloys or stacks thereof, and may be formed using one or more MOCVD processes, one or more ALD processes, one or more sputter deposition processes, or one or more other suitable processes.

[0082] The third field plate 136.3 may be the same material as the first field plate 136.1 and / or the second field plate 136.2, or may be a different material, such as a different conductive material (e.g., metal). The third field plate 136.3 of FIG. 12 may be connected to the source contact 122 using one or more of the conductive paths described in FIGS. 3 and 4. In some examples, the third field plate 136.3 may be connected to a gate contact or other bias or power contact. In some examples, the third field plate 136.3 may be floating.

[0083] FIG. 13 illustrates a cross-sectional view of an example HEMT device 160 according to an exemplary embodiment of the present disclosure. FIG. 13 is intended to depict the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The HEMT device 160 of FIG. 13 is similar to the HEMT device 100 of FIG. 2. Insulating layers 130, 132, and 134 are not shown, but may form part of the HEMT device 160 in some embodiments. In some examples, the III-nitride semiconductor structure 102 may be N-polar. In some examples, the III-nitride semiconductor structure 102 may be metal-polar.

[0084] The HEMT device 160 includes a field reduction structure including an implanted region 164 within the III-nitride semiconductor structure 102. The implanted region 164 may be within the III-nitride semiconductor structure 102 in a region 162 between the gate contact 126 and the drain contact 124 (e.g., a drain access region). The implanted region 164 may be within the second cap layer 118, for example. In the example of FIG. 13, the implanted region 164 is not coupled to the drain contact 124.

[0085] Implanted region 164 may include a distribution of implanted dopants, such as silicon (Si), magnesium (Mg), fluorine (F), iron (Fe), carbon (C), tin (Sn), oxygen (O), or other dopants. Implanted region 164 may include a distribution of implanted dopants, such as silicon (Si), magnesium (Mg), fluorine (F), iron (Fe), carbon (C), tin (Sn), oxygen (O), or other dopants. 18 dopant / cm 3 The distribution of implanted dopants may have a peak dopant concentration less than a depth I below the surface of the III-nitride semiconductor structure. D It may extend to depth I D The implanted dopant distribution in implanted region 164 may range from about 125 angstroms to about 500 angstroms. W1 May be related to width I W1 may be about 20% or more, for example about 40% or more, of the width of the drain access region 162. In some examples, the width I W1 may range from about 0.3 μm to about 2.0 μm.

[0086] In some examples, the distance L between the implant region 164 and the gate contact 126 is GI There may be a distance L GI may be wide enough to separate implanted region 164 from gate contact 126, but short enough to enhance the field effect provided by implanted region 164. In some examples, distance L GI may be in the range of about 0.4 μm or less, for example, in the range of 0.05 μm to about 0.6 μm.

[0087] Implanted region 164 may be electrically connected to source contact 122. In some examples, implanted region 164 may be connected to source contact 122 using one or more conductive paths outside the active region of HEMT device 160, for example, as described with reference to FIG. 4 . Instead of connecting a field plate to source contact 122 using conductive path 139, implanted region 164 may be connected to the source contact using conductive path 139. In some examples, implanted region 164 may be connected to a gate contact or other bias or power contact. In some examples, implanted region 164 may be floating. Implanted region 164 may reduce the electric field in III-nitride semiconductor structure 102 and function as a field-reducing structure similar to a field plate.

[0088] FIG. 14 illustrates a cross-sectional view of an example HEMT device 166 according to an exemplary embodiment of the present disclosure. FIG. 14 is intended to depict the structure for purposes of identification and explanation, and is not intended to depict the structure to physical scale. The HEMT device 166 of FIG. 14 is similar to the HEMT device 160 of FIG. 13. However, in the example of FIG. 14, the implanted region 164 extends through the drain access region 162 so as to couple (e.g., electrically couple) to the drain contact 124. More specifically, the implanted region 164 has a width I such that the implanted region is coupled to the drain contact 124. W2 It has.

[0089] Implanted region 164 may include a distribution of implanted dopants, such as silicon (Si), magnesium (Mg), fluorine (F), iron (Fe), carbon (C), tin (Sn), oxygen (O), or other dopants. Implanted region 164 may include a distribution of implanted dopants, such as silicon (Si), magnesium (Mg), fluorine (F), iron (Fe), carbon (C), tin (Sn), oxygen (O), or other dopants. 18 dopant / cm 3 The distribution of implanted dopants may have a peak dopant concentration less than a depth I below the surface of the III-nitride semiconductor structure. D It may extend to depth I D The implanted dopant distribution in implanted region 164 may range from about 125 angstroms to about 500 angstroms. W1 May be related to width I W2 may be about 50% or more, for example about 60% or more, of the width of the drain access region 162. In some examples, the width I W2 may range from about 0.1 μm to about 1 μm.

[0090] In some examples, the distance L between the implant region 164 and the gate contact 126 is GI There may be a distance L GI may be wide enough to separate implanted region 164 from gate contact 126, but short enough to enhance the field effect provided by implanted region 164. In some examples, distance L GI may be in the range of about 0.4 μm or less, for example, in the range of 0.05 μm to about 0.6 μm.

[0091] Implanted region 164 may be electrically connected to source contact 122. In some examples, implanted region 164 may be connected to source contact 122 using one or more conductive paths outside the active region of HEMT device 160, for example, as described with reference to FIG. 4 . Instead of connecting a field plate to source contact 122 using conductive paths 139, implanted region 164 may be connected to the source contact using conductive paths 139. In some examples, implanted region 164 may be connected to a gate contact or other bias or power contact. Implanted region 164 may reduce the electric field in III-nitride semiconductor structure 102 and function as a field-reducing structure similar to a field plate.

[0092] In some examples, a HEMT device may include a field plate and an implant region as electric field reduction structures. For example, FIG. 15 illustrates a cross-sectional view of an example HEMT device 170 according to an exemplary embodiment of the present disclosure. FIG. 15 is intended to depict the structure for identification and explanation purposes and is not intended to depict the structure to physical scale. The HEMT device 170 of FIG. 15 is similar to the HEMT device 160 of FIG. 13. However, in addition to the implant region 164, the HEMT device 170 includes a field plate 136 overlying the III-nitride semiconductor structure 102. The field plate 136 may be similar to any of the field plates described herein. The field plate 136 of FIG. 15 may be connected to the source contact 122 using one or more of the conductive paths described in FIGS. 3 and 4. In some examples, the field plate 136 may be connected to a gate contact or other bias or power contact. In some examples, the field plate 136 may be floating.

[0093] 16 illustrates a flowchart of an example method 200 according to an exemplary embodiment of the present disclosure. The example process steps are shown in FIG. 16 for purposes of illustration and explanation. Those skilled in the art will understand that, using the disclosure provided herein, they may adapt, modify, include steps not shown, exclude steps, and / or rearrange the process steps of any method described in the present disclosure without departing from the scope of the present disclosure.

[0094] At 210, the method 200 may include forming an N-polar III-nitride semiconductor structure. For example, the method 200 may include forming an N-polar III-nitride semiconductor substrate 102 on a substrate 104, such as a silicon carbide substrate 104. The semiconductor structure 102 may be a multi-layer structure and may include one or more of a nucleation layer 106, a buffer layer 110, a barrier layer 112, a channel layer 114, a first cap layer 116, and a second cap layer 118. Details regarding these exemplary layers are described above with reference to FIG. 2. The N-polar III-nitride semiconductor structure may be formed using, for example, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE).

[0095] At 220, the method 200 may include forming a field plate overlying at least a portion of the N-polar III-nitride semiconductor structure. For example, the method 200 may include forming the field plate 136 overlying the III-nitride semiconductor structure 102, as shown in Figures 2-11. The field plate may be formed using, for example, a metallization process.

[0096] At 230, method 200 may include electrically coupling the field plate to a source contact. For example, method 200 may include coupling field plate 136 to source contact 122 using a conductive path, as described in Figures 3 and 4. In some examples, the field plate may be connected to a gate contact or other bias or power contact. In some examples, the field plate may be floating.

[0097] 17 illustrates a flowchart for forming an N-polar III-nitride semiconductor structure 210 according to an exemplary embodiment of the present disclosure. Example process steps are shown in FIG. 17 for purposes of illustration and explanation. Those skilled in the art will understand, using the disclosure provided herein, that they may adapt, modify, include steps not shown, exclude steps, and / or rearrange the process steps of any method described in the present disclosure without departing from the scope of the present disclosure.

[0098] At 212, forming the N-polar III-nitride semiconductor structure 210 may include forming a barrier layer. The barrier layer may be formed, for example, on a channel layer of the N-polar III-nitride semiconductor structure. Examples of the barrier layer 112 are described with reference to FIG. 2. The barrier layer may be formed, for example, using metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE).

[0099] At 214, forming the N-polar III-nitride semiconductor structure 210 may include forming a channel layer. The channel layer may be formed on the barrier layer, for example. Examples of the channel layer 114 are described with reference to FIG. 2. The channel layer may be formed using, for example, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE).

[0100] At 216, forming the N-polar III-nitride semiconductor structure 210 may include forming a first cap layer. The first cap layer may be formed, for example, on the channel layer. Examples of the first cap layer 116 are described with reference to FIG. 2. The first cap layer may be formed, for example, using metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE).

[0101] At 218, forming the N-polar III-nitride semiconductor structure 210 may include forming a second cap layer. The second cap layer may be formed, for example, on the first cap layer. Examples of the second cap layer 118 are described with reference to FIG. 2. The second cap layer may be formed using, for example, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE).

[0102] 18 illustrates a flowchart for forming a field plate overlying at least a portion of an N-polar III-nitride semiconductor structure according to an exemplary embodiment of the present disclosure. Example process steps are shown in FIG. 18 for purposes of illustration and explanation. Those skilled in the art, using the disclosure provided herein, will understand that they may adapt, modify, include, exclude steps not shown, and / or rearrange the process steps of any method described in the present disclosure without departing from the scope of the present disclosure.

[0103] In one example, forming a field plate overlying at least a portion of the N-polar III-nitride semiconductor structure 220 in 222 may include creating a field plate within a recess within the III-nitride semiconductor structure. For example, as illustrated in FIGS. 7-12, the field plate 136 may be formed within a recess 146 within the III-nitride semiconductor structure 102. In some examples, the recess may be within the second cap layer. In some examples, the recess may be within the first cap layer and the second cap layer.

[0104] In one example, forming a field plate overlying at least a portion of the N-polar III-nitride semiconductor structure 220 in 224 may include forming the field plate directly on top of the III-nitride semiconductor structure such that the field plate forms a Schottky contact with the N-polar III-nitride semiconductor structure. For example, as shown in Figures 6 and 7, a field plate 136 may be formed directly on top of the N-polar III-nitride semiconductor structure. In some examples, there may not be a dielectric layer between the field plate and the N-polar III-nitride semiconductor structure.

[0105] In one example, forming a field plate overlying at least a portion of N-polar III-nitride semiconductor structure 220 at 226 may include forming a dielectric layer on the N-polar III-nitride semiconductor structure. For example, as shown in FIGS. 2-5 and 8-12, dielectric layer 130 and / or dielectric layer 131 may be formed on N-polar III-nitride semiconductor structure 102. The dielectric layer may be formed using, for example, one or more MOCVD processes, one or more atomic layer deposition (ALD) processes, one or more sputter deposition processes, or one or more other deposition processes. Forming a field plate overlying at least a portion of N-polar III-nitride semiconductor structure 220 at 228 may include forming the field plate on the dielectric layer.

[0106] 19 illustrates a flowchart of an example method 240 according to an exemplary embodiment of the present disclosure. The example process steps are shown in FIG. 19 for purposes of illustration and explanation. Those skilled in the art will understand that, using the disclosure provided herein, they may adapt, modify, include steps not shown, exclude steps, and / or rearrange the process steps of any method described in the present disclosure without departing from the scope of the present disclosure.

[0107] At 242, the method 240 may include forming an N-polar III-nitride semiconductor structure. For example, the method 200 may include forming an N-polar III-nitride semiconductor substrate 102 on a substrate 104, such as a silicon carbide substrate 104. The semiconductor structure 102 may be a multi-layer structure and may include one or more of a nucleation layer 106, a buffer layer 110, a barrier layer 112, a channel layer 114, a first cap layer 116, and a second cap layer 118. Details regarding these exemplary layers are described above with reference to FIG. 2. The N-polar III-nitride semiconductor structure may be formed using, for example, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE).

[0108] At 244, the method 240 may include implanting a dopant into a region of a III-nitride semiconductor structure (e.g., an N-polar III-nitride semiconductor structure) to form an implanted region. For example, the method 240 may implant the dopant to form the implanted region 162 as shown in FIGS. 13-15. The implanted region may include a distribution of implanted dopants, such as silicon (Si), magnesium (Mg), fluorine (F), iron (Fe), carbon (C), tin (Sn), oxygen (O), or other dopants. The implanted region may have a distribution of about 1×10 18 dopant / cm 3 The implanted dopant distribution may have a peak dopant concentration of less than 100 Å. The implanted dopant distribution may extend to a depth below the surface of the III-nitride semiconductor structure. The depth may range from about 125 Å to about 500 Å.

[0109] At 246, the method may include forming a gate contact and a drain contact on the III-nitride semiconductor structure, with an implanted region between the gate contact and the drain contact. For example, as shown in Figures 13-15, implanted region 164 is between gate contact 126 and drain contact 124 in drain access region 162.

[0110] At 248, the method may include electrically coupling the implanted region to a source contact and / or a drain contact of the transistor device. For example, as shown in FIG. 14, implanted region 164 may be electrically coupled to drain contact 124. In some examples, implanted region 164 may be electrically coupled to source contact 122 using the conductive pathway shown in FIG. 4. For example, instead of connecting the field plate to source contact 122 using conductive pathway 139, implanted region 164 may be connected to the source contact using conductive pathway 139 in FIG. 4. In some examples, the implanted region may be connected to a gate contact or other bias or power contact. In some examples, the implanted region may be floating.

[0111] Exemplary aspects of the present disclosure are described below. Any of the following features or examples may be used in combination with any of the embodiments or features provided in this disclosure.

[0112] An exemplary embodiment of the present disclosure relates to a transistor device. The transistor device includes a nitrogen-polar (N-polar) III-nitride semiconductor structure. The transistor device includes a source contact, a drain contact, and a gate contact. The transistor device includes an electric field reduction structure operable to reduce an electric field in a region between the gate contact and the drain contact in the N-polar III-nitride semiconductor structure.

[0113] In some examples, the electric field reduction structure comprises a field plate overlying the N-polar III-nitride semiconductor structure, hi some examples, the field plate is electrically coupled to the source contact.

[0114] In some examples, the field plate has a laterally extending portion that overlaps at least a portion of the gate contact. In some examples, the field plate does not overlap the gate contact.

[0115] In some examples, the transistor device includes a dielectric layer between the field plate and the N-polar III-nitride semiconductor structure, hi some examples, the field plate is at least partially embedded in the N-polar III-nitride semiconductor structure.

[0116] In some examples, the field plate is directly on top of the III-nitride semiconductor structure and forms a Schottky contact with the III-nitride semiconductor structure, hi some examples, the field plate is at least partially embedded in the N-polar III-nitride semiconductor structure.

[0117] In some examples, the N-polar III-nitride semiconductor structure includes a barrier layer and a channel layer overlying the barrier layer. In some examples, the III-nitride semiconductor structure includes one or more cap layers. In some examples, the field plate is at least partially embedded within the one or more cap layers.

[0118] In some examples, the electric field reduction structure comprises an implanted region in the III-nitride semiconductor structure. In some examples, the implanted region is electrically coupled to a source contact. In some examples, the implanted region is electrically coupled to a drain contact.

[0119] In some examples, the implanted region comprises a plurality of implanted dopants, and the implanted dopants comprise silicon (Si), magnesium (Mg), fluorine (F), iron (Fe), carbon (C), tin (Sn), or oxygen (O). In some examples, the implanted region comprises about 1×10 18 dopant / cm 3 has a peak dopant concentration of less than

[0120] In some examples, the gate contact has a gate length of about 100 nm or greater.

[0121] In some examples, the transistor device includes a second field plate overlying the N-polar III-nitride semiconductor structure.

[0122] In some instances, the transistor devices are associated with operating frequencies below about 40 GHz.

[0123] In some examples, the transistor device further comprises a silicon carbide substrate.

[0124] In some examples, the transistor device is a high electron mobility transistor device.

[0125] Another exemplary embodiment of the present disclosure relates to a transistor device, the transistor device including an N-polar III-nitride semiconductor structure, the transistor device including a field plate overlying the N-polar III-nitride semiconductor structure.

[0126] In some examples, the N-polar III-nitride structure comprises a barrier layer and a channel layer overlying the barrier layer. w Ga 1-w N, w is in the range of about 0.1 to about 0.4, and the channel layer is Al x Ga 1-x N, where x is less than about 0.1. In some examples, the N-polar III-nitride semiconductor structure comprises one or more capping layers on the channel layer. In some examples, the one or more capping layers comprise a first capping layer and a second capping layer, and the first capping layer is Al y Ga 1-y N, y is in the range of about 0.1 to about 0.4, and the second cap layer is Al z Ga 1-z N, and w is less than about 0.1.

[0127] In some examples, the field plate is at least partially embedded within the second cap layer. In some examples, the field plate is at least partially embedded within the first cap layer and the second cap layer. In some examples, the second cap layer has a thickness in a range from about 250 angstroms to about 1000 angstroms.

[0128] In some examples, the field plate is electrically coupled to the source contact.

[0129] In some examples, the field plate has a laterally extending portion that overlaps at least a portion of the gate contact. In some examples, the field plate does not overlap the gate contact.

[0130] In some examples, the transistor device includes a dielectric layer between the field plate and the N-polar III-nitride semiconductor structure. In some examples, the field plate is directly on the III-nitride semiconductor structure and forms a Schottky contact with the III-nitride semiconductor structure.

[0131] In some examples, the transistor device comprises a gate contact having a gate length of about 100 nm or more, such as about 150 nm or more.

[0132] In some instances, the transistor devices are associated with operating frequencies below about 40 GHz.

[0133] In some examples, the transistor device further comprises a silicon carbide substrate.

[0134] In some examples, the transistor device is a high electron mobility transistor device.

[0135] Yet another exemplary aspect of the present disclosure relates to a transistor device. The transistor device includes a nitrogen-polar (N-polar) III-nitride semiconductor structure. The transistor device includes a source contact, a drain contact, and a gate contact. The transistor device includes an implanted region in the III-nitride semiconductor structure between the gate contact and the drain contact.

[0136] In some examples, the implanted region is electrically coupled to a source contact. In some examples, the implanted region is electrically coupled to a drain contact.

[0137] In some examples, the implanted region comprises a plurality of implanted dopants, and the implanted dopants comprise silicon (Si), magnesium (Mg), fluorine (F), iron (Fe), carbon (C), tin (Sn), or oxygen (O). In some examples, the implanted region comprises about 1×10 18 dopant / cm 3 has a peak dopant concentration of less than

[0138] In some examples, the III-nitride semiconductor structure comprises a nitrogen-polar III-nitride semiconductor structure. In some examples, the transistor device comprises a barrier layer and a channel layer. In some examples, the barrier layer comprises Al w Ga 1-w N, w is in the range of about 0.1 to about 0.4, and the channel layer is Al x Ga 1-x In some examples, the III-nitride semiconductor structure comprises a cap layer. In some examples, the cap layer comprises Al z Ga 1-z N, and z is less than about 0.1. In some examples, the cap layer has a thickness in a range from about 250 angstroms to about 1000 angstroms. In some examples, the implanted region is in the cap layer.

[0139] In some examples, the transistor device further comprises a field plate overlying the III-nitride semiconductor structure.

[0140] In some examples, the transistor device further comprises a silicon carbide substrate.

[0141] In some examples, the transistor device is a high electron mobility transistor device.

[0142] Yet another exemplary aspect of the present disclosure relates to a method for forming a transistor device, the method including forming an N-polar III-nitride semiconductor structure, the method including forming a field plate overlying at least a portion of the N-polar III-nitride semiconductor structure.

[0143] In some examples, the formation of an N-polar III-nitride semiconductor structure includes forming a barrier layer, and the barrier layer includes Al w Ga 1-w N, and w is in the range of about 0.1 to about 0.4, forming a channel layer on the barrier layer, the channel layer comprising Al x Ga 1-x N, where x is less than about 0.1, and forming a first cap layer on the channel layer, the first cap layer comprising Al y Ga 1-y N, y is in the range of about 0.1 to about 0.4, and forming a second cap layer on the first cap layer, the second cap layer comprising Al z Ga 1-z N, and w is less than about 0.1.

[0144] In some examples, forming the field plate creates a field plate within a recess in the second cap layer, hi some examples, forming the field plate creates a field plate within a recess in the first cap layer and the second cap layer.

[0145] In some examples, forming the field plate includes forming a dielectric layer on the N-polar III-nitride semiconductor structure and forming the field plate on the dielectric layer. In some examples, forming the field plate includes forming the field plate directly on the N-polar III-nitride semiconductor structure such that the field plate forms a Schottky contact with the N-polar III-nitride semiconductor structure.

[0146] In some examples, the method further comprises electrically coupling the field plate to a source contact of the transistor device.

[0147] Yet another exemplary aspect of the present disclosure relates to a method of forming a transistor device, the method including forming a III-nitride semiconductor structure, the method including implanting a dopant into a region of the III-nitride semiconductor structure to form an implanted region, and the method including forming a gate contact and a drain contact on the III-nitride semiconductor structure, with the implanted region between the gate contact and the drain contact.

[0148] In some examples, the method electrically couples the implanted region to a source contact of the transistor device. In some examples, the method electrically couples the implanted region to a drain contact of the transistor device.

[0149] In some examples, the dopant comprises one or more of silicon (Si), magnesium (Mg), fluorine (F), iron (Fe), carbon (C), tin (Sn), or oxygen (O). In some examples, the implantation of the dopant provides a peak dopant concentration in the implanted region of about 1×10 18 dopant / cm 3 The dopant is implanted so that the dopant concentration is less than 1000 .mu.m.

[0150] In some instances, forming the III-nitride semiconductor structure forms an N-polar III-nitride semiconductor structure.

[0151] While the present subject matter has been described in detail with reference to specific exemplary embodiments thereof, it will be appreciated that those skilled in the art, upon attaining the foregoing understanding, may readily make alterations, variations, and equivalents to such embodiments. Accordingly, the scope of the present disclosure is intended to be illustrative rather than limiting, and the disclosure of the present subject matter is not intended to exclude the inclusion of such modifications, variations, and / or additions to the present subject matter that would be readily apparent to those skilled in the art.

Claims

1. 1. A transistor device comprising: a nitrogen-polar (N-polar) Group III nitride semiconductor structure; a source contact, a drain contact, and a gate contact; an electric field reduction structure operable to reduce an electric field in a region between the gate contact and the drain contact in the N-polar III-nitride semiconductor structure.

2. 10. The transistor device of claim 1, The transistor device, wherein the electric field reduction structure comprises a field plate overlying the N-polar III-nitride semiconductor structure.

3. 3. The transistor device of claim 2, The field plate is electrically coupled to the source contact.

4. 3. The transistor device of claim 2, The field plate has a laterally extending portion that overlaps at least a portion of the gate contact.

5. 3. The transistor device of claim 2, The transistor device, wherein the field plate does not overlap the gate contact.

6. 3. The transistor device of claim 2, The transistor device further comprising a dielectric layer between the field plate and the N-polar III-nitride semiconductor structure.

7. 7. The transistor device of claim 6, The transistor device, wherein the field plate is at least partially embedded within the N-polar Group III-nitride semiconductor structure.

8. 3. The transistor device of claim 2, A transistor device wherein the field plate is directly above the III-nitride semiconductor structure and forms a Schottky contact with the III-nitride semiconductor structure.

9. 9. The transistor device of claim 8, The transistor device, wherein the field plate is at least partially embedded within the N-polar Group III-nitride semiconductor structure.

10. 3. The transistor device of claim 2, The N-polar III-nitride semiconductor structure comprises a barrier layer and a channel layer on the barrier layer.

11. 11. The transistor device of claim 10, The N-polar Group III-nitride semiconductor structure comprises one or more cap layers.

12. 12. The transistor device of claim 11, The transistor device, wherein the field plate is at least partially embedded within the one or more cap layers.

13. 10. The transistor device of claim 1, The transistor device, wherein the electric field reduction structure comprises an implanted region in the III-nitride semiconductor structure.

14. 14. The transistor device of claim 13, The implanted region is electrically coupled to the source contact.

15. 14. The transistor device of claim 13, The implanted region is electrically coupled to the drain contact.

16. 14. The transistor device of claim 13, 1. A transistor device, wherein the implanted region comprises a plurality of implanted dopants, the implanted dopants comprising silicon (Si), magnesium (Mg), fluorine (F), iron (Fe), carbon (C), tin (Sn), or oxygen (O).

17. 14. The transistor device of claim 13, The implanted area is approximately 1×10 １８ Dopant / cm ３ a transistor device having a peak dopant concentration of less than

18. 10. The transistor device of claim 1, The transistor device, wherein the gate contact has a gate length of about 100 nm or greater.

19. 12. The transistor device of claim 11, The transistor device comprises a second field plate overlying the N-polar III-nitride semiconductor structure.

20. 10. The transistor device of claim 1, The transistor device is associated with an operating frequency of less than about 40 GHz.

21. 10. The transistor device of claim 1, The transistor device further comprises a silicon carbide substrate.

22. 10. The transistor device of claim 1, The transistor device is a high electron mobility transistor device.

23. 1. A transistor device comprising: a nitrogen-polar (N-polar) Group III nitride semiconductor structure; a field plate overlying the N-polar III-nitride semiconductor structure.

24. 24. The transistor device of claim 23, The N-polar III-nitride structure comprises a barrier layer and a channel layer on the barrier layer.

25. 25. The transistor device of claim 24, The barrier layer is Al ｗ Ga １－ｗ N, w ranging from about 0.1 to about 0.4; The channel layer is made of Al ｘ Ga １－ｘ N, where x is less than about 0.

1.

26. 26. The transistor device of claim 25, The N-polar III-nitride semiconductor structure comprises one or more cap layers on the channel layer.

27. 27. The transistor device of claim 26, The one or more cap layers include a first cap layer and a second cap layer, the first cap layer being Al ｙ Ga １－ｙ N, y is in the range of about 0.1 to about 0.4, and the second cap layer is Al ｚ Ga １－ｚ N, and w is less than about 0.

1.

28. 28. The transistor device of claim 27, The field plate is at least partially embedded in the second cap layer.

29. 28. The transistor device of claim 27, The field plate is at least partially embedded within the first cap layer and the second cap layer.

30. 28. The transistor device of claim 27, The transistor device, wherein the second cap layer has a thickness in the range of about 250 angstroms to about 1000 angstroms.

31. 24. The transistor device of claim 23, The field plate is electrically coupled to a source contact.

32. 32. The transistor device of claim 31 , The field plate has a laterally extending portion that overlaps at least a portion of a gate contact.

33. 32. The transistor device of claim 31 , A transistor device, wherein the field plate does not overlap a gate contact.

34. 24. The transistor device of claim 23, The transistor device further comprising a dielectric layer between the field plate and the N-polar III-nitride semiconductor structure.

35. 24. The transistor device of claim 23, A transistor device wherein the field plate is directly above the III-nitride semiconductor structure and forms a Schottky contact with the III-nitride semiconductor structure.

36. 24. The transistor device of claim 23, The transistor device comprises a gate contact having a gate length of about 100 nm or greater.

37. 37. The transistor device of claim 36, The transistor device comprises a gate contact having a gate length of about 150 nm or greater.

38. 24. The transistor device of claim 23, The transistor device is associated with an operating frequency of less than about 40 GHz.

39. 24. The transistor device of claim 23, The transistor device further comprises a silicon carbide substrate.

40. 24. The transistor device of claim 23, The transistor device is a high electron mobility transistor device.

41. 1. A transistor device comprising: a group III nitride semiconductor structure; a source contact, a drain contact, and a gate contact; an implanted region within the III-nitride semiconductor structure in a region between the gate contact and the drain contact.

42. 42. The transistor device of claim 41, The implanted region is electrically coupled to the source contact.

43. 42. The transistor device of claim 41, The implanted region is electrically coupled to the drain contact.

44. 42. The transistor device of claim 41, 1. A transistor device, wherein the implanted region comprises a plurality of implanted dopants, the implanted dopants comprising silicon (Si), magnesium (Mg), fluorine (F), iron (Fe), carbon (C), tin (Sn), or oxygen (O).

45. 42. The transistor device of claim 41, The implanted area is approximately 1×10 １８ Dopant / cm ３ a transistor device having a peak dopant concentration of less than

46. 42. The transistor device of claim 41, The transistor device, wherein the III-nitride semiconductor structure comprises a nitrogen-polar III-nitride semiconductor structure.

47. 42. The transistor device of claim 41, The transistor device comprises a barrier layer and a channel layer.

48. 48. The transistor device of claim 47, The barrier layer is Al ｗ Ga １－ｗ N, w ranging from about 0.1 to about 0.4; The channel layer is made of Al ｘ Ga １－ｘ N, where x is less than about 0.

1.

49. 48. The transistor device of claim 47, The III-nitride semiconductor structure comprises a cap layer.

50. 50. The transistor device of claim 49, The cap layer is Al ｚ Ga １－ｚ N, and z is less than about 0.

1.

51. 51. The transistor device of claim 50, The cap layer has a thickness in the range of about 250 angstroms to about 1000 angstroms.

52. 51. The transistor device of claim 50, The implanted region is in the cap layer.

53. 51. The transistor device of claim 50, The transistor device further comprising a field plate overlying the III-nitride semiconductor structure.

54. 42. The transistor device of claim 41, The transistor device further comprises a silicon carbide substrate.

55. 42. The transistor device of claim 41, The transistor device is a high electron mobility transistor device.

56. 1. A method of forming a transistor device, comprising: forming a nitrogen-polar (N-polar) Group III nitride semiconductor structure; forming a field plate overlying at least a portion of the N-polar III-nitride semiconductor structure.

57. 57. The method of claim 56, The formation of the N-polar Group III nitride semiconductor structure includes: A barrier layer is formed, and the barrier layer is Al ｗ Ga １－ｗ N, w ranging from about 0.1 to about 0.4; A channel layer is formed on the barrier layer, and the channel layer is made of Al ｘ Ga １－ｘ N, where x is less than about 0.1; A first cap layer is formed on the channel layer, and the first cap layer is Al ｙ Ga １－ｙ N, y ranging from about 0.1 to about 0.4; A second cap layer is formed on the first cap layer, and the second cap layer is Al ｚ Ga １－ｚ N, and w is less than about 0.

1.

58. 58. The method of claim 57, The method, wherein forming a field plate creates a field plate in a recess in the second cap layer.

59. 58. The method of claim 57, The method, wherein forming a field plate comprises forming a field plate in a recess in the first cap and second cap layers.

60. 57. The method of claim 56, The formation of the field plate is forming a dielectric layer on the N-polar Group III nitride semiconductor structure; forming the field plate on the dielectric layer.

61. 57. The method of claim 56, The method of claim 1, wherein forming a field plate comprises forming a field plate directly on the N-polar III-nitride semiconductor structure such that the field plate forms a Schottky contact with the N-polar III-nitride semiconductor structure.

62. 57. The method of claim 56, The method further comprises electrically coupling the field plate to a source contact of the transistor device.

63. 1. A method of forming a transistor device, comprising: forming a Group III nitride semiconductor structure; implanting a dopant into a region of the III-nitride semiconductor structure to form an implanted region; forming a gate contact and a drain contact on the III-nitride semiconductor structure such that the implanted region is between the gate contact and the drain contact.

64. 64. The method of claim 63, electrically coupling the implanted region to a source contact of the transistor device.

65. 64. The method of claim 63, The method further comprises electrically coupling the implanted region to the drain contact of the transistor device.

66. 64. The method of claim 63, The method, wherein the dopant comprises one or more of silicon (Si), magnesium (Mg), fluorine (F), iron (Fe), carbon (C), tin (Sn), or oxygen (O).

67. 64. The method of claim 63, The dopant implantation is performed to provide a peak dopant concentration in the implanted region of about 1×10 １８ Dopant / cm ３ The method further comprises implanting the dopant so that the dopant concentration is less than 1000 ppm.

68. 64. The method of claim 63, The method, wherein forming the Group III nitride semiconductor structure forms an N-polar Group III nitride semiconductor structure.

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