Bypassed gate transistor with improved stability

Abstract

The transistor device includes a plurality of gate fingers extending in a first direction and spaced apart from one another in a second direction, each of the gate fingers comprising at least first and second spaced apart, generally collinear gate finger segments electrically connected to one another, the first gate finger segment separated from the second gate finger segment in the first direction by a gap region extending in the second direction, and a resistor disposed in the gap region.

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 18 / 121,628, filed March 15, 2023, which is a continuation-in-part of U.S. Patent Application No. 17 / 492,032, filed October 1, 2021, which is in turn a continuation-in-part of U.S. Patent Application No. 16 / 907,983, filed June 22, 2020, which is in turn a continuation-in-part of U.S. Patent Application No. 16 / 182,642, filed November 7, 2018. 15 / 587,830, filed May 5, 2017, which claims priority under 35 U.S.C. §120 as a divisional application of U.S. patent application Ser. No. 15 / 587,830, filed May 5, 2017, which in turn claims priority under 35 U.S.C. §120 as a continuation-in-part of U.S. patent application Ser. No. 15 / 073,201, filed March 17, 2016, the entire contents of each of which are incorporated herein by reference.

[0002] The inventive concepts described herein relate to microelectronic devices, and more particularly to high-power, high-frequency transistors having unit cell-based structures. [Background technology]

[0003] Electrical circuits that require high power handling capabilities while operating at high frequencies, such as radio frequencies (500 MHz), S-band (3 GHz), and X-band (10 GHz), have become increasingly prevalent in recent years. The increase in high-power, high-frequency circuits has created a corresponding increase in demand for transistors that can handle higher power loads while still operating reliably at radio and microwave frequencies.

[0004] To provide increased output power, transistors with larger gate perimeters have been developed. One technique for increasing the effective gate perimeter of a transistor is to provide multiple transistor cells connected in parallel. For example, a high-power transistor may include multiple gate fingers extending in parallel between respective elongated source and drain contacts, as illustrated in FIG.

[0005] In particular, FIG. 1 illustrates a metal layout of a conventional transistor structure 10, including a gate pad 12, a source pad 22, and a drain pad 32 on a semiconductor structure 20. FIG. 1 is a plan view (i.e., a top-down view) of the device. As shown in FIG. 1, in conventional transistor 10, gate pad 12 is connected by gate bus 14 to multiple gate fingers 16 that extend parallel in a first direction (e.g., the y-direction indicated in FIG. 1). Source pad 22 is connected to multiple parallel source contacts 26 via source bus 24, and drain pad 32 is connected to multiple drain contacts 36 via drain bus 34. Each gate finger 16 extends along the y-direction between a pair of adjacent source and drain contacts 26, 36. A unit cell of transistor 10 is illustrated by box 40 and includes a gate finger 16 that extends between adjacent source and drain contacts 26, 36. "Gate length" refers to the distance of the gate metallization in the x-direction, while "gate width" is the distance that the source and drain contacts 26, 36 overlap in the y-direction. That is, the "width" of a gate finger 16 refers to the dimension of the gate finger 16 that extends parallel to adjacent source / drain contacts 26, 36 (the distance along the y-direction). The gate perimeter of a device refers to the sum of the gate widths of each gate finger 16 of the device 10.

[0006] In addition to adding unit cells, the gate perimeter of a multi-cell transistor device may be increased by making the gate fingers wider (i.e., longer in the y-direction). Wider gate fingers in a device, however, can adversely affect the high-frequency performance of the device. Also, making the gate fingers wider usually means that the gate fingers must handle increased current densities, which can cause electromigration of the gate finger metallization. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] US Patent Application Publication No. 2002 / 0066908 [Patent Document 2] US Patent Application Publication No. 2002 / 0167023 [Patent Document 3] US Publication No. 2004 / 0061129 [Patent Document 4] U.S. Patent No. 7,906,799 [Patent Document 5] U.S. Patent No. 6,316,793 [Patent Document 6] US Patent Application Publication No. 2003 / 0102482 Summary of the Invention

[0008] A transistor device according to some embodiments includes a source contact extending in a first direction, a gate finger extending in the first direction adjacent to the source contact, and a drain contact adjacent to the gate finger. The gate finger is between the drain contact and the source contact. A gate pad is electrically connected to the gate finger at multiple points along the gate finger.

[0009] The device further includes a gate jumper extending in the first direction and conductively connected to the gate pad, the gate pad being conductively connected through the gate jumper to at least one of a plurality of points along the gate finger.

[0010] The device may further include a gate bus connected to the gate jumper and the gate finger, and a gate signal distribution bar spaced from the gate bus in the first direction and connecting the gate jumper to the gate finger.

[0011] A transistor device according to a further embodiment includes a gate pad, a gate finger in conductive contact with the gate pad at a first location on the gate finger and extending in a first direction, and a gate jumper in conductive contact with the gate pad and extending in the first direction, the gate jumper conductively connected to the gate finger at a second location on the gate finger spaced from the first location such that a gate signal received at the gate pad is applied to the gate finger at both the first location and the second location.

[0012] A transistor device according to a further embodiment includes a gate bus, a gate finger in contact with the gate bus and extending in a first direction, and a gate jumper in contact with the gate bus and extending in the first direction, the gate jumper making conductive contact with the gate finger at a location along the gate finger that is spaced from the gate bus in the first direction.

[0013] A transistor device according to a further embodiment includes a substrate, a gate bus on the substrate, and first and second source contact segments on the substrate and extending in a first direction. The first and second source contact segments are separated from each other in the first direction by a gap. The device further includes a gate finger on the substrate and connected to the gate bus. The gate finger extends in the first direction adjacent to the source contact segments. The device further includes a drain contact on the substrate adjacent to the gate finger, the gate finger being between the drain contact and the source contact segment, a gate jumper connected to the gate bus, the gate jumper spanning the source contact segments and extending in the first direction, and a gate signal distribution bar on the substrate extending from the gap between the first and second source contact segments to the gate finger. A gate signal distribution bar contacts the gate fingers at a gate signal distribution point spaced from the gate bus in the first direction, the gate signal distribution bar being conductively connected to the gate jumper.

[0014] A transistor according to a further embodiment includes a drain contact extending along a first axis, a source contact extending along a second axis parallel to the first axis, gate fingers extending between the source and drain contacts, and a plurality of spaced apart gate resistors electrically connected to the gate fingers, wherein at least a first of the gate resistors is disposed in a portion of a region between the first and second axes that is between first and second ends of the gate fingers when the transistor is viewed from above.

[0015] In some embodiments, the gate finger may include a plurality of discontinuous, collinear gate finger segments electrically connected to one another. The transistor may further include a gate jumper electrically connected between the gate bus and a first one of the gate finger segments. A first gate resistor of the gate resistors may be inserted along an electrical path between the gate jumper and the first one of the gate finger segments. The transistor may also include a first gate signal distribution bar inserted along an electrical path between the gate jumper and the first one of the gate finger segments. A first gate resistor of the gate resistors may be inserted along an electrical path between the first gate signal distribution bar and the first one of the gate finger segments. Each gate finger segment may be part of a respective gate split, and the transistor may further include an odd-mode resistor positioned between two adjacent gate splits.

[0016] In some embodiments, the source contact includes a plurality of collinear, discontinuous source contact segments, and a gate jumper extends across the source contact. A first gate signal distribution bar may extend into a gap between two adjacent source contact segments. An odd-mode resistor may be interposed between the first gate signal distribution bar and a second gate signal distribution bar that is collinear with the first gate signal distribution bar. Additionally, the transistor may include a second source contact including a plurality of collinear, discontinuous source contact segments without a gate jumper extending across it, and an odd-mode resistor may be between two adjacent ones of the source contact segments of the second source contact.

[0017] According to yet a further embodiment, a transistor includes a source contact extending in a first direction, a gate jumper extending in the first direction, and a gate finger including a plurality of discontinuous gate finger segments that may be collinear with one another. The transistor further includes a plurality of spaced-apart gate resistors electrically connected to the gate jumper. A first one of the gate finger segments is connected to the gate jumper through a first one of the gate resistors.

[0018] In some embodiments, the source contact includes a plurality of discontinuous source contact segments, and a first one of the gate resistors is located in a gap between two adjacent source contact segments. A gate jumper may extend across at least some of the source contact segments. The transistor may further include a drain contact extending in a first direction adjacent to the gate finger such that the gate finger extends between the source contact and the drain contact, a second gate finger including a plurality of discontinuous, collinear gate finger segments extending in the first direction such that the drain contact extends between the gate finger and the second gate finger, and a second source contact including a plurality of discontinuous source contact segments extending in the first direction adjacent to the second gate finger. An odd-mode resistor may be provided in a gap between two adjacent source contact segments of the second source contact.

[0019] A gate signal distribution bar may extend between the gate jumper and a first one of the gate finger segments of the first gate finger and between the gate jumper and a first one of the gate finger segments of the second gate finger. The gate signal distribution bar may be disposed in a gap between two adjacent source contact segments of the source contact. An odd-mode resistor may be connected between the gate signal distribution bar and a second gate signal distribution bar connecting the gate finger segments of the plurality of additional gate fingers to the second gate jumper.

[0020] A transistor according to a further embodiment includes a plurality of gate fingers extending in a first direction and spaced apart from one another in a second direction perpendicular to the first direction, each of the gate fingers comprising at least spaced apart, generally collinear first and second gate finger segments, the first gate finger segment separated from the second gate finger segment in the first direction by a gap region extending in the second direction, and a resistor disposed within the gap region.

[0021] In some embodiments, the transistor further includes a plurality of source contacts extending in the first direction, each source contact including a plurality of discontinuous source contact segments, each source contact extending between a respective pair of gate fingers, and a plurality of drain contacts extending in the first direction, each drain contact extending between a respective pair of gate fingers. A gate bus may be electrically connected to the gate fingers, and a gate jumper may be electrically connected to the gate bus, the gate jumper being interposed along an electrical path between at least some of the gate finger segments and the gate bus.

[0022] In some embodiments, the resistor may be an odd-mode resistor positioned between two adjacent source contact segments of one of the source contacts. In other embodiments, the resistor may be a gate resistor inserted along the electrical path between the gate jumper and a first gate finger segment of a first one of the gate fingers. In these embodiments, the gate resistor may be inserted along a first gate signal distribution bar extending between the gate jumper and a first gate finger segment of a first one of the gate fingers.

[0023] According to a further embodiment of the present invention, there is provided a transistor comprising a semiconductor layer structure. A source contact, a drain contact, and a gate finger are formed on a top surface of the semiconductor layer structure, with the gate finger being positioned between the source contact and the drain contact. The transistor further comprises a gate jumper positioned above and spanning the source contact and electrically connected to at least a portion of the gate finger. The source contact extends continuously over the top surface of the semiconductor layer structure without any gaps dividing the source contact into segments.

[0024] In some embodiments, a gate finger may include multiple discontinuous gate finger segments.

[0025] In some embodiments, the transistor further comprises a gate bus, and at least one of the discontinuous gate finger segments is electrically connected to the gate bus through a gate jumper.

[0026] In some embodiments, the source contacts may be on a first major surface of the semiconductor layer structure, and the transistor may further comprise a source bus layer on a second major surface of the semiconductor layer structure, and a plurality of source contact plugs extending through the semiconductor layer structure to electrically connect the source contacts to the source bus layer.

[0027] In some embodiments, the source contact may include at least a first widened portion, a second widened portion, and a narrowed portion physically and electrically connecting the first widened portion to the second widened portion, and the first and second widened portions may be wider than the narrowed portion in a direction perpendicular to a longitudinal axis of the source contact and parallel to a bottom surface of the semiconductor layer structure.

[0028] In some embodiments, the transistor may further include a gate signal distribution bar above the semiconductor layer structure at the same height as the gate jumper, the gate signal distribution bar extending from the gate jumper toward the gate finger. In some embodiments, the gate signal distribution bar is interposed in an electrical path between the gate jumper and at least a portion of the gate finger. In some embodiments, the gate signal distribution bar may be electrically connected to the gate finger by a conductive via.

[0029] In some embodiments, the transistor may further comprise a series gate resistor inserted in the electrical path connecting the gate bus to the gate signal distribution bar.

[0030] In some embodiments, a longitudinal axis of the source contact, a longitudinal axis of the drain contact, and a longitudinal axis of the gate finger each extend in a first direction.

[0031] According to a further embodiment of the present invention, there is provided a transistor comprising a semiconductor layer structure, a source contact extending in a first direction on an upper surface of the semiconductor layer structure, a drain contact extending in the first direction on the upper surface of the semiconductor layer structure, and a gate finger extending in the first direction on the upper surface of the semiconductor layer structure, the gate finger being positioned between the source contact and the drain contact, wherein one of the source contact and the drain contact includes first and second widened portions on the upper surface of the semiconductor layer structure that are physically and electrically connected to each other by a narrowed portion.

[0032] In some embodiments, the source contact may include first and second widened portions and a narrowed portion, the first and second widened portions being wider than the narrowed portion in a direction perpendicular to a longitudinal axis of the source contact and parallel to a bottom surface of the semiconductor layer structure.

[0033] In some embodiments, the transistor may further comprise a gate bus and a gate jumper electrically connected to the gate bus, the gate jumper being positioned above and across the source contact, and at least a portion of the gate finger being electrically connected to the gate bus through the gate jumper.

[0034] In some embodiments, the gate finger may be a plurality of discontinuous gate finger segments.

[0035] In some embodiments, the transistor may further include a gate signal distribution bar formed in the same metal layer as the gate jumper, the gate signal distribution bar extending from the gate jumper toward the gate finger. In some embodiments, the gate signal distribution bar may be electrically connected to at least a portion of the gate finger by a vertical contact plug.

[0036] In some embodiments, a plane that is perpendicular to the longitudinal axis of the gate jumper and perpendicular to the plane defined by the bottom surface of the semiconductor layer structure may extend through both the narrow portion of the source contact and the vertical contact plug.

[0037] In some embodiments, the transistor may further comprise a series gate resistor inserted in the electrical path connecting the gate bus to the gate signal distribution bar.

[0038] In some embodiments, the transistor may further comprise a source bus layer and a plurality of source contact plugs electrically connecting the source contacts to the source bus layer.

[0039] In some embodiments, a first of the discontinuous gate finger segments may be electrically connected to the gate bus through a series gate resistor or may not be electrically connected to the gate bus through a gate jumper.

[0040] According to yet a further embodiment of the present invention, there is provided a transistor comprising: a semiconductor layer structure; a source contact extending in a first direction on an upper surface of the semiconductor layer structure; a drain contact extending in the first direction on the upper surface of the semiconductor layer structure; a gate finger extending in the first direction on the upper surface of the semiconductor layer structure, the gate finger being positioned between the source contact and the drain contact and comprising a plurality of discontinuous gate finger segments; a gate bus; a gate jumper electrically connected to the gate bus, the gate jumper having a longitudinal axis extending in the first direction and positioned above the source contact; and a gate signal distribution bar formed in the same metal layer as the gate jumper, the gate signal distribution bar extending from the gate jumper toward a first discontinuous one of the discontinuous gate finger segments.

[0041] In some embodiments, the source contact includes first and second widened portions on the top surface of the semiconductor layer structure that are physically and electrically connected to one another by a narrowed portion, a gate jumper is positioned above the source contact, and a first discontinuous gate finger segment of the discontinuous gate finger segments is electrically connected to a gate bus through the gate jumper.

[0042] In some embodiments, the gate signal distribution bar may be electrically connected to a first of the discontinuous gate finger segments by a vertical contact plug.

[0043] In some embodiments, a plane that is perpendicular to the longitudinal axis of the gate jumper and perpendicular to the plane defined by the bottom surface of the semiconductor layer structure may extend through both the narrow portion of the source contact and the vertical contact plug.

[0044] In some embodiments, the transistor may further comprise a series gate resistor inserted in the electrical path connecting the gate bus to the gate signal distribution bar, hi some embodiments, the series gate resistor may be implemented as part of the gate jumper.

[0045] In some embodiments, the transistor may further comprise a series gate resistor inserted in the electrical path connecting the gate bus to the gate signal distribution bar.

[0046] In some embodiments, a second of the discontinuous gate finger segments may be electrically connected to the gate bus through a series gate resistor, or may not be electrically connected to the gate bus through a gate jumper.

[0047] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate certain embodiments of the invention. [Brief explanation of the drawings]

[0048] [Figure 1] FIG. 1 is a plan view of a metal layout of a conventional multi-cell transistor. [Figure 2] FIG. 2 is a plan view of a metal layout of a transistor according to some embodiments. [Figure 3] FIG. 3 is a partial isometric view of the transistor of FIG. 2. [Figure 4] 3 is a partial cross-sectional view of the transistor of FIG. 2 taken along line A-A' of FIG. 2; [Figure 5] FIG. 3 is a plan view of an enlarged version of the transistor of FIG. 2. [Figure 6] FIG. 6 is a detailed plan view of a small portion of the transistor of FIG. 5. [Figure 7] 3 is a cross-sectional view of a unit cell of the transistor device taken along line B-B' in FIG. 2. [Figure 8] FIG. 10 is a plan view of a metal layout of a transistor according to a further embodiment. [Figure 9A] 9 is a partial cross-sectional view taken along line AA' of FIG. 8. [Figure 9B] FIG. 9 is a partial cross-sectional view taken along line BB' in FIG. 8. [Figure 10] FIG. 9 is a plan view of an enlarged version of the transistor of FIG. 8. [Figure 11] FIG. 11 is a detailed plan view of a small portion of the transistor of FIG. [Figure 12] FIG. 10 is a plan view of a metal layout of a transistor according to an additional embodiment. [Figure 13] FIG. 10 is a plan view of a metal layout of a transistor according to yet an additional embodiment. [Figure 14] FIG. 10 is a plan view of a metal layout of a transistor according to yet a further embodiment. [Figure 15] FIG. 10 is a plan view of a metal layout of a transistor according to an additional embodiment. [Figure 16] FIG. 10 is a plan view of a metal layout of a transistor according to a still further embodiment of the present invention. [Figure 17] FIG. 10 is a plan view of a metal layout of a transistor according to a still further embodiment of the present invention. [Figure 18] FIG. 10 is a plan view of a metal layout of a transistor according to a still further embodiment of the present invention. [Figure 19] FIG. 10 is a plan view of a metal layout of a transistor according to a still further embodiment of the present invention. [Figure 20] FIG. 10 is a plan view of a metal layout of a transistor according to a still further embodiment of the present invention. [Figure 21] FIG. 10 is a plan view of a metal layout of a transistor according to a still further embodiment of the present invention. [Figure 22] FIG. 10 is a plan view of a metal layout of a transistor according to a still further embodiment of the present invention. [Figure 23] FIG. 10 is a plan view of a metal layout of a transistor according to a still further embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0049]

[0013] Exemplary embodiments of the inventive concepts are described more fully below with reference to the accompanying drawings, in which embodiments of the invention are shown. The inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concepts to those skilled in the art. Like numbers refer to like elements throughout the specification.

[0050] Embodiments of the inventive concepts provide multi-cell transistor devices with large effective gate widths. By providing gate signals to gate fingers at multiple locations along their widths, the high-frequency gain performance of the transistor may be improved and electromigration concerns typically associated with wide gate fingers may be mitigated. According to some embodiments, larger gate widths of multi-cell transistor devices may be accommodated by adding a second metal layer over the source regions of the unit cells to act as gate jumpers. The gate jumpers are connected to the gate fingers at various locations along the gate fingers, effectively dividing the gate fingers into multiple segments. The gate jumpers may be provided by a second metal layer extending over and above the source contacts connecting the gate pads to the gate segments. In some embodiments, the gate jumpers may extend over and above the drain contacts or gate fingers instead of over and above the source contacts.

[0051] By effectively dividing the gate fingers into segments and using gate jumpers to distribute the gate signal to each of the gate finger segments, the gain performance of the transistor may be improved and electromigration concerns may be mitigated.

[0052] Thus, an embodiment of the inventive concept provides a transistor layout that defines multiple unit cells in series per gate finger. Respectively, each of the unit cells has a shorter effective gate width. However, when connected in series, the unit cells can increase the effective length of a single gate finger. The gate fingers of the series-connected unit cells are connected to a gate bus using a second metal bridge that spans the source contacts of the unit cells. The metal bridge spans along the surface of the substrate between the source contacts and connects between the source contacts to a connection bar that connects to the gate fingers.

[0053] A transistor having a layout as described herein may have higher frequency performance and higher output power while simultaneously reducing current density, which can improve device reliability.

[0054] According to further embodiments of the present invention, a multi-cell transistor having a large effective gate width is provided in which multiple series gate resistors (also referred to herein as "gate resistors") are distributed throughout the device. For example, the transistor may have segmented gate fingers, with a series gate resistor provided for each gate finger segment or pair of gate finger segments. This approach eliminates long feedback loops within the gate fingers and drains of the transistor structure by making them sufficiently lossy to avoid high levels of instability. The distributed series gate resistors may be located, for example, in gap regions provided between the gate finger segments of the gate fingers.

[0055] Thus, in some embodiments, a transistor is provided that includes a drain contact extending along a first axis, a source contact extending along a second axis parallel to the first axis, and a gate finger extending between the source and drain contacts. The gate finger may comprise a plurality of physically discontinuous, collinear gate finger segments electrically connected to one another by one or more other structures (e.g., gate jumpers). The transistor further includes a plurality of spaced-apart gate resistors electrically connected to the gate finger. At least one of the gate resistors is disposed in a portion of a region between the first and second axes that is between the first and second ends of the gate finger when viewed from above the transistor. In some embodiments, the gate jumper may be electrically connected to the gate finger, and the gate jumper may be electrically connected to a gate bus. A gate jumper may be inserted along an electrical path between a first one of the gate finger segments and a gate bus, and a first one of the gate resistors may be inserted along the electrical path between the gate jumper and the first one of the gate finger segments.

[0056] In another embodiment, a transistor is provided that includes a source contact extending in a first direction, a gate jumper extending in the first direction, and a gate finger having a plurality of discontinuous gate finger segments extending in the first direction. The transistor further includes a plurality of spaced-apart gate resistors, each electrically connected to the gate jumper. A first one of the gate finger segments is connected to the gate jumper through a first one of the gate resistors.

[0057] In accordance with yet further embodiments of the present invention, a multi-cell transistor having a large effective gate width is provided in which multiple odd-mode resistors are distributed throughout the device. In an exemplary embodiment, the odd-mode resistors may be disposed within gap regions formed between "gate splits," where a gate split refers to a region where multiple gate finger segments extend parallel to one another. The odd-mode resistors may be distributed throughout these gap regions to further improve transistor stability. The gate resistors described above may also be located within these gap regions.

[0058] Accordingly, in an additional embodiment, a transistor is provided that includes a plurality of gate fingers extending in a first direction and spaced apart from one another in a second direction perpendicular to the first direction, each of the gate fingers comprising at least first and second spaced apart, generally collinear gate finger segments electrically connected to one another, the first gate finger segment separated from the second gate finger segment in the first direction by a gap region extending in the second direction. At least one resistor is disposed in the gap region. The at least one resistor may be an odd-mode resistor and / or a series gate resistor.

[0059] Transistors according to embodiments of the inventive concepts may have larger effective gate widths, support increased power density levels, and exhibit improved frequency response compared to conventional transistors. Furthermore, the gate series resistor and odd-mode resistor, if provided, may help prevent feedback loops that can generate unwanted signals at frequencies low enough to be near or within the operating frequency range of the transistor. Accordingly, the transistors may also exhibit improved stability and, therefore, have improved manufacturing yields and / or better reliability.

[0060] It will be appreciated that the embodiments described above may be combined in any manner. For example, a transistor may be provided that includes both a distributed gate resistor and a distributed odd-mode resistor. Similarly, a transistor with non-segmented gate fingers may include either or both a distributed gate resistor and a distributed odd-mode resistor.

[0061] An embodiment of the present invention will now be described in more detail with reference to Figures 2 to 15.

[0062] Figure 2 is a plan view of a metal layout of a transistor 100 according to some embodiments. The transistor is formed on a semiconductor structure 120 that includes one or more device epitaxial layers, which are described in more detail below. The layout in Figure 2 is simplified for ease of understanding and includes a gate pad 112 connected to a gate bus 114 and a drain pad 132 connected to a drain bus 134. Source pads and source buses are omitted from Figure 2 for clarity, but are illustrated in Figures 5 and 6.

[0063] A plurality of gate fingers 116 are connected to a gate bus 114 and extend in the y-direction. Similarly, a plurality of drain contacts 136 are connected to the drain bus 134 and extend parallel to and adjacent to each of the gate fingers 116. Although only four gate fingers 116 and three drain contacts 136 are illustrated in FIG. 2 , it will be appreciated that the transistor 100 may have many more gate fingers 116 and drain contacts 136, such that the transistor has many unit cells.

[0064] Source contacts 162 are also provided and extend in the y-direction parallel to adjacent ones of the gate fingers 116. The source contacts 162 are divided in the y-direction into respective source contact segments 162a, 162b, and 162c. The source contact segments may be connected using source contact bars 128 (FIG. 6) that extend laterally (in the x-direction) across the device structure. The source contact segments 162a, 162b, and 162c may also be connected by other means. For example, source contact plugs may be provided that electrically connect each source contact segment 162a, 162b, and 162c to a common conductive layer, for example, located at a lower level of the device.

[0065] Adjacent ones of the source contact segments 162a-162c are separated by a gap 162g. While Figure 2 illustrates three source contact segments 162a-162c per source contact 162, it will be appreciated that the inventive concepts are not limited to such a configuration and that a source contact 162 may include two or more source contact segments 162a-162c.

[0066] The gate fingers 116 may extend parallel to the source contacts 162 for the entire length of the source contacts 162. However, because the source contacts 162 are divided into source contact segments 162a-162c, the source contact segments 162a, 162b, and 162c define multiple series unit cells 40a, 40b, and 40c for each gate finger 116. That is, each gate finger 116 functions as a gate contact for multiple unit cells 40a, 40b, and 40c that are laid out in the direction in which the gate finger 116 extends (the y-direction) and define the width of the gate finger 116. Therefore, the total width that each gate finger 116 contributes to the overall gate perimeter of the device is equal to the distance that the gate finger 116 overlaps its adjacent source contact segments 162a, 162b, and 162c in the y-direction.

[0067] The transistor 100 further includes a plurality of gate jumpers 172 that extend along the y-direction parallel to the gate fingers 116. The gate jumpers 172 may be formed over the source contacts 162 and may be insulated from the source contacts 162 by, for example, a dielectric layer and / or an air gap. The gate jumpers 172 are electrically connected to the gate bus 114 and connect each gate finger 116 to the gate bus 114 at multiple locations along the gate finger 116.

[0068] In particular, gate jumpers 172 are provided at multiple locations along the width of the device and connect to gate fingers 116 through gate signal distribution bars 174 that extend laterally (x-direction) within gaps 162g between adjacent ones of source contact segments 162a, 162b, and 162c. The gate signal distribution bars 174 contact the gate fingers 116 at respective gate signal distribution points 176. Thus, an electrical signal ("gate signal") applied to gate pad 112 is carried to gate bus 114 and then to gate jumpers 172, which distribute the gate signal to gate fingers 116 at multiple locations (gate signal distribution points 176) along the width of gate fingers 116. Thus, in the embodiment of FIG. 2, rather than gate fingers 116 carrying the gate signal across the entire width of the device, the gate signal is carried across most of the width of the device by gate jumpers 172 and then distributed to gate fingers 116 at various locations along the width of the device.

[0069] Gate jumper 172 may have a larger cross-sectional area than gate finger 116 and therefore may be better able to handle higher current densities than gate finger 116 without the problems typically associated with increased gate width, such as electromigration and reduced high frequency gain performance.

[0070] Figure 3 is a partial isometric view of the metal layout of transistor 100, and Figure 4 is a partial cross-sectional view taken along line A-A' in Figure 2. As can be seen in Figures 3 and 4, gate jumper 172 is formed on a metal level higher than the metal level of source contact segments 162a, 162b, and 162c, gate fingers 116, gate bus 114, and gate signal distribution bar 174. Gate jumper 172 is connected to gate bus 114 and gate signal distribution bar 174 by vertical contact plug 178.

[0071] The gate jumpers 172, gate buses 114, vertical contact plugs 178, and gate signal distribution bars 174 may be formed from conductive materials such as copper or aluminum, which have very low resistance.

[0072] FIG. 5 is a plan view of an expanded version of transistor 100, and FIG. 6 is a detailed plan view of a small portion 150 of the metal layout of FIG. 5 (i.e., the portion within the dotted box in FIG. 5). Transistor 100 includes a plurality of unit cells 40 extending vertically (in the y-direction). Each unit cell 40 includes one gate finger 116 that extends across the entire width of the device and is subdivided into series unit cells 40a, 40b, and 40c arranged vertically (in the y-direction) as described above. In the example illustrated in FIGS. 5 and 6, each unit cell 40 has an overall width of 1120 microns, and series unit cells 40a, 40b, and 40c have widths of 370 microns, 380 microns, and 370 microns, respectively, although the inventive concept is not limited to these particular dimensions. In this manner, the effective gate width of the device may be increased.

[0073] 6, gate pad 112 and gate bus 114 are provided at one end of the structure, while drain pad 132 and drain bus 134 are provided at the other end of the structure. Source pad 122 is provided on a side of the structure and is connected to source bus 124. Source bus 124 is connected to a plurality of source contact bars 128, which extend laterally (x-direction) to contact source contact segments 162a, 162b, and 162c. As mentioned above, source contact segments 162a, 162b, and 162c may be electrically connected in other ways, such as through the use of source contact plugs that electrically connect each source contact segment 162a, 162b, and 162c to a common conductive layer.

[0074] The detailed view of portion 150 of the device layout of transistor 100 in FIG. 6 also illustrates gate fingers 116, gate jumpers 172, gate signal distribution bars 174, and gate signal distribution points 176 where gate signal distribution bars 174 contact gate fingers 116.

[0075] 7 is a cross-sectional view of a unit cell 40 of the transistor device 100 taken along line B-B' in FIG. 2. The transistor structure 100 includes a semiconductor structure 120 including a substrate 200, which may comprise, for example, 4H-SiC or 6H-SiC. A channel layer 210 is formed on the substrate 200, and a barrier layer 220 is formed on the channel layer 210. The channel layer 210 and the barrier layer 220 may comprise III-nitride-based materials, with the material of the barrier layer 220 having a higher bandgap than the material of the channel layer 210. For example, the channel layer 210 may comprise GaN, while the barrier layer 220 may comprise AlGaN.

[0076] Due to the bandgap difference between the barrier layer 220 and the channel layer 210 and the piezoelectric effect at the interface between the barrier layer 220 and the channel layer 210, a two-dimensional electron gas (2DEG) is induced in the channel layer 210 at the junction between the channel layer 210 and the barrier layer 220. The 2DEG acts as a highly conductive layer that enables conduction between the source and drain regions of the device directly below the source contact segment 162b and the drain contact 136, respectively. The source contact segment 162b and the drain contact 136 are formed on the barrier layer 220. The gate finger 116 is formed on the barrier layer 220 between the drain contact 136 and the source contact segment 162b. The gate jumper 172 spans the source contact segment 162b and is connected to the gate finger 116 through a vertical contact plug 178 and a gate signal distribution bar 174. Vertical contact plug 178 and gate signal distribution bar 174 are disposed in gap 162g between adjacent source contact segments 162a-162c and do not physically contact source contact segments 162a-162c. Note that source contact segment 162b is offset in the y-direction from the cross section along line B-B' (see FIG. 2) and is therefore not actually present in the cross section of FIG. 7, but is illustrated in FIG. 7 for ease of explanation above.

[0077] A first interlayer insulating layer 232 is formed over the drain contact 136, the gate fingers 116, the source contact segments 162b, and the gate signal distribution bar 174. The interlayer insulating layer 232 may include a dielectric material such as SiN or SiO2. A vertical contact plug 178 penetrates the first interlayer insulating layer 232. The gate jumper 172 is formed on the first interlayer insulating layer 232, and the first interlayer insulating layer 232 insulates the gate jumper 172 from the source contact segments 162b. A second interlayer insulating layer 234 may be formed over the first interlayer insulating layer 232 and the gate jumper 172. The second interlayer insulating layer 234 may include a dielectric material such as SiN or SiO2.

[0078] The material of the gate fingers 116 may be selected based on the composition of the barrier layer 220. However, in certain embodiments, conventional materials capable of making Schottky contacts to nitride-based semiconductor materials may be used, such as Ni, Pt, NiSix, Cu, Pd, Cr, W, and / or WSiN. The drain contact 136 and source contact segments 162 may include a metal, such as TiAlN, that can form an ohmic contact to GaN.

[0079] High-power transistors according to embodiments of the present invention may include series gate resistors and odd-mode resistors to stabilize feedback loops within the gate fingers and drain of the device. In high-power devices, gates may have long gate widths to increase the gate perimeter of the device, resulting in long feedback loops. Because these high-power transistors have large transconductance values, feedback loops may be prone to instability. In particular, feedback loops may generate unwanted signals that may be within or outside the frequency band of the transistor's operation. In either case, the generation of such signals can be problematic and render the transistor unusable. Feedback loop instability tends to increase with the length of the feedback loop.

[0080] According to further embodiments of the present invention, high-power transistors are provided that include multiple series gate resistors and / or odd-mode resistors distributed throughout the device, particularly along long gate fingers. Distributed series gate resistors and / or odd-mode resistors can be particularly advantageous in transistors with segmented gate fingers, as such devices may include gap regions between "gate splits" that are natural locations for placing series gate resistors and / or odd-mode resistors along the width of the gate fingers. As used herein, the term "gate split" refers to a shorter array of gate finger segments created when a long gate finger is segmented into multiple gate finger segments, as discussed above with reference to Figures 2-7. The gap regions present between adjacent gate splits may be convenient locations for implementing distributed series gate resistors and odd-mode resistors, as discussed in more detail below.

[0081] It has been found that by distributing series gate resistors and / or odd-mode resistors along the extended width of a gate finger, the feedback loop can become sufficiently lossy that potential instabilities can be overcome. Therefore, distributing series gate resistors and / or odd-mode resistors along the extended width of a gate finger can improve device yield or reduce device failure rates in the field. Furthermore, when series gate resistors and / or odd-mode resistors are distributed along and between gate finger segments of segmented gate fingers, relatively small resistance levels can be used. For example, if a transistor has three gate splits, the resistance level can be approximately one-third the size of the resistance level that would be used if the gate fingers were not segmented. Furthermore, in practice, the reduction in resistance value has been found to be even greater. For example, when three gate splits are used, the series resistor included along each gate segment can have a resistance value that is one-quarter to one-fifth the resistance value of the series gate resistor implemented on the gate pad. The use of resistors with low resistance reduces losses and therefore leads to the transistor having a higher gain while also exhibiting improved stability.

[0082] FIG. 8 is a plan (top) view of a metal layout of a transistor 300 according to a further embodiment, implementing both a series gate resistor and an odd-mode resistor in a distributed manner, as discussed above. The transistor 300 is formed on a semiconductor structure 320 that includes one or more device epitaxial layers. The semiconductor structure 320 may be the same as the semiconductor structure 120 discussed above with reference to FIG. 7. As with the previous figures, the layout of FIG. 8 is simplified for ease of understanding and includes a pair of gate pads 312 connected to a respective pair of gate buses 314, along with a drain pad 332 connected to a drain bus 334. A source pad 322 and a source bus are also included in the transistor 300 but are omitted from FIG. 8 for ease of illustration. The source pad 322 is shown in FIG. 10.

[0083] A plurality of gate fingers 316 are connected to each gate bus 314 and extend in the y-direction. Each gate finger 316 is divided into three gate finger segments 316a, 316b, and 316c in the y-direction. As discussed below, the gate finger segments 316a, 316b, and 316c of each gate finger 316 may be electrically connected to one another via gate jumpers 372, gate signal distribution bars 374, and vertical contact plugs 378 (FIG. 9A). A plurality of drain contacts 336 are connected to the drain bus 334 and extend parallel to adjacent ones of the gate fingers 316. The gate signal distribution bars 374 may be formed at a different vertical level within the device than the gate distribution bars 174 of the transistor 100, allowing the gate signal distribution bars 374 to pass over the drain contacts 336, as discussed below. Source contacts 362 are also provided and extend parallel to adjacent ones of the gate fingers 316 in the y-direction. The source contacts 362 are also divided into respective source contact segments 362a, 362b, and 362c in the y-direction. The source contact segments 362a, 362b, and 362c may be electrically connected to one another via source contact plugs 364. Each source contact plug 364 may electrically connect the respective source contact segments 362a, 362b, and 362c to a common conductive layer that functions as a source bus. This source bus may be located, for example, at a lower level of the device. In some embodiments, multiple source contact plugs 364 may be provided for each source contact segment 362a, 362b, and 362c. In FIG. 8, two exemplary source contact plugs 364 are illustrated on one source contact segment 362c. The source contact plugs 364 for the other source contact segments 362a, 362b, 362c have been omitted from FIG. 8 (as well as from FIGS. 9A-9B and 12-13) to simplify the drawing.10 and 11 illustrate, for example, how a pair of source contact plugs 364 may be provided for each source contact segment 362a, 362b, and 362c. The source contact segments 362a, 362b, and 362c may also be electrically connected by other means, such as, for example, a source contact bar. In FIG. 8, a total of 16 segmented gate fingers 316, eight segmented source contacts 362, and eight drain contacts 336 are shown. However, it will be appreciated that the transistor 300 may have more gate fingers 316, source contacts 362, and drain contacts 336 such that the transistor 300 has a larger number of unit cells. In other embodiments, fewer gate fingers 316, source contacts 362, and drain contacts 336 may be provided.

[0084] Adjacent ones of gate finger segments 316a-316c are separated by gap 316g, and adjacent ones of source contact segments 362a-362c are separated by gap 362g. While Figure 8 illustrates three gate finger segments 316a-316c and three source contact segments 362a-362c for each gate finger 316 and source contact 362, the inventive concepts are not limited to such configuration. Thus, it will be appreciated that gate finger 316 may include more than one gate finger segment, and source contact 362 may include more than one source contact segment.

[0085] The gate fingers 316 may extend parallel to the source contacts 362 for the entire length of the source contacts 362. Because the gate fingers 316 and source contacts 362 are segmented, multiple unit cells 340a, 340b, and 340c are defined along each gate finger 316. That is, each gate finger segment 316a-316c functions as a gate contact for a respective unit cell 340a, 340b, and 340c laid out in the direction along which the gate fingers 316 extend (the y-direction). The sum of the widths of the gate finger segments 316a-316c defines the total width of each gate finger 316. Therefore, the total width that each gate finger 316 contributes to the overall gate perimeter of the device is equal to the sum of the widths of the gate finger segments 316a-316c in the y-direction.

[0086] The transistor 300 further includes a plurality of gate jumpers 372 extending along the y-direction parallel to the gate fingers 316. The gate jumpers 372 may be formed on a metal level higher than the metal levels of the source contact segments 362, the gate fingers 316, and the gate bus 314. The gate jumpers 372 may be formed across the source contacts 362 or may be insulated from the source contacts 362 by, for example, a dielectric layer and / or an air gap. The gate jumpers 372 need not extend across the source contact segment 362c, which is farthest from the gate bus 314. The gate jumpers 372 are electrically connected to the gate bus 314. The gate jumpers 372 may electrically connect some or all of the gate finger segments 316a-316c of each gate finger 316 to one of the gate buses 314. 8, each gate jumper 372 electrically connects gate finger segments 316b and 316c to gate bus 314, while gate finger segment 316a is connected to gate bus 314 via a more direct connection. Gate finger segment 316a may be connected to gate bus 314 through gate jumper 372 in other embodiments. In some embodiments, gate jumper 372 may be positioned across drain contact 336 or gate finger 316 instead of across source contact 362.

[0087] FIG. 9A is a partial cross-sectional view taken along line A-A' in FIG. 8. FIG. 9B is a partial cross-sectional view taken along line B-B' in FIG. 8. As can be seen in FIGS. 8 and 9A, a plurality of gate jumpers 372, gate signal distribution bars 374, and vertical contact plugs 378 are provided. The gate jumpers 372 are connected to the gate bus 314 and the gate signal distribution bars 374 by the vertical contact plugs 378. The gate jumpers 372, gate signal distribution bars 374, and vertical contact plugs 378 are used to connect each gate finger segment 316b-316c to one of the gate buses 314. The gate signal distribution bars 374 may be formed in a higher metal layer within the device than the gate fingers 316. For example, the gate signal distribution bars 374 may be formed in the same metal layer of the device as the gate jumpers 372, as shown in FIG. 9A. A vertical contact plug 378 may connect the gate jumper 372 to the gate bus 314. Additional vertical contact plugs 378 (not visible in the cross-sectional view of FIG. 9A but located at the point where each gate signal distribution bar passes across a gate resistor 380 in the plan view of FIG. 8) may physically and electrically connect the gate signal distribution bar 374 to the gate resistors and the gate finger segments 316a-316c connected to the gate resistors. As mentioned above, the gate jumpers 372 may extend across and above the source contacts 362. As can be seen in FIG. 8, the gate jumpers 372 are located across every other source contact 362, in contrast to the transistor 100 of FIGS. 2-7, which included gate jumpers 172 extending across every source contact 162. Each gate jumper 372 of transistor 300 of FIGS. 8-9B therefore feeds four gate fingers 316 instead of two gate fingers 116 as in the case of transistor 100.The gate signal distribution bars 374 are formed in a higher metal layer within the device than the gate distribution bars 174 of transistor 100 to allow each gate signal distribution bar 374 to pass over two drain contacts 336 to connect to the outer gate finger segments of the four gate finger segments 316a-316c.

[0088] The gate jumpers 372, gate buses 314, vertical contact plugs 378, and gate signal distribution bars 374 may be formed from conductive materials such as copper or aluminum, which have very low resistance.

[0089] 8 and 9A, gate signal distribution bars 374 extend laterally (in the x-direction) within gaps 362g between adjacent ones of source contact segments 362a, 362b, and 362c. The gate signal distribution bar 374 coupled to the first gate finger segment 316a may be coupled to two of the gate finger segments 316a. Each of the gate signal distribution bars 374 coupled to the second or third gate finger segments 316b, 316c may be coupled to four of the gate finger segments 316b or 316c. As can be seen in FIG. 8, each gate signal distribution bar 374 coupled to the first gate finger segment 316a may be connected to one of the gate buses 314 through a gate resistor 380. The gate signal distribution bar 374 coupled to gate finger segment 316a may be part of the same metal layer as the gate fingers 316, since these gate signal distribution bars 374 do not need to cross the drain contact 336, or may be part of the same metal layer as the gate jumpers 372. Each gate signal distribution bar 374 coupled to either the second gate finger segment 316b or the third gate finger segment 316c may connect to one of the gate buses 314 through one of the gate jumpers 372, or may connect to the gate finger segment 316b, 316c through a respective vertical contact plug 378, as can be seen in Figures 8 and 9A. A series gate resistor 380 is provided in the electrical path between each gate finger segment 316b, 316c and its associated gate signal distribution bar 374.

[0090] 8 and 9A, the distribution of an electrical signal applied to the left gate pad 312 in FIG. 8 to the left-most gate finger segments 316a, 316b, 316c in FIG. 8 will now be discussed. When a gate signal is applied to the gate pad 312, the gate signal is carried to the left gate bus 314. The gate signal travels from the left gate bus 314 through a first gate signal distribution bar 374 and a first series gate resistor 380 to the first gate finger segment 316a. Gate signals also travel from the left gate bus 314 through a first vertical contact plug 378 connecting the gate bus 314 to the gate jumper 372, through the gate jumper 372 to a second gate signal distribution bar 374, and through the second gate signal distribution bar 374 to the second vertical contact plug 378 connecting to the leftmost second gate finger segment 316 b through a second series gate resistor 380. Similarly, gate signals travel from the left gate bus 314 through the first vertical contact plug 378 to the gate jumper 372, through the gate jumper 372 to a third gate signal distribution bar 374, and through the third gate signal distribution bar 374 to the third vertical contact plug 378 connecting to the leftmost third gate finger segment 316 c through a third series gate resistor 380.

[0091] 8 and 9A, the gate signal does not travel along the entire length of any gate finger 316, but instead travels only along the length of the gate finger segment (e.g., gate finger segment 316a), or along the length of the gate finger segment and a portion of the gate jumper 372 (e.g., gate finger segment 316b), or along the length of the gate finger segment and the entire length of the gate jumper 372 (e.g., gate finger segment 316c). The gate jumper 372 may have a larger cross-sectional area than the gate fingers 316 and may therefore be better able to handle higher current densities than the gate fingers 316 without the problems typically associated with increased gate width, such as electromigration and reduced high-frequency gain performance. The gate signal also travels along a portion of the gate signal distribution bar 374 and vertical contact plug 378. It should be noted, however, that Figure 8 is not drawn to scale, and that the distance that a gate signal travels along any gate signal distribution bar 374 may be very short (e.g., less than 5%) compared to the length of the gate finger segment in the y-direction, as can be seen in Figures 10-11. The distance traveled along the vertical contact plug 378 is also very short. Thus, the distance that a gate signal travels along a narrow conductive trace may be reduced.

[0092] As discussed above, transistor 300 includes multiple series gate resistors 380 distributed throughout the device. In particular, a series gate resistor 380 is provided at or near one end of each gate finger segment 316a, 316b, 316c. As shown in FIG. 8 , gate finger 316 is divided into three “gate splits”: a first gate split 382a comprising gate finger segment 316a, a second gate split 382b comprising gate finger segment 316b, and a third gate split 382c comprising gate finger segment 316c. A first gap region 384a is provided between the gate bus 314 and the first gate split 382a, a second gap region 384b is provided between the gate splits 382a and 382b, and a third gap region 384c is provided between the gate splits 382b and 382c.

[0093] As shown in FIG. 8 , series gate resistor 380 may be formed within gap regions 384a-384c described above. Series gate resistor 380 may be formed, for example, by depositing a conductive material with a higher resistivity compared to the conductive materials used to form gate finger 316, drain contact 336, source contact 362, etc. Series gate resistor 380 may be provided within any suitable vertical level of transistor 300. In one embodiment, series gate resistor 380 may be formed on the same metallization level as source contact 362, drain contact 336, and gate finger 316, as can be seen or inferred from FIGS. 8 and 9A . It will also be appreciated that gate resistor 380 (or odd-mode resistor 390, discussed below) may be replaced with other lossy elements that may be functionally equivalent to a resistor, such as, for example, a series inductor-capacitor circuit.

[0094] As discussed below with reference to FIG. 12 , instead of the distributed series gate resistors 380 included in transistors according to certain embodiments of the present invention, a single series gate resistor 80 may be provided between each gate pad 312 and its associated gate bus 314. When the series gate resistors are implemented as a single series gate resistor 80 between each gate pad 312 and its corresponding gate bus 314, each series gate resistor 80 may need to have a relatively high resistance to reduce or prevent device instability. In transistor 300, multiple series gate resistors 380 are positioned between the gate splits 382 of the device. Each of the gate resistors 380 may have a much smaller resistance than would be required if the gate resistors 80 were located only between the gate pad 312 and the gate bus 314.

[0095] In some embodiments, each gate finger segment 316a, 316b, 316c may have its own associated series gate resistor 380, while in other embodiments, some gate finger segments may share a series gate resistor 380. In the particular embodiment depicted in Figure 8, all of the gate finger segments 316b, 316c have their own associated series gate resistor 380, while the pair of gate finger segments 316a share a single series gate resistor 380. It will be appreciated that in other embodiments, some of the gate finger segments 316a-316c may not have an associated gate resistor 380.

[0096] By distributing the series gate resistors at two or more locations along the gate finger 316, the feedback loop within the gate finger and the transistor drain may be made sufficiently lossy that instability may be reduced or eliminated. This may improve device yield and / or reduce the incidence of device failure in the field. Furthermore, as discussed above, and as can be seen in FIG. 8 , the current path along any particular gate finger segment 316 a, 316 b, 316 c may pass through only a single series gate resistor 380. Because the series gate resistor 380 has a relatively small resistance, power loss is reduced, and the transistor 300 may therefore support higher gain levels for a given size device.

[0097] As can be seen in FIG. 8 , transistor 300 includes a drain contact 336 extending in the y-direction along a first axis, a source contact 362 extending in the y-direction along a second axis parallel to the first axis, and a gate finger 316 extending between source contact 362 and drain contact 336. Gate finger 316 includes a plurality of discontinuous, collinear gate finger segments 316 a, 316 b, 316 c electrically connected to one another. Transistor 300 further includes a plurality of spaced-apart gate resistors 380 electrically connected to gate finger 316. Each gate resistor 380 may be coupled between a respective one of gate finger segments 316 a, 316 b, 316 c and a respective one of gate signal distribution bars 374. At least one of gate resistors 380 is disposed between the first axis and the second axis. Gate jumpers 372 are inserted along the electrical paths between gate bus 314 and gate fingers 316. Gate jumpers 372 are inserted along the respective electrical paths between gate finger segments 316b and 316c and gate bus 314, and respective gate resistors 380 are inserted along the respective electrical paths between gate jumpers 372 and gate finger segments 316b, 316c.

[0098] 8, transistor 300 includes a source contact 362 extending in the y-direction, a gate jumper 372 extending in the y-direction, and a gate finger 316 comprising a plurality of discontinuous, electrically connected gate finger segments 316a, 316b, and 316c. Transistor 300 further includes a plurality of spaced-apart gate resistors 380. Gate finger segments 316b and 316c are connected to gate jumper 372 through respective first and second gate resistors 380. The pair of gate finger segments 316a are connected to gate bus 314 through respective gate resistors 380.

[0099] As further shown in FIG. 8 , the transistor 300 also includes odd-mode resistors 390. The odd-mode resistors 390 are provided to eliminate long odd-mode instability feedback loops within the device. In particular, instability can occur as the number of gate fingers 316 supplied by the gate jumpers 372 increases. For example, the transistor may be stable when the gate jumpers 372 supply four gate fingers 316, but may begin to exhibit instability when the gate jumpers 372 are used to supply eight gate fingers 316. The timing of instability may be a function of the gate finger width and the frequency of operation of the device. The odd-mode resistors 390 may be inserted between adjacent gate signal distribution bars 374. When the transistor 300 is operating normally, the voltage on both sides of each odd-mode resistor 390 should be the same, and therefore no current should flow between adjacent gate signal distribution bars 374.

[0100] The odd-mode resistor 390 may be disposed in the gap region 384 between adjacent gate splits 382. As shown in Figures 8 and 9B, the odd-mode resistor 390 may be implemented on the same metallization level as the gate signal distribution bar 374 and the source contact 362, for example, or may be directly connected between two adjacent gate distribution bars 374. The odd-mode resistor 390 may also be inserted between adjacent gate buses 314.

[0101] Thus, the transistor 300 may include a plurality of gate fingers 316 extending in the y-direction and spaced apart in the x-direction. Each gate finger 316 may include a plurality of spaced apart, generally collinear gate finger segments 316a, 316b, and 316c electrically connected to one another, with the gate finger segments 316a, 316b, and 316c disposed within respective gate splits 382a, 382b, and 382c separated by gap regions 384b and 384c. An odd-mode resistor 390 is disposed within the gap regions 384b and 384c. In an exemplary embodiment, the odd-mode resistor 390 may be interposed between adjacent gate signal distribution bars 374.

[0102] It will also be appreciated that in some embodiments, the source contacts 362 need not be segmented. In particular, the gate resistors 380 and odd-mode resistors may both be implemented in the same metal layer as the gate signal distribution bars 374 and gate jumpers 372. In such implementations, the source contacts 362 need not be segmented. Accordingly, it will be appreciated that in other embodiments, the resistors 380, 390 may be implemented directly above, or above and to the sides of, the source contacts 362, and each source contact 362 may be a single, continuous (i.e., non-segmented) source contact 362.

[0103] While FIG. 8 depicts a transistor 300 including segmented gate fingers 316 and segmented source contacts 362, it will be appreciated that embodiments of the present invention are not limited in this regard. For example, in other embodiments, the drain contacts 336 may be segmented in a similar manner, with each drain contact including, for example, three separate segments. When the drain contacts 336 are segmented, they may be electrically connected to each other, for example, via a drain contact plug and another metallization layer within the device. In embodiments in which the drain contacts are segmented, the source contacts 362 may or may not be segmented. Additionally, the gate fingers 316 may be segmented as shown in FIG. 8 or may not be segmented as shown in FIG. 2 (and FIGS. 14-15). Segmenting the drain contacts may provide additional space in the region between the gate splits for gate resistors 380 and / or odd-mode resistors 390. As a simple example of such an embodiment having a segmented drain contact 336, transistor 300 of Figure 8 may be modified so that reference numerals 332, 334, and 336 are source pad, source bus, and source contact, respectively, and reference numerals 362, 362a / 362b / 362c, and 364 are drain contact, drain contact segment, and drain contact plug, respectively. In other words, Figure 8 may also be viewed as an embodiment having segmented gate fingers 316 and segmented drain contact 362 by simply reversing the source and drain characteristics.

[0104] Figure 10 is a plan view of an enlarged version of transistor 300 of Figure 8. Figure 11 is a detailed plan view of a small portion 302 of transistor 300 of Figure 10.

[0105] 10-11, transistor 300 includes a plurality of unit cells extending vertically (in the y-direction). Each unit cell includes a gate finger 316 that extends across the entire width of the device and is subdivided into vertically (in the y-direction) arranged series unit cells 340a, 340b, and 340c as described above. In the embodiment illustrated in FIGS. 10 and 11, each of unit cells 340 has an overall width of 1120 microns, and series unit cells 340a, 340b, and 340c have widths of 370 microns, 380 microns, and 370 microns, respectively, although the inventive concepts are not limited to these particular dimensions.

[0106] A plurality of gate busses 314 are provided at one end of the structure, and a drain bus 334 is provided at the other end of the structure. Source pads 322 are provided on the sides of the structure and are connected to source busses located, for example, on an underlying metallization layer (not shown) of the device. Source contact segments 362a, 362b, and 362c are connected to the source busses via contact plugs 364.

[0107] The detailed view of portion 302 of the device layout of transistor 300 in FIG. 11 also illustrates gate finger 316, gate jumper 372, gate signal distribution bar 374, series gate resistor 380, and odd-mode resistor 390.

[0108] Transistors according to embodiments of the inventive concepts may include semiconductor structures that are multi-layered. For example, as discussed above with reference to FIG. 7 , semiconductor structure 120 of transistor 100 may include substrate 200 (e.g., 4H—SiC or 6H—SiC) having at least channel layer 210 and barrier layer 220 formed thereon. The same is true with respect to other transistors according to embodiments of the inventive concepts depicted herein. Thus, it will be appreciated that the discussion of semiconductor structure 120 in FIG. 7 applies equally to the semiconductor structures of each of the other embodiments described herein, although metallization and other aspects of the device will vary based on differences between the various embodiments depicted in the figures. Thus, for example, it will be appreciated that all of the transistors described herein may include a silicon carbide substrate and III-nitride-based channel and barrier layers, and the semiconductor structures of these transistors may operate in the manner described with reference to FIG. 7 .

[0109] 12 is a plan view of a metal layout of a transistor 400 in accordance with a further embodiment of the inventive concept. Transistor 400 is similar to transistor 300 discussed above with reference to FIGS. 8-11, except that transistor 400 uses a series gate resistor 80 connected between each gate pad 312 and a respective gate bus 314 instead of the distributed series gate resistor 380 included in transistor 300. Apart from this modification, the two transistors 300, 400 may otherwise be essentially identical, and therefore further discussion of transistor 400 will be omitted.

[0110] Figure 13 is a plan view of a metal layout of a transistor 500 in accordance with yet a further embodiment of the inventive concept. Transistor 500 is also similar to transistor 300 discussed above with reference to Figures 8-11, except that transistor 500 uses a single odd-mode resistor 90 between each pair of adjacent gate buses 314 and does not include the distributed odd-mode resistor 390 provided in gap regions 384b, 384c of transistor 300 of Figure 8. Apart from this modification, the two transistors 300, 500 may otherwise be essentially identical, and therefore further discussion of transistor 500 will be omitted.

[0111] It will be appreciated that features of the embodiments described above may be combined in any manner to create multiple additional embodiments. For example, FIG. 14 is a plan view of a metal layout of a transistor 100′ that is identical to transistor 100 described above, except that it has been modified to include series gate resistor 180, which may be identical to series gate resistor 380 of FIG. 8. As another example, FIG. 15 is a plan view of a metal layout of a transistor 300′ that is similar to transistor 300 described above, except that gate fingers 316 are not segmented and the location of series gate resistor 380 has been modified accordingly. It will be appreciated that FIGS. 14 and 15 are provided to illustrate some of the possible combinations of different embodiments that result in additional embodiments.

[0112] As discussed above, in some embodiments, source contacts 362 are not segmented, but instead are each implemented as a single continuous source contact 362. Figure 16 is a plan view illustrating a metal layout of transistor 600 according to an embodiment of the inventive concept, including such a configuration. Transistor 600 is similar to transistor 300 discussed above with reference to Figures 8-11, and therefore the following description will focus on the differences between transistor 600 and transistor 300.

[0113] As shown in FIG. 16 , each source contact 662 is not segmented but instead implemented as a single continuous source contact 662. Thus, the length of each source contact 662 in the y-direction may be approximately the same as the length of each drain contact 336 in the y-direction. As discussed above, although the segmented source contact segments 362 a, 362 b, 362 c forming each source contact 362 of the transistor 300 are commonly connected to a source bus layer below the semiconductor layer structure 320 through a source via 364, the electrical path length connecting each source contact segment 362 a, 362 b, 362 c to an adjacent source contact segment 362 a, 362 b, 362 c may be relatively long, resulting in parasitic inductance. As a result, the behavior of the transistor, particularly at operation near and above the “knee” frequency, may be distorted, which may adversely affect the transistor's performance, frequency response, and / or stability. Parasitic inductance can also make it difficult to accurately model transistor behavior, complicating the design process. The undesirable effects discussed above may be reduced or eliminated by using a non-segmented, continuous source contact 662 on the top surface of semiconductor layer structure 320, as shown in FIG.

[0114] Because the source contact 662 is continuous rather than segmented, there is less space between the gate splits for additional circuit elements. As a result, as shown in FIG. 16 , the odd-mode resistor 390 provided in the gap 362g between the source contact segments 362a, 362b, and 362c of transistor 300 is omitted in transistor 600. Similarly, the series gate resistor 380 provided in transistor 300 of FIG. 8 for the second and third gate splits (i.e., the gate splits including source contact segments 362b and 362c, respectively) is omitted in transistor 600 and instead replaced with multiple series gate resistors 380a formed in gate bus 314 along the electrical path to each gate jumper 372. 16 shows the series gate resistor 380a formed within the gate bus 314, it will be appreciated that the series gate resistor 380a may be formed anywhere along the gate signal path between the gate bus 314 and the second or subsequent gate split. For example, in other embodiments, the gate resistors may be formed within conductive vias connecting the gate bus 314 to each gate jumper 372, within the gate signal distribution bar 374 (FIG. 17), or within the gate jumper 372 (see FIG. 18).

[0115] Also, in transistor 600, gate jumpers 372 are formed across every source contact 662, whereas in transistor 300, gate jumpers 372 are formed only on every other source contact 362. As a result, each gate jumper 372 in transistor 600 feeds only two gate fingers 316, while the gate jumpers 372 in transistor 300 each feed four gate fingers 316. One potential advantage of each gate jumper 372 feeding only two gate fingers 316 is that the gate signal distribution bar 374 does not need to cross across the drain contacts 336. This may simplify manufacturing and may also help reduce parasitic gate-drain capacitance. Furthermore, by adding gate jumpers 372, the length of the conduction path that each gate signal must traverse to reach the far end of each gate finger 316 may be the same, which is not the case for transistor 300 in FIGS. 8-11 . The design of transistor 600 can help mitigate phase dispersion issues that arise due to differences in the lengths of the gate signal paths, which can result in a loss of gain and are therefore undesirable.

[0116] As discussed above with reference to FIG. 9A , in transistor 300, gate signal distribution bars 374 are formed in the same metal layer as gate jumpers 372. Although not visible in the cross section of FIG. 9A , conductive vias 378 physically and electrically connect each gate signal distribution bar 374 to a respective segment of discontinuous gate fingers 316, as discussed above with reference to FIGS. 8-11 . These conductive vias 378 are shown in FIG. 16 . In transistor 300 of FIG. 8 , discontinuous source contacts 362 are used, and therefore sufficient space for conductive vias 378 is provided in gaps 362g between adjacent source contact segments 362a, 362b, and 362c. In transistor 600, gaps 362g are not provided (because source contact 662 is continuous), and therefore there may not be space for conductive vias 378 while maintaining sufficient tolerances between conductive vias 378 and other metallization, such as source contacts 662 and drain contacts 336. As a result, a notch may be formed in each source contact 662 such that the "width" of the source contact is narrowed (i.e., smaller in the x-direction) relative to the remainder of the source contact 662. As a result, each source contact 662 may include two or more wide portions 662a, with adjacent wide portions 662a connected by intervening narrow portions 662b. The provision of narrow portions 662b creates additional space to make room for conductive vias 378 that connect each gate distribution bar 374 to its respective gate finger segment 316a, 316b, 316c. The conductive vias 378 are positioned adjacent to the narrow portions 662b of the source contact 662. Thus, for each conductive via 378, a plane perpendicular to the longitudinal axis of its associated gate jumper 372 (i.e., a plane extending in the x-direction in FIG. 16 ) and a plane perpendicular to the plane defined by the bottom surface of the semiconductor layer structure 320 (i.e., a plane also extending in the z-direction in FIG. 16 ) extend through both the conductive via 378 and the narrow portion 662 b of its associated source contact 662.

[0117] It will be appreciated that narrow portion 662b of source contact 662 may be omitted in other embodiments (e.g., when there is sufficient space for conductive via 378 without a notch in source contact 662).

[0118] 16 , according to some embodiments of the present invention, a transistor 600 is provided that includes a semiconductor layer structure 320. A source contact 662, a drain contact 336, and a gate finger 316 are formed on the top surface of the semiconductor layer structure 320, with the gate finger 316 being positioned between the source contact 662 and the drain contact 336. The transistor 600 further includes a gate jumper 372 positioned above and across the source contact 662 and electrically connected to at least a portion of the gate finger 316. The source contact 662 extends continuously over the top surface of the semiconductor layer structure 320 without any gaps dividing the source contact 662 into segments.

[0119] In some embodiments, gate finger 316 comprises a plurality of discontinuous gate finger segments 316 a, 316 b, and 316 c. The transistor may further comprise a gate bus 314, and at least one of discontinuous gate finger segments 316 a, 316 b, and 316 c is electrically connected to gate bus 314 through gate jumper 372. Source contact 662 may include at least a first widened portion 662 a-1, a second widened portion 662 a-2, and a narrowed portion 662 b that physically and electrically connects first widened portion 662 a-1 to second widened portion 662 a-2. The first and second widened portions 662a-1, 662a-2 may be wider than the narrowed portion 662b-1 in a direction perpendicular to the longitudinal axis of the source contact 662 and parallel to the bottom surface of the semiconductor layer structure 320 (i.e., in the x-direction in FIG. 16).

[0120] The transistor 600 may further include a gate signal distribution bar 374 at the same height as the gate jumper 372 above the semiconductor layer structure 320. The gate signal distribution bar 374 may extend from the gate jumper 372 toward the gate finger 316 and may be interposed in an electrical path between the gate jumper 372 and at least a portion of the gate finger 316. The gate signal distribution bar 374 may be electrically connected to the gate finger 316 by a conductive via 378. A series gate resistor 380a may be interposed in the electrical path connecting the gate bus 314 to the gate signal distribution bar 374. Furthermore, the longitudinal axes of the source contact 662, the drain contact 336, and the gate finger 316 may each extend in a first direction (the y-direction in FIG. 16 ).

[0121] 16 , according to a further embodiment of the present invention, a transistor is provided that includes a semiconductor layer structure 320, a source contact 662, a drain contact 336, and a gate finger 316 formed on an upper surface of the semiconductor layer structure 320, wherein the gate finger 316 is positioned between the source contact 662 and the drain contact 336. The source contact 662 includes first and second widened portions 662a-1, 662a-2 that are physically and electrically connected to each other by a narrowed portion 662b. The first and second widened portions 662a-1, 662a-2 may be wider than the narrowed portion 662b in a direction perpendicular to the longitudinal axis of the source contact 662 and parallel to the lower surface of the semiconductor layer structure 320 (i.e., in the x-direction). The transistor may further include a gate bus 314 and a gate jumper 372 electrically connected to the gate bus 314, which may be positioned above and across the source contact 662. At least a portion of the gate finger 316 may be electrically connected to the gate bus 314 through the gate jumper 372.

[0122] 16 , according to yet a further embodiment of the present invention, a transistor is provided that includes a semiconductor layer structure 320, a source contact 662, a drain contact 336, and a gate finger 316 including a plurality of discontinuous gate finger segments 316 a, 316 b, and 316 c. The source contact 662, the drain contact 336, and the gate finger 316 each extend in a first direction (x-direction) on an upper surface of the semiconductor layer structure 320, and the gate finger 316 is positioned between the source contact 662 and the drain contact 336. The transistor further includes a gate bus 314 and a gate jumper 372 electrically connected to the gate bus 314, the gate jumper 372 having a longitudinal axis extending in the first direction and positioned above and spanning the source contact 662. The transistor also includes a gate signal distribution bar 374 in the same metal layer as the gate jumper 372, the gate signal distribution bar 374 extending from the gate jumper 372 toward the first discontinuous ones of the discontinuous gate finger segments 316b.

[0123] 16 illustrates transistor 600 including three gate splits, it will be appreciated that embodiments of the present invention are not limited in this respect. For example, in other embodiments, transistor 600 may include only two gate splits, or may include four or more gate splits.

[0124] FIG. 17 is a plan view of a metal layout of a transistor 600′ in accordance with an embodiment of the inventive concept, which is a modified version of transistor 600 of FIG. 16 . Transistor 600′ may be identical to transistor 600, except that it includes series gate resistors 380 along all three gate branches, omitting the additional series gate resistor 380a in transistor 600. In the embodiment of FIG. 17 , series gate resistor 380 is implemented within gate signal distribution bar 374, similar to the embodiments depicted in FIGS. 14 and 15 . In other embodiments, series gate resistor 380 may instead be implemented within gate finger segments 316b, 316c, or within conductive vias 378 connecting gate signal distribution bar 374 to gate finger segments 316b, 316c. Apart from this modification, the two transistors 600, 600′ may otherwise be essentially identical, and therefore further discussion of transistor 600′ will be omitted.

[0125] FIG. 18 is a plan view of a metal layout of a transistor 600″ according to an embodiment of the inventive concept, which is another modified version of transistor 600 of FIG. 16 . Transistor 600″ may be identical to transistor 600 except that it includes a series gate resistor 380b implemented along each gate jumper 372, omitting the added series gate resistor 380a in transistor 600. Apart from this modification, the two transistors 600, 600″ may otherwise be essentially identical, and therefore further discussion of transistor 600″ will be omitted.

[0126] FIG. 19 is a plan view of a metal layout of a transistor 700 in accordance with yet a further embodiment of the inventive concept. Transistor 700 is similar to transistor 600 of FIG. 16 but includes several notable differences. First, transistor 700 includes only two gate splits instead of the three included in transistor 600. Also, transistor 700 includes a continuous gate finger 316 instead of the gate finger being divided into multiple discontinuous segments 316a, 316b, and 316c as in transistor 600. Finally, the direct connections between gate bus 314 and the ends of gate fingers 316 adjacent to gate bus 314 are omitted in transistor 700, as are the series gate resistors 380 inserted along these direct connections in transistor 600. As a result, each gate finger 316 is center-fed through one of gate jumpers 372. This design may be advantageous in that it may further reduce phase dispersion in that it further reduces the phase difference between the gating signals applied to the center of each gating finger 316 and the gating signals applied to the ends of each gating finger 316. This may result in increased gain.

[0127] FIG. 20 is a plan view of a metal layout of a transistor 800 in accordance with yet a further embodiment of the inventive concept. Transistor 800 is similar to transistor 600 of FIG. 16 , except that the gate distribution bars 374 of transistor 800 are oriented at an angle of approximately 45 degrees relative to the longitudinal axis of each gate jumper 372, rather than being oriented perpendicular to the longitudinal axis of each gate jumper 372 as shown in the other embodiments described above. This approach may advantageously shorten the gate signal path. Any of the embodiments disclosed herein may be modified so that the gate signal distribution bars 374 are oriented at an angle other than 90 degrees relative to the longitudinal axis of each gate jumper 372 (i.e., the gate signal distribution bars 374 are oriented at an oblique angle relative to the longitudinal axis of each gate jumper 372).

[0128] It will also be appreciated that in other embodiments, a segmented source contact, such as source contact 362 of transistor 300 of Figures 8-11, may be used, with separate electrical connections provided on the top surface of semiconductor layer structure 320 that electrically connect the discontinuous source contact segments 362a, 362b, 362c on the upper side of semiconductor layer structure 320. For example, the source connector segments may be implemented in the same metal layer as gate jumper 372, or may be implemented in a different metal layer (upper or lower) than gate jumper 372. These source connector segments may be electrically connected to the discontinuous source contact segments 362a, 362b, 362c through conductive vias.

[0129] Figure 21 is a plan view of a small portion of a metal layout of a transistor 900 including such a source connector segment. As shown in Figure 21, the transistor 900 includes a discontinuous source contact 362 including three source contact segments 362a, 362b, and 362c. Also provided are source connector segments 963 implemented in a metal layer above (i.e., above the semiconductor layer structure) the metal layer containing the gate jumper 372. Conductive vias 964 electrically connect each source connector segment 963 to the underlying source contact segments 362a, 362b, and 362c.

[0130] While the embodiments illustrated in the previous figures position the gate jumpers 372 above and spanning the respective source contacts 362 / 662, as previously mentioned, embodiments of the present invention are not limited in this respect. FIG. 22 is a plan view of a metal layout of a transistor 1000 in accordance with yet a further embodiment of the inventive concepts, in which the gate jumpers 372 extend above and spanning the drain contacts 336. While each drain contact 336 extends approximately to the gate bus 314, it will be seen that most of each drain contact 336 is covered by the respective gate jumper 372, and thus only about one-third of each drain contact 336 is visible in FIG. 22. In the depicted embodiment, both the drain contacts 336 and the source contacts 1062 are implemented as continuous contacts without any notches (narrowed portions) formed thereon. It will be appreciated that in other embodiments, source contact 1062 may be replaced with a discontinuous source contact, such as source contact 362 of FIG. 8, or a continuous source contact with a notch, such as source contact 662 of FIG. 16.

[0131] FIG. 23 is a simplified plan (top) view of a metal layout of a transistor 1100 according to yet a further embodiment of the present invention. The embodiment of FIG. 23 illustrates how a second gate bus may be provided and a gate resistor may be electrically connected between the first gate bus and the second gate bus. Transistor 1100 is similar to transistor 600 of FIG. 16 . Therefore, the following description of transistor 1100 will primarily focus on the differences between transistor 600 and transistor 1100.

[0132] As shown in FIG. 23 , the transistor 1100 is formed on a semiconductor structure 320 including one or more device epitaxial layers, which may be, for example, the semiconductor structure 320 discussed above with reference to FIG. 7 . A plurality of gate fingers 316 are provided, each having a respective longitudinal axis extending in the y-direction. Each gate finger 316 is divided in the y-direction into three discontinuous gate finger segments 316 a, 316 b, and 316 c separated from one another by a gap 316 g. It will be appreciated that the gate finger segments 316 a, 316 b, and 316 c may each have approximately the same length or may have different lengths. For example, in some embodiments, at least one gate finger segment 316 a, 316 b, or 316 c may be at least 20% longer than another one of the gate finger segments 316 a, 316 b, or 316 c. It will also be appreciated that in other embodiments, each gate finger 316 may be divided into more or fewer segments, or each gate finger 316 may be a continuous gate finger. Gate fingers 316 may be identical to gate fingers 316 of transistor 600 of FIG. 16, and therefore further discussion thereof will be omitted.

[0133] Transistor 1100 further includes a first gate bus 314-1 and a second gate bus 314-2, which may be substantially identical to gate bus 314 of transistor 600. Both gate buses 314-1 and 314-2 extend in the x-direction (i.e., the longitudinal axis of each gate bus 314-1 and 314-2 extends in the x-direction). First gate bus 314-1 may be a continuous gate bus (or a substantially continuous gate bus), and second gate bus 314-2 may be a segmented gate bus including multiple discontinuous gate bus segments 315, for example, including first segments 315a and second segments 315b arranged in an alternating manner. Adjacent segments 315a and 315b of second gate bus 314-2 may be separated from each other along the x-direction. In some embodiments, first gate bus 314-1 and second gate bus 314-2 may both be formed in the first metallization layer, and in some embodiments, gate fingers 316, drain contact 336, drain bus 334, and / or source contact 362 may also be formed in the first metallization layer.

[0134] Transistor 1100 further comprises a plurality of gate resistors 1180a, 1180b. Each gate resistor 1180a, 1180b may electrically connect first gate bus 314-1 to a respective one of segments 315 of second gate bus 314-2. In some embodiments, gate resistors 1180a, 1180b may be formed at a lower level within the device (i.e., between semiconductor structure 320 and first gate bus 314-1 and second gate bus 314-2). In other embodiments, gate resistors 1180a, 1180b may be formed at a higher level within the device than first gate bus 314-1 and second gate bus 314-2 (i.e., further above semiconductor structure 320). In some embodiments, gate resistors 1180a, 1180b may be formed at a lower level within the device than first gate bus 314-1 and second gate bus 314-2. In some embodiments, each gate resistor 1180a, 1180b may be in direct contact with both the first gate bus 314-1 and a respective one of the segments 315 of the second gate bus 314-2.

[0135] A plurality of drain contacts 336 are connected to the drain bus 334. The drain contacts 336 extend parallel to adjacent ones of the gate fingers 316. Source contacts 362 are also provided and extend parallel to adjacent ones of the gate fingers 316 in the y-direction. The source contacts 362 may be continuous (as shown) or segmented into multiple (i.e., two or more) discontinuous segments. A source contact plug 364 may electrically connect each source contact 362 to a common conductive layer, which may function as a source bus, for example, located in a lower level of the device. For simplicity, only two representative source contact plugs 364 are illustrated in FIG. 23. The drain contacts 336, drain bus 334, source contacts 362, and source contact plugs 364 have been described in detail above (e.g., with reference to FIG. 16), and therefore further description thereof will be omitted here.

[0136] The transistor 1100 further includes a plurality of gate jumpers 372 extending along the y-direction parallel to the gate fingers 316. The gate jumpers 372 are connected to the first gate bus 314-1 through the second gate bus 314-2 and vertically overlap the source contacts 362. The gate jumpers 372 are provided across every source contact 362 such that each gate jumper 372 supplies the second and third gate finger segments 316b, 316c of two gate fingers 316. The gate jumpers 372 may be identical to the gate jumpers 372 of the transistor 300 or transistor 600 described above, and therefore further description thereof will be omitted. Each gate jumper 372 is electrically connected to a respective second segment 315b of the second gate bus 314-2. The gate jumpers 372 may be electrically connected directly to their associated second segments 315b of the second gate bus 314-2, or more generally, may be electrically connected through intervening conductive elements, such as conductive vias (not shown for simplicity of illustration). The transistor 1100 further includes a gate signal distribution bar 374 that electrically connects the gate jumpers 372 to the second and third gate finger segments 316b, 316c of the gate finger 316. The gate signal distribution bar 374 may have, for example, the design of the gate signal distribution bar 374 of the transistor 600 of FIG. 16 (or any other of the gate distribution bars discussed above), and therefore further description thereof will be omitted.

[0137] As shown in FIG. 23 , the first gate finger segment 316 a of the gate finger 316 is directly connected to the first segment 315 a of the second gate bus 314-2. In the depicted embodiment, two of the first gate finger segments 316 a extend from each first segment 315 a of the second gate bus 314-2. These first gate finger segments 316 a may be monolithic with their associated first segment 315 a. The second segment 315 b of the second gate bus 314-2 is electrically connected to a respective one of the gate jumpers 372, as shown. As discussed above, each gate finger 316 is segmented into a first gate finger segment 316 a, a second gate finger segment 316 b, and a third gate finger segment 316 c. A gate signal input to gate pad 312 flows along first gate bus 314-1, and then respective sub-components of the gate signal flow through first resistor 1180a to first segment 315a of second gate bus 315-2 and then to first gate finger segment 316a of each gate finger 316. Additional sub-components of these gate signals are passed from first gate bus 314-1 to second resistor 1180b and then to second segment 315b of second gate bus 315-2 and then to gate jumper 372 and from gate jumper 372 to second and third gate finger segments 316b, 316c of each gate finger 316. Thus, it can be seen that the sub-component of the gate signal flowing to the first gate finger segment 316a of each gate finger 316 flows through the first resistor 1180a, while the sub-component of the gate signal flowing to the second and third gate finger segments 316b, 316c of each gate finger 316 flows through the second resistor 1180b.

[0138] The transistor 1100 described above includes multiple series gate resistors 1180 a, 1180 b; thus, the gate resistors are distributed throughout the transistor 1100 rather than being provided as a single, very large lumped gate resistor. Additionally, at least two gate resistors 1180 (i.e., one first gate resistor 1180 a and one second gate resistor 1180 b) may be provided along the power path for each gate finger 316. As discussed above, by distributing the series gate resistors at two or more locations along the gate finger 316, the feedback loop within the gate finger 316 and drain contact 336 of the transistor 1100 may be made sufficiently lossy so that instability may be reduced or eliminated. This may improve device yield and / or reduce the incidence of device failure in the field. Furthermore, as explained above, the current path along a particular gate finger segment 316a, 316b, 316c may pass through only a single series gate resistor 1180a, 1180b, as can be seen in Figure 23. Because the series gate resistor 1180a, 1180b may have a relatively small resistance, power losses are reduced and the transistor 1100 may therefore support higher gain levels for a device of a given size.

[0139] As further shown in FIG. 23, one or more odd-mode resistors 390 may also be included in transistor 1100 to eliminate odd-mode instability feedback loops within the device. The purpose and implementation of odd-mode resistors 390 have been discussed above, so further description thereof will be omitted. The unit cell transistors included in transistor 1100 may have a symmetrical layout. The dashed line LS in FIG. 23 indicates the line of symmetry.

[0140] It will be appreciated that while transistor 1100 includes segmented gate fingers 316 and continuous source contact 362, embodiments of the present invention are not limited in this respect. For example, in other embodiments, gate fingers 316 may be continuous (while still providing the manner illustrated in FIG. 23). Segmenting gate fingers 316, however, may provide a more stable device, as continuous gate fingers may have more loops that could cause instability. As another example, source contact 362 may be segmented into two or more segments, as discussed in various embodiments above. The continuous source contact of transistor 1100, however, may provide improved performance in some applications.

[0141] 23 , according to some embodiments of the present invention, a transistor 1100 is provided that includes a plurality of gate fingers 316, the plurality of gate fingers 316 having respective longitudinal directions extending in a first direction (y-direction) and spaced apart from one another in a second direction (x-direction) perpendicular to the first direction. The transistor also includes a first gate bus 314-1, a first resistor 1180a electrically connected between the first gate bus 314-1 and a first segment 316b of a first gate finger 316 of the plurality of gate fingers, and a second resistor 1180b electrically connected between the first gate bus 314-1 and a second segment 316b of the first gate finger 316.

[0142] The transistors may further include a gate jumper 372 electrically connecting the first gate bus 314-1 to the second segment 316b of the first gate finger 316. A second resistor 1180b may be electrically connected between the first gate bus 314-1 and the gate jumper 372. Furthermore, the first segment 316a of the first gate finger 316 and the second segment 316b of the first gate finger 316 are separated from each other in the first direction (y-direction) by a gap region 316g. In some embodiments, the first resistor 1180a may also be electrically connected between the first gate bus 314-1 and the first segment 316a of the second gate finger 316 of the plurality of gate fingers. These transistors may also include a gate signal distribution bar 374 that electrically connects the gate jumper 372 to the second segment 316 b of the first gate finger 316 .

[0143] Transistor 1100 may also include a source contact 362 (e.g., a continuous source contact), and gate jumper 372 may extend across and vertically overlap source contact 362. Additionally, transistor 1100 may further include a second gate bus 314-2, and first resistor 1180a may electrically connect first gate bus 314-1 to second gate bus 314-2. In some embodiments, the second gate bus 314-2 may be a segmented gate bus including a plurality of first segments 315a and a plurality of second segments 315b spaced apart from one another (e.g., in an alternating manner) along the second direction (x-direction), and the first resistor 1180a may electrically connect the first gate bus 314-1 to the first segment 315a of the second gate bus 314-2, and the second resistor 1180b may electrically connect the first gate bus 314-1 to the second segment 315b of the second gate bus 314-2.

[0144] As described above, in some embodiments, the first gate bus 314-1 and the second gate bus 314-2 may both be part of a first metallization layer, and the first resistor 1180a and the second resistor 1180b may both be part of a second metallization layer. The first resistor 1180a and the second resistor 1180b may each vertically overlap both the first gate bus 314-1 and the second gate bus 314-2. In some embodiments, the first resistor 1180a and / or the second resistor 1180b may directly contact the first gate bus 314-1 and / or the second gate bus 314-2. The transistor 1100 may be a gallium nitride-based high electron mobility transistor.

[0145] Still referring to FIG. 23, it can be seen that according to a further embodiment of the present invention, there is provided a transistor 1100 comprising a plurality of gate fingers 316 having respective longitudinal axes extending in a first direction (y-direction) and spaced apart from one another in a second direction (x-direction) perpendicular to the first direction, a first gate bus 314-1, a second gate bus 314-2 spaced apart from the first gate bus 314-1 in the first (y) direction, and a first resistor 1180a electrically connecting the first gate bus 314-1 to the second gate bus 314-2.

[0146] In some embodiments, second gate bus 314-2 comprises a segmented gate bus including multiple segments 315a, 315b spaced apart from one another along the second (x) direction, and first resistor 1180a electrically connects first gate bus 314-1 to first segment 315a of second gate bus 314-2. Transistor 1100 may further comprise second resistor 1180b electrically connecting first gate bus 314-1 to second segment 315b of second gate bus 314-2. Transistor 1100 may also comprise source contact 362 and gate jumper 372 extending across and vertically overlapping source contact 362. The first resistor 1180a may be electrically connected between the first gate bus 314-1 and the first segment 316a of the first gate finger 316, and the second resistor 1180b may be electrically connected between the first gate bus 314-1 and the gate jumper 372. The gate jumper 372 may electrically connect the first gate bus 314-1 to the second segment 316b of the first gate finger 316.

[0147] Still referring to FIG. 23, in accordance with yet a further embodiment of the present invention, there is provided a transistor comprising a plurality of gate fingers 316 having respective longitudinal axes extending in a first (y) direction and spaced apart from one another in a second (x) direction perpendicular to the first direction; a first gate bus 314-1; a first resistor 1180a coupled between the first gate bus 314-1 and a first segment 316a of a first of the plurality of gate fingers 316; and a second resistor 1180b coupled between the first gate bus 314-1 and a second segment 316b of the first gate finger 316. The first segment 316a of the first gate finger 316 is spaced apart from the second segment 316b of the first gate finger 316, and the first segment 316a of the first gate finger 316 is closer to the first gate bus 314-1 than the second segment 316b of the first gate finger 316.

[0148] The transistor 1100 may also include a segmented second gate bus 314-2 including a plurality of segments 315 spaced apart from one another along the second (x) direction, wherein the first resistor 1180a may electrically connect the first gate bus 314-1 to the first segment 315a of the second gate bus 314-2 and the second resistor 1180b may electrically connect the first gate bus 314-1 to the second segment 315b of the second gate bus 314-2. The transistor 1100 may further include a gate jumper 372 electrically connecting the first gate bus 314-1 to the second segment 316b of the first gate finger 316. The second resistor 1180b may be electrically connected between the first gate bus 314-1 and the gate jumper 372, and may be electrically connected between the first gate bus 314-1 and the first segment 316b of the second gate finger 316 of the plurality of gate fingers.

[0149] Embodiments of the inventive concepts may be particularly well suited for use with III-nitride-based high electron mobility transistor (HEMT) devices. As used herein, the term "III-nitrides" refers to those semiconductor compounds formed between nitrogen and the group III elements of the periodic table, usually aluminum (Al), gallium (Ga), and / or indium (In). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. All of these compounds have an empirical formula of one mole of nitrogen bonded to one mole of total group III elements.

[0150] Suitable structures for GaN-based HEMTs that may utilize embodiments of the present invention are described, for example, in US Pat. Nos. 5,629,299; 5,729,313 ... and 5,729,313, the disclosures of which are hereby incorporated by reference in their entireties.

[0151] In particular embodiments of the present invention, substrate 200 may be a semi-insulating silicon carbide (SiC) substrate, which may be, for example, the 4H polytype of silicon carbide. Other candidate polytypes of silicon carbide include the 3C, 6H, and 15R polytypes.

[0152] Optional buffer, nucleation, and / or transition layers (not shown) may be provided on the substrate 200 below the channel layer 210. For example, an AlN buffer layer may be included to provide a suitable crystal structure transition between the silicon carbide substrate and the remainder of the device. A strain-balancing transition layer may also be provided, as described, for example, in U.S. Patent No. 6,223,999, the disclosure of which is incorporated herein by reference as if fully set forth herein. Additionally, one or more capping layers, such as a SiN capping layer, may be provided on the barrier layer 220.

[0153] Silicon carbide has a much closer crystal lattice match to III-nitrides than sapphire (Al2O3), a very common substrate material for III-nitride devices. The closer lattice match of SiC may result in higher quality III-nitride films than those commonly available on sapphire. Silicon carbide also has very high thermal conductivity, so that the total output power of III-nitride devices on silicon carbide is not typically limited by the heat dissipation of the substrate, as is the case for the same devices formed on sapphire. The availability of semi-insulating silicon carbide substrates may also provide device isolation and reduced parasitic capacitance. Suitable SiC substrates are manufactured, for example, by Cree Corporation of Durham, North Carolina, the assignee of the present invention.

[0154] While silicon carbide may be used as the substrate material, embodiments of the present invention may utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, and InP. In some embodiments, a suitable buffer layer may also be formed.

[0155] In some embodiments of the present invention, the channel layer 210 may be formed of, for example, Al, provided that the energy of the conduction band edge of the channel layer 210 is less than the energy of the conduction band edge of the barrier layer 220 at the interface between the channel layer and the barrier layer. x Ga 1-x In certain embodiments of the present invention, X=0, indicating that the channel layer 210 is GaN. The channel layer 210 may also be other III-nitrides, such as InGaN or AlInGaN. The channel layer 210 may be undoped or unintentionally doped and may be grown to a thickness greater than about 20 Å. The channel layer 210 may also be a multi-layer structure, such as a superlattice or a combination of GaN or AlGaN, etc.

[0156] Channel layer 210 may have a bandgap smaller than that of barrier layer 220, and channel layer 210 may also have a greater electron affinity than barrier layer 220. In certain embodiments of the inventive concepts, barrier layer 220 is AlN, AlInN, AlGaN, or AlInGaN having a thickness between about 0.1 nm and about 10 nm. In particular embodiments of the inventive concepts, barrier layer 220 is sufficiently thick and has a sufficiently high Al composition and doping to induce a significant carrier concentration at the interface between channel layer 210 and barrier layer 220.

[0157] The barrier layer 220 may be a III-nitride and have a bandgap larger than that of the channel layer 210 and a lower electron affinity than the channel layer 210. Thus, in certain embodiments of the present invention, the barrier layer 220 may comprise AlGaN, AlInGaN, and / or AlN, or a combination of these layers. The barrier layer 220 may be, for example, from about 0.1 nm to about 30 nm thick. In certain embodiments of the present invention, the barrier layer 220 is undoped or has a thickness of about 10 nm to about 30 nm. 19 cm -3 In some embodiments of the present invention, the barrier layer 220 is doped with an n-type dopant to a concentration of less than Al.x Ga 1-x is N, where 0 < x < 1. In certain embodiments, the aluminum concentration is about 25%. However, in other embodiments of the present invention, the barrier layer 220 comprises AlGaN having an aluminum concentration between about 5% and about 100%. In certain embodiments of the present invention, the aluminum concentration exceeds about 10%.

[0158] Embodiments of the present invention are described with reference to a GaN high electron mobility transistor (HEMT) structure, but the concepts of the present invention are not limited to such devices. Thus, embodiments of the present invention may include other transistor devices having a plurality of unit cells and control electrodes. Embodiments of the present invention preferably have a wider control electrode and may be suitable for use in any semiconductor device in which there are a plurality of unit cells of the device. Thus, for example, embodiments of the present invention may be suitable for use in various types of devices such as MESFETs, MMICs, SITs, LDMOSs, BJTs, pHEMTs, etc. manufactured using SiC, GaN, GaAs, silicon, etc.

[0159] Although terms such as first, second, etc. may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present invention, a first element could be termed a second element, and similarly, a second element could be termed a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0160] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0161] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms used herein should be interpreted to have a meaning consistent with their meaning in the context of this specification and related art, and it will be further understood that they will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0162] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "on" another element, it will be understood that it can be directly on or extending directly onto the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it will also be understood that it can be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0163] Relative terms such as "lower," "upper," "top," "below," "horizontal," "lateral," "vertical," and the like may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0164] Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Also, deviations from the shapes of the illustrations are to be expected as a result, for example, of manufacturing techniques and / or tolerances. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but should include, for example, deviations in shapes that result from manufacturing.

[0165] The drawings and specification disclose exemplary embodiments of the invention, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

1. a plurality of gate fingers having respective longitudinal axes extending in a first direction and spaced apart from one another in a second direction perpendicular to the first direction; a first gate bus; a first resistor electrically connected between the first gate bus and a first segment of a first gate finger of the plurality of gate fingers; a second resistor electrically connected between the first gate bus and the second segment of the first gate finger; A transistor comprising:

2. 2. The transistor of claim 1, further comprising a gate jumper electrically connecting said first gate bus to said second segment of said first gate finger.

3. 3. The transistor of claim 2, wherein the second resistor is electrically connected between the first gate bus and the gate jumper.

4. 4. The transistor of claim 1, wherein the first segment of the first gate finger and the second segment of the first gate finger are separated from each other in the first direction by a gap region.

5. 5. The transistor of claim 1, wherein the first resistor is also electrically connected between the first gate bus and a first segment of a second gate finger of the plurality of gate fingers.

6. 4. The transistor of claim 2, further comprising a gate signal distribution bar electrically connecting the gate jumper to the second segment of the first gate finger.

7. 4. The transistor of claim 2, further comprising a source contact, the gate jumper vertically overlapping the source contact.

8. 4. The transistor of claim 1, further comprising a second gate bus, wherein the first resistor electrically connects the first gate bus to the second gate bus.

9. 9. The transistor of claim 8, wherein the second gate bus comprises a segmented gate bus including a plurality of segments spaced apart from one another along the second direction, the first resistor electrically connecting the first gate bus to a first segment of the plurality of segments of the second gate bus, and the second resistor electrically connecting the first gate bus to a second segment of the plurality of segments of the second gate bus.

10. 10. The transistor of claim 9, wherein the first gate bus and the second gate bus are both part of a first metallization layer, and the first resistor and the second resistor are both part of a second metallization layer.

11. 9. The transistor of claim 8, wherein the first resistor and the second resistor vertically overlap both the first gate bus and the second gate bus, respectively.

12. 10. The transistor of claim 9, wherein the first resistor is in direct contact with both the first gate bus and the second gate bus.

13. The transistor of any of claims 1 to 12, wherein the transistor is a gallium nitride based high electron mobility transistor.

14. 6. The transistor of claim 5, further comprising a third resistor electrically connected between the first gate bus and a first segment of a third gate finger of the plurality of gate fingers, wherein a gate jumper also electrically connects the first gate bus to a second segment of the third gate finger.

15. a plurality of gate fingers having respective longitudinal axes extending in a first direction and spaced apart from one another in a second direction perpendicular to the first direction; a first gate bus; a second gate bus spaced from the first gate bus in the first direction; a first resistor electrically connecting the first gate bus to the second gate bus; A transistor comprising:

16. 16. The transistor of claim 15, wherein the second gate bus comprises a segmented gate bus including a plurality of segments spaced apart from one another along the second direction, and the first resistor electrically connects the first gate bus to a first segment of the plurality of segments of the second gate bus.

17. 17. The transistor of claim 16, further comprising a second resistor electrically connecting the first gate bus to a second segment of the plurality of segments of the second gate bus.

18. 18. The transistor of claim 15, further comprising: a source contact; and a gate jumper extending across the source contact, wherein the first resistor is electrically connected between the first gate bus and a first segment of a first gate finger of the plurality of gate fingers, and the second resistor is electrically connected between the first gate bus and the gate jumper.

19. 20. The transistor of claim 18, wherein the gate jumper electrically connects the first gate bus to a second segment of the first gate finger.

20. 20. The transistor of claim 15, wherein the first segment of the first gate finger and the second segment of the first gate finger are separated from each other in the first direction by a gap region.

21. 21. The transistor of claim 17, wherein the first resistor and the second resistor vertically overlap both the first gate bus and the second gate bus, respectively, when viewed from above the transistor.

22. 22. The transistor of claim 15, wherein a first resistor is in direct contact with both the first gate bus and the second gate bus.

23. 20. The transistor of claim 17, wherein the first gate bus and the second gate bus are both part of a first metallization layer, and the first resistor and the second resistor are both part of a second metallization layer.

24. 24. The transistor of claim 15, wherein a longitudinal axis of the first gate bus extends in the second direction.

25. 17. The transistor of claim 16, wherein a first segment of a first gate finger of the plurality of gate fingers is directly connected to a first segment of the plurality of segments of the second gate bus.

26. 26. The transistor of claim 25, wherein the first segment of a second gate finger of the plurality of gate fingers is directly connected to the first segment of the plurality of segments of the second gate bus.

27. a plurality of gate fingers having respective longitudinal axes extending in a first direction and spaced apart from one another in a second direction perpendicular to the first direction; a first gate bus; a first resistor coupled between the first gate bus and a first segment of a first gate finger of the plurality of gate fingers; a second resistor coupled between the first gate bus and a second segment of the first gate finger; Equipped with a transistor, wherein the first segment of the first gate finger is spaced from the second segment of the first gate finger, and the first segment of the first gate finger is closer to the first gate bus than the second segment of the first gate finger.

28. 28. The transistor of claim 27, further comprising a segmented second gate bus including a plurality of segments spaced apart from one another along the second direction, wherein the first resistor electrically connects the first gate bus to a first segment of the plurality of segments of the second gate bus and the second resistor electrically connects the first gate bus to a second segment of the plurality of segments of the second gate bus.

29. 30. The transistor of claim 28, wherein the first gate bus and the second gate bus are both part of a first metallization layer, and the first resistor and the second resistor are both part of a second metallization layer.

30. 30. The transistor of claim 27, wherein the first resistor and the second resistor vertically overlap both the first gate bus and the second gate bus, respectively, when viewed from above the transistor.

31. 30. The transistor of any of claims 27 to 29, wherein the first resistor is in direct contact with both the first gate bus and the second gate bus.

32. 30. The transistor of any of claims 27 to 29, further comprising a gate jumper electrically connecting the first gate bus to the second segment of the first gate finger.

33. 33. The transistor of claim 32, wherein the second resistor is electrically connected between the first gate bus and the gate jumper.

34. 30. The transistor of claim 27, wherein the first resistor is also electrically connected between the first gate bus and a first segment of a second gate finger of the plurality of gate fingers.

35. 33. The transistor of claim 32 further comprising a source contact, the gate jumper extending across the source contact.

36. 30. The transistor of any of claims 27 to 29, wherein the transistor is a gallium nitride based high electron mobility transistor.

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