Power semiconductor device and method for manufacturing a power semiconductor device - Patents.com

Abstract

A power semiconductor device (1) is defined, comprising: a first electrode (2); a first semiconductor layer (3) of a first conductivity type; a drift layer (4) of the first conductivity type; a second semiconductor layer (5) of a second conductivity type different from the first conductivity type; and a second electrode (6), wherein at least one of the first semiconductor layer (3) and the second semiconductor layer (5) comprises an oxide layer (24) extending into an active region (9) of the power semiconductor device (1) surrounded by a termination region (8) of the power semiconductor device (1), and wherein at least one of the first semiconductor layer (3) and the second semiconductor layer (5) has a sloped structure (19). Further, a method for manufacturing the power semiconductor device (1) is defined.

Description

[Technical Field]

[0001] The present disclosure relates to power semiconductor devices and methods for manufacturing power semiconductor devices. [Background technology]

[0002] SUMMARY OF THE INVENTION Embodiments of the present disclosure relate to power semiconductor devices with improved performance. Further embodiments of the present disclosure relate to methods for manufacturing such power semiconductor devices. Summary of the Invention [Means for solving the problem]

[0003] This is achieved by the subject matter of the independent claims. Further embodiments are evident from the dependent claims in the following description.

[0004] Power semiconductor devices are described, where hereinafter the term "power" refers to power semiconductor modules, power semiconductor devices, and / or power semiconductor chips configured to handle voltages and currents of, for example, greater than 100V and / or greater than 10A, illustratively voltages up to 10kV and amperages up to 10kA.

[0005] According to one embodiment, a power semiconductor device includes a first electrode. The first electrode exemplarily extends laterally. For example, the first electrode is configured to be electrically conductively contacted from the outside. Exemplarily, the first electrode includes or consists of a metal.

[0006] The first electrode may include a first layer and a second layer stacked on top of each other in a vertical direction perpendicular to the horizontal direction. For example, the first layer may include a metal different from the metal included in the second layer. The first layer may illustratively include molybdenum, and the second layer may illustratively include aluminum and / or other metals such as copper, titanium, and / or nickel. In particular, the first layer is configured to be electrically conductively contacted from the outside, and the second layer is a metallization. For example, the metallization may be applied using a sputtering process or a vapor deposition process.

[0007] According to an embodiment, a power semiconductor device includes a first semiconductor layer of a first conductivity type. The first semiconductor layer exemplarily extends laterally. For example, the first semiconductor layer includes or consists of a semiconductor material. Exemplarily, the semiconductor material is silicon-based. The first semiconductor layer includes, for example, a first dopant of the first conductivity type.

[0008] According to an embodiment, a power semiconductor device includes a drift layer of a first conductivity type. The drift layer exemplarily extends laterally. For example, the drift layer includes or consists of a semiconductor material. Exemplarily, the semiconductor material includes or consists of the same material as the first semiconductor layer. The drift layer includes, for example, a further first dopant of the first conductivity type. The further first dopant of the drift layer is, for example, the same dopant as the first semiconductor layer.

[0009] For example, the maximum doping concentration of the drift layer is lower than the maximum doping concentration of the first semiconductor layer, for example, at least one order of magnitude lower than the maximum doping concentration of the first semiconductor layer.

[0010] According to an embodiment, a power semiconductor device includes a second semiconductor layer of a second conductivity type different from the first conductivity type. The second semiconductor layer exemplarily extends laterally. For example, the second semiconductor layer includes or consists of a semiconductor material. Exemplarily, the semiconductor material includes or consists of the same material as the first semiconductor layer. The first semiconductor layer includes, for example, a second dopant of the second conductivity type.

[0011] Illustratively, the first conductivity type is n-type and the second conductivity type is p-type, or vice versa, e.g., the first dopant is an n-type dopant and the second dopant is a p-type dopant, or vice versa.

[0012] According to an embodiment, the power semiconductor device includes a second electrode. The second electrode exemplarily extends laterally. For example, the second electrode is configured to be electrically conductively contacted from the outside. Exemplarily, the second electrode includes or consists of a metal.

[0013] The second electrode may include a third layer and a fourth layer stacked one on top of the other. For example, the third layer may include a metal different from the metal included in the fourth layer. The third layer may illustratively include aluminum and / or other metals such as copper, titanium, nickel, tungsten, platinum, and / or gold, and the fourth layer may illustratively include molybdenum. In particular, the third layer is a metallization, and the additional layer is configured to be electrically conductively contacted from the outside.

[0014] For example, the first electrode may be a cathode electrode of the power semiconductor device and the second electrode may be an anode electrode of the power semiconductor device, or vice versa.

[0015] The first layer and the fourth layer do not exist in, for example, a power semiconductor device. The first layer and the fourth layer are provided to handle, for example, a power semiconductor device, and the first electrode includes only the second layer, and the second electrode includes only the third layer.

[0016] According to an embodiment of the power semiconductor device, an oxide layer is disposed on at least one of the first and second semiconductor layers, the oxide layer extending into an active region of the power semiconductor device surrounded by a termination region of the power semiconductor device. The termination region is a peripheral region of the power semiconductor device, and the active region is a central region of the power semiconductor device, which is a peripheral region that laterally completely surrounds the active region in the lateral direction.

[0017] The active region is located at a center of mass of the power semiconductor device and extends laterally in a direction toward at least one edge of the power semiconductor device, and the termination region extends laterally along an edge region of the power semiconductor device that defines the active region.

[0018] For example, the oxide layer may be disposed only on the first semiconductor layer, or only on the second semiconductor layer, or alternatively, the oxide layer may be disposed on both the first semiconductor layer and the second semiconductor layer.

[0019] The oxide layer extends into the active region, particularly from the termination region toward the center of mass. Exemplarily, the oxide layer has a shape that is circular, elliptical, or polygonal, such as rectangular, in plan view. In particular, the shape of the oxide layer in plan view corresponds to the outline of the power semiconductor device, particularly the drift layer, in plan view.

[0020] If an oxide layer is disposed on the first semiconductor layer, the oxide layer faces the first electrode and in particular comprises the semiconductor material of the first semiconductor layer oxidized.

[0021] For example, the oxide layer is produced by partially applying a plasma-enhanced chemical vapor deposition (PECVD) process to the underside of the first semiconductor layer. In particular, the material of the oxide layer is applied to the underside of the first semiconductor layer, in particular completely covering it. After that, a photoresist is applied to the underside of the material of the oxide layer, in particular completely covering it. The photoresist is structured, in particular using a mask, for example, to produce the oxide layer.

[0022] For example, the oxide layer protrudes vertically beyond the first semiconductor layer in the direction of the first electrode. If an oxide layer is disposed on the second semiconductor layer, the oxide layer faces the second electrode and in particular comprises the semiconductor material of the second semiconductor layer oxidized.

[0023] For example, the oxide layer is produced by partially applying a plasma-enhanced chemical vapor deposition (PECVD) process to the upper surface of the first semiconductor layer. In particular, the material of the oxide layer is applied to the upper surface of the second semiconductor layer, particularly completely covering it. After that, a photoresist is applied to the upper surface of the material of the oxide layer, particularly completely covering it. The photoresist is structured, for example, using a mask, to produce the oxide layer.

[0024] For example, the oxide layer protrudes vertically beyond the second semiconductor layer in the direction of the second electrode. The oxide layer has a vertical height of 1 μm or less.

[0025] For example, the power semiconductor described herein may be a fast recovery diode, particularly a free-floating discrete fast recovery diode. Furthermore, the power semiconductor described herein may be a reverse-conducting integrated gate commutated thyristor (RC-IGCT). The RC-IGCTS includes a diode section and a GCT section, with an isolation region disposed between the diode section and the GCT section. The diode includes all of the elements described herein in the active region, and the isolation region is formed from all of the elements in the termination region.

[0026] In summary, such a power semiconductor device having a combination of a first and / or second semiconductor layer and an oxide layer can provide, among other advantages, the following:

[0027] Advantageously, the oxide layer reduces the emitter injection efficiency in the termination region. Due to the oxide region, the termination region of the power semiconductor device is effectively electrically isolated from operation in the conductive (ON) state by significantly reducing the emitter injection efficiency in the termination region. Advantageously, less heat is generated in the termination region, which has a lower cooling capacity. Therefore, thermal stability is improved during high frequency operation or surge current events, allowing the power semiconductor device to operate at higher temperatures.

[0028] Due to the oxide layer in the active region, particularly adjacent to the termination region, the emitter injection efficiency can be advantageously reduced and particularly accurately predetermined.

[0029] According to a further embodiment of the power semiconductor device, the first electrode, the first semiconductor layer, the drift layer, the second semiconductor layer, and the second electrode are stacked on top of each other along a vertical stacking direction. Directly adjacent elements, for example, are in direct contact with each other. Illustratively, the first layer of the first electrode faces away from the first semiconductor layer, and the second layer of the first electrode faces the first semiconductor layer. Illustratively, the third layer of the second electrode faces the second semiconductor layer, and the fourth layer of the second electrode faces away from the second semiconductor layer.

[0030] According to a further embodiment of the power semiconductor device, the first semiconductor layer includes a first sublayer facing the first electrode and a second sublayer facing the drift layer. For example, the maximum doping concentration of the first sublayer is higher than the maximum doping concentration of the second sublayer, for example, by at least one order of magnitude higher than the maximum doping concentration of the second sublayer.

[0031] According to a further embodiment of the power semiconductor device, the second semiconductor layer includes a third sublayer facing the drift layer and a fourth sublayer facing the second electrode. For example, the fourth sublayer has a maximum doping concentration higher than the maximum doping concentration of the third sublayer, for example, at least one order of magnitude higher than the maximum doping concentration of the third sublayer.

[0032] According to a further embodiment of the power semiconductor device, one of the first electrode and the second electrode spans the active region and the termination region, in particular, only one of the first electrode and the second electrode spans the active region and the termination region.

[0033] For example, the first electrode extends laterally completely over the first semiconductor layer. In particular, the second layer of the first electrode completely covers the underside of the first sublayer of the first semiconductor layer, especially in the active region and the termination region. Illustratively, the first layer of the first electrode covers the second layer of the first electrode only in the active region. This means that the first layer of the first electrode extends laterally only in the active region.

[0034] Alternatively, the second electrode extends laterally completely over the second semiconductor layer. In particular, the third layer of the second electrode completely covers the top surface of the fourth sublayer of the second semiconductor layer, particularly in the active region and the termination region. Illustratively, the fourth layer of the second electrode covers the third layer of the second electrode only in the active region. This means that the fourth layer of the second electrode extends laterally only over the active region.

[0035] According to a further embodiment of the power semiconductor device, the other of the first and second electrodes extends only over the active region.

[0036] If the first electrode completely covers the first semiconductor layer in the lateral direction, i.e., extends over the active and termination regions, the second electrode extends only over the active region, and in particular, the third and fourth layers of the second electrode have the same lateral extent.

[0037] If the second electrode completely covers the second semiconductor layer in the lateral direction, i.e., extends into the active region and the termination region, the first electrode extends only into the active region, and in particular, the first and second layers of the first electrode are coextensive in the lateral direction.

[0038] According to further embodiments of the power semiconductor device, the fourth sublayer laterally spans the active region and the termination region. For example, the fourth sublayer overlaps the active region and at least partially overlaps the termination region in a plan view. If the second semiconductor layer has a sloped structure, the fourth sublayer overlaps the termination region by at least 20% or at least 50% in a plan view.

[0039] According to a further embodiment of the power semiconductor device, the fourth sub-layer extends only in the active region, in particular the fourth sub-layer overlaps only the active region and not the termination region in plan view.

[0040] This advantageously further reduces the emitter efficiency in the termination region. According to an embodiment of the power semiconductor device, at least one of the first semiconductor layer and the second semiconductor layer has a sloped structure. Illustratively, each of the first semiconductor layer and the second semiconductor layer has a lower surface and an upper surface that extend laterally, and the upper surface and the lower surface are connected by at least one side surface. At least one side surface of the first semiconductor layer and the second semiconductor layer is inclined with respect to the up-down direction in the termination region.

[0041] For example, the ramp structure is arranged in the end region, in particular, the ramp structure is arranged only in the end region, which means that the ramp structure defines the extent of the end region in the lateral direction.

[0042] According to a further embodiment of the power semiconductor device, the second semiconductor layer is tapered towards the second electrode in the termination region, in that a sloped structure is arranged in the second semiconductor layer such that a side surface of the second semiconductor layer encloses an angle of less than 90° with the top surface of the drift layer.

[0043] Depending on the angle, i.e. depending on the steepness of the slope structure, the junction depth can be predetermined, which means that depending on the angle the emitter efficiency in the termination region can be precisely preset.

[0044] According to a further embodiment of the power semiconductor device, the first semiconductor layer is tapered towards the first electrode in the termination region, in that a sloped structure is arranged in the first semiconductor layer such that a side surface of the first semiconductor layer encloses an angle of less than 90° with the lower surface of the drift layer.

[0045] Advantageously, the emitter efficiency in the termination region can be preset particularly accurately as a function of the angle.

[0046] According to a further embodiment of the power semiconductor device, an oxide layer is located on the first sub-layer in the active region and in the termination region, and illustratively, a lower surface of the first sub-layer and a lower surface of the oxide layer do not lie in a common plane.

[0047] Illustratively, the oxide layer extends only partially in the active region and completely in the termination region, and when the sloped surface structure is disposed on the second semiconductor layer, the oxide layer completely covers the first electrode in the termination region.

[0048] Alternatively, if the bevel structure is disposed on the first semiconductor layer, the oxide layer completely covers the second electrode in the termination region.

[0049] According to a further embodiment of the power semiconductor device, the oxide layer is located between the first sublayer and the first electrode. Illustratively, the lower surface of the first sublayer and the lower surface of the oxide layer are in direct contact with the first electrode, in particular the second layer.

[0050] According to a further embodiment of the power semiconductor device, the oxide layer extends laterally from the termination region into the active region to an extension distance, in particular, the oxide layer extends laterally from the interface between the termination region and the active region into the active region to an extension distance.

[0051] According to a further embodiment of the power semiconductor device, the extension distance is between 1 and 7 times the vertical height of the drift layer, in particular between 3 and 5 times the height of the drift layer.

[0052] Such an extension distance advantageously reduces emitter efficiency at the interface between the termination region and the active region.

[0053] According to a further embodiment of the power semiconductor device, a further oxide layer is located on the fourth sublayer in the active region, illustratively such that the top surfaces of the fourth sublayer and the further oxide layer do not lie in a common plane.

[0054] If the sloped structure is disposed on the second semiconductor layer, the additional oxide layer only partially covers the second electrode in the active region, while the termination region, for example, does not have the additional oxide layer.

[0055] Alternatively, if the sloped structure is disposed on the first semiconductor layer, the additional oxide layer may only partially cover the first electrode in the active region, and the termination region may, for example, not have the additional oxide layer.

[0056] According to a further embodiment of the power semiconductor device, a further oxide layer is located between the fourth sublayer and the second electrode. Illustratively, the top surface of the fourth sublayer and the top surface of the oxide layer are in direct contact with the second electrode, in particular the third layer.

[0057] According to a further embodiment of the power semiconductor device, the further oxide layer extends laterally from the termination region into the active region to a further extension distance, in particular from the interface between the termination region and the active region into the active region to a further extension distance.

[0058] According to a further embodiment of the power semiconductor device, the further extension distance is between 1 and 7 times the vertical height of the drift layer, in particular between 3 and 5 times the height of the drift layer.

[0059] The further extension distance may be equal to the extension distance, or the further extension distance may be different from the extension distance.

[0060] According to a further embodiment, the power semiconductor device comprises a passivation, for example, the passivation enveloping a layer of the power semiconductor device. The first electrode and the second electrode are particularly partially free of the passivation. For example, the first layer of the first electrode and the fourth layer of the second electrode are free of the passivation.

[0061] Passivation involves the application of electrically insulating materials, such as dielectric materials. For example, passivation materials include semi-insulating materials on silicon surfaces. In addition to insulating the semiconductor surface from the surroundings, the role of such materials is to drain leakage currents to one of the electrodes, especially at high temperatures.

[0062] According to a further embodiment of the power semiconductor device, the first electrode, the first semiconductor layer, the drift layer, the second semiconductor layer, and the second electrode are surrounded by a passivation in the termination region, for example, the side surfaces of the layers and the electrodes are completely covered by the passivation.

[0063] Illustratively, the sloped structures are completely buried in the passivation, meaning that the side surfaces forming the sloped structures are completely covered with the passivation.

[0064] Advantageously, power semiconductor devices are protected from the environment by passivation.

[0065] According to a further embodiment of the power semiconductor device, the first semiconductor layer is structured by several doped regions of the second conductivity type in the termination region.

[0066] The doped regions extend into the termination region. Illustratively, each doped region has a shape in plan that is circular, elliptical, or polygonal, such as rectangular. In particular, the shape of the doped regions in plan corresponds to the outline of the power semiconductor device, in particular the drift layer, in plan.

[0067] For example, the doped region may be disposed within a semiconductor layer without an oxide layer disposed therein. If the first semiconductor layer includes a doped region, the oxide layer may be disposed on the second semiconductor layer. If the second semiconductor layer includes a doped region, the oxide layer may be disposed on the first semiconductor layer.

[0068] Illustratively, the first sub-layer includes a doped region and / or the fourth sub-layer includes a doped region.

[0069] According to a further embodiment of the power semiconductor device, the first sublayer is laterally divided into segments by the doped regions. Illustratively, the segments are laterally separated by the doped regions, meaning that directly adjacent segments are not in physical contact with each other.

[0070] By means of a doped region, in particular a combination of an oxide layer and a doped region, the emitter efficiency can be particularly accurately predetermined and reduced.

[0071] Furthermore, methods for manufacturing power semiconductor devices are described herein by which the power semiconductor devices described hereinabove can be manufactured or by which the power semiconductor devices described hereinabove can be manufactured, and therefore features relating to the power semiconductor devices are also disclosed with reference to the methods and vice versa.

[0072] According to one embodiment of the method, a semiconductor material is provided with a drift layer. Exemplarily, the semiconductor material is silicon-based. The semiconductor material is provided in particular as a wafer.

[0073] Illustratively, the drift layer of the first conductivity type is created during the pulling of the silicon ingot, i.e., the drift layer is present in the starting silicon wafer prior to fabrication.

[0074] According to an embodiment of the method, a first semiconductor layer of a first conductivity type is formed in the drift layer from a first side. Illustratively, a first dopant may be introduced into the wafer, e.g., the drift layer, from the first side, e.g., by at least one of an ion implantation or a deposition process, followed by a diffusion process.

[0075] According to an embodiment of the method, a second semiconductor layer of a second conductivity type different from the first conductivity type is formed in the drift layer from a second side opposite the first side. Illustratively, a second dopant may be introduced into the wafer, e.g., the drift layer, from the second side, e.g., by at least one of an ion implantation or a deposition process, followed by a diffusion process.

[0076] According to an embodiment of the method, a bevel structure is formed in at least one of a first semiconductor layer and a second semiconductor layer in a termination region surrounding an active region of a power semiconductor device.

[0077] According to an embodiment of the method, an oxide layer is formed on at least one of the first semiconductor layer or the second semiconductor layer.

[0078] According to a further embodiment of the method, the ramp structure is formed by a grinding process. The accompanying figures are included to provide a further understanding. In the figures, elements of identical structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. [Brief explanation of the drawings]

[0079] [Figure 1] 1 is a cross-sectional view of a power semiconductor device in accordance with an exemplary embodiment. [Figure 2] 1 is a cross-sectional view of a power semiconductor device in accordance with an exemplary embodiment. [Figure 3] 1 is a cross-sectional view of a power semiconductor device in accordance with an exemplary embodiment. [Figure 4] 1 is a schematic plan view of a power semiconductor device according to an exemplary embodiment; [Figure 5] 1 is an exemplary diagram of hole density for various exemplary embodiments of a power semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0080] 1 comprises a first electrode 2 comprising a first layer 14 and a second layer 15, and a second electrode 6 comprising a third layer 16 and a fourth layer 17. The power semiconductor device 1 further comprises a first semiconductor layer 3 of a first conductivity type comprising a first sub-layer 10 and a second sub-layer 11, and a second semiconductor layer 5 of a second conductivity type comprising a third sub-layer 12 and a fourth sub-layer 13. Furthermore, the power semiconductor device 1 comprises a drift layer 4.

[0081] The first electrode 2, specifically the first layer 14 and the second layer 15; the first semiconductor layer 3, specifically the first sublayer 10 and the second sublayer 11; the drift layer 4; the second semiconductor layer 5, specifically the third sublayer 12 and the fourth sublayer 13; and the second electrode 6, specifically the third layer 16 and the fourth layer 17, are stacked on top of each other in a stacking direction corresponding to the vertical direction. Each layer extends in a horizontal direction perpendicular to the vertical direction. Furthermore, each layer is in direct contact with each other. The bottom surfaces of the layers face the first electrode 2, and the top surfaces of the layers face the second electrode 6.

[0082] The second layer 15 of the first electrode 2 completely covers the underside of the first sublayer 10 of the first semiconductor layer 3. The first layer 14 of the first electrode 2 completely covers the underside of the second layer 15 only in the active region 9 of the power semiconductor device 1. This means that the first layer 14 completely overlaps, and in particular is congruent with, the active region 9 in the lateral direction in a plan view.

[0083] In particular, the plan view is a view of the top surface of each element of the power semiconductor device 1 as seen from above and below.

[0084] The active area 9 is located at and extends laterally around the center of mass of the power semiconductor device 1. Figure 1 shows only half of the power semiconductor device 1. Illustratively, the left edge of Figure 1 contains the center of mass.

[0085] A termination region 8 extends laterally along an edge region of the power semiconductor device 1 that defines an active region 9. The first layer 14 of the first electrode 2 is absent in the termination region 8. This means that the first layer 14 does not overlap the termination region 8 in the lateral direction in a plan view.

[0086] The third layer 16 of the second electrode 6 completely covers the top surface of the fourth sublayer 13 of the second semiconductor layer 5 only in the active region 9. The fourth layer 17 of the second electrode 6 completely covers the top surface of the third layer 16. This means that the third layer 16 and the fourth layer 17 each completely overlap, and in particular are congruent with, the active region 9 in the lateral direction in a plan view.

[0087] The third layer 16 and the fourth layer 17 of the second electrode 6 are absent in the termination region 8. This means that the third layer 16 and the fourth layer 17 do not overlap with the termination region 8 in the lateral direction in a plan view.

[0088] The second semiconductor layer 5 has a sloped structure 19 in the termination region 8. The side surface of the second semiconductor layer 5 connecting the upper surface and the lower surface of the second semiconductor layer 5 is sloped with respect to the vertical direction. The side surface of the second semiconductor layer 5 is sloped only in the termination region 8. The angle between the side surface of the second semiconductor layer 5 and the lower surface of the second semiconductor layer 5 is smaller than 90°, particularly smaller than 45°. This means that the third sublayer 12 and the fourth sublayer 13 are tapered toward the second electrode 6 in the termination region 8.

[0089] An oxide layer 24 extending into the active region 9 and the termination region 8 is disposed on the first sublayer 10 of the first semiconductor layer 3. The oxide layer 24 faces the first electrode 2. The oxide layer 24 comprises the semiconductor material of the first semiconductor layer 3.

[0090] The lower surface of the oxide layer 24 protrudes above the lower surface of the first sublayer 10 in the vertical direction toward the first electrode 2. The first electrode 2 completely covers the lower surfaces of the first sublayer 10 and the oxide layer 24.

[0091] Oxide layer 24 extends only partially into active region 9 and completely into termination region 8, meaning that oxide layer 24 completely overlaps termination region 8 in a plan view. Oxide layer 24 extends laterally into active region 9 from the interface between active region 9 and termination region 8 to an extension distance 23. Extension distance 23 is between 1 and 7 times the vertical height of drift layer 4.

[0092] The power semiconductor device 1 further comprises a passivation 18. The passivation 18 encases the layers of the power semiconductor device 1, the first electrode 2 and the second electrode 6 in particular being partially free of the passivation 18.

[0093] 2, the fourth sublayer 13 of the second semiconductor layer 5 includes an oxide layer 24. In contrast to the exemplary embodiment of FIG. 1, the oxide layer 24 extends only into the active region 9. This means that the oxide layer 24 completely overlaps the active region 9 over an extension distance 23 in a plan view, and furthermore, the oxide layer 24 does not overlap the termination region 8 in a plan view.

[0094] The oxide layer 24 faces the second electrode 6. The oxide layer 24 comprises the semiconductor material of the second semiconductor layer 5.

[0095] The upper surface of the oxide layer 24 protrudes above the upper surface of the fourth sublayer 13 in the vertical direction toward the second electrode 6. The second electrode 6 completely covers the upper surfaces of the fourth sublayer 13 and the oxide layer 24.

[0096] Similar to FIG. 1, oxide layer 24 extends laterally into active region 9 from the interface between active region 9 and termination region 8 to a distance 23 .

[0097] The power semiconductor device 1 according to the exemplary embodiment of Figure 4 has an oxide layer 24 and a further oxide layer 25. The oxide layer 24 on the first sublayer 10 corresponds to the oxide layer 24 of Figure 1, and the further oxide layer 25 on the fourth sublayer 13 corresponds to the oxide layer 24 of Figure 2.

[0098] The power semiconductor device 1 according to the exemplary embodiment of Figure 4 is a plan view of one of the power semiconductor devices 1 according to one of Figures 1 to 3. In the plan view, the upper surface of the fourth layer 17 and the passivation 18 are freely accessible. The external shape of the power semiconductor device 1 is circular.

[0099] The doped regions are not visible in this view and are therefore shown as dashed lines. The doped regions extend into the termination region 8, and each of the doped regions completely surrounds the active region 9 in the lateral direction. In particular, each of the doped regions has a circular shape in plan view that corresponds to the outline of the power semiconductor device 1 in plan view.

[0100] In the diagram according to FIG. 5, the y-axis represents the hole density ρ (unit: cm -3 ), and the x-axis represents the distance x (unit: μm) from the center of the power semiconductor device 1 to the edge region in the lateral direction within the drift layer 4.

[0101] The curve C1 corresponds to a typical power semiconductor device 1 without the first semiconductor layer 3 having the oxide layer 24. The curve C2 corresponds to the power semiconductor device 1 according to Figure 1, the curve C3 corresponds to the power semiconductor device 1 according to Figure 2 and the curve C4 corresponds to the power semiconductor device 1 according to Figure 3. [Explanation of symbols]

[0102] Reference sign 1. Power semiconductor devices 2 First electrode 3 First semiconductor layer 4 Drift layer 5 Second semiconductor layer 6 Second electrode 7 Doped Region 8 Termination area 9 Active area 10 First Sub-Layer 11 Second Sub-Layer 12 Third Sub-Layer 13 Fourth Sub-Layer 14 First Layer 15 Second Layer 16 Third Layer 17 Fourth Layer 18 Passivation 19 Slope structure 20 segments 21 Further doped regions 23 Extended distance 24 oxide layer 25 Further oxide layers

Claims

1. a first electrode (2), a first semiconductor layer (3) of a first conductivity type; a drift layer (4) of the first conductivity type; a second semiconductor layer (5) of a second conductivity type different from the first conductivity type; a second electrode (6) and A power semiconductor device (1) comprising: an oxide layer (24) extending into an active region (9) of the power semiconductor device (1) surrounded by a termination region (8) of the power semiconductor device (1) is disposed on at least one of the first semiconductor layer (3) and the second semiconductor layer (5); A power semiconductor device (1), wherein at least one of the first semiconductor layer (3) and the second semiconductor layer (5) has a bevel structure (19) in the termination region (8).

2. 2. The power semiconductor device according to claim 1, wherein the first electrode, the first semiconductor layer, the drift layer, the second semiconductor layer, and the second electrode are stacked on one another along a vertical stacking direction.

3. the first semiconductor layer (3) comprises a first sublayer (10) facing the first electrode (2) and a second sublayer (11) facing the drift layer (4); the maximum doping concentration of the first sublayer (10) is greater than the maximum doping concentration of the second sublayer (11); the second semiconductor layer (5) comprises a third sub-layer (12) facing the drift layer (4) and a fourth sub-layer (13) facing the second electrode (6); the maximum doping concentration of the fourth sublayer (13) is higher than the maximum doping concentration of the third sublayer (12); A power semiconductor device (1) according to any one of claims 1 or 2.

4. one of the first electrode (2) and the second electrode (6) extends into the active region (9) and the termination region (8); the other of the first electrode (2) and the second electrode (6) extends only over the active area (9); A power semiconductor device (1) according to any one of claims 1 to 3.

5. the fourth sub-layer (13) extends laterally in the active region (9) and in the termination region (8), or the fourth sublayer (13) extends only to the active region (9); A power semiconductor device (1) according to any one of claims 3 or 4.

6. the second semiconductor layer (5) is tapered towards the second electrode (6) in the termination region (8); and the first semiconductor layer (3) is tapered towards the first electrode (2) in the termination region (8); The power semiconductor device (1) according to any one of claims 1 to 5, wherein the power semiconductor device (1) is at least one of the above.

7. the oxide layer (24) is located on the first sub-layer (10) in the active region (9) and in the termination region (8); the oxide layer (24) is located between the first sublayer (10) and the first electrode (2); A power semiconductor device (1) according to any one of claims 3 to 6.

8. the oxide layer (24) extends laterally from the termination region (8) into the active region (9) by a distance (23); The extension distance (23) is 1 to 7 times the vertical height of the drift layer (4). A power semiconductor device (1) according to any one of claims 1 to 7.

9. the oxide layer (24) is disposed on the first semiconductor layer (3); a further oxide layer (25) is located on the fourth sub-layer (13) in the active area (9); the further oxide layer is located between the fourth sublayer (13) and the second electrode (6); A power semiconductor device (1) according to any one of claims 3 to 8.

10. the further oxide layer (25) extends laterally from the termination region (8) to a further extension distance (23) into the active region (9); The further extension distance (23) is equal to or greater than 1 time and equal to or less than 7 times the vertical height of the drift layer (4). A power semiconductor device (1) according to claim 9.

11. the first semiconductor layer (3) is structured by several doped regions (7) of the second conductivity type in the termination region (8), A power semiconductor device (1) according to any one of claims 1 to 10.

12. The first sublayer (10) is laterally divided into segments (20) by the doped regions (7). A power semiconductor device (1) according to claim 11.

13. Passivation (18) Furthermore, The first electrode (2), the first semiconductor layer (3), the drift layer (4), the second semiconductor layer (5), and the second electrode (6) are surrounded by the passivation (18). A power semiconductor device (1) according to any one of claims 1 to 12.

14. 1. A method for manufacturing a semiconductor device, comprising: - providing a drift layer (4) of a first conductivity type in a semiconductor material; - manufacturing a first semiconductor layer (3) of said first conductivity type in said drift layer (4) from a first side; - fabricating a second semiconductor layer (5) of a second conductivity type different from the first conductivity type in the drift layer (4) from a second side opposite to the first side; - manufacturing a bevel structure (19) in at least the first semiconductor layer (3) and the second semiconductor layer (5) in a termination region (8) surrounding an active region (9) of the power semiconductor device (1); - Producing an oxide layer (24) on at least one of the first semiconductor layer (3) or the second semiconductor layer (5); Including, The method, wherein the semiconductor device further comprises a first electrode (2) and a second electrode (6).

15. The ramp structure (19) is manufactured by a grinding process. The method of claim 14, wherein the at least one of

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