Multilayer internal spacers for gate-all-around devices

Abstract

Semiconductor devices (e.g., gate-all-around (GAA) type devices), process tools for manufacturing GAA type devices, methods for manufacturing GAA type devices, and multilayer internal spacers for GAA type devices are described. The multilayer internal spacer comprises internal layers, intermediate layers, and external layers within a superlattice structure formed on the top surface of a substrate. The superlattice structure has multiple semiconductor material layers (e.g., silicon-germanium (SiGe)) and corresponding multiple channel layers (e.g., silicon (Si)) arranged alternately as multiple stacked pairs. In some embodiments, the method is carried out in-situ in an integrated deposition and etching system.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to semiconductor devices. More particularly, embodiments of the present disclosure are directed to gate-all-around (GAA) type devices and methods of forming GAA type devices having multilayer internal spacers.

Background Art

[0002] Transistors are a major component of most integrated circuits. Since the drive current, and thus the speed, of a transistor is proportional to the gate width of the transistor, generally, faster transistors require a larger gate width. Thus, there is a trade-off between transistor size and speed, and "fin" field-effect transistors (finFETs) have been developed to address the conflicting goals of transistors with maximum drive current and minimum size. FinFETs are characterized by fin-shaped channel regions that greatly increase the transistor size without significantly increasing the footprint of the transistor, and are currently applied to many integrated circuits. However, finFETs have specific drawbacks.

[0003] As the feature sizes of transistor devices continue to shrink to achieve higher circuit density and higher performance, it is necessary to improve the transistor device structure to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and horizontal gate-all-around (hGAA) structures. The hGAA type device structure includes a plurality of lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. The hGAA structure provides good electrostatic control and may become widely popular in complementary metal-oxide semiconductor (CMOS) wafer manufacturing.

[0004] One challenge in CMOS wafer manufacturing (and GAA formation) is reducing parasitic capacitance. In attempts to reduce parasitic capacitance and optimize the speed of ring oscillators composed of GAA-type devices, low-κ dielectric materials for internal spacers in GAA-type devices are being investigated.

[0005] However, there is a trade-off between the κ value of internal spacers and "robustness," particularly for GAA-type devices that require a nanosheet release process, where materials with lower κ values ​​exhibit greater resistance to dry etching and / or wet etching processes. Damage / penetration of internal spacers at weak corners is one of the main factors contributing to reduced yield in GAA-type devices.

[0006] Therefore, there is a need for improved methods to form internal spacers for gate-all-around (GAA) type devices. [Overview of the project]

[0007] One or more embodiments of this disclosure relate to methods for manufacturing electronic devices. In some embodiments, the method includes forming a multilayer internal spacer comprising an internal layer, an intermediate layer, and an external layer within a superlattice structure formed on the top surface of a substrate. The superlattice structure comprises a plurality of semiconductor material layers and a corresponding plurality of channel layers arranged alternately as a plurality of stacked pairs. The plurality of semiconductor material layers include silicon germanium (SiGe), and the corresponding plurality of channel layers include silicon (Si). In some embodiments, forming a multilayer internal spacer includes depositing internal layers in recesses of the plurality of semiconductor material layers, depositing intermediate layers on the internal layers, and depositing external layers on the intermediate layers, the external layers being adjacent to source and drain regions.

[0008] Additional embodiments of this disclosure relate to methods for manufacturing electronic devices. In some embodiments, the method includes forming a multilayer internal spacer comprising an internal layer, an intermediate layer, and an external layer within a superlattice structure formed on the top surface of a substrate. The superlattice structure comprises a plurality of semiconductor material layers and a corresponding plurality of channel layers arranged alternately as a plurality of stacked pairs. The plurality of semiconductor material layers include silicon germanium (SiGe), and the corresponding plurality of channel layers include silicon (Si). In some embodiments, forming a multilayer internal spacer includes depositing an internal layer in the recesses of the plurality of semiconductor material layers, optionally etching the internal layer, depositing an intermediate layer on the internal layer, etching a portion of the intermediate layer, and depositing an external layer on the intermediate layer, wherein the external layer is adjacent to source and drain regions, and etching the external layer.

[0009] Further embodiments of this disclosure relate to processing tools. In some embodiments, the processing tool comprises a central transfer station with a robot configured to move a substrate, a plurality of process stations, each process station connected to the central transfer station and providing a processing area separated from the processing areas of adjacent process stations, the plurality of process stations comprising chemical vapor deposition (CVD) chambers and etching chambers, and a controller connected to the central transfer station and the plurality of process stations. The controller is configured to actuate the robot to move the substrate between the process stations and to control a process cycle for manufacturing multilayer internal spacers for gate-all-around (GAA) devices. The multilayer internal spacer comprises internal, intermediate, and external layers within a superlattice structure formed on the top surface of the substrate. The superlattice structure comprises a plurality of semiconductor material layers and a corresponding plurality of channel layers arranged alternately as a plurality of stacked pairs. The plurality of semiconductor material layers include silicon germanium (SiGe), and the corresponding plurality of channel layers include silicon (Si). A process cycle for forming a multilayer internal spacer by thermochemical vapor deposition (CVD) includes depositing an internal layer in the recesses of multiple semiconductor material layers, depositing an intermediate layer on the internal layer, and depositing an external layer on the intermediate layer, the external layer being adjacent to the source and drain regions.

[0010] To allow for a more detailed understanding of the features of this disclosure listed above, a more detailed description of this disclosure, which is briefly outlined above, may be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings are merely typical embodiments of this disclosure and should not be considered as limiting its scope, as this disclosure may allow for other equally effective embodiments. [Brief explanation of the drawing]

[0011] [Figure 1]This is a process flow diagram of a method for forming one or more electronic devices according to one or more embodiments. [Figure 2A] This is a schematic cross-sectional view of one or more electronic devices according to one or more embodiments. [Figure 2B] This is a schematic cross-sectional view of one or more electronic devices according to one or more embodiments. [Figure 2C] This is a schematic cross-sectional view of one or more electronic devices according to one or more embodiments. [Figure 2D] This is a schematic cross-sectional view of one or more electronic devices according to one or more embodiments. [Figure 2E] This is a schematic cross-sectional view of one or more electronic devices according to one or more embodiments. [Figure 2F] This is a schematic cross-sectional view of one or more electronic devices according to one or more embodiments. [Figure 2G] This is a schematic cross-sectional view of one or more electronic devices according to one or more embodiments. [Figure 2H] This is a schematic cross-sectional view of one or more electronic devices according to one or more embodiments. [Figure 2I] This is a schematic cross-sectional view of one or more electronic devices according to one or more embodiments. [Figure 2J] This is a schematic cross-sectional view of a device according to one or more embodiments. [Figure 3] This is a process flow diagram of a method for forming a multilayer internal spacer according to one or more embodiments. [Figure 3A] This is a schematic cross-sectional view of one manufacturing stage of a multilayer internal spacer shown in Figure 3, according to one or more embodiments. [Figure 3B] This is a schematic cross-sectional view of one manufacturing stage of a multilayer internal spacer shown in Figure 3, according to one or more embodiments. [Figure 3C] This is a schematic cross-sectional view of one manufacturing stage of a multilayer internal spacer shown in Figure 3, according to one or more embodiments. [Figure 3D] This is a schematic cross-sectional view of one manufacturing stage of a multilayer internal spacer shown in Figure 3, according to one or more embodiments. [Figure 4]It is a process flow diagram of a method for forming a multilayer internal spacer according to one or more embodiments. [Figure 4A] It is a schematic cross-sectional view of a manufacturing stage of the multilayer internal spacer of FIG. 4 according to one or more embodiments. [Figure 4B] It is a schematic cross-sectional view of a manufacturing stage of the multilayer internal spacer of FIG. 4 according to one or more embodiments. [Figure 4C] It is a schematic cross-sectional view of a manufacturing stage of the multilayer internal spacer of FIG. 4 according to one or more embodiments. [Figure 4D] It is a schematic cross-sectional view of a manufacturing stage of the multilayer internal spacer of FIG. 4 according to one or more embodiments. [Figure 4E] It is a schematic cross-sectional view of a manufacturing stage of the multilayer internal spacer of FIG. 4 according to one or more embodiments. [Figure 4F] It is a schematic cross-sectional view of a manufacturing stage of the multilayer internal spacer of FIG. 4 according to one or more embodiments. [Figure 5] It is a schematic top view of an exemplary multi-chamber processing system for forming an electronic device according to one or more embodiments.

Best Mode for Carrying Out the Invention

[0012] For ease of understanding, the same reference numbers are used, where possible, to denote the same elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without further elaboration.

[0013] Before describing multiple exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the structures or process steps described in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0014] As used herein and in the appended claims, the term “substrate” refers to the surface or portion of a surface on which the process acts. Furthermore, unless otherwise explicitly stated in the context, it will be understood by those skilled in the art that “substrate” may also refer to only a portion of a substrate. In addition, “deposition on a substrate” may refer to both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0015] As used herein, “substrate” refers to any substrate or material surface formed on a substrate that is subjected to a film treatment during a manufacturing process. For example, substrate surfaces that may be treated include, depending on the application, materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise generate or graft target chemical moieties to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to direct film treatment of the substrate surface itself, any of the film treatment steps disclosed herein may be performed on underlying layers formed on the substrate as more detailed below, and the term “substrate surface” is intended to include underlying layers as indicated in the context. Therefore, for example, when a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface includes depends on what film is deposited, as well as the specific chemical reaction used.

[0016] As used herein and in the appended claims, terms such as “precursor,” “reactant,” and “reactive gas” are interchangeable to refer to any gas species capable of reacting with the substrate surface.

[0017] As used herein, the term "in-situ" refers to processes carried out entirely in the same processing chamber, or in different processing chambers connected as part of a processing system, where each of those processes is carried out without the intervention of vacuum breaking. As used herein, the term "ex-situ" refers to processes carried out in at least two different processing chambers, where one or more of those processes are carried out with the intervention of vacuum breaking. In some embodiments, the processes are carried out without vacuum breaking or exposure to ambient air.

[0018] A transistor is a circuit component or element often formed in a semiconductor device. Depending on the circuit design, a transistor is formed in a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric sandwiched between the gate electrode and the channel region in the substrate.

[0019] As used herein, the term “field-effect transistor” or “FET” refers to a transistor that uses an electric field to control the electrical behavior of a device. Enhancement-mode field-effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by the voltage difference between the device body and the gate. The three terminals of an FET are the source (S) where carriers enter the channel, the drain (D) where carriers exit the channel, and the gate (G), which modulates the channel conductivity. Conventionally, the current entering the channel at the source (S) is I S It is called the current entering the channel at the drain (D) and the current is I D It is called [this]. The drain-source voltage is V DSIt is called a gate (G) and the current entering the channel at the drain (i.e., I D ) can be controlled.

[0020] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and its voltage determines the device's conductivity. This ability to change conductivity with increasing voltage is used to amplify or switch electronic signals. A MOSFET is based on the modulation of charge concentration by a metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body and isolated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a separate highly doped region separated by the body region. These regions can be either p-type or n-type, but both are of the same type and are the opposite type to the body region. Unlike the body, the source and drain are highly doped, as indicated by the "+" sign after the doping type.

[0021] If a MOSFET is an n-channel or nMOS FET, the source and drain are in the n+ region, and the body is in the p region. If a MOSFET is a p-channel or pMOS FET, the source and drain are in the p+ region, and the body is in the n region. The source is named as such because it is the source of charge carriers (electrons in the case of n-channels, holes in the case of p-channels) flowing through the channel, and similarly, the drain is where the charge carriers exit the channel.

[0022] As used herein, the term “Fin field-effect transistor (FinFET)” refers to a substrate-mounted MOSFET transistor in which the gate is located on two or three sides of the channel, forming a double or triple gate structure. FinFET devices are given the common name FinFET because the channel region forms “fins” on the substrate. FinFET devices have fast switching times and high current densities.

[0023] As used herein, the term “gate all around (GAA)” is used to refer to an electronic device, such as a transistor, in which the gate material surrounds the channel region on all sides. The channel region of a GAA transistor may include nanowires or nanoslabs, or nanosheets, bar-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA-type device has a plurality of vertically separated horizontal nanowires or horizontal bars, thereby making the GAA transistor a stacked horizontal gate all around (hGAA) transistor.

[0024] As used herein, the term "nanowire" refers to a wire with a diameter of nanometers (10⁻¹⁰ -9 This refers to nanostructures on the order of meters. Nanowires may be defined as having a length-to-width ratio greater than 1000. Alternatively, nanowires may be defined as structures whose thickness or diameter is limited to tens of nanometers or less, and whose length is not limited. Nanowires are used in transistors and some laser applications, and in one or more embodiments, they are fabricated from semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in logic CPUs, GPUs, MPUs, and transistors for volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term “nanosheet” refers to a two-dimensional nanostructure with a thickness in the range of about 0.1 nm to about 1000 nm.

[0025] Embodiments of the present disclosure will be described with reference to drawings illustrating devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The processes shown are merely illustrative possible uses of the processes of the disclosure, and those skilled in the art will recognize that the processes of the disclosure are not limited to the illustrative applications.

[0026] Figure 1 shows a process flow diagram of Method 100 for forming an electronic device (e.g., a gate-all-around device (GAA) 290) according to some embodiments of the present disclosure. Method 100 is described below in relation to Figures 2A to 2J, which show the manufacturing steps of a semiconductor structure according to some embodiments of the present disclosure. Figures 2A to 2J show cross-sectional views of a GAA device 290 according to one or more embodiments. Method 100 may be part of a multi-stage manufacturing process for a semiconductor device. Therefore, Method 100 may be carried out in any suitable processing chamber coupled to a cluster tool such as the processing system 400 shown in Figure 5. The processing system 400 may include processing chambers for manufacturing a semiconductor device, such as chambers configured to perform etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chambers used for manufacturing a semiconductor device.

[0027] Method 100 for forming the GAA type device 290 begins in operation 102 by providing a substrate 200 having a top surface 202 (as shown in Figure 2A). In some embodiments, the substrate 200 may be a bulk semiconductor substrate. As used herein, the term “bulk semiconductor substrate” refers to a substrate in which the entire substrate is made of semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor material may include one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 200 includes a semiconductor material, e.g., silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 200 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While some examples of materials on which substrates can be formed are described herein, any material that can function as a base on which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be mounted falls within the spirit and scope of this disclosure.

[0028] In some embodiments, the semiconductor material may be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term “n-type” refers to a semiconductor formed by doping an electron donor element into a true semiconductor during manufacturing. The term n-type derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. As used herein, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration higher than the electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof. In some embodiments, the substrate may be doped to supply a high dose of dopant to a first location on the surface of the substrate 200 in order to prevent the turn-on of the parasitic bottom device.

[0029] At least one superlattice structure 204 is formed on the top surface 202 of the substrate 200 (as shown in Figure 2A). The superlattice structure 204 comprises a plurality of semiconductor material layers 226 and a corresponding plurality of channel layers 224 arranged alternately as a plurality of stacked pairs. In some embodiments, the plurality of stacked groups include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In some embodiments, the silicon-germanium (SiGe) may contain germanium (Ge) in a mole fraction ranging from 0% to 50%. In some embodiments, the plurality of semiconductor material layers 226 include silicon-germanium (SiGe), and the plurality of channel layers 224 include silicon (Si). In some embodiments, the plurality of semiconductor material layers 226 and the corresponding plurality of channel layers 224 may include any number of lattice-matched material pairs suitable for forming the superlattice structure 204. In some embodiments, the plurality of semiconductor material layers 226 and the corresponding plurality of channel layers 224 comprise about 2 to about 50 pairs of lattice-matched materials. In some embodiments, the plurality of channel layers 224 may be doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

[0030] In one or more embodiments, the thickness of the plurality of semiconductor material layers 226 and the plurality of channel layers 224 is in the range of about 2 nm to about 50 nm, in the range of about 3 nm to about 20 nm, or in the range of about 2 nm to about 15 nm.

[0031] In some embodiments, the dielectric material 246 is deposited on the substrate 200 using a conventional chemical vapor deposition method. In some embodiments, the dielectric material 246 is recessed below the top surface 202 of the substrate 200 so that the bottom of the superlattice structure 204 is formed from the substrate 200.

[0032] Referring to Figure 2B, in some embodiments, a substitution gate structure (e.g., a dummy gate structure 208) is formed and patterned on the superlattice structure 204. The dummy gate structure 208 defines the channel region of the transistor device. The dummy gate structure 208 may be formed using any suitable conventional deposition and patterning process known in the art. The dummy gate structure 208 may contain any suitable material known to those skilled in the art. In some embodiments, the dummy gate structure 208 comprises one or more of a dummy gate metal layer and a dummy gate polycrystalline silicon layer.

[0033] Referring to Figure 2C, in some embodiments, the sidewall spacer 210 is formed along the outer wall of the dummy gate structure 208. In some embodiments, the sidewall spacer 210 includes suitable insulating materials known in the art, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. In some embodiments, the sidewall spacer 210 is formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma atomic layer deposition, plasma chemical vapor deposition, or low-pressure chemical vapor deposition.

[0034] Referring to Figure 2D, in operation 108, in some embodiments, the source trench 232 and the drain trench 234 are formed adjacent to the superlattice structure 204 on either side of the superlattice structure 204. In some embodiments, the source trench 232 is formed adjacent to a first end of the superlattice structure 204, and the drain trench 234 is formed adjacent to a second opposite end of the superlattice structure 204. In the embodiment shown in Figure 2D, one of the source trench 232 or the drain trench 234 is not shown on the front of the superlattice structure 204. The other end of the superlattice structure 204 has the other of the source trench 232 or the drain trench 234.

[0035] Referring to Figure 2E, in operation 110, a shallow trench isolation (STI) 250 is formed beneath the superlattice structure 204. As used herein, the term “shallow trench isolation (STI)” refers to an integrated circuit mechanism that prevents leakage current. In one or more embodiments, the STI is formed by depositing one or more dielectric materials (such as silicon dioxide) to fill a trench or opening and removing the excess dielectric using a technique such as chemical mechanical planarization (CMP).

[0036] In one or more embodiments, an opening (not shown) is formed beneath the superlattice structure 204. In one or more embodiments, the opening may be formed beneath the superlattice structure 204 by isotropic etching. In some embodiments, the superlattice structure 204 comprises alternating layers of silicon (Si) and silicon germanium (SiGe), such as a plurality of semiconductor material layers 226 and a plurality of corresponding channel layers 224, which are isotropically etched to form an opening beneath the superlattice structure 204.

[0037] In operation 112, as shown in Figure 2F, the internal spacer 212 is formed after selectively indenting the semiconductor material layer 226 from the source / drain trenches 232 / 234. Embodiments of this disclosure relate to a method for forming an electronic device (e.g., method 100) that includes forming a multilayer internal spacer 212 in operation 112, as shown in Figures 3, 3A-3D, 4, and 4A-4F.

[0038] Embodiments of this disclosure are advantageous in that they have a generally low effective capacity (C eff This invention relates to a composite (multilayer) internal spacer configuration that has the following properties, while also possessing high resistance to dry etching and wet etching processes.

[0039] Embodiments of this disclosure are advantageous in that they provide overall lower effective capacitance (C) compared to conventional single-layer and double-layer internal spacers in comparable GAA-type devices. effThis specification applies to composite (multilayer) internal spacer configurations in GAA-type device dimensions of less than 3 nm, having the following characteristics: The multilayer internal spacers described herein comprise an internal layer, an intermediate layer, and an external layer. In some embodiments, one or more of the internal or external layers include a high-κ dielectric material, such as a high-κ dielectric material having a κ value of 6 or greater. In some embodiments, the intermediate layer includes a low-κ dielectric material, such as a low-κ dielectric material having a κ value of 4.2 or less. For example, in an embodiment in which the internal layer has a thickness in the range of 0.5 nm to 2 nm and includes a high-κ dielectric material with a κ value of 6, the intermediate layer has a thickness in the range of 2 nm to 5 nm and includes a low-κ dielectric material with a κ value of 4.2, and the external layer has a thickness in the range of 0.5 nm to 2 nm and includes a high-κ dielectric material with a κ value of 6, the GAA-type device gives about 0.1792 femtofarads per micrometer (fF / μm).

[0040] Figures 3 and 4 show process flow diagrams of a method (operation 112 of method 100) for forming a multilayer internal spacer 212 that can be used in method 100 for forming an electronic device (e.g., a GAA type device 290). Figures 3A to 3D show schematic cross-sectional views of the manufacturing stages of the multilayer internal spacer 212 of Figure 3. Figures 4A to 4F show schematic cross-sectional views of the manufacturing stages of the multilayer internal spacer 212 of Figure 4.

[0041] In some embodiments, the multilayer internal spacer 212 comprises an internal layer 212A, an intermediate layer 212B, and an external layer 212C within a superlattice structure 204 formed on the top surface 202 of the substrate 200. In some embodiments, the superlattice structure 204 comprises a plurality of semiconductor material layers 226 and a corresponding plurality of channel layers 224 arranged alternately as a plurality of stacked pairs. The plurality of semiconductor material layers 226 contain silicon germanium (SiGe), and the corresponding plurality of channel layers 224 contain silicon (Si).

[0042] In some embodiments, forming a multilayer internal spacer in operation 112 includes depositing an internal layer in a recess of a plurality of semiconductor material layers (operation 112A), depositing an intermediate layer on the internal layer (operation 112B), and depositing an external layer on the intermediate layer (operation 112C), wherein the external layer is adjacent to the source region and the drain region.

[0043] Referring to Figures 3 and 3A, in some embodiments, during operation 112A, the inner layer 212A is formed along the recesses of a plurality of semiconductor material layers 226. In some embodiments, the inner layer 212A is formed along a substitution gate structure (e.g., a dummy gate structure 208). The inner layer 212A may include any suitable insulating material known in the art, such as a high-κ dielectric material. In one or more embodiments, the high-κ dielectric material has a κ value of 6 or more. In some embodiments, the high-κ dielectric material of the inner layer 212A includes one or more of silicon nitride (SiN), silicon carbonitride (SiCN), or nitrogen-rich silicon oxycarbonitride (SiOCN). In some embodiments, the inner layer 212A is formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma atomic layer deposition, plasma chemical vapor deposition, low-pressure chemical vapor deposition, or isotropic deposition. In some embodiments, the inner layer 212A has a thickness in the range of 0.5 nm to 2 nm.

[0044] Referring to Figures 3 and 3B, in some embodiments, during operation 112B, an intermediate layer 212B is formed in the inner layer 212A. The intermediate layer 212B may include any suitable insulating material known in the art, such as a low-κ dielectric material. In one or more embodiments, the low-κ dielectric material has a κ value of 4.2 or less. In some embodiments, the low-κ dielectric material of the intermediate layer 212B includes one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or spin-on dielectrics. In some embodiments, the intermediate layer 212B is formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma atomic layer deposition, plasma chemical vapor deposition, low-pressure chemical vapor deposition, or isotropic deposition. In some embodiments, the intermediate layer 212B has a thickness in the range of 2 nm to 5 nm.

[0045] Referring to Figures 3 and 3C, in some embodiments, during operation 112C, the outer layer 212C is formed on the intermediate layer 212B, and the outer layer 212C is adjacent to the source and drain regions 236 / 238, which are further described below. The outer layer 212C may include any suitable insulating material known in the art, such as a high-κ dielectric material. In one or more embodiments, the high-κ dielectric material has a κ value of 6 or greater. In some embodiments, the high-κ dielectric material of the outer layer 212C includes one or more of silicon nitride (SiN), silicon carbonitride (SiCN), or nitrogen-rich silicon oxycarbonitride (SiOCN). In some embodiments, the outer layer 212C is formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma atomic layer deposition, plasma chemical vapor deposition, low-pressure chemical vapor deposition, or isotropic deposition. In some embodiments, the outer layer 212C has a thickness in the range of 0.5 nm to 2 nm.

[0046] In some embodiments, the multilayer internal spacers 212 (e.g., internal layer 212A, intermediate layer 212B, and external layer 212C) are formed by a thermochemical vapor deposition process at temperatures within the range of 400°C to 650°C, including any partial range and values ​​within that range.

[0047] In some embodiments, the multilayer internal spacers 212 (e.g., internal layer 212A, intermediate layer 212B, and external layer 212C) are deposited conformally. As used herein, the term “conformal” means that the layer conforms to the shape of the feature or layer. The conformality of a layer is typically quantified by the ratio of the average thickness of the layer deposited on the sidewall of a feature to the average thickness of the same deposited layer on the field, i.e., top surface, of the substrate. In some embodiments, the multilayer internal spacers 212 (e.g., internal layer 212A, intermediate layer 212B, and external layer 212C) are deposited by a thermochemical vapor deposition process having conformality in the range of 70% to 90%. As used in this context, “conformality in the range of 70% to 90%” means that the ratio of the average thickness of the described layer deposited on the sidewall of a feature to the average thickness of the same deposited layer on the field, i.e., top surface, of the substrate is in the range of 70% to 90%.

[0048] The multilayer internal spacers 212 (e.g., internal layer 212A, intermediate layer 212B, and external layer 212C) may be any suitable shape, including, but not limited to, circular, square, rectangular, or any other polygon.

[0049] In some embodiments, the multilayer internal spacers 212 (e.g., internal layer 212A, intermediate layer 212B, and external layer 212C) are substantially free of seams and / or voids. As used in this context, “substantially free” means that less than 5% of the total composition of the multilayer internal spacers 212 (e.g., internal layer 212A, intermediate layer 212B, and external layer 212C), including less than 4%, less than 3%, less than 2%, less than 1%, less than 0.5%, and less than 0.1%, are seams and / or voids on an atomic basis.

[0050] The etching process of operation 112' may include any suitable etching process that is selective for the multilayer internal spacers 212 (e.g., internal layer 212A, intermediate layer 212B, and external layer 212C). In some embodiments, the etching process of operation 112' includes one or more wet etching processes or dry etching processes.

[0051] In some embodiments, the dry etching process may include conventional plasma etching or a remote plasma-assisted dry etching process such as the SiCoNi® etching process available from Applied Materials, Inc., located in Santa Clara, California. In the SiCoNi® etching process, the device is exposed to plasma species of H2, NF3, and / or NH3, e.g., plasma-excited hydrogen and fluorine species. For example, in some embodiments, the device may be subjected to simultaneous exposure to H2, NF3, and NH3 plasmas. The SiCoNi® etching process may be carried out in a SiCoNi® Preclean chamber, which can be integrated into one of various multi-processing platforms, including the Centura®, Dual ACP, Producer® GT, and Endura® platforms available from Applied Materials®. The wet etching process may include a hydrofluoric acid (HF) rust process, i.e., a so-called "HF rust" process, in which HF etching of the surface is performed, leaving the surface hydrogen-terminated. Alternatively, any other liquid-based pre-epitaxial pre-cleaning process may be used. In some embodiments, the process includes sublimation etching for the removal of native oxides. The etching process may be plasma-based or thermal-based. The plasma process may be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0052] Embodiments of this disclosure are advantageous in that they provide overall lower effective capacitance (C) compared to conventional single-layer and double-layer internal spacers in comparable GAA-type devices. eff This invention relates to composite (multilayer) internal spacer configurations in GAA-type device dimensions of less than 3 nm, having the following characteristics: For example, in an embodiment in which the internal layer 212A has a thickness in the range of 0.5 nm to 2 nm and contains a high-κ dielectric material with a κ value of 6, the intermediate layer 212B has a thickness in the range of 2 nm to 5 nm and contains a low-κ dielectric material with a κ value of 4.2, and the outer layer 212C has a thickness in the range of 0.5 nm to 2 nm and contains a high-κ dielectric material with a κ value of 6, the GAA-type device gives approximately 0.1792 femtofarads per micrometer (fF / μm).

[0053] Figures 4 and 4A to 4F show another embodiment of forming a multilayer internal spacer (operation 112). Figures 4A to 4F show schematic cross-sectional views of the manufacturing steps of the multilayer internal spacer 212 of Figure 4. Figure 4A shows the deposition of an internal layer in the recesses of multiple semiconductor material layers (112A). Figure 4B shows etching a portion of the internal layer (operation 112A'). Figure 4C shows the deposition of an intermediate layer on the internal layer (operation 112B). Figure 4D shows etching a portion of the intermediate layer (operation 112B'). Figure 4E shows the deposition of an external layer on the intermediate layer (operation 112C). Figure 4F shows etching a portion of the external layer (operation 112C'). The deposition operations 112A, 112B, and 112C in Figure 4 may be the same as the deposition operations 112A, 112B, and 112C in Figure 3. The etching processes for operations 112A', 112B', and 112C' in Figure 4 may be the same as the etching process for operation 112' in Figure 3.

[0054] Additional embodiments of this disclosure, as shown in Figure 5, relate to a processing system 400 and the method described herein for forming a multilayer internal spacer 212 for a GAA-type device 290. Examples of processing systems that can be suitably modified in accordance with the teachings provided herein include the Centura®, Dual ACP, Producer® GT, and Endura® platforms, commercially available from Applied Materials® in Santa Clara, California, as well as other processing systems that may be utilized. It is assumed that other processing systems (including those from other manufacturers) can be adapted to benefit from the embodiments described herein.

[0055] The processing system 400 may include any dielectric deposition product (DDP) commercially available from Applied Materials® in Santa Clara, California. In some embodiments, the processing system 400 includes a low-κ silicon oxycarbide (SiOC) dielectric chemical vapor deposition (CVD) chamber. In some embodiments, the processing system 400 includes an advanced unit process solution by combining the low-κ silicon oxycarbide (SiOC) dielectric chemical vapor deposition (CVD) chamber with a Sym3® etching system commercially available from Applied Materials® in Santa Clara, California, providing an integrated tool solution (e.g., an integrated periodic CVD deposition and etching processing system). In some embodiments, the processing system 400 includes an integrated module for forming multilayer internal spacers (operation 112 of method 100). In some embodiments, the processing system 400 is also particularly useful for horizontal wordline applications in 3D memory and for forming contact / sidewall spacers.

[0056] While not intended to be constrained by theory, it is thought that conformal growth is obtained at lower growth rates, while non-conformal films tend to grow at higher growth rates (e.g., greater than approximately 1 Å / cycle). The growth rate (also called the deposition rate) is expressed as the average thickness deposited per cycle. Advantageously, the processing system 400 provides conformal growth for atomic layer deposition (ALD) type and higher growth rates for chemical vapor deposition (CVD) techniques.

[0057] In some embodiments, the operations of the method described herein are performed in the same processing chamber. In some embodiments, the operations of the method described herein are performed in different processing chambers. In some embodiments, the different processing chambers are connected as part of a processing system. In some embodiments, the operations of the method described herein are performed without the intervention of vacuum breaking.

[0058] In some embodiments, one or more of the operations of the method of the disclosure are performed in-situ as described herein. In some embodiments, one or more of the operations of the method of the disclosure are performed ex-situ as described herein.

[0059] Figure 5 shows a schematic top view of an example of a multi-chamber processing system 400 according to an embodiment of the present disclosure. The processing system 400 generally includes a factory interface 402, load lock chambers 404, 406, transfer chambers 408, 410 having transfer robots 412, 414 respectively, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430. As detailed herein, wafers in the processing system 400 may be processed in and transferred between various chambers without exposing the wafers to the ambient environment outside the processing system 400 (e.g., ambient atmospheric environment that may be present in a manufacturing plant). For example, wafers may be processed in and transferred between various chambers in a low-pressure (e.g., about 300 Torr or less) or vacuum environment without disrupting the low-pressure or vacuum environment during the various processes performed on the wafers in the processing system 400. Thus, the processing system 400 may provide an integrated solution for processing a portion of wafers.

[0060] In the illustrated example in Figure 5, the factory interface 402 includes a docking station 440 and a factory interface robot 442 for facilitating wafer transfer. The docking station 440 is configured to receive one or more front-opening unified pods (FOUPs) 444. In some examples, each factory interface robot 442 generally includes a blade 448 located at one end of the factory interface robot 442, which is configured to transfer wafers from the factory interface 402 to the load lock chambers 404, 406.

[0061] Load lock chambers 404 and 406 have ports 450 and 452, respectively, connected to the factory interface 402, and ports 454 and 456, respectively, connected to the transfer chamber 408. Transfer chamber 408 further has ports 458 and 460, respectively, connected to the holding chambers 416 and 418, and ports 462 and 464, respectively, connected to the processing chambers 420 and 422. Similarly, transfer chamber 410 has ports 466 and 468, respectively, connected to the holding chambers 416 and 418, and ports 470, 472, 474, and 476, respectively, connected to the processing chambers 424, 426, 428, and 430. Ports 454, 456, 458, 460, 462, 464, 466, 468, 470, 472, 474, and 476 may be slit valve openings having slit valves for passing wafers through, for example, by transfer robots 412 and 414, and for providing a seal between each chamber to prevent gas from passing between each chamber. Generally, any port is open for transferring wafers through it; otherwise, the port is closed.

[0062] The load lock chambers 404, 406, transfer chambers 408, 410, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430 may be fluid-coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluid-coupled to the various chambers. During operation, the factory interface robot 442 transfers wafers from the FOUP 444 through port 450 or 452 to the load lock chamber 404 or 406. The gas and pressure control system then pumps down the load lock chamber 404 or 406. The gas and pressure control system further maintains the transfer chambers 408, 410 and the holding chambers 416, 418 in a low internal pressure or vacuum environment (which may include an inert gas). Therefore, pumping down the load lock chamber 404 or 406 facilitates passing the wafer between, for example, the atmospheric environment of the factory interface 402 and the low-pressure or vacuum environment of the transfer chamber 408.

[0063] With the wafer in the pumped-down load lock chamber 404 or 406, the transfer robot 412 transfers the wafer from the load lock chamber 404 or 406 to the transfer chamber 408 through port 454 or 456. The transfer robot 412 can then transfer the wafer to one of the processing chambers 420 or 422 through their respective ports 462 or 464 for processing, and to the holding chambers 416 or 418 through their respective ports 458 or 460 for holding awaiting further transfer, and / or transfer the wafer between any of these chambers. Similarly, the transfer robot 414 is capable of accessing wafers in the holding chamber 416 or 418 through port 466 or 468, and can transfer wafers to processing chambers 424, 426, 428, 430 for processing through ports 470, 472, 474, 476 respectively, and to any of the holding chambers 416, 418 for holding awaiting further transfer through ports 466, 468 respectively, and / or transfer wafers between any of these chambers. The transfer and holding of wafers in and between the various chambers may take place in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0064] Processing chambers 420, 422, 424, 426, 428, and 430 may be any suitable chamber for processing wafers. In some embodiments, processing chamber 420 may be capable of performing an annealing process, processing chamber 422 may be capable of performing a cleaning process, and processing chambers 424, 426, 428, and 430 may be capable of performing an epitaxial growth process. In some examples, processing chamber 422 may be capable of performing a cleaning process, processing chamber 420 may be capable of performing an etching process, and processing chambers 424, 426, 428, and 430 may be capable of performing their respective epitaxial growth processes. Processing chamber 422 may be a SiCoNi® Preclean chamber available from Applied Materials, Santa Clara, California. Processing chamber 420 may be a Selectra® Etch chamber available from Applied Materials, Santa Clara, California.

[0065] A system controller 490 is coupled to the processing system 400 to control the processing system 400 or its components. For example, the system controller 490 may control the operation of the processing system 400 by directly controlling the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, and 430 of the processing system 400, or by controlling controllers associated with the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, and 430. During operation, the system controller 490 enables data acquisition and feedback from each chamber to adjust the performance of the processing system 400.

[0066] The system controller 490 generally includes a central processing unit (CPU) 492, memory 494, and support circuitry 496. The CPU 492 may be any form of general-purpose processor that can be used in an industrial environment. The memory 494, or non-temporary computer-readable medium, is accessible by the CPU 492 and may be one or more of the following: local or remote random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or any other form of digital storage. The support circuitry 496 is coupled to the CPU 492 and may include a cache, clock circuitry, input / output subsystems, power supply, etc. Various methods disclosed herein may generally be carried out under the control of the CPU 492 by the CPU 492 executing computer instruction code stored in memory 494 (or in the memory of a particular processing chamber) as, for example, software routines. Once the computer instruction code is executed by the CPU 492, the CPU 492 controls the chamber to perform the processes relating to the various methods.

[0067] Other processing systems may have different configurations. For example, more or fewer processing chambers may be coupled to a transfer device. In the illustrated example, the transfer device includes transfer chambers 408, 410 and holding chambers 416, 418. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., zero holding chambers) may be implemented as transfer devices in the processing system.

[0068] The process may generally be stored in the memory of the system controller 557 as a software routine that, when executed by a processor, causes a processing chamber to perform the process of the disclosure. The software routine may be stored and / or executed by a second processor (not shown) located away from the hardware controlled by the processor. Some or all of the methods of the disclosure may be performed in hardware. Thus, the process may be implemented in software, for example as an application-specific integrated circuit or other type of hardware implement, or as a combination of software and hardware, using a computer system in hardware. When the software routine is executed by a processor, it transforms a general-purpose computer into a dedicated computer (controller) that controls the chamber operation so that the process can be performed.

[0069] One or more embodiments of the present disclosure relate to a non-temporary computer-readable medium containing instructions that, when executed by a controller of the processing chamber, cause the processing chamber to perform the actions described herein.

[0070] In some embodiments, after forming a multilayer internal spacer 212 comprising an internal layer 212A, an intermediate layer 212B, and an external layer 212C, Method 100 proceeds to form subsequent components of the GAA-type device 290.

[0071] In operation 114, the source region 236 and / or the drain region 238 are formed in the source / drain trench 232 / 234. In some embodiments, the outer layer 212C is adjacent to the source region 236 and the drain region 238. In other embodiments, the inner layer 212A is adjacent to the source region 236 and the drain region 238. In some embodiments, the source region 236 and / or the drain region 238 are formed from any suitable semiconductor material, but are not limited to silicon, germanium, silicon germanium, silicon phosphorus, silicon arsenic, etc. In one or more embodiments, the source region 236 and the drain region 238 may be individually doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

[0072] In some embodiments, the source region 236 and the drain region 238 may be formed using any suitable deposition process, such as an epitaxial deposition process.

[0073] Referring to Figure 2H, in some embodiments, an interlayer dielectric (ILD) layer 220 is blanket-deposited onto the source / drain regions 236 / 238, the dummy gate structure 208, and the sidewall spacers 210. The ILD layer 220 may be deposited using conventional chemical vapor deposition methods (e.g., plasma chemical vapor deposition and low-pressure chemical vapor deposition). In one or more embodiments, the ILD layer 220 is formed from any suitable dielectric material, but is not limited to undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride. In one or more embodiments, the ILD layer 220 is then polished backward using conventional chemical mechanical planarization (CMP) to expose the top of the dummy gate structure 208. In some embodiments, the ILD layer 220 is polished to expose the top of the dummy gate structure 208 and the top of the sidewall spacers 210.

[0074] In operation 116, as shown in Figure 2H, the dummy gate structure 208 is removed to expose the channel region 214 of the superlattice structure 204. The ILD layer 220 protects the source / drain region 236 / 238 during the removal of the dummy gate structure 208. The dummy gate structure 208 may be removed using any conventional etching method, such as plasma dry etching or wet etching. In some embodiments, the dummy gate structure 208 comprises polycrystalline silicon, and the dummy gate structure 208 is removed by a selective etching process. In some embodiments, the dummy gate structure 208 comprises polycrystalline silicon, and the superlattice structure 204 comprises alternating layers of silicon (Si) and silicon germanium (SiGe).

[0075] In operation 116, as shown in Figure 2H, the multiple semiconductor material layers 226 are selectively etched between the multiple channel layers 224 in the superlattice structure 204. For example, if the superlattice structure 204 consists of silicon (Si) layers and silicon germanium (SiGe) layers, the silicon germanium (SiGe) is selectively etched to form channel nanowires 240. The multiple semiconductor material layers 226, e.g., silicon germanium (SiGe), may be removed using any known etchant that is selective to the multiple channel layers 224, e.g., silicon (Si), and the etchant etches the multiple semiconductor material layers 226 at a rate significantly greater than that of the multiple channel layers 224. In some embodiments, selective dry etching or wet etching processes may be used. In some embodiments, when multiple channel layers 224 are silicon (Si) and multiple semiconductor material layers 226 are silicon germanium (SiGe), the silicon germanium layers may be selectively removed using wet etching agents such as carboxylic acid / nitric acid / HF aqueous solutions and citric acid / nitric acid / HF aqueous solutions, but are not limited to these.

[0076] In one or more embodiments, as shown in Figure 2H, the removal of multiple semiconductor material layers 226 leaves voids 228 between multiple channel layers 224. The voids 228 between the multiple channel layers 224 have a thickness of approximately 3 nm to approximately 20 nm. The remaining channel layers 224 form a vertical array of channel nanowires 240 coupled to source / drain regions 232, 234. The channel nanowires 240 extend parallel to the top surface of the substrate 200 and are aligned with each other to form a single row of channel nanowires 240. The formation of source regions 236 and drain regions 238, as well as the formation of optional lateral etching stop layers, advantageously provides self-alignment and structural integrity in the formation of the channel structure.

[0077] The isotropic etching process may include any suitable etching process that is selective for the semiconductor material of the multiple channel layers 224. In some embodiments, the isotropic etching process of operation 116 includes one or more of a wet etching process or a dry etching process. In some embodiments, the isotropic etching process of operation 116 includes a dry etching process.

[0078] In one or more embodiments, operation 118 of method 100 corresponds to one or more processes known to those skilled in the art for completing an hGAA-type device, such as substitutional metal gate formation. For example, in one or more embodiments not shown, a high-k dielectric is formed. The high-k dielectric may be any suitable high-k dielectric material deposited by any suitable deposition technique known to those skilled in the art. The high-k dielectric in some embodiments includes hafnium oxide. In some embodiments, a conductive material such as titanium nitride (Tin), tungsten (W), cobalt (Co), aluminum (Al), etc., is deposited on the high-k dielectric. The conductive material may be formed using any suitable deposition process, such as atomic layer deposition (ALD), but not limited to, to ensure the formation of a layer having a uniform thickness around each of the multiple channel layers 224.

[0079] In one or more embodiments, as shown in Figure 2I, the gate electrode 252 is formed in a void 228 between a plurality of channel layers 224. The gate electrode may be formed from any suitable gate electrode material known in the art. The gate electrode material is deposited using any suitable deposition process, such as atomic layer deposition (ALD), to ensure that the gate electrode is formed around and between each of the plurality of channel layers 224. In one or more embodiments, the gate electrode is deposited by CVD, as the available space for the gate electrode to be housed between nanosheets is limited. In one or more embodiments, the gate electrode 252 comprises one or more of the following: titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and titanium aluminum (TiAl), and, but not limited to, compounds thereof, including titanium aluminum carbide (TiAlC), titanium aluminum oxide (TiAlO), titanium aluminum oxynitride (TiAlON), titanium aluminum carbon chloride (TiAlCCl), etc. In some embodiments, the gate electrode 252 comprises a void.

[0080] In the context of the descriptions of the materials and methods discussed herein (particularly in the context of the following claims), the terms “a,” “an,” and “the,” as well as similar references, should be interpreted as encompassing both singular and plural, unless otherwise indicated herein or explicitly contradicting the context. The descriptions of ranges of values ​​herein are intended merely as a convenient way to refer individually to each distinct value falling within that range, unless otherwise indicated herein, and each distinct value is incorporated into the specification as it would be if described individually herein. Any method described herein may be performed in any suitable order, unless otherwise indicated herein or explicitly contradicting the context. The use of any and all examples or illustrative language presented herein (e.g., “etc.”) is intended merely to highlight the materials and methods and does not impose limitations on their scope unless otherwise requested. Nothing herein should be interpreted as indicating that any unrequested element is essential to the implementation of the disclosed materials and methods.

[0081] Throughout this specification, any mention of “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “one embodiment” means that any particular feature, structure, material, or property described in relation to that embodiment is included in at least one embodiment of this disclosure. Therefore, any occurrence of phrases such as “in one or more embodiments,” “a particular embodiment,” “in one embodiment,” or “in one embodiment” in various parts of this specification does not necessarily refer to the same embodiment of this disclosure. Furthermore, any particular feature, structure, material, or property may be combined in any suitable manner in one or more embodiments.

[0082] While the disclosures herein have been described in relation to specific embodiments, those skilled in the art will understand that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and alterations can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Thus, the disclosure may include modifications and alterations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for manufacturing electronic devices, Forming a multilayer internal spacer comprising an internal layer, an intermediate layer, and an external layer within a superlattice structure formed on the top surface of the substrate. Includes, The superlattice structure comprises a plurality of semiconductor material layers and a corresponding plurality of channel layers arranged alternately as a plurality of stacked pairs, wherein the plurality of semiconductor material layers include silicon germanium (SiGe), and the corresponding plurality of channel layers include silicon (Si), and the multilayer internal spacers are formed by The process involves depositing the inner layer in the recessed areas of the plurality of semiconductor material layers, Depositing the intermediate layer on the aforementioned inner layer, The method involves depositing the outer layer on the intermediate layer, wherein the outer layer is deposited adjacent to the source region and the drain region. Methods that include...

2. The method according to claim 1, wherein the multilayer internal spacer is formed by a thermochemical vapor deposition process at a temperature in the range of 400°C to 650°C.

3. The method according to claim 1, wherein one or more of the inner layer or the outer layer have a thickness in the range of 0.5 nm to 2 nm.

4. The method according to claim 1, wherein one or more of the inner layer or the outer layer comprises a high-κ dielectric material.

5. The method according to claim 4, wherein the high-κ dielectric material has a κ value of 6 or more.

6. The method according to claim 4, wherein the high-κ dielectric material comprises one or more of silicon nitride (SiN), silicon carbonitride (SiCN), or nitrogen-rich silicon oxycarbonitride (SiOCN).

7. The method according to claim 1, wherein the intermediate layer has a thickness in the range of 2 nm to 5 nm.

8. The method according to claim 1, wherein the intermediate layer comprises a low-κ dielectric material.

9. The method according to claim 8, wherein the low-κ dielectric material has a κ value of 4.2 or less.

10. The method according to claim 8, wherein the low-κ dielectric material comprises one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or a spin-on dielectric.

11. The method according to claim 1, wherein the multilayer internal spacer is substantially free of seams and / or voids.

12. The method according to claim 1, wherein the electronic device is a gate-all-around (GAA) type device.

13. The method according to claim 1, further comprising etching one or more of the outer layer or the intermediate layer.

14. A method for manufacturing electronic devices, Forming a multilayer internal spacer comprising an internal layer, an intermediate layer, and an external layer within a superlattice structure formed on the top surface of the substrate. Includes, The superlattice structure comprises a plurality of semiconductor material layers and a corresponding plurality of channel layers arranged alternately as a plurality of stacked pairs, wherein the plurality of semiconductor material layers include silicon germanium (SiGe), and the corresponding plurality of channel layers include silicon (Si), and the multilayer internal spacers are formed by The process involves depositing the inner layer in the recessed areas of the plurality of semiconductor material layers, The internal layer is to be etched as needed, Depositing the intermediate layer on the aforementioned inner layer, Etching a portion of the aforementioned intermediate layer, The method involves depositing the outer layer on the intermediate layer, wherein the outer layer is deposited adjacent to the source region and the drain region. Etching the aforementioned outer layer Methods that include...

15. The method according to claim 14, wherein the process is carried out in an integrated deposition and etching system.

16. The method according to claim 14, wherein the multilayer internal spacer is formed by a thermochemical vapor deposition process at a temperature in the range of 400°C to 650°C.

17. The method according to claim 14, wherein one or more of the inner layer or the outer layer comprises a high-κ dielectric material.

18. The method according to claim 14, wherein the intermediate layer comprises a low-κ dielectric material.

19. The method according to claim 14, wherein the multilayer internal spacer is substantially free of seams and / or voids.

20. A central transfer station equipped with a robot configured to move circuit boards, A plurality of process stations, each process station connected to the central transfer station and providing a processing area separated from the processing area of ​​adjacent process stations, the plurality of process stations comprising chemical vapor deposition (CVD) chambers and etching chambers, A controller connected to the central transfer station and the plurality of process stations, the controller is configured to operate the robot to move the substrate between process stations and to control a process cycle for manufacturing a multilayer internal spacer for a gate-all-around (GAA) type device, the multilayer internal spacer comprising an internal layer, an intermediate layer, and an external layer within a superlattice structure formed on the top surface of the substrate, the superlattice structure comprising a plurality of semiconductor material layers and a corresponding plurality of channel layers arranged alternately as a plurality of stacked pairs, the plurality of semiconductor material layers comprising silicon germanium (SiGe), the corresponding plurality of channel layers comprising silicon (Si), and the process cycle comprising forming the multilayer internal spacer by a thermochemical vapor deposition (CVD) process, which includes depositing the internal layer in the recesses of the plurality of semiconductor material layers, depositing the intermediate layer on the internal layer, and depositing the external layer on the intermediate layer, the external layer being adjacent to source and drain regions. A processing tool equipped with these features.

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