Interposer with solder resist posts

The interposer with solder resist posts and TIM addresses thermal management issues in semiconductor devices by improving heat dissipation and reducing delamination, thereby enhancing thermal performance.

JP2026509115APending Publication Date: 2026-03-17QUALCOMM INC
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2024-01-30
Publication Date
2026-03-17

AI Technical Summary

Technical Problem

Conventional semiconductor device designs face challenges with poor thermal performance as device size decreases and power density increases, leading to deteriorating thermal management in electronic devices.

Method used

An interposer with solder resist posts and a thermal interface material (TIM) is used to enhance thermal coupling between the die and interposer, improving heat dissipation through an array of solder resist posts on the interposer's lower surface, which mitigates delamination and allows for efficient heat transfer.

Benefits of technology

The solution provides improved thermal dissipation and reduces delamination, enhancing the thermal performance of semiconductor devices by maintaining effective heat transfer pathways.

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Abstract

Apparatus and method for manufacturing an apparatus are disclosed. In one embodiment, the apparatus may include an interposer comprising a first metal layer, a second metal layer, a plurality of vias configured to thermally and electrically bond the first and second metal layers, and a plurality of solder resist posts disposed on the lower surface portion of the second metal layer; a package substrate; a die electrically coupled to the package substrate; and a thermal interface material (TIM) disposed on the die, configured to thermally bond the die to the lower surface portion of the second metal layer.
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Description

Technical Field

[0002] , , ,

[0003]

[0001] The present disclosure generally relates to an apparatus including a semiconductor structure including a method of manufacturing the same, and more particularly, to a semiconductor structure including an interposer having a plurality of solder resist posts.

Background Art

[0002] Integrated circuit technology has made great progress in improving computing power by miniaturizing active components. Various packaging technologies can be found in many electronic devices, including processors, servers, radio frequency (RF) integrated circuits, and the like. Advanced packaging and processing techniques enable multi-die devices and system-on-a-chip (SOC) devices, such as composite devices that can include multiple functional blocks, where each functional block is designed to perform a specific function, such as a microprocessor function, a graphics processing unit (GPU) function, a communication function (e.g., Wi-Fi, Bluetooth®, and other communications), and the like.

[0003] Integrated circuits (ICs) are becoming increasingly common in electronic devices. ICs can be implemented in the form of an IC die (or IC chip, or simply a die or chip) having a set of integrated electronic circuits on it. In some implementations, an IC die includes a semiconductor substrate, various electrical components on the substrate (e.g., transistors, resistors, capacitors, and / or inductors), and various conductive structures that connect these electrical components to form a set of electronic circuits. The manufacturing process for producing the electrical components can be collectively referred to as the front-end-of-line (FEOL) process. The manufacturing process for forming parts of the conductive structure in the form of layers of conductive wires and vias can be collectively referred to as the back-end-of-line (BEOL) process. In some applications, the process for forming other parts of the conductive structure that connect the electrical components to the layers of conductive wires and vias (e.g., contacts / connectors) can be collectively referred to as the middle-of-line (MOL) process.

[0004] With advancements in manufacturing technology, the size of semiconductor devices is shrinking along with the reduction in component size. Package-on-a-package (PoP) is an integrated circuit packaging method for vertically combining discrete logic and memory to reduce semiconductor device size in molded embedded package / molded embedded package on package (MEP) and other semiconductor device technologies. For example, high-performance mobile devices use PoP package structures, but conventional designs have poor thermal performance. Thermal management is an ongoing challenge for modern electronic devices where device size is decreasing and power density is increasing. As processing demands increase and / or package size decreases (e.g., faster processors, memory, etc.), the thermal performance of conventional MEP-type package structures deteriorates.

[0005] Therefore, there is a need for systems, apparatus, and methods that overcome the shortcomings of conventional semiconductor device design, including the methods, systems, and apparatus provided herein in the following disclosures. [Overview of the project]

[0006] The following provides a simplified overview of one or more embodiments disclosed herein. Therefore, the following overview should not be considered a broad overview of all conceivable embodiments, nor should it be considered to identify any major or essential elements of all conceivable embodiments, nor should it be considered to define the scope associated with any particular embodiment. Accordingly, the sole purpose of the following overview is to provide a simplified overview of a specific concept relating to one or more embodiments of the mechanism disclosed herein, prior to the “Modes for Carrying Out the Invention” presented below.

[0007] In one embodiment, the apparatus may include an interposer comprising a first metal layer, a second metal layer, a plurality of vias configured to thermally and electrically bond the first and second metal layers, and a plurality of solder resist posts disposed on the lower surface portion of the second metal layer; a package substrate; a die electrically coupled to the package substrate; and a thermal interface material (TIM) disposed on the die, configured to thermally bond the die to the lower surface portion of the second metal layer.

[0008] In one embodiment, a method for manufacturing the apparatus may include forming an interposer comprising a first metal layer, a second metal layer, a plurality of vias configured to thermally and electrically bond the first and second metal layers, and a plurality of solder resist posts disposed on the lower surface portion of the second metal layer; preparing a package substrate; preparing a die electrically coupled to the package substrate; and depositing a thermal interface material (TIM) on the die, the TIM being configured to thermally bond the die to the lower surface portion of the second metal layer.

[0009] Those skilled in the art will see from the accompanying drawings and "Modes for Carrying Out the Invention" that other purposes and advantages associated with the embodiments disclosed herein will become apparent.

[0010] The accompanying drawings are provided to aid in describing various aspects of this disclosure and are provided solely for illustrative purposes, not to limit those aspects. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows an apparatus according to one or more aspects of the present disclosure. [Figure 2A] This figure shows a part of an apparatus manufactured according to one or more aspects of the present disclosure. [Figure 2B] This figure shows a part of an apparatus manufactured according to one or more aspects of the present disclosure. [Figure 3A] This figure shows an exemplary partial method for manufacturing an apparatus according to one or more embodiments of the present disclosure. [Figure 3B] This figure shows an exemplary partial method for manufacturing an apparatus according to one or more embodiments of the present disclosure. [Figure 3C] This figure shows an exemplary partial method for manufacturing an apparatus according to one or more embodiments of the present disclosure. [Figure 3D] This figure shows an exemplary partial method for manufacturing an apparatus according to one or more embodiments of the present disclosure. [Figure 3E]This figure shows an exemplary partial method for manufacturing an apparatus according to one or more embodiments of the present disclosure. [Figure 3F] This figure shows an exemplary partial method for manufacturing an apparatus according to one or more embodiments of the present disclosure. [Figure 3G] This figure shows an exemplary partial method for manufacturing an apparatus according to one or more embodiments of the present disclosure. [Figure 3H] This figure shows an exemplary partial method for manufacturing an apparatus according to one or more embodiments of the present disclosure. [Figure 3I] This figure shows an exemplary partial method for manufacturing an apparatus according to one or more embodiments of the present disclosure. [Figure 3J] This figure shows an exemplary partial method for manufacturing an apparatus according to one or more embodiments of the present disclosure. [Figure 4] This is a flowchart of a method for manufacturing an apparatus according to one or more embodiments of the present disclosure. [Figure 5] This figure shows a mobile device according to one or more aspects of the present disclosure. [Figure 6] This figure shows various electronic devices that may be various devices according to one or more aspects of the present disclosure.

[0012] By convention, features depicted in the drawings may not be drawn to scale. Therefore, the dimensions of the depicted features may be enlarged or reduced as appropriate for clarity. By convention, some of the drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular apparatus or method. Furthermore, similar reference numerals indicate similar features throughout this specification and the drawings. [Modes for carrying out the invention]

[0013] The aspects of this disclosure are provided in the following description and related drawings, which cover various examples provided for illustrative purposes. Alternative embodiments can be devised without departing from the scope of this disclosure. Furthermore, well-known elements of this disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of this disclosure.

[0014] In this specification, the terms “exemplary” and / or “example” are used to mean “to serve as an example, case, or illustration.” Any aspect described herein as “exemplary” and / or “example” should not necessarily be construed as being preferable or advantageous to any other aspect. Similarly, the term “aspects of the disclosure” does not require that all aspects of the disclosure include the described features, advantages, or modes of operation.

[0015] In some of the exemplary implementations described, instances are identified where some of the structure and operation of various components are derived from known prior art and can then be configured according to one or more embodiments. In such instances, internal details of parts of the structure and / or operation of known prior art may be omitted to help avoid potential ambiguity of the concepts shown in the exemplary embodiments disclosed herein.

[0016] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to be limiting. The singular forms "a", "an", and "the" used in this specification are to be construed to include the plural forms as well, unless the context clearly dictates otherwise. The terms "comprises", "comprising", "includes", and / or "including" when used in this specification, specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Additionally, terms such as "approximately", "generally", etc. are intended to indicate that the examples provided are not intended to be limited to exact numerical values or geometric shapes, and include normal variations due to manufacturing tolerances and variations, material variations, and other design considerations.

[0017] As described above, various embodiments generally relate to an apparatus including a PoP device that includes an interposer having a plurality of solder resist posts (SR posts), and a thermal interface material (TIM) disposed on the die to provide improved thermal coupling between the die and the interposer.

[0018] Certain aspects of the subject matter described in this disclosure may be implemented to realize one or more of the following potential advantages. In some examples, a plurality of SR posts disposed on an exposed lower surface portion of an interposer (i.e., an exposed copper (Cu) plane on the lower side) are provided. The SR posts provide support between the interposer and a die (e.g., a SOC die) on which a TIM is disposed on the die. The TIM enables heat dissipation from the die to the interposer. The SR posts may be formed in the form of an array uniformly disposed on a lower opening in a second metal layer (M2 layer) of the interposer by a standard SR exposure / development process. In one aspect, the SR posts result in a reduction in delamination between the TIM and the copper. These and other advantages and alternatives will be understood from the following disclosure, the related drawings, and the claims.

[0019] Figure 1 shows an exemplary apparatus 100 according to an aspect of the present disclosure. In some aspects, as shown in Figure 1, the apparatus 100 includes an interposer 110, a package substrate 120, a die 130, and a TIM 140 disposed on the die and thermally coupled to the die 130 and the interposer 110. As used herein, the interposer 110 is configured to electrically couple the package substrate 120, and in some aspects, the die 130 through the package substrate, to another package (e.g., a die, a package substrate, and optionally additional components), the package substrate, and / or the die. The interposer 110 may be considered a substrate interposer because it is configured to electrically couple to the package substrate 120. The interposer 110 includes a first metal layer 111, a second metal layer 112, and a plurality of interposer vias 114 that thermally couple the first metal layer 111 and the second metal layer 112. Multiple solder resist posts 118 (SR posts) are arranged on the lower surface portion 113 of the second metal layer 112. The lower surface portion 113 is exposed because it is not covered by the lower solder resist 119. However, as will be further described below, some portions are covered by the SR posts 118. The lower surface portion 113 of the second metal layer 112 is thermally bonded to the die 130 through the TIM 140. Specifically, portions of the TIM 140 extending between the SR posts 118 provide a heat conduction path to the lower surface portion 113 of the second metal layer 112, and multiple interposer vias 114 provide thermal bonding to the first metal layer 111, which allows heat dissipation from the die 130 through both metal layers of the interposer 110 (the first metal layer 111 and the second metal layer 112). In some embodiments, the TIM 140 is at least one of a thermal paste or a thermal film. In some embodiments, TIM140 is a polymer thermal interface material (PTIM), such as ShinEtsu G-769EL or other similar materials.In contrast to conventional designs having a mold compound (such as mold compound 170) positioned between the die and the interposer, the various embodiments disclosed herein result in improved heat dissipation from the die 130 through the TIM 140 and the exposed lower portion 113.

[0020] As shown in Figure 1, the die 130 is electrically coupled to the package substrate 120, and the underfill 132 provides an additional mechanical coupling between the die 130 and the package substrate 120. The interposer 110 is electrically coupled to the upper side of the package substrate 120 by a plurality of interposer connectors 150. The interposer connectors 150 may be copper pillars, copper balls, solder, solder balls, a combination thereof, or any preferred connector. A mold compound 170, positioned between the interposer 110 and the package substrate 120, encloses the interposer connectors 150, the die 130, and the TIM 140. A plurality of package connectors 160 are positioned on the lower portion of the package substrate, opposite to the plurality of interposer connectors 150. In some embodiments, the plurality of package connectors 160 are ball grid arrays (BGAs). In other embodiments, the plurality of package connectors 160 may be copper pillars, copper balls, solder, solder balls, a combination thereof, or any preferred connector. Multiple package connectors 160 provide connection to external devices and electrical coupling to the die 130 and interposer 110 through metal layers 121 and vias 123. Additional components 162, such as resistors, capacitors, inductors, and any other components specified in various design configurations, may be electrically coupled to the package substrate.

[0021] It will be understood that the illustrated configurations and descriptions provided herein are merely for the purpose of illustrating the various embodiments disclosed herein. For example, one or more dies may be present within the apparatus 100. Furthermore, additional components may be provided, such as the design having more or fewer metal layers and vias within the package substrate 120 and / or interposer 110. Accordingly, the above-described examples and related figures should not be construed as limiting the various embodiments disclosed and claimed herein.

[0022] Figure 2A shows a portion of an exemplary apparatus 200A according to an embodiment of the present disclosure. Elements of apparatus 200A that are the same as or similar to those of apparatus 100 are given the same reference numerals, and for some elements, their labeling and detailed description may be omitted.

[0023] As shown in Figure 2A, the interposer 210A includes a second metal layer 212A (a trace visible beneath the lower solder resist 219A), as well as a plurality of interposer vias (invisible) that thermally bond the first metal layer (invisible) and the second metal layer 212A. A plurality of solder resist posts 218A (SR posts) are positioned on the lower portion 213A of the second metal layer 212A. The lower portion 213A is exposed because it is not covered by the lower solder resist 219A. However, some portions are covered by the SR posts 218A. It will be understood that the SR posts 218A are formed from the same material as the lower solder resist 219A and have similar height / thickness. In the lower view presented here, the SR posts 218A have a circular shape. In the illustrated embodiment, the SR posts 218A are formed as an array of circular posts. The SR post 218A helps to mitigate any copper delamination of the exposed lower portion 213A during the manufacturing process, but still allows the portion of the lower portion 213A to have room for thermal bonding with the TIM, as described above. In some embodiments, it will be understood that the SR post 218A has a size (diameter) of about 100 micrometers (um). In some embodiments, multiple SR posts 218A are formed in the form of an array with a pitch of about 200 micrometers (um). In some embodiments, the SR post 218A has a size (diameter) in the range of 50um to 100um. In some embodiments, multiple SR posts 218A are formed in the form of an array with a pitch in the range of 100um to 200um. It will be understood that these dimensions are provided merely as examples and should not be construed as limiting the various embodiments disclosed or claimed herein.

[0024] Figure 2B shows a portion of an exemplary apparatus 200B according to an embodiment of the present disclosure. Elements of apparatus 200B that are the same as or similar to those of apparatuses 100 and 200A are given the same reference numerals, and for some elements, their labeling and detailed description may be omitted.

[0025] As shown in Figure 2B, the interposer 210B includes a second metal layer 212B (a trace visible beneath the lower solder resist 219B), as well as a number of interposer vias (invisible) that thermally bond the first metal layer (invisible) and the second metal layer 212B. A number of solder resist posts 218B (SR posts) are positioned on the underside portion 213B of the second metal layer 212B. The underside portion 213B is exposed because it is not covered by the lower solder resist 219B. However, some portions are covered by the SR posts 218B. It will be understood that the SR posts 218B are formed from the same material as the lower solder resist 219B and have similar height / thickness. In the bottom view presented here, the SR posts 218B have a roughly rectangular shape (roughly square in this example). In this embodiment, the SR posts 218B are formed as an array of rectangular (square) posts in the illustrated embodiment. The SR post 218B helps to mitigate any copper delamination of the exposed lower portion 213B during the manufacturing process, but still allows the portion of the lower portion 213B to have room for thermal bonding with the TIM, as described above. In some embodiments, it will be understood that the SR post 218B has a size (side) of about 100 micrometers (um). In some embodiments, multiple SR posts 218B are formed in the form of an array with a pitch of about 200 micrometers (um). In some embodiments, the SR post 218B has a size (side) in the range of 50um to 100um. In some embodiments, multiple SR posts 218B are formed in the form of an array with a pitch in the range of 100um to 200um. It will be understood that these dimensions are provided merely as examples and should not be construed as limiting the various embodiments disclosed or claimed herein. Furthermore, it will be understood that the various embodiments are not limited to a specific SR post design, and in various embodiments, the SR post may be circular, oval, rectangular, triangular, irregular, or a combination thereof. Similarly, the size and pitch may be uniform or non-uniform and may differ from the exemplary values ​​provided.It will be understood that these dimensions and geometric shapes are provided merely as examples and should not be construed as limiting the various embodiments disclosed or claimed herein.

[0026] To fully illustrate the design aspects of this disclosure, methods of fabrication are presented. Other fabrication methods are also possible, and the methods described are presented solely to aid in understanding the concepts disclosed herein.

[0027] Figures 3A to 3J illustrate exemplary partial methods for manufacturing apparatus (such as the above-described 100, 200A, and 200B) according to one or more aspects of the present disclosure. Many of the elements shown in Figures 3A to 3J that are the same or similar as those of apparatus 100, 200A, and 200B are given the same or similar reference numerals, and their detailed descriptions may be omitted.

[0028] As shown in Figure 3A, in some embodiments, the process for manufacturing the apparatus 300 begins with preparing the base substrate 301 of the interposer 310. In some embodiments, the base substrate 301 may be a copper-clad laminate (CCL), pre-impregnated glass (PPG), or other suitable base material.

[0029] As shown in Figure 3B, in some embodiments, the process for manufacturing the apparatus 300 proceeds to via formation in the base substrate 301 of the interposer 310. In some embodiments, the base substrate 301 may be patterned and etched, drilled, or fabricated using other conventional techniques to form via openings 302.

[0030] As shown in Figure 3C, in some embodiments, the process for manufacturing the apparatus 300 proceeds to copper plating and patterning of the interposer 310. As shown, after copper plating and patterning, the interposer 310 includes a first metal layer 311, a second metal layer 312, and a number of interposer vias 314 that thermally and electrically connect the first metal layer 311 and the second metal layer 312. The lower portion 313 of the second metal layer 312 will not be covered by solder resist and will therefore be exposed in future processing.

[0031] As shown in Figure 3D, in some embodiments, the process for manufacturing the apparatus 300 proceeds to a solder resist treatment, including lamination, exposure, and development, which forms the upper solder resist 317 and lower solder resist 319 of the interposer 310. As shown, after the solder resist treatment, the interposer 310 includes a first metal layer 311, a second metal layer 312, and a plurality of interposer vias 314 that thermally and electrically connect the first metal layer 311 and the second metal layer 312. The lower portion 313 is exposed as it is not covered by the lower solder resist 319. A plurality of solder resist posts 318 (SR posts) are placed on the lower portion 313 of the second metal layer 312. As described above, various shapes, sizes, and patterns may be used for the SR posts 318. Finally, a plurality of interposer connectors 350 may be attached to the second metal layer 312 of the interposer 310. The interposer connector 350 may consist of copper pillars, copper balls, solder, solder balls, a combination thereof, or any other suitable connector.

[0032] As shown in Figure 3E, in some embodiments, the process for manufacturing the apparatus 300 proceeds to provide a die 330 having an underfill 332 which is electrically coupled to the package substrate 320 and provides an additional mechanical coupling between the die 330 and the package substrate 320. The package substrate 320 includes a metal layer 321 and vias 323 which provide electrical connections to external devices and to the die 330.

[0033] As shown in Figure 3F, in some embodiments, the process for manufacturing the apparatus 300 proceeds to deposit TIM 340 onto a die 330 placed on a package substrate 320. The TIM 340 is configured to enable thermal bonding to the die 330. In some embodiments, the TIM 340 is at least one of a thermal paste that can be applied to the die 330 through a dispensing device. In some embodiments, the TIM 340 is a thermal film. In some embodiments, the TIM 340 is a polymer thermal interface material (PTIM), such as ShinEtsu G-769EL or other similar material.

[0034] As shown in Figure 3G, in some embodiments, the process for manufacturing the apparatus 300 proceeds to the mounting of the interposer 310 to a thermo-compression bonding (TCB) head 382. The mounting is performed in preparation for the TCB process. Specifically, the TCB process is performed to mount the interposer 310, which has an interposer connector 350, to a package substrate 320 and a die 330 on which TIM 340 is deposited. The interposer 310 is configured as shown and described with respect to Figure 3D and includes a plurality of SR posts 318 positioned on the lower surface portion 313 of the second metal layer 312 of the interposer 310.

[0035] As shown in Figure 3H, in some embodiments, the process for manufacturing the apparatus 300 proceeds to the point where the interposer 310 is mounted on the TCB head 382 and the TCB process is performed. During the TCB process, process parameters such as temperature, force, and displacement are continuously monitored to bring about the bonding of various components. As shown, the TCB head 382 can provide the heat, force, and displacement for bonding the interposer connector 350 to the package substrate 320. In addition, the TIM 340 is bonded to the lower portion 313 of the second metal layer 312 of the interposer 310 through an opening between the SR posts 318. As described herein, the TIM 340 provides a thermal bond between the die 330 and the interposer 310.

[0036] As shown in Figure 3I, in some embodiments, the process for manufacturing the apparatus 300 proceeds to the removal of the interposer 310 from the TCB head 382 (not shown). After the TCB process, the interposer connector 350 is electrically coupled to the package substrate 320 and the interposer 310. In addition, the TIM 340 is bonded to the die 330 and to the lower portion 313 of the second metal layer 312 of the interposer 310 through an opening between the SR post 318. A mold compound 370 is deposited between the interposer 310 and the package substrate 320, sealing the interposer connector 350, the die 330, and the TIM 340.

[0037] As shown in Figure 3J, in some embodiments, the process for manufacturing the apparatus 300 proceeds to the installation of the package connector 360. The process can begin with the interposer connector 350 coupling the interposer 310 to the package substrate 320. In addition, the TIM 340 is bonded to the die 330 and to the lower portion 313 of the second metal layer 312 of the interposer 310 through an opening between the SR posts 318. A mold compound 370, positioned between the interposer 310 and the package substrate 320, encloses the interposer connector 350, the die 330, and the TIM 340. The package connector 360 is positioned on the lower portion of the package substrate 320, opposite to the multiple interposer connectors 350. In some embodiments, the multiple package connectors 360 are a ball grid array (BGA) and can be installed on the package substrate 320 through a reflow process. In other embodiments, the multiple package connectors 360 may be copper pillars, copper balls, solder, solder balls, combinations thereof, or any preferred connector. Additional components 362, such as resistors, capacitors, inductors, and / or any other components specified in various design configurations, may be electrically coupled to the package substrate 320. Since the configuration of the apparatus 300 is similar to that of the apparatus 100 described above, some similar elements shown will not be labeled and / or described in detail.

[0038] It will be understood that the aforementioned manufacturing processes are provided merely as general examples of some aspects of the present disclosure and are not intended to limit the scope of the present disclosure or the attached claims. Furthermore, many details of manufacturing processes known to those skilled in the art may be omitted or combined in the summarized process portion to facilitate understanding of the various aspects disclosed without detailed descriptions of each detail and / or all possible process variations.

[0039] Figure 4 shows a method 400 for manufacturing an apparatus (such as apparatus 100, 200A, 200B, or 300) according to an aspect of the present disclosure. In operation 410, an interposer (e.g., interposer 110 or 310) is formed, comprising a first metal layer, a second metal layer, a plurality of interposer vias configured to thermally and electrically couple the first and second metal layers, and a plurality of solder resist posts positioned on the underside portion of the second metal layer.

[0040] In operation 420, the method proceeds to preparing a package substrate (e.g., package substrate 120 or 320). In some embodiments, the package substrate may be prepared as a separate component or may be manufactured as part of the overall manufacturing process. The package substrate has a plurality of metal layers and vias interconnecting the metal layers. In addition, as described and shown in the above disclosure and accompanying drawings, pads or openings in the solder resist are provided for connection to the interposer.

[0041] In operation 430, the method proceeds to prepare a die electrically coupled to a package substrate (e.g., die 130 or 330 and package substrate 120 or 320). In some embodiments, the die and package substrate may be provided as an assembled component. In some embodiments, the die and package substrate may be provided as separate components and electrically coupled as part of a manufacturing process. In some embodiments, the die and package substrate may be manufactured as part of an overall manufacturing process. It will be understood that multiple manufacturers and / or manufacturing facilities may be used to provide the die, package substrate, and / or die electrically coupled to the package substrate as components.

[0042] In operation 440, the method proceeds to deposit a thermal interface material (TIM) onto the die (e.g., die 130 or 330, and TIM 140 or 340). The TIM is configured to thermally bond the die to the lower portion of the second metal layer. In some embodiments, the TIM may be either a thermal paste or a thermal film. In some embodiments, the TIM is a polymer thermal interface material (PTIM).

[0043] As described above, various other process steps, such as thermal bonding and package connector mounting, may be performed to bring about the final device. Additional processing / fabrication may include coupling additional dies (e.g., memory) or components to the interposer, marking, package framing, and other conventional processes to bring about the finished device. Furthermore, depending on the various embodiments disclosed, it will be understood that the device may include various configurations and may be a complete device such as a PoP, a molded embedded package-on-package (MEP), an integrated electronic component, or a mobile device, and other devices described herein. Thus, from the above disclosure, it will be understood that additional processes for fabricating the various embodiments disclosed herein are evident, and that a literal representation of the above processes is neither presented nor illustrated in the accompanying drawings. It will be understood that the sequence of fabrication processes is not necessarily in any particular order, and that later processes may be described earlier for convenience and to provide an example of the breadth of the various embodiments disclosed.

[0044] The devices and functionalities disclosed above may be designed and stored in computer files (e.g., Register-Transfer Level (RTL), Geometric Data Stream (GDS), Gerber, etc.) stored on a computer-readable medium. Some or all of such files may be provided to a manufacturer, manufacturer, and / or manufacturing facility for the purpose of manufacturing a device based on such files. The resulting product may include various components, including a semiconductor wafer, which is then cut into semiconductor dies and packaged into semiconductor packages, integrated devices, PoP devices, system-on-chip devices, etc., which may then be used in the various devices described herein.

[0045] It will be understood that various embodiments of the disclosure herein can be described as functional equivalents of structures, materials, and / or devices described and / or recognized by those skilled in the art. For example, in one embodiment, the apparatus may include means for performing the various functionalities described above. It will be understood that the aforementioned embodiments are provided merely as examples, and the various embodiments claimed are not limited to the specific references and / or figures cited as examples.

[0046] Figure 5 shows a mobile device 500 according to an aspect of the present disclosure. In some aspects, the mobile device 500 may be realized by including one or more ICs that include a semiconductor structure (e.g., a PoP structure) as disclosed herein.

[0047] In some embodiments, the mobile device 500 may be configured as a wireless communication device. As shown in the figure, the mobile device 500 includes a processor 501. The processor 501 may be communicatively coupled to a memory 532 via a link, which may be a die-to-die link or a chip-to-chip link. The mobile device 500 also includes a display 528 and a display controller 526, the display controller 526 being coupled to the processor 501 and the display 528. The mobile device 500 may include an input device 530 (e.g., a physical or virtual keyboard), a power supply 544 (e.g., a battery), a speaker 536, a microphone 538, and a wireless antenna 542. In some embodiments, the power supply 544 may directly or indirectly provide supply voltage to operate some or all of the components of the mobile device 500.

[0048] In some embodiments, Figure 5 may include a coder / decoder (CODEC) 534 (e.g., an audio and / or voice codec) coupled to a processor 501, a speaker 536 and a microphone 538 coupled to the codec 534, and a wireless antenna 542 and a wireless circuit 540 (which may include a modem, RF circuit configuration, filter, etc.) coupled to the processor 501.

[0049] In some embodiments, one or more of the following components include a processor 501 (e.g., SoC, application processor (AP)), a display controller 526, a memory 532, a codec 534, and a wireless circuit 540 (e.g., a baseband interface), including a semiconductor structure (e.g., a PoP structure / component) in various forms as described in this disclosure.

[0050] Figure 5 shows a mobile device 500, but it should be noted that a similar architecture may be used to realize devices including set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), stationary data units, computers, laptops, tablets, communication devices, mobile phones, or other similar devices.

[0051] Figure 6 shows various electronic devices 610, 620, and 630 that may be integrated with ICs 612, 622, and 632 according to embodiments of this disclosure (e.g., including PoP structures / components). For example, a mobile phone device 610, a laptop computer device 620, and a stationary terminal device 630 may each be generally considered user equipment (UE) and may include one or more ICs, such as ICs 612, 622, and 632, as well as a power supply for providing a supply voltage to power the ICs. ICs 612, 622, and 632 may correspond to ICs including semiconductor structures manufactured based on the examples described above with reference to, for example, Figures 1, 2A, and 2B, and Figures 3A to 3J.

[0052] Devices 610, 620, and 630 shown in Figure 6 are merely non-limiting examples. Other electronic devices may also feature ICs including semiconductor structures as described herein, including, but are not limited to, a group of devices (e.g., electronic devices) that include mobile devices, handheld personal communication system (PCS) units, portable data units such as personal information terminals, global positioning system (GPS) devices, navigation devices, set-top boxes, music players, video players, entertainment units, meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in automobiles (e.g., autonomous vehicles), Internet of Things (IoT) devices, access points, base stations, or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0053] It will be understood that various embodiments of the disclosure herein can be described as functional equivalents of structures, materials, and / or devices described and / or recognized by those skilled in the art. For example, in one embodiment, the apparatus may include means for performing the various functionalities described above. It will be understood that the aforementioned embodiments are provided merely as examples, and the various embodiments claimed are not limited to the specific references and / or figures cited as examples.

[0054] One or more of the components, processes, features, and / or functions shown in Figures 1 to 6 may be reconfigured and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. In some implementations, Figures 1 to 6 and their corresponding descriptions may be used to manufacture, fabricate, supply, and / or produce integrated devices. In some implementations, the device may include dies, integrated devices, die packages, ICs, device packages, IC packages, wafers, semiconductor devices, System in Package (SiP), System on Chip (SoC), Package on Package (PoP) devices, and the like.

[0055] The terms “User Equipment” (or “UE”), “User Device,” “User Terminal,” “Client Device,” “Communication Device,” “Wireless Device,” “Wireless Communication Device,” “Handheld Device,” “Mobile Device,” “Mobile Terminal,” “Mobile Station,” “Handset,” “Access Terminal,” “Subscriber Device,” “Subscriber Terminal,” “Subscriber Station,” and “Terminal,” as used herein, and their variations, may interchangeably refer to any suitable mobile or stationary device capable of receiving wireless communications and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive devices in motor vehicles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include devices that communicate with other devices capable of receiving wireless communications and / or navigation signals via short-range wireless connections, infrared connections, wireline connections, or other connections, regardless of whether satellite signal reception, support data reception, and / or position-related processing are performed in the device itself or in another device. UE can be embodied by any of several types of devices, including but not limited to printed circuit (PC) cards, CompactFlash® devices, external or internal modems, wireless or wireline telephones, smartphones, tablets, consumer tracking devices, and asset tags.

[0056] Wireless communication between electronic devices can be based on a variety of technologies, including code division multiple access (CDMA), W-CDMA, time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency division multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP® Long Term Evolution (LTE), 5G new wireless, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi), and IEEE 802.15.4 (Zigbee / Thread), or other protocols that may be used in wireless communication networks or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart).

[0057] Nothing described or illustrated in this application, whether or not such components, actions, features, benefits, advantages, or equivalents are described in the claims, is intended to be made publicly available.

[0058] Furthermore, those skilled in the art will understand that various exemplary logic blocks, modules, circuits, and algorithmic actions described herein in relation to the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly demonstrate that hardware and software are interchangeable, various exemplary components, blocks, modules, circuits, and actions are described above in general terms with respect to their functionality. Whether such functionality is implemented as hardware or as software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art will understand that the functionality described may be implemented in various ways with respect to each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0059] While several embodiments of a device have been described, it should be understood that these embodiments also constitute descriptions of corresponding methods, and therefore, blocks or components of a device should also be understood as corresponding method actions or features of method actions. Similarly, embodiments described with respect to or as method actions also constitute descriptions of corresponding blocks, details, or features of the corresponding device. Some or all of the method actions can be performed by (or using) hardware devices, such as, for example, a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, some or more of the most important method actions can be performed by such devices.

[0060] In the embodiments for carrying out the above invention, it will be seen that different features are grouped together in the examples. This form of disclosure should not be understood as an intention that the exemplary clauses have more features than are explicitly stated within each clause. Rather, the various embodiments of this disclosure may contain fewer features than all the features of the individual exemplary clauses disclosed. Accordingly, the following clauses should be considered as incorporated into the description, and each clause may be valid on its own as a separate example. Each dependent clause may refer within itself to a particular combination with one of the other clauses, but the embodiments (one or more) of that dependent clause are not limited to that particular combination. It will be understood that other exemplary clauses may also contain combinations of embodiments (one or more) of dependent clauses with the subject matter of any other dependent clause or independent clause, or any combination of features with other dependent clauses and independent clauses. The various embodiments disclosed herein explicitly include certain combinations (e.g., contradictory embodiments such as defining an element as both an electrical insulator and an electrical conductor) unless it is explicitly stated or easily inferred that such combinations are not intended. Furthermore, even if a clause is not directly subordinate to an independent clause, it is intended that the form of the clause may be included in any other independent clause.

[0061] Implementation examples are described in the following numbered sections.

[0062] Clause 1. Apparatus comprising: an interposer including a first metal layer, a second metal layer, a plurality of vias configured to thermally and electrically bond the first and second metal layers, and a plurality of solder resist posts disposed on the lower surface portion of the second metal layer; a package substrate; a die electrically coupled to the package substrate; and a thermal interface material (TIM) disposed on the die, configured to thermally bond the die to the lower surface portion of the second metal layer.

[0063] Clause 2. The apparatus according to Clause 1, wherein the TIM is at least one of a thermal paste or a thermal film.

[0064] Clause 3. The apparatus according to Clause 1 or 2, wherein the TIM is a polymer thermal interface material (PTIM).

[0065] Clause 4. The apparatus according to any one of Clauses 1 to 3, wherein the number of solder resist posts is at least one of the following shapes: circular, oval, rectangular, triangular, irregular, or a combination thereof.

[0066] Clause 5. The apparatus described in any of Clauses 1 to 4, wherein multiple solder resist posts have a size of approximately 50 micrometers (um) to 100 um.

[0067] Clause 6. The apparatus described in any of Clauses 1 to 5, wherein multiple solder resist posts are arranged in an array.

[0068] Clause 7. The apparatus described in Clause 6, wherein multiple solder resist posts have a pitch of approximately 100 micrometers (um) to 200 um.

[0069] Clause 8. The apparatus according to any one of Clauses 1 to 7, further comprising a plurality of interposer connectors configured to electrically couple an interposer to a package substrate.

[0070] Clause 9. The apparatus described in Clause 8, wherein multiple interposer connectors are at least one of copper pillars, copper balls, solder, solder balls, or a combination thereof.

[0071] Clause 10. The apparatus according to Clause 8 or 9, further comprising a mold compound disposed between the interposer and the package substrate.

[0072] Clause 11. The apparatus according to Clause 10, wherein the mold compound encapsulates multiple interposer connectors, dies, and TIMs.

[0073] Clause 12. The apparatus according to Clause 10 or 11, further comprising a plurality of package connectors located on the underside of the package substrate, opposite to the plurality of interposer connectors.

[0074] Clause 13. The apparatus described in Clause 12, wherein multiple package connectors are ball grid arrays (BGAs).

[0075] Clause 14. An apparatus as described in any of Clauses 1 to 13, wherein the apparatus comprises a package-on-package (PoP) device.

[0076] Clause 15. An apparatus as described in any of Clauses 1 to 14, comprising at least one of the following: a music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, stationary terminal, tablet computer, computer, wearable device, Internet of Things (IoT) device, laptop computer, server, access point, base station, or in-vehicle device.

[0077] Clause 16. A method for manufacturing an apparatus, comprising: forming an interposer including a first metal layer, a second metal layer, a plurality of vias configured to thermally and electrically bond the first and second metal layers, and a plurality of solder resist posts disposed on the lower surface portion of the second metal layer; preparing a package substrate; preparing a die electrically coupled to the package substrate; and depositing a thermal interface material (TIM) on the die, configured to thermally bond the die to the lower surface portion of the second metal layer.

[0078] Clause 17. The method according to Clause 16, wherein the TIM is at least one of a thermal paste or a thermal film.

[0079] Clause 18. The method according to Clause 16 or 17, wherein the TIM is a polymer thermal interface material (PTIM).

[0080] Clause 19. The method according to any one of Clauses 16 to 18, wherein the plurality of solder resist posts are at least one of the following shapes: circular, oval, rectangular, triangular, irregular, or a combination thereof.

[0081] Clause 20. The method according to any of Clauses 16 to 19, wherein multiple solder resist posts have a size of approximately 50 micrometers (um) to 100 um.

[0082] Clause 21. The method according to any of Clauses 16-20, wherein multiple solder resist posts are in an array.

[0083] Clause 22. The method according to Clause 21, wherein multiple solder resist posts have a pitch of approximately 100 micrometers (um) to 200 um.

[0084] Clause 23. The method according to any one of Clauses 16 to 22, further comprising a plurality of interposer connectors configured to electrically couple an interposer to a package substrate.

[0085] Clause 24. The method according to Clause 23, wherein the multiple interposer connectors are at least one of copper pillars, copper balls, solder, solder balls, or a combination thereof.

[0086] Clause 25. The method according to Clause 23 or 24, further comprising a mold compound placed between the interposer and the package substrate.

[0087] Clause 26. The method according to Clause 25, wherein the mold compound encapsulates multiple interposer connectors, dies, and TIMs.

[0088] Clause 27. The method according to Clause 25 or 26, further comprising a plurality of package connectors located on the underside of the package substrate, opposite to the plurality of interposer connectors.

[0089] Clause 28. The method according to Clause 27, wherein the multiple package connectors are ball grid arrays (BGAs).

[0090] Clause 29. The method according to any one of Clauses 16 to 28, wherein the apparatus comprises a package-on-package (PoP) device.

[0091] Clause 30. The method according to any one of Clauses 16 to 29, wherein the device comprises at least one of the following: a music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, stationary terminal, tablet computer, computer, wearable device, Internet of Things (IoT) device, laptop computer, server, access point, base station, or in-vehicle device.

[0092] Those skilled in the art will understand that information and signals can be represented using a wide variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips, which may be mentioned throughout the above description, can be represented by voltage, electric current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0093] While the above disclosures represent exemplary aspects of the Disclosure, it should be noted that various changes and modifications can be made herein without departing from the scope of the Disclosure as defined by the appended claims. The functions, steps, and / or actions of the method claims in the aspects of the Disclosure described herein do not need to be performed in any particular order. Furthermore, elements of the Disclosure may be described or claimed in the singular, but the plural is intended unless a limitation to the singular is expressly stated. [Explanation of Symbols]

[0094] 100 devices 110 Interposer 111 First metal layer 112 Second metal layer 113 Bottom part 114 Interposavia 118 Registration Post 119 Resist 120 Package Substrates 121 Metal layer 123 Beer 130 Die 132 Underfill 150 Interposer Connectors 160 Package Connectors 162 components 170 Mold Compound 200A device 200B equipment 210A Interposer 210B Interposer 212A Second metal layer 212B Second metal layer 213A Bottom part 213B Bottom part 218A Solder resist post 218B Solder Resist Post 219A Lower solder mask 219B Lower solder mask 300 equipment 301 Base board 302 Via opening 310 Interposer 311 First metal layer 312 Second metal layer 313 Bottom part 314 Interposavia 317 Resist 318 Solder Resist Posts 319 Resist 320 Package Substrates 321 Metal layer 323 Beer 330 Die 332 Underfill 350 Interposer Connectors 360 Package Connector 362 components 370 Mold Compound 382 TCB head 500 mobile devices 501 Processor 526 Display Controller 528 displays 530 Input Devices 532 memory 534 codec 536 Speakers 538 Microphone 540 Wireless Circuits 542 Wireless Antenna 544 Power supply 610 Mobile Phone Devices 620 Laptop Computer Devices 630 Stationary terminal devices

Claims

1. It is a device, An interposer comprising a first metal layer, a second metal layer, a plurality of vias configured to thermally and electrically bond the first and second metal layers, and a plurality of solder resist posts disposed on the lower surface portion of the second metal layer, Package substrate and A die electrically coupled to the aforementioned package substrate, A thermal interface material (TIM) disposed on the die, configured to thermally bond the die and the lower surface portion of the second metal layer, A device equipped with the following features.

2. The apparatus according to claim 1, wherein the TIM is at least one of a thermal paste or a thermal film.

3. The apparatus according to claim 1, wherein the TIM is a polymer thermal interface material (PTIM).

4. The apparatus according to claim 1, wherein the plurality of solder resist posts are at least one of the following shapes: circular, oval, rectangular, triangular, irregular, or a combination thereof.

5. The apparatus according to claim 1, wherein the plurality of solder resist posts have a size of about 50 micrometers (um) to 100 um.

6. The apparatus according to claim 1, wherein the plurality of solder resist posts are an array.

7. The apparatus according to claim 6, wherein the plurality of solder resist posts have a pitch of about 100 micrometers (um) to 200 um.

8. The apparatus according to claim 1, further comprising a plurality of interposer connectors configured to electrically couple the interposer to the package substrate.

9. The apparatus according to claim 8, wherein the plurality of interposer connectors are at least one of copper pillars, copper balls, solder, solder balls, or a combination thereof.

10. The apparatus according to claim 8, further comprising a mold compound disposed between the interposer and the package substrate.

11. The apparatus according to claim 10, wherein the mold compound encloses the plurality of interposer connectors, the die, and the TIM.

12. The apparatus according to claim 10, further comprising a plurality of package connectors arranged on the lower surface portion of the package substrate opposite to the plurality of interposer connectors.

13. The apparatus according to claim 12, wherein the plurality of package connectors are a ball grid array (BGA).

14. The apparatus according to claim 1, wherein the apparatus comprises a package-on-package (PoP) device.

15. The apparatus according to claim 1, wherein the apparatus comprises at least one of the following: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, or an in-vehicle device.

16. A method for manufacturing an apparatus, To form an interposer comprising a first metal layer, a second metal layer, a plurality of vias configured to thermally and electrically bond the first and second metal layers, and a plurality of solder resist posts disposed on the lower surface portion of the second metal layer, Prepare a package substrate, To prepare a die electrically coupled to the aforementioned package substrate, A thermal interface material (TIM) configured to thermally bond the die and the lower surface portion of the second metal layer, wherein the TIM is deposited on the die, Methods that include...

17. The method according to claim 16, wherein the TIM is at least one of a thermal paste or a thermal film.

18. The method according to claim 16, wherein the TIM is a polymer thermal interface material (PTIM).

19. The method according to claim 16, wherein the plurality of solder resist posts are at least one of the following shapes: circular, oval, rectangular, triangular, irregular, or a combination thereof.

20. The method according to claim 16, wherein the plurality of solder resist posts have a size of about 50 micrometers (um) to 100 um.

21. The method according to claim 16, wherein the plurality of solder resist posts are an array.

22. The method according to claim 21, wherein the plurality of solder resist posts have a pitch of about 100 micrometers (um) to 200 um.

23. The method according to claim 16, further comprising a plurality of interposer connectors configured to electrically couple the interposer to the package substrate.

24. The method according to claim 23, wherein the plurality of interposer connectors are at least one of copper pillars, copper balls, solder, solder balls, or a combination thereof.

25. The method according to claim 23, further comprising a mold compound disposed between the interposer and the package substrate.

26. The method according to claim 25, wherein the mold compound encloses the plurality of interposer connectors, the die, and the TIM.

27. The method according to claim 25, further comprising a plurality of package connectors disposed on the lower surface portion of the package substrate opposite to the plurality of interposer connectors.

28. The method according to claim 27, wherein the plurality of package connectors are a ball grid array (BGA).

29. The method according to claim 16, wherein the apparatus comprises a package-on-package (PoP) device.

30. The method according to claim 16, wherein the apparatus comprises at least one of the following: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, or an in-vehicle device.