4F2 memory structure with optimized cell layout

Abstract

4F 2 A two-dimensional dynamic random access memory array may include vertical pillar transistors arranged in a honeycomb pattern to maximize the footprint of available capacitors at the top of the memory array. Bit lines may partially intersect the bottom source / drain regions of two adjacent columns of vertical transistors, and the columns may be staggered based on the honeycomb pattern. Word lines may have a variable width, increasing when they surround the gate region of a transistor and decreasing when they are between adjacent transistors. Each transistor stage may be formed individually and stepwise, with the bottom source / drain region and bit lines completed first, followed by the gate region and word lines, and then the top source / drain region and capacitors.

Description

[Technical Field]

[0001] [Cross-reference of related applications] This application is for "MEMORY STRUCTURE WITH 4F 2 Claiming the interests and priority of U.S. Nonprovisional Application No. 18 / 186,091, titled “Optimized Cell Layout,” filed on 17 March 2023, the contents of which are incorporated herein by reference in their entirety for all purposes.

[0002] This disclosure is generally 4F 2 This document describes the design of a 2D dynamic random access memory array. More specifically, this disclosure describes a 4F array with increased bit line pitch and word line pitch. 2 This document describes the hexagonal layout of memory arrays. [Background technology]

[0003] Dynamic Random Access Memory (DRAM) structures have been shrinking over time. For example, the 1T-1C (one transistor, one capacitor) DRAM cell structure is 8F 2 Sizes up to 6F 2 The size has been successfully scaled down to the minimum feature size (where F is the minimum feature size). The cell size is 4F. 2 Designs have been proposed to further reduce the size to [a certain size]. However, when the cell size of DRAM is reduced so dramatically, there is a problem that the feature size continues to shrink. For example, the proposed 4F 2 The design tends to increase leakage current and reduce the pitch between word lines and bit lines within the memory array. This makes isolation between memory cells difficult and reduces the size of the cell capacitors. Furthermore, the manufacturing process for such small 4F cells 2 It is not well-suited for patterning and forming cells. Therefore, improvements are needed in this field. [Overview of the project]

[0004] In some embodiments, a two-dimensional (2D) DRAM array may include a plurality of bit lines arranged in a first horizontal direction, a plurality of word lines arranged in a second horizontal direction, and a plurality of transistors arranged in a vertical direction orthogonal to the first and second horizontal directions, wherein the plurality of bit lines intersect the bottom source / drain regions of the plurality of transistors and the plurality of word lines intersect the gate regions of the plurality of transistors. The plurality of transistors may be arranged in a honeycomb pattern.

[0005] In some embodiments, a 2D DRAM array may include a plurality of bit lines arranged in a first horizontal direction, a plurality of word lines arranged in a second horizontal direction, and a plurality of transistors arranged in a vertical direction orthogonal to the first and second horizontal directions, wherein the plurality of bit lines intersect the bottom source / drain regions of the plurality of transistors and the plurality of word lines intersect the gate regions of the plurality of transistors. The pitch of the plurality of bit lines can be greater than 2F, where F is defined as the feature size and the unit cell area of the 2D DRAM array is 4F 2 is defined as.

[0006] In some embodiments, a method of forming a 2D DRAM array includes forming a first source / drain region for a plurality of vertical transistors and forming a plurality of bit lines in contact with the first source / drain region. The method may also include, after forming the first source / drain region and the plurality of bit lines, forming a gate region for the plurality of vertical transistors and forming a plurality of word lines in contact with the gate region. Additionally, the method may include, after forming the gate region and the plurality of word lines, forming a second source / drain region for the plurality of vertical transistors and forming a plurality of capacitors in contact with the second source / drain region.

[0007] In any embodiment, any or all of the following features may be realized in any combination, without limitation: Multiple bit lines may only partially intersect the bottom source / drain regions of multiple transistors. The array also includes multiple spacers between the multiple bit lines, and these spacers may also partially intersect the bottom source / drain regions of multiple transistors. The pitch of the multiple bit lines is greater than 2F. The unit cell area of ​​the 2D DRAM array is 4F. 2 This can be done, where F can be defined as the feature size. This array can also include multiple capacitors located in the top source / drain regions of multiple transistors, and the multiple capacitors are It may have a footprint of TIFF2026509872000002.tif10170 or larger. The honeycomb pattern can arrange multiple transistors such that one transistor among multiple transistors is adjacent to six other transistors. Within a 2D DRAM array, multiple word lines may have non-uniform widths, and multiple bit lines may have non-uniform widths. Multiple word lines may be thinner when they are between multiple transistors than when they are around multiple transistors. The array may also include multiple spacers between multiple word lines, and the multiple spacers may have a triangular wave pattern. The pitch of multiple word lines may be greater than 2F. The gate regions of multiple transistors may include epitaxial silicon that can be formed using an epitaxial growth process from the silicon substrate beneath the multiple transistors. Forming a first source / drain region and multiple bit lines may include forming a sacrificial layer on a silicon substrate, etching multiple holes in the sacrificial layer, forming a first source / drain region within the multiple holes, removing the sacrificial layer, forming bit line material around the first source / drain region in place of the sacrificial layer, and forming multiple bit lines around the first source / drain region from the bit line material. Forming a gate region and multiple word lines may include forming a sacrificial layer on the first source / drain region and multiple bit lines, etching multiple holes in the sacrificial layer that are perpendicular to the first source / drain region, forming a gate region within the multiple holes, removing the sacrificial layer, forming word line material around the gate region, and forming multiple word lines around the gate region from the word line material. Forming a second source / drain region and a plurality of bit lines may include forming a sacrificial layer on the gate region and a plurality of word lines, etching a plurality of holes in the sacrificial layer that are aligned perpendicular to the gate region, forming a second source / drain region within the plurality of holes, and forming a plurality of capacitors on the second source / drain region.The gate regions of multiple vertical transistors are formed by selective epitaxial growth.

[0008] A further understanding of the properties and advantages of various embodiments can be achieved by referring to the remainder of this specification and the drawings. In the drawings, similar reference numerals are used throughout several drawings to refer to similar components. In some cases, sub-numbers are associated with reference numerals to indicate one of several similar components. When a reference numeral is referenced without specifying an existing sub-number, it is intended to refer to all such several similar components. [Brief explanation of the drawing]

[0009] [Figure 1A] A perspective view of a conventional 4F2 memory array is shown. [Figure 1B] A top view of a conventional 4F2 memory array is shown. [Figure 2A] A perspective view of a 4F2 memory array with optimized memory cell spacing according to one embodiment is shown. [Figure 2B] This is a top view of a 4F2 memory array with optimized memory cell spacing according to one embodiment. [Figure 2C] This is a top view of a 4F2 memory array with optimized memory cell spacing according to one embodiment. [Figure 3] A flowchart 300 of a method for forming a 2D DRAM array according to several embodiments is shown. [Figure 4A-B] This shows the gradually increasing steps of a process for forming a 2D DRAM array according to one embodiment. [Figure 4C-D] This shows the gradually increasing steps of a process for forming a 2D DRAM array according to one embodiment. [Figure 4E-F] This shows the gradually increasing steps of a process for forming a 2D DRAM array according to one embodiment. [Figure 4G-H] This shows the gradually increasing steps of a process for forming a 2D DRAM array according to one embodiment. [Figure 4I-J] Shows the gradually increasing stages of a process for forming a 2D DRAM array according to one embodiment. [Figure 4K-L] Shows the gradually increasing stages of a process for forming a 2D DRAM array according to one embodiment. [Figure 4M-O] Shows the gradually increasing stages of a process for forming a 2D DRAM array according to one embodiment. [Figure 4P-Q] Shows the gradually increasing stages of a process for forming a 2D DRAM array according to one embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the present disclosure, 4F 2 Describes how a two-dimensional dynamic random access memory array can include vertical pillar transistors arranged in a honeycomb pattern to maximize the footprint of the available capacitors at the top of the memory array. Bit lines can partially intersect the bottom source / drain regions of two adjacent columns of vertical transistors, where the columns can be offset based on the honeycomb pattern. Word lines can have a variable width that increases when the word line surrounds the gate region of the transistor and decreases when between adjacent transistors. Each transistor stage can be formed individually and stepwise, first completing the bottom source / drain regions and bit lines, then the gate regions and word lines, and then the top source / drain regions and capacitors.

[0011] 4F 2 DRAM arrays classified as such are important for increasing the density of DRAM cells within a memory array. However, as the minimum or critical feature size (referred to as "F") continues to shrink, such existing 4F 2 memory array designs are becoming increasingly problematic. Specifically, as F approaches below 10 nm, these existing 4F 2The design is related to the processing and manufacturing difficulties required to achieve high density and small device size. These existing 4F 2 The design may also have performance issues such as RC delay, larger leakage current, poor insulation between memory cells, reduced capacitor size, and the floating body effect of vertical transistors.

[0012] The embodiments described herein provide a more efficient 4F for vertical 1T-1C DRAM memory cells. 2 We propose a memory cell layout. Instead of arranging vertical pillar transistors and capacitors in an orthogonal or rectangular grid, each memory cell region can be defined as a non-rectangular parallelogram. In the resulting memory array, vertical memory cells are placed in an offset arrangement for more efficient placement of memory cells, and still 4F 2 Maintains the cell area. The offset placement of memory cells increases the capacitor area and lengthens the insulation distance between capacitors. In addition, the pitch of word lines and bit lines can be increased without increasing the cell area. This shortens the RC delay for charging / discharging memory cells. Existing 4F 2 The document also describes processing techniques that resolve many of the problems encountered when manufacturing memory cells.

[0013] Figures 1A and 1B show the conventional 4F 2The diagram shows a perspective view and a top view of the memory array 100. The memory array 100 may include a plurality of word lines 102 arranged in a first layer on the substrate. The word lines 102 may be conductive traces used to select the word lines of memory cells in the memory array 100. The memory array 100 may also include a plurality of bit lines 104 arranged in a second layer on the substrate. The plurality of bit lines may be conductive traces used to select the bit lines of memory cells in the memory array 100. By activating one of the plurality of bit lines 104 and one of the plurality of word lines 102, individual cells in the memory array 100 can be selected. The first and second layers may include different metal layers formed at different times during the manufacturing process. For example, the first layer containing the word lines 102 may be formed on top of the second layer containing the bit lines 104, such that these two layers do not intersect.

[0014] Multiple vertical memory cells may be directly located on the intersections between multiple word lines 102 and multiple bit lines 104. Each of the multiple vertical memory cells may contain a vertical transistor, which may be referred to as a vertical pillar transistor. The channel material of the transistor may be formed from a single-crystal silicon pillar. This silicon pillar is formed by etching the substrate. Forming the above pillar presents a challenge in controlling the size of the silicon pillar, because as the capacitor diameter and channel diameter decrease, the aspect ratio of the etched holes tends to increase. Each of the multiple vertical memory cells may also contain a vertical capacitor 106. The vertical memory cell may operate by storing a charge in the vertical capacitor 106 that indicates the stored memory state.

[0015] To compare with the optimized memory array described below, this conventional 4F 2It is useful to describe the dimensional characteristics of the unit cell area 116 of the memory array. For example, the capacitor footprint 108 can be defined as a circular area surrounding each vertical capacitor 106. The capacitor footprint 108 is the horizontal cross-sectional area of ​​the capacitor, which may include the cross-sectional area extended to contact with the capacitor area from the adjacent memory cell. Assuming that the diameter of the vertical capacitor 106 is approximately equal to the critical feature size F, Figure 1A shows that the size of the capacitor footprint 108 is πF 2 This is defined as, i.e., it can be defined as the circular cross-sectional area of ​​the capacitor footprint 108 having radius F. The word line pitch of the multiple word lines 102 and the bit line pitch 114 of the multiple bit lines 104 can be defined as 2F. Thus, the total cross-sectional area of ​​the unit cell area 116 is 4F. 2 This is the result.

[0016] Figures 2A to 2C show a 4F with optimized memory cell spacing according to several embodiments. 2 A top view and a perspective view of the memory array are shown. The memory array 200 may include a plurality of bit lines arranged in a first horizontal direction. The first horizontal direction can be a layer or plane substantially parallel to the underlying substrate on which the memory array 200 is formed. The memory array 200 may also include a plurality of word lines arranged in a second horizontal direction. The second horizontal direction can also be a layer or plane substantially parallel to the underlying substrate and / or the plurality of bit lines. The second horizontal direction can be substantially perpendicular to the first horizontal direction, as shown in Figure 2B. Furthermore, the memory array 200 may include a plurality of transistors arranged in a vertical direction perpendicular to the first and second horizontal directions, such as vertical transistors or vertical pillar transistors. Each memory cell in the memory array 200 may include a vertical transistor and a capacitor.

[0017] The arrangement of memory cells in the memory array 200 can be characterized in several different ways and distinguished from the arrangement of memory cells in the conventional memory array 100. Firstly, the spacing and arrangement of the vertical transistors 220 and capacitors 206 do not have to follow a rectangular orthogonal grid pattern like that of the conventional memory array 100. Instead, the capacitors 206 (together with the vertical transistors 220) can be spaced apart in alternating rows offset by half the distance between the vertical transistors 220. For example, the memory cells 230 in the first row can be arranged in a row with regular spacing in the first direction (for example, from left to right in Figure 2B). The memory cells 232 in the second row can also be arranged in a row with regular spacing in the first direction, but the memory cells 232 in the second row can be offset from the memory cells 230 in the first row. For example, as shown in Figure 2B, the vertical transistor 220 and capacitor 206 in the second column 232 of the memory cell may be aligned midway between the vertical transistor 220 and capacitor 206 in the first column 230 of the memory cell.

[0018] Overall, the capacitors 206 can be arranged in a "honeycomb" pattern, in contrast to the orthogonal grid pattern of the conventional memory array 100. This arrangement is illustrated in Figure 2C, where the honeycomb pattern 233 is superimposed on the memory array 200. The honeycomb pattern can be arranged such that each memory cell is surrounded by or adjacent to six other memory cells. Each memory cell can be surrounded by a virtual hexagonal shape, as shown. Note that the hexagons do not need to be regular, but can be compressed vertically or horizontally based on the desired spacing between memory cells. In other embodiments, regular hexagons (i.e., interior angles of 60°) may be used to maintain equal spacing.

[0019] The unit cell area 216 of the memory array 200 can also be distinguished from the rectangular unit cell area 116 in the conventional memory array 100. The unit cell area 216 can be defined as one of the hexagons in Figure 2C. Alternatively, the unit cell area 216 can be defined as the shape formed by connecting the center points of four adjacent capacitors. As shown in Figure 2B, the shape of the unit cell area 216 can be a non-rectangular parallelogram. In either definition, the unit cell area is still 4F. 2 It may have an area of ​​. However, the cross-sectional area of ​​the capacitor footprint 208 can be given as follows: That is, TIFF2026509872000003.tif10170

[0020] This capacitor footprint 208 is πF in the conventional memory array 100. 2 Note that this is larger than the capacitor footprint 108. The capacitor footprint 208 can be defined as the area in the memory array 200 where a capacitor can be formed. This capacitor is shown below in Figures 4P to 4Q. The capacitor footprint 208 can generally have a diameter larger than the diameter of the vertical transistors 220. However, the capacitor footprint 208 may be limited by the spacing between the vertical transistors 220. The honeycomb arrangement for this embodiment maximizes the available capacitor footprint 208 without increasing the overall size of the unit cell area 216. Thus, one of the many advantages provided by this embodiment is that the capacitor area is larger, but still 4F 2 The key is maintaining the area of ​​each unit cell.

[0021] Another way to characterize the memory array 200 to distinguish it from the conventional memory array 100 is to refer to the placement of the bit line 204 relative to the vertical pillars of the capacitor 206 and vertical transistor 220. Specifically, in the conventional memory array 100, the capacitor 106 and vertical transistor 120 are aligned at the intersection of the word line 102 and the bit line 104. The vertical transistor 120 is completely enveloped by both the word line 102 and the bit line 104, so that these lines intersect the vertical transistor 120 completely, rather than only partially. In contrast, the vertical transistor 220 is offset from the bit line 204 in the memory array 200. Specifically, the bit line 204 intersects the vertical transistor 220 such that the vertical transistor 220 is enveloped by the bit line 204 by about half. For example, in the top view provided by Figure 2B, the bit line 204 only partially intersects the two offset columns of transistor 220 (below the capacitor 206). Therefore, each bit line 204 can partially intersect two offset rows of transistors. Similarly, the spacer layers 205 between the bit lines 204 also partially intersect two offset rows of transistors 220. In the honeycomb arrangement, since the transistors 220 and capacitors 206 do not form a linear row of transistors 220, the bit lines 204 can instead be formed to be wide enough to intersect two of the offset rows of transistors 220. For example, a bit line 204 can intersect the first side of a pillar in the first row 230 of the memory cell and the second side of a pillar in the second row 232 of the memory cell.

[0022] Since the bit line 204 only needs to partially intersect with the row of vertical transistors 220, this makes it possible to make the bit line pitch 214 larger than the bit line pitch 114 of the conventional memory array 100. Specifically, the bit line pitch 214 can be larger than the bit line pitch 114 of the conventional memory array 100, which is 2F. When the bit line 204 is not aligned with the midpoint of the vertical transistors 220, the bit line pitch can be approximately 2.31F or greater. Furthermore, the bit line 204 can be connected to or in contact with the side wall of the bottom source / drain connection 242 (e.g., an N-type doped source / drain). As shown below, the semiconductor pillar of the vertical transistor 220 can also be connected to the substrate 243, which mitigates the "floating body" problem in DRAM transistors, i.e., the problem where the transistor body is not connected to voltage and leads to a floating or unstable body state.

[0023] Another way to characterize the memory array 200 is by the shape of the spacer layers 203 between the word lines 202. To accommodate the offset rows of memory cells, the spacer layers 203 between the word lines may be formed as a "zigzag" pattern. The spacer layers 203 may also be described as triangular patterns, nonlinear patterns, and / or wave patterns. The spacer layers 203 may also be characterized as following the approximate contour of the vertical transistors 220. For example, the spacer layers 203 may be positioned to maintain at least a minimum distance from each of the vertical transistors 220.

[0024] The memory array 200 can also be characterized by the shape of the word lines 202 themselves. For example, the word lines 202 can be described as being non-uniform, or having a non-uniform width (i.e., the width or distance of the word lines 202 between adjacent rows of spacer layers 203). The width of the word lines 202 increases when they are around a vertical transistor 220 to a maximum width aligned with the center of the vertical transistor 220, but decreases when they are between vertical transistors 220 to a narrower minimum width aligned with the midpoint between two adjacent vertical transistors 220 in the same row (e.g., the first row of memory cells 230). The shape of the word lines 202 can also be described as maintaining at least a minimum distance between vertical transistors 220 and spacer layers 203 (e.g., at the midpoint between two vertical transistors 220), and maintaining at least a minimum distance between adjacent spacer layers 203 (e.g., at the midpoint between adjacent vertical transistors 220). The width of the word line 202 can be maximized at the midpoint between each vertical pillar of the vertical transistor 220, and minimized at the midpoint between the vertical pillars of the vertical transistor 220. This arrangement also increases the pitch of the word lines of the memory array 200 so that it is greater than 2F of the conventional memory array 100.

[0025] Figure 3 shows a flowchart 300 of a method for forming a 2D DRAM array according to several embodiments. Figures 4A to 4Q show progressively increasing steps of the process for forming a 2D DRAM array according to several embodiments. Examples of each step described in Figure 3 may be illustrated in Figures 4A to 4Q below. However, these figures are not limiting to the steps in Figure 3. Instead, when describing the steps of flowchart 300, the following exemplary figures are simply referred to as examples.

[0026] This method, This process may include forming a first source / drain region for a plurality of vertical transistors and forming a plurality of bit lines that contact the first source / drain region (302). Overall, the process allows each stage of the transistor to be gradually formed on top of previously completed stages. For example, the first source / drain region and bit lines can be formed during the first processing stage, then the gate region and word lines can be formed during the second processing stage, and furthermore, the second source / drain region and capacitor can be formed during the third processing stage, where each processing stage is completed before the next processing stage begins.

[0027] Figure 4A shows a first stack deposition having a first hole pattern in the stack. The first stack may be formed on a silicon substrate 402. An etching stop layer 404 may be formed on the silicon substrate 402. The etching stop layer 404 may be formed from SiN or other similar material and may have a thickness of about 2 nm to about 20 nm, where the thickness is measured in the vertical direction shown in the figure. A sacrificial layer 406 is formed on top of the etching stop layer 404. The sacrificial layer 406 may be formed from SiO or other similar material and may have a thickness of about 5 nm to about 50 nm. A chemical-mechanical polishing (CMP) stop layer 408 may be formed on top of the sacrificial layer 406. The CMP stop layer 408 may be formed from silicon nitride or other similar material and may have a thickness of about 2 nm to about 20 nm. These layers may be formed using various processes such as damascene processes and deposition processes.

[0028] The surface of the stack may be patterned with a first hole pattern, as shown in Figure 4A. These holes may be patterns for the transistor pillars of vertical transistors. As shown, the holes 410 may be patterned with a honeycomb pattern as described above. The holes may be patterned using a lithography process and then etched to form the holes 410. The critical dimension (CD) of the holes 410 may be about 5 nm to about 15 nm (i.e., about 0.5 F to about 1.5 F for the critical feature size F) when F is about 10 nm. Note that the holes 410 may be etched to at least the level of the silicon substrate 402. For example, the holes 410 may be etched to expose at least the top surface of the silicon substrate 402. In some embodiments, the holes 410 may be etched to a level below the top surface of the silicon substrate 402. As a result, as will be described later, it becomes possible to connect the silicon pillar of the vertical transistor to the silicon substrate 402 and / or grow it from the silicon substrate.

[0029] Figure 4B shows how the holes 410 can be filled with pillar material 412. For example, several different materials can be used for the pillar material 412 used for the vertical pillars of a transistor based on this process. For example, the pillar material 412 may include crystalline semiconductors such as silicon, germanium, silicon-germanium, and / or other similar materials. These materials can also be used in the form of polycrystalline semiconductors. In some embodiments, metal oxide semiconductor materials such as indium gallium zinc oxide (IGZO) can be used for the pillar material 412. In some embodiments, the pillar material 412 can be formed by epitaxial growth of epitaxial silicon within the holes 410. The silicon substrate 402 can be used as a base for growing epitaxial silicon within the holes 410 for a selective epitaxial growth (SEG) process. Alternatively, the pillar material 412 can be formed by conformally filling the holes 410 with a polycrystalline semiconductor layer.

[0030] Figure 4C shows the result of a planarization process to eliminate any overburden resulting from filling the holes 410 with pillar material 412. By growing or forming the pillar material 412, the pillar material 412 may extend beyond the top of the holes 410. To form a horizontal and uniform height of pillar material 412, the stack may be subjected to a planarization process that removes the top of the stack, such as a CMP process. For example, a planarization process can eliminate any overburden of pillar material 412 and remove the CMP stop layer 408, ultimately exposing the sacrificial layer 406.

[0031] Figure 4D shows the removal of the sacrificial layer 406. The sacrificial layer 406 can be removed using a selective etching process. Note that the SiO of the sacrificial layer 406 has high selectivity for the SiN of the etching stop layer 404. These materials are used only as examples and are not intended to be limiting. Other materials with sufficient selectivity differences for the etching process may be used. The etching process may include a wet etching process or a dry etching process. For example, a wet etching process using dilute HF may be used to selectively remove SiO.

[0032] After the sacrificial layer 406 is removed, the surface of the pillar material 412 may be doped to form source / drain regions and contacts for the bit lines. For example, an N-type dopant may be used to dope the surface of the silicon pillar. The dopant may include phosphorus, arsenic, and / or other similar materials. In some embodiments, the doping concentration is about 1 e19 / cm³. 3 ~About 1e21 / cm 3 This is possible. The depth of the resulting N+ region can be in the range of approximately 1 nm to approximately 7 nm in the pillar material 412.

[0033] Figure 4E shows the formation of bit line material 416, which can be used for bit lines within a memory cell. After the doping process described earlier, the bit line material 416 may be formed over the etching stop layer 404. In some embodiments, a barrier layer may also be formed using a barrier material such as titanium nitride or tantalum nitride. The barrier layer may be formed before the bit line material 416 is formed. The bit line material 416 can be formed using any type of deposition process. The bit line material 416 may include N+ polysilicon, titanium, molybdenum, ruthenium, iridium, and / or other similar materials. In some cases, the bit line material 416 may be formed over or covering the pillar material 412. Thus, this process may also include performing other planarization processes, such as a CMP process, to eliminate excess deposition of the bit line material 416 down to the level of the pillar material 412.

[0034] Figure 4F shows the patterning and formation of individual bit lines 420 in the bit line material 416. The patterning process can be performed using any lithography process, and the bit line material 416 can be selectively etched against the etching stop layer 404. For example, the bit lines 420 can be selectively patterned and / or etched using an SiO mask. The bit line material 416 can be removed down to the etching stop layer 404. As described above, each bit line 420 can intersect with an offset row of pillar material 412. For each vertical transistor, the bit line 420 can intersect with the pillar material 412 at approximately the midpoint of the pillar material 412. In other embodiments, the intersections are increased or decreased so that each vertical transistor intersects with more than half or less than half of the pillar material 412. Selective etching leaves voids 418 between the bit lines 420, which can be filled with insulating material.

[0035] Figure 4G shows the insulating material 422 between the bit lines 420. The insulating material 422 may correspond to the spacer layer 205 in Figure 2B. The insulating material 422 can insulate the bit lines 420 from each other. In some embodiments, the width of the insulating material 422 may be approximately equal to the width of the bit lines 420. In other embodiments, the lines of the insulating material 422 can be made wider or narrower in response to the bit lines 420 being narrower or wider. The insulating material 422 can be implemented using any insulator such as SiO. At this stage, the bit lines 420 are formed, separated, and positioned so as to intersect the source / drain regions formed by the pillar material 412 for each vertical transistor.

[0036] Returning briefly to Figure 3, the method may also include forming gate regions for multiple vertical transistors and forming multiple word lines that contact the gate regions (304). Note that this second processing step may be performed after the first source / drain regions and multiple bit lines have been formed. For example, the gate regions and word lines may be formed on a flat surface containing the completed first source / drain regions and multiple bit lines. As will be discussed later, the gate regions may be formed so as to be directly aligned with the first source / drain regions from the first processing step.

[0037] Figure 4H shows a second stack deposition process used to form channels for vertical transistors on top of the source / drain regions. An etching stop layer 424 may be formed using SiN or other similar material having a thickness of about 2 nm to about 20 nm. A sacrificial layer 426 may be formed using SiO or other similar material having high etching selectivity to the etching stop layer 424. The sacrificial layer 426 may have a thickness of about 20 nm to about 1000 nm. A CMP stop layer 428 may be formed using SiN or other similar material and may have a thickness of about 2 nm to about 20 nm. These layers may be formed as previously described in Figure 4A. Similarly, the holes 440 may be patterned using the same patterning as previously described in Figure 4A so that the holes 440 are aligned on the pillar material 412 forming the source / drain regions described above. Multiple etching processes can be used to form the holes 440, where each etching process is selective for the CMP stop layer 428, the sacrificial layer 426, and the etching stop layer 424. For example, a series of SiN / SiO / SiN etching processes can be used. As described above, the CD of the holes 440 can be about 0.5F to about 1.5F.

[0038] Figure 4I shows the formation of channels for a vertical transistor. As previously described in Figures 4B to 4D, holes 440 can be filled using several different processes and / or materials. For example, channel material 442 can be formed from epitaxial silicon using a SEG process. Channel material 442 may involve conformal filling of polysilicon semiconductor layers within holes 440. Filling materials may include metal oxides such as Si, Ge, SiGe, IGZO, and / or other suitable materials. A planarization process may be performed to eliminate any excess deposition of channel material 442 extending beyond holes 440 and to remove the CMP stop layer 428. This can create a uniform height in all channels of the vertical transistor. The sacrificial layer 426 may then be removed down to the etching stop layer 424, exposing the vertical pillars of the channels formed by the channel material 442.

[0039] Figure 4J shows the formation of gate oxide 444 around each vertical pillar formed by the channel material 442. The gate oxide 444 can be formed from a material such as SiO or other similar material. For example, SiO can be oxidized from the vertical pillars of the pillar material 412 and used as the gate oxide 444. The thickness of the gate oxide can be approximately 1 nm to 10 nm. Although not explicitly shown in Figure 4J due to size constraints, a gate metal can also be formed on the gate oxide film 444.

[0040] Figure 4K shows the formation of the word wire material 453. The word wire material 453 may be formed from any of the aforementioned materials that realize the bit wire 420. For example, the word wire material 453 may be formed from tungsten, molybdenum, and other similar conductors. Like the bit wire material 416 described above, the word wire material 453 may be formed to extend beyond or on top of the channel material 442. A planarization process may be performed to eliminate any excess deposition of the word wire material 453. As shown in Figure 4K, the planarization process may also remove the gate oxide 444 from the top of the channel pillar to expose the channel material 442.

[0041] Figure 4L shows the formation of word lines 446. As described above for the process of forming bit lines 420, voids 441 can be formed between the word lines 446 formed by the etching process using a pattern or mask defining the spacer layer 203 in Figure 2B. As described above, the voids 441 may have a triangular, zigzag, or wave pattern with uniform width. The resulting word lines 446 may have a non-uniform width, which increases when the word lines 446 surround the channel material 442 and decreases when the word lines 446 are routed between adjacent pillars of the channel material 442 in a certain row of the memory cell. The voids 441 may serve to separate adjacent word lines.

[0042] Figure 4M shows the formation of a spacer layer 203 between word lines 446 from Figure 2B. The spacer layer can be formed from any insulating material 443, such as SiO, a dielectric, or other similar material. In some embodiments, a planarization process can be performed to form a flat surface on top of the stack for the formation of subsequent layers.

[0043] Returning briefly to Figure 3, the method may also include forming a second source / drain region for multiple vertical transistors and forming multiple capacitors in contact with the second source / drain region (306). Note that this third processing step may be performed after the gate region and multiple word lines have been formed. For example, the second source / drain region may be formed on a flat surface containing the completed gate region and multiple word lines. As will be discussed later, the second source / drain region may be formed so as to be directly aligned with the gate region from the first processing step.

[0044] Figure 4N shows the deposition process for the third stack. The third stack deposition process can be carried out in a similar manner to the first and / or second stack deposition processes described earlier. For example, an etching stop layer 443 (e.g., SiN) may be formed with a thickness of approximately 2 nm to 20 nm. A sacrificial layer 447 (e.g., SiO) may be formed with a thickness of approximately 2 nm to 20 nm. A CMP stop layer 449 (e.g., SiN) may be formed with a thickness of approximately 2 nm to 20 nm. Holes 450 may be patterned and etched downward through the etching stop layer 443 to expose the channel material 442 from the lower layer. The etching process may be selected sequentially for each of the etching stop layer 443, the sacrificial layer 447, and the CMP stop layer 449. The holes 450 may be sized to fit with existing vertical transistor pillars, as described earlier.

[0045] Figure 4O shows the formation of the source / drain region at the top of the vertical transistor. Holes 450 may be filled with pillar material 452 as described above for the bottom source / drain region. For example, pillar material 452 may be formed from epitaxial silicon doped with phosphorus, arsenic, or other similar material via an injection process. In some embodiments, the stack 454 may then be planarized to produce a horizontal surface. At this stage, the pillar material 412, channel material 442, and pillar material 452 can form a continuous and uniform vertical pillar for the vertical transistor, even if each part of the pillar was fabricated individually in various processing stages.

[0046] Figures 4P and 4Q show the formation of capacitors 456 on vertical transistors as part of each individual memory cell. Capacitors 456 can be formed using conventional techniques such as forming the bottom electrode, forming the dielectric, and forming the top electrode. Note that the capacitor footprint of capacitor 456 is maximized and generally larger than the diameter of the corresponding vertical transistor.

[0047] It should be understood that the specific steps shown in Figure 3 provide a specific method for forming a 2D DRAM memory array according to various embodiments. Steps in other sequences may also be performed according to alternative embodiments. For example, in alternative embodiments, the steps described above may be performed in a different order. Furthermore, the individual steps shown in Figure 3 may include a plurality of substeps, which may be performed in various sequences depending on the individual step. In addition, additional steps may be added or omitted according to a particular application. Numerous variations, modifications, and alternatives are also included in the scope of this disclosure.

[0048] In this specification, the terms “about,” “approximately,” or “substantially” may be interpreted as being within the range expected by those skilled in the art in light of this specification.

[0049] In the preceding explanation, for the sake of clarity, numerous specific details were included to provide a complete understanding of various embodiments. However, it will be apparent that some embodiments can be implemented without some of these specific details. In other examples, well-known structures and devices are shown in the form of block diagrams.

[0050] The above description provides only illustrative embodiments and does not limit the scope, applicability, or configuration of this disclosure. Rather, the prior description of various embodiments provides a feasible disclosure for realizing at least one embodiment. It should be understood that various modifications can be made to the function and arrangement of the components without departing from the idea and scope of some of the embodiments described in the appended claims.

[0051] Specific details are given in the above description to provide a complete understanding of the embodiments. However, it will be found that embodiments can be implemented without the above-mentioned specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in the form of block diagrams to avoid obscuring the embodiments with unnecessary details. In other examples, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary details to avoid obscuring the embodiments.

[0052] Furthermore, note that individual embodiments have been described as processes, shown as flowcharts, flow diagrams, data flow diagrams, structural diagrams, or block diagrams. While flowcharts may describe steps as a sequential process, many of these steps can be executed in parallel or simultaneously. Moreover, the order of the steps can be changed. A process terminates when its steps are completed, but there may be additional steps not shown in the diagram. A process can correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination corresponds to the function's return value to the calling function or the main function.

[0053] The term “computer-readable medium” includes, but is not limited to, portable or fixed-storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or transporting instructions and / or data. A code segment, or machine-executable instruction, may represent any combination of a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or instruction, data structure, or program statement. A code segment may be connected to other code segments or hardware circuits by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, transferred, or transmitted via any appropriate means, including memory sharing, message passing, token passing, network transmission, etc.

[0054] Furthermore, the embodiments may be implemented by hardware, software, firmware, middleware, microcode, a hardware description language, or any combination thereof. When implemented by software, firmware, middleware, or microcode, the program code or code segments for performing the required tasks may be stored in a machine-readable medium. The processor can then perform the required tasks.

[0055] While the features are described in the above specification with reference to specific embodiments, it should be noted that not all embodiments are limited thereto. Various features and aspects of several embodiments can be used individually or in combination. Furthermore, embodiments can be used in any number of environments and applications beyond those described herein without departing from the broader idea and scope of this specification. Accordingly, this specification and the drawings are intended to be illustrative, not limiting.

[0056] Furthermore, for illustrative purposes, the method has been described in a specific order. It should be understood that in alternative embodiments, the method may be performed in an order different from that described. Furthermore, it should be understood that the method described herein may be performed by hardware components or embodied by a sequence of machine-executable instructions, such instructions may be used to cause a machine, such as a general-purpose or special-purpose processor or a logic circuit programmed with the instructions, to perform the method. The machine-executable instructions may be stored in one or more machine-readable media, such as a CD-ROM or other type of optical disc, floppy disk, ROM, RAM, EPROM, EEPROM, magnetic card or optical card, flash memory, or other type of machine-readable media suitable for storing electronic instructions. Alternatively, the method may be performed by a combination of hardware and software.

Claims

1. A two-dimensional (2D) dynamic random access memory (DRAM) array, A first set of horizontally arranged bit lines, A second set of horizontally arranged word lines, A plurality of transistors arranged in a vertical direction perpendicular to the first horizontal direction and the second horizontal direction, wherein the plurality of bit lines intersect with the bottom source / drain regions of the plurality of transistors, and the plurality of word lines intersect with the gate regions of the plurality of transistors, Includes, The aforementioned plurality of transistors are arranged in a honeycomb pattern. A two-dimensional (2D) dynamic random access memory (DRAM) array.

2. The 2D DRAM array according to claim 1, wherein the plurality of bit lines partially intersect only with the bottom source / drain regions of the plurality of transistors.

3. The 2D DRAM array according to claim 2, further comprising a plurality of spacers between the plurality of bit lines, wherein the plurality of spacers also partially intersect the bottom source / drain regions of the plurality of transistors.

4. The pitch of the aforementioned multiple bit lines is greater than 2F, where F is defined as the feature size and the unit cell area of ​​the 2D DRAM array is 4F. ２ A 2D DRAM array as defined in claim 1.

5. The unit cell area of ​​the aforementioned 2D DRAM array is 4F ２ The 2D DRAM array according to claim 1, wherein F is defined as the feature size, and the unit cell area is defined as a non-rectangular parallelogram or hexagon in the honeycomb pattern.

6. The plurality of capacitors are further arranged in the uppermost source / drain region of the plurality of transistors, and the plurality of capacitors are A 2D DRAM array according to claim 1, having a footprint of, where F is defined as the feature size.

7. The 2D DRAM array according to claim 1, wherein the honeycomb pattern is formed by arranging the plurality of transistors such that one of the plurality of transistors is adjacent to the other six transistors.

8. A two-dimensional (2D) dynamic random access memory (DRAM) array, A first set of horizontally arranged bit lines, A second set of horizontally arranged word lines, A plurality of transistors arranged in a vertical direction perpendicular to the first horizontal direction and the second horizontal direction, wherein the plurality of bit lines intersect with the bottom source / drain regions of the plurality of transistors, and the plurality of word lines intersect with the gate regions of the plurality of transistors, Includes, The pitch of the aforementioned multiple bit lines is greater than 2F, where F is defined as the feature size and the unit cell area of ​​the 2D DRAM array is 4F. ２ It is defined as follows: A two-dimensional (2D) dynamic random access memory (DRAM) array.

9. The 2D DRAM array according to claim 8, wherein in the 2D DRAM array, the plurality of word lines have non-uniform widths and the plurality of bit lines have non-uniform widths.

10. The 2D DRAM array according to claim 9, wherein the plurality of word lines are thinner between the plurality of transistors than they are around the plurality of transistors.

11. The 2D DRAM array according to claim 8, wherein the plurality of transistors are arranged in a honeycomb pattern.

12. The 2D DRAM array according to claim 8, further comprising a plurality of spacers between the plurality of word lines, wherein the plurality of spacers have a triangular wave pattern.

13. The 2D DRAM array according to claim 8, wherein the pitch of the plurality of word lines is greater than 2F.

14. The 2D DRAM array according to claim 8, wherein the gate regions of the plurality of transistors include epitaxial silicon formed from a silicon substrate below the plurality of transistors using an epitaxial growth process.

15. A method for forming a two-dimensional (2D) dynamic random access memory (DRAM) array, To form a first source / drain region for multiple vertical transistors, and to form multiple bit lines that contact the first source / drain region, After forming the first source / drain region and the plurality of bit lines, form the gate region for the plurality of vertical transistors and form the plurality of word lines that contact the gate region. After forming the gate region and the plurality of word lines, a second source / drain region for the plurality of vertical transistors is formed, and a plurality of capacitors in contact with the second source / drain region are formed. including, A method for forming a two-dimensional (2D) dynamic random access memory (DRAM) array.

16. The method according to claim 15, wherein the plurality of vertical transistors are arranged in a honeycomb pattern.

17. Forming the first source / drain region and the plurality of bit lines is Forming a sacrificial layer on a silicon substrate, Etching multiple holes in the aforementioned sacrificial layer, The first source / drain region is formed within the plurality of holes, The removal of the aforementioned sacrificial layer, Instead of the sacrificial layer, a bit line material is formed around the first source / drain region, Forming the plurality of bit lines around the first source / drain region from the bit line material, The method according to claim 15, including the method described in claim 15.

18. Forming the gate region and the plurality of word lines is, Forming a sacrificial layer on the first source / drain region and the plurality of bit lines, In the sacrificial layer, a plurality of holes aligned perpendicularly to the first source / drain region are etched, Forming the gate region within the plurality of holes, The removal of the aforementioned sacrificial layer, Forming word line material around the gate region, Forming the plurality of word lines around the gate region from the word line material, The method according to claim 15, including the method described in claim 15.

19. Forming the second source / drain region and the plurality of capacitors is Forming a sacrificial layer on the gate region and the plurality of word lines, In the sacrificial layer, a plurality of holes aligned perpendicular to the gate region are etched, The second source / drain region is formed within the plurality of holes, Forming the plurality of capacitors on the second source / drain region, The method according to claim 15, including the method described in claim 15.

20. The method according to claim 15, wherein the gate regions of the plurality of vertical transistors are formed by selective epitaxial growth.

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