MTJ-based chiral spin current supply structure for memory

Abstract

A memory structure is provided that includes a chiral spin-current supply structure. The chiral spin-current supply structure includes an internal core made of a spin collector material, a spin-conductive insulating layer surrounding the internal core, and a charge-current-conductive spin-orbit spin-current generation layer surrounding the spin-conductive insulating layer. The horizontal plane of the internal core of the chiral spin-current supply structure is in contact with a magnetic tunnel junction structure.

Description

[Background technology]

[0001] This application relates to a memory structure, and more specifically, to a chiral spin current supply structure for a two-terminal hybrid magnetic tunnel junction (SOT-MTJ) device that is switched by spin-orbit torque and magnetic tunnel spin torque.

[0002] In magnetic tunnel junctions (MTJs) used in spin-transfer torque magnetic random access memory (STT-RAM), further reduction of write current is needed, particularly in embedded memory technology applications requiring switching times of less than 10 ns. There is a minimum switching spin current imposed by device physics, which is currently on the order of 30-60 μA in charge current units for fast switching of approximately 10 ns. Therefore, to further reduce the switching charge current, a better conversion from a charge current structure to a vertically polarized spin current is required.

[0003] Charge-spin current conversion related to spin-orbit torque (SOT) has demonstrated the feasibility of achieving high charge-spin current conversion efficiency. However, in most materials, the spin polarization is limited to the plane of the interface through which the spin current crosses due to the spin-orbit action. In the most efficient spin-current driven magnetic switching utilizing so-called "anti-damping" switching, it is desirable to have the spin current polarization in the direction of the easy axis with respect to the moment of the switching magnet. High-density STT-MRAM utilizes MTJs with a free layer (FL) moment that is magnetized perpendicularly, so the polarization is incompatible with the spin current generated by the SOT within its film plane. Therefore, it becomes difficult to use the spin current generated by the SOT in STT-MRAM technology. Furthermore, high spin conductance is required between the SOT conductor and the ferromagnetic conductor to be switched. For this reason, high-quality direct interface contact is often required between the SOT conductor and the ferromagnet forming the magnetic free layer of the MTJ structure. If both are good conductors, this can result in a large charge-current shunt, potentially reducing the net charge-spin current conversion efficiency of the SOT.

[0004] Research is underway on spin-conducting materials that are charge insulators, i.e., materials with a large spin-conductance to charge-conductance ratio. Recent reports have shown that a large spin current can be carried across 30 nm NiO by a magnon current. This indicates a high spin current density (equivalent to 10⁻¹⁰ 6 A / cm 2 At an order of magnitude, the apparent spin conductance was sufficient, and we were able to demonstrate the switching of nanomagnets by spin torque drive.

[0005] Given these advancements, it is now feasible to investigate a new type of hybrid SOT-MTJ spin-torque switching device that simultaneously applies the spin current generated by SOT and STT to the switching of perpendicular magnetization (PMA) nanomagnets. This will further reduce the switching current of two-terminal STT-MTJ devices by combining their respective effects. [Overview of the Initiative]

[0006] A memory structure is provided that includes a chiral spin-current supply structure. In some embodiments, the chiral spin-current supply structure includes an internal core made of a spin collector material, a spin-conductive but charge-insulating layer surrounding the internal core (hereinafter referred to as the spin-conductive insulating layer), and a charge-current-conductive spin-orbit spin-current generation layer surrounding the spin-conductive insulating layer. The horizontal plane of the internal core of the chiral spin-current supply structure is in contact with a magnetic tunnel junction structure.

[0007] The chiral spin current supply structure of this invention provides a chiral conduction path by its shape. Spin current from an SOT layer with remarkably perpendicular spin polarization (i.e., a charge-current-conducting spin-orbit spin current generation layer) is generated by structural chiral selection, passes through a magnetic insulator (i.e., a spin-conducting insulating layer), is delivered to the surface via a spin current conductor, and contacts the switching nanomagnet of the MTJ structure. This structure leverages its shape to simultaneously achieve the following three goals: (1) supplying a perpendicularly polarized spin current to the top surface; (2) that the spin current originates from the SOT interface, which is the primary contribution, rather than some higher-order, usually weak effect requiring the development of special materials that break mirror symmetry; and (3) preventing shunting of the charge current, thereby decoupling the spin current conversion efficiency and the total resistance of the SOT conductor.

[0008] In one embodiment of the present application, a memory structure is provided. In one embodiment, the memory structure includes a chiral spin-current supply structure comprising an internal core made of a spin collector material, a spin-conductive insulating layer surrounding the internal core, and a charge-current-conductive spin-orbit spin-current generation layer surrounding the spin-conductive insulating layer; a magnetic tunnel junction (MTJ) structure having a magnetic free layer forming an interface with the surface of the internal core; and a charge-current connection portion connecting the internal core to the charge-current-conductive spin-orbit spin-current generation layer.

[0009] In some embodiments of the present application, the spin collector material is composed of a metal or metal alloy having spin conductance equivalent to a good spin-conducting metal such as copper, and at room temperature, the effective spin conductivity is

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[0010] In some embodiments of the present application, the spin collector material includes, but is not limited to, Cu, Ag, Au, or alloys thereof.

[0011] In some embodiments of the present application, the spin-conducting insulating layer is composed of a magnetic insulator.

[0012] In some embodiments of the present application, the magnetic insulator is, but is not limited to, iron oxide (FeO x ), nickel oxide (NiO), or YIG (Y3Fe5O 12 ) includes.

[0013] In some embodiments of the present application, the charge-current-conducting spin-orbit spin-current generation layer includes a spin-orbit torque (SOT) channel material.

[0014] In some embodiments of the present application, the SOT channel material includes, but is not limited to, β-Ta, β-W, Cu x Pt 1-x , Cu 1-x Ta x , Pd x Pt 1-x , Au x Pt 1-x , Pt, Bi2Se3, WTe2, PtTe2, TaS2, Pt x Rh 1-x , or any material known to produce a large charge-spin conversion such as SOT, where x is between 0 and 1. Its interface with the spin-conductive charge insulator can be further processed using an ultrathin (atomic thickness) "doping" layer of a spin-conductive material (including, but not limited to, Cu, Ag, or Au).

[0015] In some embodiments of the present application, the MTJ structure includes, from bottom to top, the magnetic free layer, magnetic tunnel barrier layer, magnetic reference layer, and electrode layer described above. In such embodiments, the MTJ structure is disposed on the chiral spin current supply structure.

[0016] In some embodiments of the present application, the MTJ structure includes, from bottom to top, an electrode layer, a magnetic reference layer, a magnetic tunnel barrier layer, and the magnetic free layer described above. In such embodiments, the MTJ structure is disposed under the chiral spin current supply structure.

[0017] In some embodiments of the present application, the memory structure further includes a conductive structure that directly contacts the horizontal plane of the charge current-conductive spin-orbit spin current generation layer.

[0018] In some embodiments of the present application, the conductive structure is disposed within the interconnect dielectric layer.

[0019] In some embodiments of the present application, the spin-conducting insulating layer has an internal sidewall and an external sidewall, the internal sidewall of the spin-conducting insulating layer forms an interface with the external sidewall of the internal core, and the external sidewall of the spin-conducting insulating layer forms an interface with the internal sidewall of the charge-current-conducting spin-orbit spin-current-generating layer.

[0020] In some embodiments of the present invention, the outer sidewalls of the inner core, the inner and outer sidewalls of the spin-conducting insulating layer, and the inner sidewalls of the charge-current-conducting spin-orbit spin-current-generating layer are all significantly perpendicular (i.e., ±10%) to the horizontal plane of adjacent interconnection levels.

[0021] In some embodiments of the present invention, the outer sidewalls of the inner core, the inner and outer sidewalls of the spin-conducting insulating layer, and the inner sidewalls of the charge-current-conducting spin-orbit spin-current-generating layer are all inclined with respect to the horizontal plane of adjacent interconnection levels.

[0022] In some embodiments of the present invention, a charge-current-conducting spin-orbit spin-current-generating layer supports a chiral charge-current flow surrounding the inner core to generate a spin current substantially spin-polarized outward from the horizontal plane of the inner core in contact with the MTJ structure.

[0023] In some embodiments of the present application, the MTJ structure has a first diameter d1, the internal core has a second diameter d2, the spin-conducting insulating layer has a third diameter d3, and the charge-current-conducting spin-orbit spin-current-generating layer has a fourth diameter d4. Here, d1 is smaller than d2, d2 is smaller than d3, and d3 is smaller than d4.

[0024] In some embodiments of the present invention, the charge-current connection enables the flow of chiral charge-current within the charge-current-conducting spin-orbit spin-current generation layer.

[0025] In some embodiments of the present application, the charge-current connection is a direct electrical contact structure.

[0026] In some embodiments of the present invention, the charge-current connection is provided by controlling the amount of leakage current flowing across the spin-conductive insulating layer from the internal core to the charge-current-conductive spin-orbit spin-current generation layer, thereby accumulating current flow within the charge-current-conductive spin-orbit spin-current generation layer and forming a chiral charge-current. In the present invention, the charge connection relates to the charge-current connection between the internal core and the charge-current-conductive spin-orbit spin-current generation layer.

[0027] In some embodiments of the present application, a charge-current-conducting spin-orbit spin-current generation layer is electrically connected to a first terminal, and an MTJ structure is electrically connected to a second terminal.

[0028] In another embodiment, the memory structure includes an MTJ structure having a recess in the interconnect dielectric layer and a spin collector material layer disposed thereon, a spin-conductive insulating layer disposed on the sidewall of the spin collector material layer, and a charge-current-conductive spin-orbit spin-current generation layer disposed on the spin-conductive insulating layer; and a magnetic free layer forming an interface with the surface of the spin collector material layer. [Brief explanation of the drawing]

[0029] [Figure 1] Figure 1A is a cross-sectional view of a chiral spin current supply structure according to one embodiment of the present application.

[0030] Figure 1B is a top view of the chiral spin current supply structure illustrated in Figure 1A.

[0031] [Figure 2] Figure 2A is a cross-sectional view of a memory structure including the chiral spin current supply structure illustrated in Figure 1A.

[0032] Figure 2B is a top view of the chiral spin current supply structure illustrated in Figure 2A.

[0033] [Figure 3]This is a cross-sectional view of a memory structure including a chiral spin current supply structure according to another embodiment of the present application.

[0034] [Figure 4-1] Figure 4A is a cross-sectional view illustrating a method that can be used to form a chiral spin current supply structure according to the present invention, and Figure 4B is a cross-sectional view illustrating a method that can be used to form a chiral spin current supply structure according to the present invention. [Figure 4-2] Figure 4C is a cross-sectional view illustrating a method that can be used to form a chiral spin current supply structure according to the present invention, Figure 4D is a cross-sectional view illustrating a method that can be used to form a chiral spin current supply structure according to the present invention, Figure 4E is a cross-sectional view illustrating a method that can be used to form a chiral spin current supply structure according to the present invention, and Figure 4F is a cross-sectional view illustrating a method that can be used to form a chiral spin current supply structure according to the present invention.

[0035] [Figure 5] Figure 5A is a cross-sectional view of a simplified memory structure according to the present invention, which is in the form of a linear SOT channel laminated on only one side wall.

[0036] Figure 5B is a top view of the structure shown in Figure 5A. [Modes for carrying out the invention]

[0037] The present application will now be described in more detail by referring to the following description and the accompanying drawings. Note that the drawings are provided for illustrative purposes only and are therefore not drawn to scale. Also note that similar and corresponding elements are referenced by similar reference numerals.

[0038] The following description includes numerous specific details, such as particular structures, components, materials, dimensions, processing steps, and techniques, to help understand the various embodiments of the present application. However, it should be clear to those skilled in the art that the various embodiments of the present application are implementable even without these specific details. In other instances, well-known structures or processing steps are not described in detail to avoid obscuring the present application.

[0039] When an element, such as a layer, region, or substrate, is described as being "on" or "over" another element, it is understood that the element may be directly above the other element, or there may be an element in between. Conversely, when an element is described as being "directly on" or "directly over" another element, there is no element in between. When an element is described as being "beneath" or "under" another element, it is understood that the element may be directly below the other element, or there may be an element in between. Conversely, when an element is described as being "directly beneath" or "directly under" another element, there is no element in between.

[0040] As described above, a chiral spin current supply structure for use in memory structures is provided. The chiral spin current supply structure includes an internal core made of a spin collector material, a spin-conducting insulating layer surrounding the internal core, and a charge-current-conducting spin-orbit spin current generation layer surrounding the spin-conducting insulating layer. An MTJ structure is positioned on the horizontal plane of the internal core of the chiral spin current supply structure. This structure utilizes its shape to simultaneously achieve the following three goals: (1) supplying a vertically polarized spin current to the upper surface; (2) ensuring that the spin current originates from the SOT interface, which is the primary contributor, rather than from some higher-order, usually weak, effects that require the development of special materials to break mirror symmetry; and (3) preventing charge current shunting, thereby decoupling spin current conversion efficiency and the total resistance of the SOT conductor.

[0041] First, referring to Figures 1A and 1B, an example of a chiral spin current supply structure 10 according to one embodiment of the present invention is shown. In particular, the chiral spin current supply structure 10 illustrated in Figures 1A and 1B includes an internal core 12 made of a spin collector material, a spin-conductive insulating layer 14 surrounding the internal core 12, and a charge-current-conductive spin-orbit spin current generation layer 16 surrounding the spin-conductive insulating layer 14. As illustrated in the top view provided in Figure 1B, the chiral spin current supply structure 10 of the present invention has a cylindrical shape (i.e., a disk shape); however, other shapes, particularly rectangular or square shapes, may also be realized, and these shapes are often easier to manufacture lithographically.

[0042] The internal core 12 is a solid structure having an external sidewall S1out and a second diameter d2; the first diameter d1 is used in this application to define the diameter of the MTJ structure (see, for example, Figure 2B). In this application, d2 represents the diameter of the internal core in contact with the MTJ structure. The spin-conducting insulating layer 14 has an internal sidewall S2in, an external sidewall S2out, and a third dimension d3, and the charge-current-conducting spin-orbit spin-current-generating layer 16 has an internal sidewall S3in, an external sidewall S3out, and a fourth dimension d4. In this application, various diameters are as shown in Figure 1A or Figure 2B.

[0043] In this embodiment, the internal sidewall S2in of the spin-conductive insulating layer 14 forms an interface with the external sidewall S1out of the internal core 12, and the external sidewall S2out of the spin-conductive insulating layer 14 forms an interface with the internal sidewall S3in of the charge-current-conductive spin-orbit spin-current generation layer 16. In this embodiment of the present application, the external sidewall S1out of the internal core 12, the internal sidewalls S2in and S2out of the spin-conductive insulating layer 14, and the internal sidewall S3in (and external sidewall S3out) of the charge-current-conductive spin-orbit spin-current generation layer 16 are all substantially perpendicular (i.e., ±10%) to the horizontal plane of the substrate (i.e., the interconnection level 18 / 20 shown in Figure 2A). In some embodiments of the present invention, as illustrated in Figure 3, the outer sidewall S1out of the inner core 12, the inner sidewall S2in and outer sidewall S2out of the spin-conductive insulating layer 14, and the inner sidewall S3in of the charge-current-conductive spin-orbit spin-current generation layer 16 are all inclined (i.e., tapered) with respect to the horizontal plane of the substrate, i.e., the interconnection level 18 / 20 shown in Figure 3. The structure shown in Figure 3 can alleviate manufacturing challenges and increase the contact area of ​​the structure.

[0044] In this application, d1 is smaller than d2, d2 is smaller than d3, and d3 is smaller than d4. The chiral spin current supply structure 10 shown in Figure 1A also has a height h, and the charge-current-conducting spin orbital spin current generation layer 16 has a width w. In some embodiments, the height h may be 10 nm to 100 nm or more, and the width w may be 1 nm to 10 nm. It should be noted that the height and width ranges mentioned herein are exemplary ranges, and other ranges may be used as needed.

[0045] Here, each component / element of the chiral spin current supply structure 10 illustrated in Figures 1A and 1B will be described in more detail; these elements are also applicable to the chiral spin current supply structure 10 shown in Figures 2A, 2B and 3. The internal core 12 of the chiral spin current supply structure 10 is composed of a spin collector material. The term "spin collector material" is used throughout this application to define a metal or metallic alloy having high spin conductance and a long spin diffusion length. An example of such a spin collector material may be copper, which, at room temperature, can be converted to charge units.

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[0046] The spin-conducting insulating layer 14 of the chiral spin current supply structure 10 is composed of a magnetic insulator. The magnetic insulator used as the spin-conducting insulating layer 14 in this application is a highly spin-conducting material that is also an insulator with respect to charge conductance. Exemplary magnetic insulators that may be used as the spin-conducting insulating layer 14 include, but are not limited to, FeO x NiO, or YIG(Y3Fe5O 12) is present. The width of the spin-conductive insulating layer 14 that surrounds the internal core 12 in the lateral direction is usually 1 nm to 10 nm. However, in this application, other widths may be used for the spin-conductive insulating layer 14.

[0047] The charge-current-conducting spin-orbit spin-current generation layer 16 of the chiral spin-current supply structure 10 is made of an SOT channel material. The SOT channel material used as the charge-current-conducting spin-orbit spin-current generation layer 16 in this application provides the necessary charge-spin conversion and allows the same charge current to flow through the MTJ structure. Exemplary SOT channel materials that may be used as the charge-current-conducting spin-orbit spin-current generation layer 16 in this specification include, but are not limited to, β-Ta, β-W, and Cu. x Pt 1-x Cu 1-x Ta x , Pd x Pt 1-x Au x Pt 1-x , Pt, Bi2Se3, WTe2, PtTe2, TaS2, Pt x Rh 1-x There is any material known to produce a large SOT charge-spin conversion efficiency, where x is 0 to 1. Other types of channel materials that could be used, like SOT, are so-called orbital moment generating alloys, such as CuOx / Pt or CuN / Pt. The charge-current-conducting spin-orbital-spin-current generating layer 16 surrounding the spin-conducting insulating layer 14 has the width w described above.

[0048] It should be noted that the charge-current-conducting spin-orbit spin-current generation layer 16 supports the flow of chiral charge-current surrounding the inner core 12 so as to generate a spin-current that is substantially spin-polarized outward from the horizontal plane of the inner core in contact with the MTJ structure. In this situation, the chirality of the charge-current flow in the charge-current-conducting spin-orbit spin-current generation layer 16 surrounding both the spin-conducting insulating layer 14 and the inner core 12 (i.e., left-handed coordinate system) forms a vector relationship between the direction of charge-current flow and the spin-polarization direction of the resulting spin-current.

[0049] It should be noted that the spin-conducting insulating layer 14 forms a first interface with the internal core 12 and a second interface with the charge-current-conducting spin-orbit spin-current generation layer 16. Both of these interfaces are atomically clean interfaces. An "atomically clean interface" is defined as an interface free of impurity elements, where the interfacial conductance per unit area with respect to spin current, when converted to charge-current units,

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[0050] As shown in Figure 1B, the charge-current-conducting spin-orbit spin current generation layer 16 generates a charge current in the circumferential direction within the layer.

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[0051] Although not shown in Figures 1A to 1B, the chiral spin current supply structure 10 may be laterally surrounded by a dielectric material, such as an interconnect dielectric material. The entire structure surrounding the chiral spin current supply structure 10 may be chemically polished to produce a smooth, chemically clean surface for growing the MTJ layer on top. This aspect of the present invention is evident from the process flow shown in Figures 4A to 4F.

[0052] Referring here to Figures 2A and 2B, a memory structure including the chiral spin-current supply structure 10 illustrated in Figures 1A and 1B is illustrated. In particular, the memory structure of the present application is a two-terminal device including, in addition to the chiral spin-current supply structure 10, interconnection levels 18 / 20 and MTJ structures 26 / 28 / 30 / 32. The interconnection level includes a conductive structure 20 and an interconnection dielectric layer 18; the conductive structure 20 is embedded in the interconnection dielectric layer 18 and may have an uppermost surface that is coplanar with the uppermost surface of the interconnection dielectric layer 18. As illustrated in Figure 2A, the conductive structure 20 is in direct contact with the horizontal plane (i.e., the bottom surface) of the charge-current-conducting spin-orbit spin-current generation layer 16. In the illustrated embodiment, the interconnection levels 18 / 20 are located below the chiral spin-current supply structure 10, and the MTJ structures 26 / 28 / 30 / 32 are located above both the chiral spin-current supply structure 10 and the interconnection structures 18 / 20.

[0053] As further shown, the charge-current-conducting spin-orbit spin-current generation layer 16 is electrically connected to the first terminal 22 (via the conductive structure 20), and the MTJ structures 26 / 28 / 30 / 32 are electrically connected to the second terminal 34 (via another conductive structure (not specifically illustrated in the drawings of this application)). The memory structure shown in Figures 2A to 2B also includes a charge-current connection section that connects the internal core 12 to the charge-current-conducting spin-orbit spin-current generation layer 16 (via the direct electrical contact structure 24 in the illustrated embodiment).

[0054] The conductive structure 20 that may be used in this application is made of a conductive metal or a conductive metal alloy. Examples of conductive materials that may be used in this application to provide the conductive structure 20 include, but are not limited to, Cu, Al, Cu-Al alloys, W, Ru, or Rh. In some embodiments (not shown), a diffusion barrier liner may be present along at least the side walls (and, in some embodiments, along the bottom wall) of the conductive structure 20. If present, the diffusion barrier liner may be made of any well-known diffusion barrier material, e.g., Ta, TaN, Ti, TiN, W, or WN. In some embodiments, the diffusion barrier liner may include a material laminate of two or more types of diffusion barrier materials. In some examples, the diffusion barrier liner may be made of a Ta / TaN laminate or a Ti / TiN laminate.

[0055] The interconnect dielectric layer 18 is composed of any interconnect dielectric material, including, for example, silicon oxide (SiOx), silsesquioxane, C-doped oxides containing atoms of Si, C, O, and H (i.e., organic silicates), thermosetting polyarylene ethers, or multilayers thereof. The term “polyarylene” is used herein to refer to aryl substructures or inertly substituted aryl substructures, whose annealed substructures are linked to one another by chemical bonds, fused rings, or inert linking groups (e.g., oxygen, sulfur, sulfone, sulfoxide, carbonyl, and the like). The interconnect dielectric layer 18 may have a dielectric constant of about 4.0 or less (all dielectric constants referred to herein are measured relative to vacuum unless otherwise specified). In some embodiments, the interconnect dielectric layer 18 has a dielectric constant of 2.8 or less. These dielectrics generally exhibit less parasitic crosstalk compared to dielectric materials with a dielectric constant greater than 4.0.

[0056] The interconnection level 18 / 20 may be formed using back-end-of-the-line (BEOL) techniques well known to those skilled in the art, such as a damascene process that provides the conductive structure 20 following the deposition of the interconnection dielectric layer 18. The interconnection dielectric layer 18 may be deposited, for example, by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or spin-on coating.

[0057] The interconnection levels 18 / 20 may be located above at least one lower metal level (not shown) and a front-end-of-the-line (FEOL), also not shown. In some embodiments, the metal level may be a middle-of-the-line (MOL) level. In other embodiments, the metal level may be at least one lower interconnection level of the multilevel interconnection structure. In further embodiments, the metal level may be a combination of the MOL level and at least one lower interconnection level of the multilevel interconnection structure. The metal level may include a bottom conductive structure embedded in a dielectric layer. The FEOL may include a semiconductor substrate on which one or more semiconductor devices (e.g., transistors) providing logic functions and memory read / write functions are formed. The metal level and FEOL may be formed using materials and techniques well known to those skilled in the art. Therefore, to avoid obscuring the memory structure of the present application, the materials and techniques used to provide the metal level and FEOL are not described herein.

[0058] In some embodiments, as illustrated in Figure 2A, the MTJ structure is a laminate containing magnetic material, and from bottom to top, includes a magnetic free layer 26, a magnetic tunnel barrier layer 28, a magnetic reference layer 30, and an electrode layer 32. In one such embodiment, the magnetic free layer 26 forms an interface with the internal core 12. As can be deduced from Figures 2A and 3, but not shown, in other embodiments, the entire structure may be inverted, i.e., the MTJ structure may be located below the chiral spin current generating structure 10. In this case, the MTJ structure is in contact with a conductive structure 20 located above the MTJ structure, and the ends of the chiral spin orbit spin current generating layer 16 are in contact with a second terminal 34. The charge connection element 24 from the internal core 12 to the charge current conducting spin orbit spin current generating layer 16 is located at the bottom of the chiral spin current generating structure 10. In such embodiments, the MTJ structure would include, from bottom to top, an electrode layer 32, a magnetic reference layer 30, a magnetic tunnel barrier layer 28, and a magnetic free layer 26. The magnetic free layer 26 now forms an interface with the internal core 12 located on top of the MTJ structure.

[0059] The magnetic free layer 26 is composed of at least one magnetic material whose magnetization orientation can be altered relative to the magnetization orientation of the magnetic reference material. Exemplary materials for the magnetic free layer 26 include, but are not limited to, alloys and / or multilayers consisting of cobalt, iron, cobalt-iron alloys, nickel, nickel-iron alloys, and cobalt-iron-boron alloys. The thickness of the magnetic free layer 26 can be 0.3 nm to 3 nm; however, other thicknesses are also possible and may be used as the thickness of the magnetic free layer 26.

[0060] The tunnel barrier layer 28 is composed of an insulating material and is formed to a thickness that provides adequate tunnel resistance. Exemplary insulating materials for the tunnel barrier layer 28 include, but are not limited to, magnesium oxide, aluminum oxide, titanium oxide, or materials with higher electrical tunnel conductance (e.g., semiconductors or low-bandgap insulators). The thickness of the tunnel barrier layer 28 is determined by the chosen material. In some examples, the thickness of the tunnel barrier layer 28 can be 0.5 nm to 1.5 nm; however, other thicknesses are possible as long as the thickness of the tunnel barrier layer 28 provides adequate tunnel resistance.

[0061] The magnetization of the magnetic reference layer 30 is fixed. The magnetic reference layer 30 is composed of a metal or metal alloy containing one or more metals that exhibit high spin polarization. In alternative embodiments, exemplary metals for forming the magnetic reference layer include iron, nickel, cobalt, chromium, boron, and manganese. Exemplary metal alloys may include the metals exemplified above. In another embodiment, the magnetic reference layer 30 may have a multilayer structure comprising: (1) a highly spin-polarized interface with the tunnel barrier layer 28 formed of metals and / or metal alloys using the metals described above; and (2) a region composed of one or more materials exhibiting strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials with strong PMA that may be used include metals such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, which may be arranged as alternating layers. The region of strong PMA may also include alloys exhibiting strong PMA, exemplary of which are cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium, iron-platinum, and / or iron-palladium. These alloys may be arranged as alternating layers. In some embodiments, these alternating layers in the magnetic reference layer may be separated by an exchange coupling layer (such as Ru) to align their magnetization directions in opposite directions, forming a so-called synthetic antiferromagnet to reduce dipole coupling between the magnetic reference layer and the magnetic free layer. In some embodiments, combinations of these materials and regions may also be used. The thickness of the magnetic reference layer 30 can be 1 nm to 5 nm; however, other thicknesses are possible and may be used as the thickness of the magnetic reference layer 30.

[0062] The electrode layer 32 is composed of a conductive material such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof. The thickness of the electrode layer 32 can be 5 nm to 100 nm; other thicknesses are also possible and may be used as the thickness of the electrode layer 32 in this application.

[0063] The MTJ structures of the present invention may be formed using a patterning process that includes etching, such as reactive ion etching (RIE) or ion beam etching, following one or more deposition processes such as CVD, PECVD, PVD, ALD (including plasma-assisted ALD), or sputtering.

[0064] In some embodiments, the direct electrical contact structure 24 typically includes one of the spin collector materials described above for the internal core 12. In such embodiments, the spin collector material providing the direct electrical contact structure 24 may be compositionally the same as or different from the spin collector material providing the internal core 12. In Figure 2A (and Figure 3A), a dotted line below the electrical contact structure 24 is shown between the internal core 12 and the direct electrical contact structure 24. This dotted line represents a hypothetical material interface that may exist between the internal core 12 and the direct electrical contact structure 24. In other embodiments, the direct electrical contact structure 24 is composed of one of the conductive materials described above for the conductive structure 20. The direct electrical contact structure 24 may be formed by deposition and lithographic patterning.

[0065] In some embodiments, the charge-current connection is provided by controlling the amount of leakage current flowing across the spin-conductive insulating layer 14 from the internal core 12 to the charge-current-conductive spin-orbit spin-current generation layer 16, thereby accumulating current flow within the charge-current-conductive spin-orbit spin-current generation layer 16 and forming a chiral charge-current. As long as the resistivity of the spin-conductive material 14 is much higher than the resistivity of the internal core 12 and the charge-current-conductive spin-orbit spin-current generation layer 16, this leakage current accumulates inside the charge-current-conductive spin-orbit spin-current generation layer 16, forming a circumferential current flow terminating in the conductive structure 20. This provides the necessary chirality definition with respect to the charge-current flow pattern. In this case, the charge-current-conducting spin-orbit spin current generation layer 16 does not need to be directly wired to the internal core 12 through the metal connector (element 24), but the charge-current-conducting spin-orbit spin current generation layer 16 still needs an electrically insulated gap between its two ends (between the contact end 29 shown in Figure 2B and the end corresponding to the original metal connector 24).

[0066] Referring now to Figure 3, a memory structure including a chiral spin-current supply structure 10 according to another embodiment of the present application is illustrated. The chiral spin-current supply structure 10 used in Figure 3 includes the elements / components described above for Figures 1A and 1B. The chiral spin-current supply structure 10 used in Figure 3 is identical to that used in Figures 2A and 2B, but differs from that used in Figures 2A and 2B in that the elements of the chiral spin-current supply structure 10 used in Figure 3 are inclined (i.e., tapered). This tapering is usually formed during the manufacturing of the chiral spin-current supply structure 10. Such tapered ends often facilitate manufacturing and do not substantially affect the efficiency of charge-spin-current conversion efficiency unless the taper angle deviates significantly from the vertical.

[0067] In particular, the memory structure illustrated in Figure 3 is a two-terminal device that includes, in addition to the chiral spin current supply structure 10, interconnection levels 18 / 20 (described above in Figures 2A-2B) and MTJ structures 26 / 28 / 30 / 32 (described above in Figures 2A-2B). The interconnection levels include a conductive structure 20 and an interconnection dielectric layer 18, both of which are described above for the embodiments illustrated in Figures 2A-2B. As illustrated in Figure 3, the conductive structure 20 is in direct contact with the horizontal plane (i.e., the bottom surface) of the charge-current-conducting spin-orbit spin current generation layer 16. This structure can be inverted as described above, and as a result, both the chiral spin current supply structure 10 and the interconnection levels 18 / 20 are positioned on top of the MTJ structures.

[0068] As further shown in Figure 3, the charge-current-conducting spin-orbit spin-current generation layer 16 is electrically connected to the first terminal 22 (via a conductive structure 20), and the MTJ structures 26 / 28 / 30 / 32 are electrically connected to the second terminal 34 (via another conductive structure (not specifically illustrated in the drawings of this application)). The memory structure shown in Figure 3 also includes a charge-current connection section that connects the internal core 12 to the charge-current-conducting spin-orbit spin-current generation layer 16 (via a direct electrical contact structure 24).

[0069] Referring to Figures 4A to 4F, examples of methods usable for forming the chiral spin current supply structure according to the present invention are shown. The methods illustrated in Figures 4A to 4F represent one usable method. However, other methods, which are readily apparent from the processing flows shown in Figures 4A to 4F, are also usable.

[0070] Referring first to Figure 4A, an exemplary structure is shown which includes a patterned dielectric layer 19 disposed on the surface of an interconnection level containing a conductive structure 20 embedded in an interconnection dielectric layer 18. This interconnection level 18 / 20 may be formed as described above. The patterned dielectric layer 19 contains one of the interconnection dielectric materials described above for the interconnection dielectric layer 18. The interconnection dielectric material providing the patterned dielectric layer 19 may be compositionally the same as or different from the interconnection dielectric material providing the interconnection dielectric layer 18. The patterned dielectric layer 19 includes openings 38 formed therein; more than one opening may be formed. The openings 38 physically expose a portion of the underlying conductive structure 20 and a portion of the underlying interconnection dielectric layer 18. The patterned dielectric layer 19 may be formed by lithographic patterning following deposition of the interconnection dielectric material (e.g., CVD, PECVD, or spin-on coating).

[0071] Next, as shown in Figure 4B, an SOT channel layer 16L and a magnetic insulator layer 14L are formed in the opening 38. The SOT channel layer 16L contains one of the SOT channel materials described above and is used to provide a charge-current-conducting spin-orbit spin-current generation layer 16. The magnetic insulator layer 14L contains one of the magnetic insulator materials described above and is used to provide a spin-conducting insulating layer 14. Both the SOT channel layer 16L and the magnetic insulator layer 14L can be formed by a relatively conformal sidewall deposition process. Some degree of tapering of the SOT channel layer 16L and the magnetic insulator layer 14L can be performed in this step of the present invention.

[0072] Next, as shown in Figure 4C, the magnetic insulator layer 14L and the SOT channel layer 16L can be removed from the bottom of the opening 38 using a directional etching process, such as directional ion beam etching. In some embodiments, the upper part of the interconnect dielectric layer can also be removed by the directional etching process. After directional etching, a portion of the magnetic insulator layer 14L and a portion of the SOT channel layer 16L remain in the opening along the sidewalls of the dielectric layer 19. The remaining portion of the SOT channel layer 16L may be referred herein to as the charge-current-conducting spin-orbit spin-current generation layer 16, and the remaining portion of the magnetic insulator layer 14L may be referred herein to as the spin-conducting insulating layer 14.

[0073] Next, as shown in Figure 4D, if necessary, an additional magnetic insulating material can be formed to provide a magnetic insulating layer 14L having a bottom. The additional magnetic insulating material is compositionally the same as the magnetic insulator used to provide the magnetic insulating layer 14L. The additional magnetic insulator can be formed by a deposition method such as CVD, PECVD, physical vapor deposition (PVD), or atomic layer deposition (ALD). This step may be omitted in some embodiments of the present application.

[0074] Next, as shown in Figure 4E, the spin collector layer 12L is formed by a deposition process such as CVD, PECVD, PVD, ALD, or sputtering. The spin collector layer 12L is a layer formed on the inside and outside of the opening 38. The spin collector layer 12L contains one of the spin collector materials described above and is used to form the internal core 12 of the chiral spin current supply structure.

[0075] Next, as shown in Figure 4F, the over-deposited portion of the spin collector layer 12L formed on the outside of the opening 38 and on the dielectric layer 19 can be removed using a planarization process, such as chemical mechanical polishing (CMP). After planarization, a portion of the spin collector layer 12L remains in the opening 38. This remaining portion of the spin collector layer 12L provides the internal core 12 of the chiral spin current supply structure 10 of the present invention.

[0076] Referring here to Figures 5A and 5B, various diagrams of the simplified memory structure according to the present invention, in the form of a linear SOT channel laminated on only one side wall, are illustrated. In these drawings, the structure includes an interconnect dielectric layer 18 (for example, one of the interconnect dielectrics described above) having a tapered side wall, on which a chiral spin current supply structure is placed. The chiral spin current supply structure includes a layer of spin collector material as an internal core 12, a spin-conducting insulating layer 14, and a charge-current-conducting spin-orbit spin current generation layer 16. The magnetic free layer 26 of the MTJ structure forms an interface with the surface of the spin collector material. In Figure 5A, h indicates the height of the chiral spin current supply structure, and L indicates the length of the side wall in the direction out of the drawing. In Figure 5B, I cg This is a charge current that flows from the internal core 12 to the via contacts (i.e., conductive structures 20) in the interconnect dielectric layer 18 through the charge-current-conducting spin-orbit spin current generation layer 16. The structures illustrated in Figures 5A and 5B can be manufactured using existing manufacturing equipment, and the magnetic insulator and SOT channel material are deposited on the sidewall structure to cover the sidewalls by substantially conformal deposition methods such as sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0077] While this application is specifically shown and described with respect to its preferred embodiments, it will be understood by those skilled in the art that the aforementioned and other modifications in form and detail can be made without departing from the spirit and scope of this application. Accordingly, this application is not limited to the exact forms and details described and illustrated, but is intended to be included within the scope of the appended claims.

Claims

1. A chiral spin current supply structure having an internal core made of a spin collector material, a spin-conducting insulating layer surrounding the internal core, and a charge-current-conducting spin-orbit spin current generation layer surrounding the spin-conducting insulating layer; A magnetic tunnel junction (MTJ) structure having a magnetic free layer that forms an interface with the surface of the internal core; and Charge-current connection section connecting the internal core to the charge-current-conducting spin-orbit spin-current generation layer A memory structure that includes the following features.

2. The memory structure according to claim 1, wherein the spin collector material is made of a metal or metal alloy having spin conductance and spin diffusion length equivalent to high-quality copper.

3. The memory structure according to claim 2, wherein the spin collector material comprises Cu, Ag, Au, or an alloy thereof.

4. The memory structure according to claim 1, wherein the spin-conducting insulating layer is made of a magnetic insulator.

5. The magnetic insulator is made of iron oxide, nickel oxide, or Y ３ Fe ５ O １２ The memory structure according to claim 4, including the memory structure described in claim 4.

6. The memory structure according to claim 1, wherein the charge-current-conducting spin-orbit spin-current generation layer includes a spin-orbit torque (SOT) channel material.

7. The SOT channel material is β-Ta, β-W, Cu ｘ Pt １－ｘ , Cu １－ｘ Ta ｘ , Pd ｘ Pt １－ｘ , Au ｘ Pt １－ｘ , Pt, Bi ２ Se ３ , WTe ２ , PtTe ２ , TaS ２ , Pt ｘ , Rh １－ｘ The memory structure according to claim 6, which includes the above and x ranges from 0 to 1.

8. The memory structure according to claim 1, wherein the MTJ structure includes, from bottom to top, the magnetic free layer, the magnetic tunnel barrier layer, the magnetic reference layer, and the electrode layer.

9. The memory structure according to claim 1, wherein the MTJ structure includes, from bottom to top, an electrode layer, a magnetic reference layer, a magnetic tunnel barrier layer, and the magnetic free layer.

10. The memory structure according to claim 1, further comprising a conductive structure that is in direct contact with the horizontal plane of the charge-current-conducting spin-orbit spin-current generation layer.

11. The memory structure according to claim 10, wherein the conductive structure is disposed within the interconnection dielectric layer.

12. The memory structure according to claim 1, wherein the spin-conductive insulating layer has an inner sidewall and an outer sidewall, the inner sidewall of the spin-conductive insulating layer forming an interface with the outer sidewall of the inner core, and the outer sidewall of the spin-conductive insulating layer forming an interface with the inner sidewall of the charge-current-conductive spin-orbit spin-current generation layer.

13. The memory structure according to claim 12, wherein the outer sidewall of the inner core, the inner sidewall and outer sidewall of the spin-conducting insulating layer, and the inner sidewall of the charge-current-conducting spin-orbit spin-current-generating layer are all perpendicular to the horizontal plane of adjacent interconnection levels.

14. The memory structure according to claim 12, wherein the outer sidewall of the inner core, the inner sidewall and outer sidewall of the spin-conducting insulating layer, and the inner sidewall of the charge-current-conducting spin-orbit spin-current-generating layer are all inclined with respect to the horizontal plane of adjacent interconnection levels.

15. The memory structure according to claim 1, wherein the charge-current-conducting spin-orbit spin-current generation layer supports the flow of chiral charge-current surrounding the internal core such that it generates a spin current substantially spin-polarized outward from the plane of the horizontal surface of the internal core that is in contact with the MTJ structure.

16. The memory structure according to claim 1, wherein the charge-current connection between the internal core and the charge-current-conducting spin-orbit spin-current generation layer enables the flow of chiral charge-current within the charge-current-conducting spin-orbit spin-current generation layer.

17. The memory structure according to claim 1, wherein the charge-current connection between the internal core and the charge-current-conducting spin-orbit spin-current generation layer is a direct-type electrical contact structure.

18. The memory structure according to claim 1, wherein the charge-current connection between the internal core and the charge-current-conducting spin-orbit spin-current generation layer is provided by controlling the amount of leakage current flowing across the spin-conducting insulating layer from the internal core to the charge-current-conducting spin-orbit spin-current generation layer, thereby accumulating a current flow within the charge-current-conducting spin-orbit spin-current generation layer and forming a chiral charge-current.

19. The memory structure according to claim 1, wherein the charge-current-conducting spin-orbit spin-current generation layer is electrically connected to a first terminal, and the MTJ structure is electrically connected to a second terminal.

20. An MTJ structure having a recess in an interconnecting dielectric layer and a spin collector material layer disposed thereon, a spin-conducting insulating layer disposed on the sidewall of the spin collector material layer, and a charge-current-conducting spin-orbit spin-current generation layer disposed on the spin-conducting insulating layer; and a magnetic free layer forming an interface with the surface of the spin collector material layer. A memory structure that includes the following features.

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