Spin-orbit torque memory device

Abstract

Spin-orbit torque magnetoresistive random-access memory (SOT MRAM) devices are provided. In each SOT MRAM device, a topological conductor (i.e., a topological metal or topological semimetal) is used for both the interconnect layer and the SOT layer, and the SOT layer and interconnect layer are integrated at the same metal level. The SOT MRAM device further includes a magnetic tunnel junction (MTJ) structure in contact with the SOT layer, and a contact structure in contact with the MTJ structure.

Description

[Background technology]

[0001] This application relates to a memory device, and more specifically to a spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) device.

[0002] MRAM is a non-volatile random-access memory (NRAM) technology in which data is stored by magnetic storage elements. These elements are typically formed from two ferromagnetic plates, each of which can hold magnetization separated by a thin dielectric layer (i.e., a tunnel barrier layer). One of the two plates (i.e., the magnetic reference or pin layer) is a magnet with a magnetic moment direction set in a specific direction; the magnetization of the other plate (i.e., the magnetic free layer) can be changed in at least two different directions to represent different digital states such as 0 and 1, thereby being applied to memory. In MRAM, such elements may be referred to as a magnetic tunnel junction (MTJ) structure. In a typical MTJ structure, the magnetization of the magnetic reference layer is fixed in one direction (e.g., upward), while the direction of the magnetic free layer can be "switched" by some external force, such as a magnetic field or a charge current that generates a spin torque. By using a smaller current (of either polarity), the resistance of the device, determined by the relative orientation of the magnetizations of the magnetic free layer and the magnetic reference layer, can be read. Resistance is generally higher when the magnetizations are antiparallel and lower when they are parallel (although this can be reversed depending on the material).

[0003] One type of MRAM that can use an MTJ structure is spin-transfer torque (STT) MRAM. STT MRAM has the advantages of lower power consumption and better scalability compared to conventional MRAM that uses a magnetic field to flip the active elements. In STT MRAM, spin-transfer torque is used to flip (switch) the orientation of the magnetic free layer. In STT MRAM devices, current passing through the MTJ structure is used to switch, or "write," the bit state of the MTJ memory elements. Current passing downward through the MTJ structure makes the magnetic free layer parallel to the magnetic reference layer, while current passing upward through the MTJ structure makes the magnetic free layer antiparallel to the magnetic reference layer.

[0004] Another type of MRAM that can utilize MTJ structures is the SOT MRAM device. SOT memory devices do not require high current to pass through the MTJ structure during write operations; this write operation is performed by current flowing through the SOT layer. SOT memory devices are being actively considered as an alternative to STT MRAM for reducing write current and eliminating read interference. Existing SOT MRAM devices include an SOT layer (for writing) made of a different material from the interconnect metal and an MTJ structure (for reading) integrated above it. The SOT layer is connected to one of the metal interconnect layers (e.g., the first metal level, M1) via an SOT via layer. Therefore, in addition to patterning the metal interconnect and the SOT layer, patterning of the SOT via layer must also be performed. Furthermore, the SOT layer and SOT vias are obstacles to increasing density and reducing parasitic resistance by inserting SOT MRAM devices between lower metal interconnect layers in advanced nodes. [Overview of the project]

[0005] SOT MRAM devices for use within structures are provided. Each of the SOT MRAM devices of the present invention uses a topological conductor (i.e., a topological metal or topological semimetal) in both the interconnect layer and the SOT layer, integrating the SOT layer and the interconnect layer at the same metal level. The SOT MRAM device further includes an MTJ structure in contact with the SOT layer and an MTJ contact structure in contact with the MTJ structure. By using a topological conductor in both the interconnect layer and the SOT layer, the SOT layer can be absorbed into the interconnect layer, eliminating the associated SOT via layer, thereby simplifying patterning and allowing for a lower metal level into which the SOT MRAM device is inserted.

[0006] In one embodiment of the present application, a memory structure is provided. In one embodiment of the present application, the memory structure comprises a SOT layer and an interconnect layer located at the same metal level of a wiring process (BEOL) structure, wherein both the SOT layer and the interconnect layer are composed of a topological conductor. In the present application, the SOT layer and the interconnect layer are composed of the same topological conductor. The memory structure further comprises an MTJ structure having a magnetic free layer and forming an interface with the SOT layer; and an MTJ contact structure in contact with the MTJ structure.

[0007] In some embodiments of the present application, the topological conductor comprises a material selected from a metal or a metalloid, wherein the metal or metalloid is protected by a non-trivial band structure topology in which conductive surface states have a surface conductivity greater than the bulk conductivity of the metal or metalloid. Typically, the surface conductivity of the topological conductor is at least twice that of the bulk conductivity.

[0008] In some embodiments of the present application, the topological conductor includes a Weyl semimetal, a multifold fermion semimetal, a magnetic Weyl semimetal, a Kramer-Weyl fermion semimetal, or a triple-point topological metal.

[0009] In some embodiments of the present application, the MTJ structure has, from bottom to top, the magnetic free layer, the tunnel barrier layer, the magnetic reference layer, and the electrode layer. In such embodiments, the MTJ structure is located above the SOT layer but below the contact structure.

[0010] In some embodiments of the present application, the MTJ structure has, from bottom to top, an electrode layer, a magnetic reference layer, a tunnel barrier layer, and the magnetic free layer. In such embodiments, the MTJ structure is located above the contact structure but below the SOT layer.

[0011] In some embodiments of the present application, the MTJ contact structure is composed of a conductive metal, a conductive metal alloy, or another topological conductor. If the MTJ contact structure is composed of a topological conductor, the topological conductor may be compositionally the same as or different from the topological conductor providing the SOT layer and the interconnect layer.

[0012] In some embodiments of the present application, the SOT layer and the interconnect layer are separated by an interconnect dielectric layer.

[0013] In some embodiments of the present application, the memory structure further comprises an SOT contact structure that is electrically connected to the SOT layer by a via structure.

[0014] In some embodiments of the present application, the memory structure further comprises an SOT contact structure which is electrically connected to the SOT layer by its via portion.

[0015] In some embodiments of the present application, the SOT contact structure described in the above embodiments comprises a conductive metal, a conductive metal alloy, or another topological conductor, wherein the other topological conductor is compositionally the same as or different from the topological conductor providing the SOT layer and the interconnect layer.

[0016] In some embodiments of the present application, the memory structure further comprises at least one via structure that contacts the bottom surface of the SOT layer.

[0017] In some embodiments of the present application, the at least one via structure is composed of a conductive metal, a conductive material alloy, or another topological conductor, the other topological conductor being compositionally the same as or different from the topological conductor providing the SOT layer and the interconnect layer.

[0018] In some embodiments of the present application, the SOT layer further comprises at least one via portion located on the side of the SOT layer opposite to the side of the SOT layer that contacts the MTJ structure, and both the SOT layer and the at least one via portion are composed of the topological conductor.

[0019] In some embodiments of the present application, the memory structure further comprises a via structure located below the interconnect layer.

[0020] In some embodiments of the present application, both the SOT layer and the interconnect layer are electrically connected to the source / drain region of the transistor.

[0021] In another aspect of the present application, a structure is provided. In one embodiment, the structure includes a memory device region in which a memory structure is located. The memory structure includes a SOT layer and an interconnect layer located at the same metal level of the BEOL structure, where both the SOT layer and the interconnect layer are composed of topological conductors. The memory structure has a magnetic free layer, a MTJ structure forming an interface with the SOT layer; and further includes a MTJ contact structure contacting the MTJ structure. In addition to the memory device region, the structure also includes a non-memory device region located adjacent to the memory device region. The non-memory device region includes another interconnect layer, where the another interconnect layer is located at the same metal level as both the SOT layer and the interconnect layer, and the another interconnect layer is composed of the topological conductor.

[0022] In some embodiments of the structure of the present application, both the SOT layer and the interconnect layer are electrically connected to the source / drain regions of transistors located within the memory device region, and the another interconnect layer is electrically connected to the source / drain regions of transistors located within the non-memory device region.

Brief Description of the Drawings

[0023] [Figure 1] It is a cross-sectional view of a structure including a SOT MRAM device according to the first embodiment of the present application.

[0024] [Figure 2] It is a cross-sectional view of a SOT MRAM device according to the second embodiment of the present application.

[0025] [Figure 3] It is a cross-sectional view of a SOT MRAM device according to the third embodiment of the present application.

[0026] [Figure 4]This is a cross-sectional view of a SOT MRAM device according to a fourth embodiment of the present application.

[0027] [Figure 5] This is a cross-sectional view of a SOT MRAM device according to the fifth embodiment of the present application.

[0028] [Figure 6-1] Figure 6A is a cross-sectional view of a method that may be used to form an SOT MRAM device according to one embodiment of the present application, Figure 6B is a cross-sectional view of a method that may be used to form an SOT MRAM device according to one embodiment of the present application, Figure 6C is a cross-sectional view of a method that may be used to form an SOT MRAM device according to one embodiment of the present application, and Figure 6D is a cross-sectional view of a method that may be used to form an SOT MRAM device according to one embodiment of the present application. [Figure 6-2] Figure 6E is a cross-sectional view of a method that may be used when forming an SOT MRAM device according to one embodiment of the present application, Figure 6F is a cross-sectional view of a method that may be used when forming an SOT MRAM device according to one embodiment of the present application, and Figure 6G is a cross-sectional view of a method that may be used when forming an SOT MRAM device according to one embodiment of the present application. [Figure 6-3] Figure 6H is a cross-sectional view of a method that may be used when forming a SOT MRAM device according to one embodiment of the present application, and Figure 6I is a cross-sectional view of a method that may be used when forming a SOT MRAM device according to one embodiment of the present application. [Figure 6-4] Figure 6J is a cross-sectional view of a method that may be used when forming a SOT MRAM device according to one embodiment of the present application, and Figure 6K is a cross-sectional view of a method that may be used when forming a SOT MRAM device according to one embodiment of the present application. [Modes for carrying out the invention]

[0029] The present application will be described in more detail here by reference to the following considerations and the drawings accompanying it. Note that the drawings of the present application are provided for illustrative purposes only and are therefore not drawn to scale. Note also that similar and corresponding elements are referenced by similar reference numerals.

[0030] The following description includes numerous specific details, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be understood by those skilled in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, well-known structures or processing steps are not described in detail in order to avoid obscuring the present application.

[0031] When an element, such as a layer, region, or substrate, is described as being "on" or "over" another element, it will be understood that the element may be directly on the other element, or there may be an intervening element. In contrast, when an element is described as being "directly on" or "directly over" another element, there is no intervening element. When an element is described as being "beneath" or "under" another element, it will be understood that the element may be directly below or directly beneath the other element, or there may be an intervening element. In contrast, when an element is described as being "directly beneath" or "directly under" another element, there is no intervening element.

[0032] As described above, SOT MRAM devices are provided in this application. In each of the SOT MRAM devices of this application, a topological conductor (i.e., a topological metal or topological semimetal) is used for both the interconnect layer and the SOT layer, and the SOT layer and interconnect layer are integrated at the same metal level. "Same metal level" means that the SOT layer and interconnect layer are located adjacent to each other laterally, and each is in one of the M1, M2, M3, ... Mn of the BEOL structure. The SOT layer and interconnect layer typically have at least one uppermost surface that is coplanar with each other. The SOT MRAM device further includes an MTJ structure in contact with the SOT layer, and an MTJ contact structure in contact with the MTJ structure. By using a topological conductor for both the interconnect layer and the SOT layer, the SOT layer can be absorbed into the interconnect layer, eliminating the associated SOT via layer, thereby simplifying patterning and lowering the metal level into which the SOT MRAM device is inserted. These and other aspects of the present application are described in more detail here.

[0033] Referring first to Figure 1, a structure according to one embodiment of the present application exists. The structure illustrated in Figure 1 includes a SOT MRAM device according to a first embodiment of the present application located within a memory device area A1. In some embodiments, and as shown in Figure 1, a non-memory device area A2 is located adjacent to the memory device area A1. In Figure 1, an enclosure with a dashed outline is shown. This enclosed area represents the area of ​​memory device area A1 in which the SOT MRAM device is housed. Figure 1 shows one type of SOT MRAM device that may be employed. Subsequent Figures 2 to 5 show other SOT MRAM devices that can be used instead of the SOT MRAM device shown in Figure 1.

[0034] In particular, the illustrated structure includes a semiconductor substrate 10; note that Figure 1 shows only the upper portion of the semiconductor substrate 10. The semiconductor substrate 10 may be composed of at least one semiconductor material having semiconductor properties. Exemplary examples of semiconductor materials that may be employed in this application include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloy, silicon germanium carbide (SiGeC) alloy, germanium (Ge), III / V compound semiconductor, II / VI compound semiconductor, or a multilayer stack comprising at least two semiconductor materials. In some embodiments, the semiconductor substrate 10 may be a bulk semiconductor substrate (i.e., a substrate composed entirely of one or more semiconductor materials). In other embodiments, the semiconductor substrate 10 may be a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes, for example, an insulating layer such as silicon dioxide and / or boron nitride positioned between a first semiconductor material and a second semiconductor material. In one example, the SOI substrate contains Si as the first semiconductor material, silicon dioxide as the insulator, and Si as the second semiconductor material.

[0035] The structure shown in Figure 1 may further include a shallow trench isolation structure 12 (or a similar insulating structure) located within the semiconductor substrate 10. The shallow trench isolation structure 12 may be used to isolate a memory device region A1 from a non-memory device region A2. The shallow trench isolation structure 12 is composed of any trench dielectric material, such as silicon oxide. In some embodiments, a trench dielectric liner, for example, made of silicon nitride (SiN), may be present along the side and bottom walls of the trench dielectric material. The shallow trench isolation structure 12 may have an upper surface that is coplanar with the uppermost surface of the unetched portion of the semiconductor substrate 10. The shallow trench isolation structure 12 may be formed by first forming trenches (by lithography and etching) within the upper portion of the semiconductor substrate 10, depositing optional trench dielectric liner material and trench dielectric material within the trenches, and then performing a planarization process or an etch-back process.

[0036] The structure shown in Figure 1 further includes several transistors. In the drawing, four transistors T1, T2, T3, and T4 are shown as an example. In the illustrated embodiment, T1, T2, and T3 are located within the memory device region A1, while T4 is located within the non-memory device region A2. In the illustrated embodiment, both T1 and T3 are access devices, with T1 functioning as the write line transistor for the memory device and T3 functioning as the read line transistor for the memory device. T2 is a dummy, i.e., inactive, transistor. T4 may be a logic transistor. Each transistor, for example, T1, T2, T3, and T4, is a field-effect transistor (FET) that includes, for example, a high-k (k is equal to or greater than 4.0) material, a gate dielectric material in contact with a semiconductor channel (the channel is located between the source and drain regions of the transistor), and a gate conductor material (including a work function metal) in contact with the gate dielectric material. FETs can be planar transistors and / or non-planar transistors. Exemplary non-planar transistors include, but are not limited to, stacked FETs, nanosheet FETs, or finFETs. The transistor also includes a source / drain region (not shown) in Figure 1. In the illustrated embodiments, the source / drain regions are located in the semiconductor substrate 10 and within the respective footprints of the transistor. The transistor may be formed using techniques well known to those skilled in the art. Note that the transistor is located at the front-end-of-the-line (FEOL) level of the structure shown in Figure 1.

[0037] The structure illustrated in Figure 1 further includes a MOL dielectric layer 16 composed of one or more middle-of-the-line (MOL) dielectric materials such as silicon oxide, silicon nitride, undoped silicate glass (US), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), spin-on low-k dielectrics, chemical vapor deposition (CVD) low-k dielectrics, or any combination thereof. The term “low-k dielectric” as used throughout this application refers to dielectric materials having a dielectric constant k less than 4.0, and it should be noted that all dielectric constants k referred to herein are referenced to vacuum unless otherwise stated. The MOL dielectric layer 16 may be formed by deposition processes including, but are not limited to, CVD, plasma-enhanced chemical vapor deposition (PECVD), or spin-on coating. The MOL dielectric layer 16 is formed between and on each of the transistors, namely T1, T2, T3, and T4.

[0038] The structure in Figure 1 further comprises a plurality of source / drain contact structures 18. Each source / drain contact structure 18 penetrates the MOL dielectric layer 16 and contacts one surface of the source / drain region (not shown) of the underlying transistor. The source / drain contact structure 18 typically has an upper surface that is coplanar with the uppermost surface of the MOL dielectric layer 16. Each source / drain contact structure 18 is composed of a contact conductor material. The contact conductor material may include, for example, silicide liners such as TiSi, NiSi, PtSi, NiPtSi, adhesive metal liners such as TiN, and conductive metals such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof. The source / drain contact structure 18 may include one or more contact liners (not shown). In one or more embodiments, the contact liners (not shown) may include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, their alloys, or stacks thereof such as Ti / TiN and Ti / WC. In one or more embodiments where a contact liner is present, the contact liner (not shown) may include a silicide liner such as TiSi, NiSi, PtSi, NiPtSi, and a diffusion barrier material as defined above. The source / drain contact structure 18 may be formed by utilizing a metallization process that includes forming contact openings within the MOL dielectric layer 16 and then filling each contact opening with at least contact conductor material (including deposition and planarization).

[0039] In this application, the MOL dielectric layer 16 and the source / drain contact structure 18 are located at the MOL level of the structure, which is above the FEOL level of the structure.

[0040] The structure in Figure 1 may further include a dielectric capping layer 19 located on the MOL dielectric layer 16. The dielectric capping layer 19 may be omitted in some embodiments of the present application. If present, the dielectric capping layer 19 is composed of a dielectric material having a different composition from the MOL dielectric layer 16. Exemplary examples of dielectric materials that can be used as the dielectric capping layer 19 include, but are not limited to, dielectric materials containing silicon, carbon, and hydrogen atoms. In some embodiments, in addition to carbon and hydrogen atoms, the dielectric material providing the dielectric capping layer 19 may contain at least one atom of nitrogen and oxygen. In other embodiments, in addition to silicon, nitrogen, carbon, and hydrogen atoms, the dielectric material providing the dielectric capping layer 19 may contain boron atoms. In one example, the dielectric material providing the dielectric capping layer 19 may consist of an NBLOK dielectric material containing silicon, carbon, hydrogen, nitrogen, and oxygen atoms. In an alternative example, the dielectric material providing the dielectric capping layer 19 may consist of a SiBCN dielectric material containing silicon, boron, carbon, hydrogen, and nitrogen atoms. The dielectric capping layer 19 can be formed using a deposition process such as CVD, PECVD, atomic layer deposition (ALD), or spin-on coating.

[0041] The structure illustrated in Figure 1 further includes a plurality of via structures 30, a plurality of interconnect layers 32Y and 32Z, and at least one SOT layer 32X. Each of the interconnect layers 32Y and 32Z, and the at least one SOT layer 32X, resides within a first interconnect dielectric layer ILD1. The interconnect layers 32Y and 32Z reside within the memory device region A1, while the interconnect layer 32Z resides within the non-memory device region A2. As shown, the plurality of interconnect layers 32Y and 32Z, and the at least one SOT layer 32X, are all located at the same metal level of the semiconductor structure. The SOT layer 32X is separated by ILD1 from the interconnect layer 32Y that resides within the memory device area A1. As shown, one end of each via structure 30 is designed to contact one of the underlying source / drain contact structures 18. As shown, several opposite ends of the via structure 30 are designed to contact interconnect layers 32Y and 32Z, and at least one opposite end of the via structure 30 is designed to contact SOT layer 32X. The multiple via structures 30, the multiple interconnect layers 32Y and 32Z, at least one SOT layer 32X, and the first interconnect dielectric layer ILD1 are formed using various deposition and metallization processes. (This aspect of the present application will be described in further detail later herein with respect to the process flow illustrated in Figures 6A to 6K.)

[0042] The first interconnect dielectric layer ILD1 may consist of any interconnect dielectric material, including, for example, silicon oxide (SiOx), silicon nitride (SiNx), SiCOH, SiNCH, SiCN, SiCNO, SiNCOH, silsesquioxane, C-doped oxides (i.e., organic silicates) containing atoms of Si, C, O, and H, thermosetting polyarylene ethers, or multilayers thereof. The term "polyarylene" is used herein to refer to aryl groups or inertly substituted aryl groups linked together by bonds, fused rings, or inert linking groups such as oxygen, sulfur, sulfone, sulfoxide, carbonyl, and the like. The first interconnect dielectric layer ILD1 may have a dielectric constant of about 4.0 or less (all dielectric constants referred to herein are measured relative to vacuum unless otherwise stated). In one embodiment, the first interconnect dielectric layer ILD1 has a dielectric constant of 2.8 or less. These dielectrics generally exhibit lower parasitic crosstalk compared to dielectric materials with dielectric constants greater than 4.0.

[0043] In some embodiments of the present application, each of the plurality of via structures 30 (the via structures are V as shown in Figures 4 and 5) x-1 The via structure (which may be labeled as such) is composed of a conductive metal or metal alloy. Exemplary examples of conductive materials that may be used when providing the via structure 30 include, but are not limited to, Cu, Al, Cu-Al alloy, W, Ru, or Rh. In other embodiments, the via structure 30 is composed of a topological conductor (as described later herein). In some embodiments, the via structure 30 may replace via portions present in the SOT layer 32X and interconnect layers 32Y and 32Z present in the structure, respectively.

[0044] In some embodiments, a diffusion barrier liner (not shown) may be present along at least the side walls (and, in some embodiments, along the bottom wall) of each of the plurality of via structures 30. If present, the diffusion barrier liner may be composed of any well-known diffusion barrier material, such as Ta, TaN, Ti, TiN, W, or WN. In some embodiments, the diffusion barrier liner may comprise a material stack of two or more diffusion barrier materials. In one example, the diffusion barrier liner may consist of a stack of Ta / TaN or a stack of Ti / TiN.

[0045] Multiple interconnect layers 32Y and 32Z, and at least one SOT layer 32X present within the first interconnect dielectric layer ILD1, are all composed of the same topological conductor. In embodiments of the present application, the topological conductors providing each of the interconnect layers 32Y and 32Z, and at least one SOT layer 32X, are either compositionally the same as or compositionally different from the topological conductors that may be used in specific embodiments of the present application to provide the via structure 30. The term “topological conductor” is used herein to define a conductive material (i.e., a topological metal or topological semimetal) having a non-trivial bulk-band structure topology that ensures the presence of a conductive surface state in which carrier scattering is suppressed, such that the conductivity of the surface is much greater (twice or more) than the conductivity of the bulk of the material (i.e., the portion of the material below the surface of the material). Topological conductors typically have a high efficiency in converting charge current to spin current, and therefore they are good spin current sources and can be used as SOT materials.

[0046] In this application, the topological conductors that can be used (i.e., topological metals or topological semimetals) are categorized according to the dimensionality of their band crossings and their band degeneracy at the band crossings. Topological conductors having 0D band crossings include Weyl semimetals and multifold-fermion semimetals. The former have a 2-fold band degeneracy, while the latter may have 3, 4, 6, or 8-fold band degeneracy at the nodes. Non-magnetic, non-centrosymmetric Weyl semimetals include TaAs, TaP, NbAs, NbP, (Mo,W)Te2, LaAlGe, and TaIrTe4. Magnetic Weyl semimetals include Co3Sn2S2, Mn 3+x Sn 1-x This includes EuCd2As2, RAlGe (where R is a rare earth metal), and PrAlGe. Multifold fermion semimetals include CoSi, RhSi, CoGe, RhGe, and AlPt. Double Weyl fermions may be used in some embodiments of the present application.

[0047] Weyl nodes and fermiarcs also exist in non-magnetic chiral crystals with associated spin-orbit interactions. Candidates for these so-called Kramer-Weyl fermion topological semimetals include Ag3BO3 (SG-156), T1Te2O6 (SG-150), Ag2Se (SG-19), etc., where SG = space group.

[0048] Topological conductors with 1D band crossings are called topological nodal-line semimetals. These semimetals include XY4 crystals (X=Ir, Ta, Re; Y=F, Cl, Br, I) that have lattices formed from octahedra, similar to Co2MnGa and IrF4.

[0049] In addition to the topological materials described above, there is another distinct type of topological conductor that can be employed: triple-point topological metals. They are characterized by having three topologically protected Weyl nodes, two of which are degenerate along highly symmetrical directions within the Brillouin zone. They are distinguished from topological semimetals in that the band gap between the conduction band and the valence band closes along this highly symmetrical line. Examples of triple-point topological metals include WC, MoC, MoP, MoN, and ZrTe.

[0050] Unlike topological insulators, topological conductors exhibit very high carrier density and high carrier mobility at the Fermi level, enabling high current-carrying capacity. When the dimensions of topological semimetals scale to less than approximately 10 nm, carrier transport via the Fermi arc state becomes significant and can overwhelm bulk-state transport. Depending on the type of impurity scattering and the type of topological semimetal, significant surface-state transport may persist up to approximately 100 nm.

[0051] Electron transmission via Fermi arc states is robust against defects and impurities once the film thickness exceeds a material-dependent threshold, for example, approximately 2.5 nm for CoSi. High mobility of Fermi arc surface electrons can be ensured even with very small film thicknesses. Furthermore, because multiple bands crossing the Weyl node are orthogonal to each other, the scattering of bulk electrons is suppressed overall, ensuring high mobility of bulk state electrons near the Weyl node. From these findings, it can be seen that topological conductors that (1) have a high Chern number, (2) have many pairs of Weyl nodes, and (3) have very few or no topologically trivial bulk bands near the Fermi level are preferred materials for application.

[0052] For example, the Weyl semimetal NbAs exhibits a resistivity (1-5 μΩ·cm) lower than its bulk resistivity (approximately 35 μΩ·cm) at the submicron scale, potentially allowing for a 50% or greater reduction in the resistivity-capacitivity product (RC) at a 5 nm node size. Extremely low resistivity (approximately 9 nΩ·cm at 2 K and 8.2 μΩ·cm at 300 K) has also been observed in the topological metal MoP. For comparison, the bulk resistivity of Cu is approximately 2 μΩ·cm, increasing to approximately 15 μΩ·cm at the 15-18 nm scale.

[0053] As discussed earlier, the topological conductors that can be used in this application are not limited to, but include Weyl semimetals such as NbAs, TaAs, NbP, TaP, (Mo,W)Te2; multifold fermion systems such as RhSi, CoSi; and magnetic Weyl semimetals such as Co3Sn2S2, Mn 3+x Sn 1-x This includes PrAlGe, etc.; Kramer-Weyl fermions such as Ag2Se, and triple-point topological metals such as MoP and WC.

[0054] The structure illustrated in Figure 1 further includes an MTJ structure 38P located within the memory device region A1. The MTJ structure 38P forms an interface with the SOT layer 32X. The MTJ structure 38P is a patterned magnetic material-containing stack including a magnetic free layer, a tunnel barrier layer, a magnetic reference layer, and an electrode layer. Other magnetic and non-magnetic layers may be present within the patterned magnetic material-containing stack providing the MTJ structure 38P. In some embodiments, the patterned magnetic material-containing stack providing the MTJ structure 38P includes, from bottom to top, a magnetic free layer, a tunnel barrier layer, a magnetic reference layer, and an electrode layer. In other embodiments, the patterned magnetic material-containing stack providing the MTJ structure 38P includes, from bottom to top, an electrode layer, a magnetic reference layer, a tunnel barrier layer, and a magnetic free layer, and this embodiment requires a complete inversion of the memory structure so that the SOT layer 32X is located above the MTJ structure 38P. In this application, the magnetic free layer of the MTJ structure 38P forms an interface with the SOT layer 32X.

[0055] The magnetic free layer consists of at least one magnetic material having a magnetization that can be reoriented relative to the magnetization orientation of the magnetic reference material. Exemplary magnetic materials for the magnetic free layer include, but are not limited to, cobalt, iron, cobalt-iron alloys, nickel, nickel-iron alloys, and cobalt-iron-boron alloys and / or multilayers. The magnetic free layer may have a thickness of 0.3 nm to 3 nm, but other thicknesses are possible and may be used as the thickness of the magnetic free layer.

[0056] The tunnel barrier layer comprises a tunnel barrier material. The tunnel barrier material is formed to a thickness that provides appropriate tunnel resistance. The tunnel barrier materials that may be used in this application include, but are not limited to, magnesium oxide, aluminum oxide, titanium oxide, or materials with higher electrical tunnel conductance, such as semiconductors or low-bandgap insulators. The thickness of the tunnel barrier layer is determined by the selected material. In one example, the tunnel barrier layer may have a thickness of 0.5 nm to 1.5 nm, but other thicknesses are possible as long as the thickness of the tunnel barrier layer provides appropriate tunnel resistance.

[0057] The magnetic reference layer is composed of a magnetic material having a fixed magnetization. The magnetic material providing the magnetic reference layer is composed of a metal or a metal alloy containing one or more metals exhibiting high spin polarization. In an alternative embodiment, exemplary metals for forming the magnetic reference layer include iron, nickel, cobalt, chromium, boron, and manganese. Exemplary metal alloys may include the metals exemplified above. In another embodiment, the magnetic reference layer may be a multilayer structure having (1) a high spin polarization region formed from a metal and / or a metal alloy using the metals described above, and (2) a region constructed from a material or multiple materials exhibiting strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials with strong PMA that may be used include metals such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, which may be arranged as alternating layers. The strong PMA region may include alloys exhibiting strong PMA, along with exemplary alloys containing cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium, iron-platinum, and / or iron-palladium. The alloys may be arranged as alternating stacked layers. In one embodiment, combinations of these materials and regions may be employed. In another embodiment, combinations of these materials and regions may form a synthetic antiferromagnetic layer that pins the magnetization of the magnetic reference layer. The magnetic reference layer may have a thickness of 0.3 nm to 30 nm, but other thicknesses are possible and may be used as the thickness of the magnetic reference layer.

[0058] The electrode layer is composed of a conductive material such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof. The electrode layer may have a thickness of 5 nm to 100 nm; other thicknesses are possible and may be used in this application.

[0059] The MTJ structure 38P may be formed by deposition and patterning. Deposition may include, but is not limited to, one or more deposition processes including atomic layer deposition (ALD) including CVD, PECVD, PVD, plasma-enhanced ALD, or sputtering. Patterning may include reactive ion etching or ion-beam etching (IBE).

[0060] The structure illustrated in Figure 1 may further include an encapsulation liner 40L located on the ILD1 and surrounding the sides of the MTJ structure 38P. The encapsulation liner 40L contains one of the dielectric materials described above with respect to the dielectric capping layer 19. The encapsulation liner 40L may be formed by depositing a dielectric material and then removing the dielectric material that provides for the encapsulation liner 40L formed on the MTJ structure 38P. This removal of the dielectric material formed on the MTJ structure 38P may be performed during the formation of contact structures 44B and 44D.

[0061] The structure illustrated in Figure 1 further includes contact structures 44B and 44D. In some embodiments, and as shown in Figures 3, 4, and 6K, contact structures 44A and 44C may be formed. Contact structure 44B provides an upper metal-level contact to the MTJ structure 38P and may therefore be referred to herein as the MTJ contact structure. Contact structure 44B forms an interface with the MTJ structure 38P. Contact structure 44D provides an upper metal-level contact to the interconnect layer 32Z located within the non-memory device region. Contact structure 44D may be referred to as the non-memory interconnect contact structure.

[0062] If a contact structure 44A is present, the contact structure 44A provides an upper metal-level contact to the SOT layer 32X formed within the memory device region A1. Therefore, the contact structure 44A may be referred to herein as an SOT contact structure. In some embodiments, the contact structure 44A (i.e., the SOT contact structure) is via portion Vx+1 and includes the same material as the contact structure 44A. In such an embodiment, the V of the contact structure 44A, which is the via portion x+1 forms an interface with the SOT layer 32X (see, for example, FIGS. 5 and 6K). In other embodiments, a via structure 31 composed of a conductive material different from the contact structure 44A forms an interface with the SOT layer 32X (see, for example, FIG. 3).

[0063] When the contact structure 44C is present, the contact structure 44C provides an upper metal level contact to the interconnect layer 32Y formed within the non-memory device region A2 (see, for example, FIG. 6K). Thus, the contact structure 44C may be referred to herein as an interconnect contact structure. In FIG. 6K, the contact structure 44C includes a via portion V x+1 and includes. The via portion V x+1 may be composed of the same or a different material from the contact structure 44C.

[0064] In the present application, the contact structures 44A, 44B, 44C, and 44D are composed of the conductive metals, conductive metal alloys, or topological conductors described above. The topological conductor providing the contact structures 44A, 44B, 44C, and 44D may be compositionally the same as or compositionally different from the topological conductor providing the interconnect layers 32Y, 32Z, and the SOT layer 32X. In an embodiment, each via portion V x+1 may be composed of a material selected from one of the conductive metals, conductive metal alloys, or the topological conductors described above and a material that is compositionally the same or compositionally different. In an embodiment including the second via structure 31, the second via structure 31 may be composed of a material compositionally different from the upper connected conductive structure. For example, the contact structure 44A may be composed of a topological conductor, while the second via structure 31 is composed of Cu. Each of the contact structures 44A, 44B, 44C, and 44D is formed using a metallization process.

[0065] The structure in Figure 1 further includes a second interconnect dielectric layer ILD2. The second ILD layer ILD2 includes at least one of the dielectric materials described above with respect to the first interconnect dielectric layer ILD1. At least a portion of each of the conductive contact structures 44A, 44B, 44C, and 44D is embedded in the second interconnect dielectric layer ILD2. The second interconnect dielectric layer ILD2 is formed by a deposition process such as CVD, PECVD, ALD, or spin-on coating. In this application, the second interconnect dielectric layer ILD2 is usually formed before the formation of the contact structures 44A, 44B, 44C, and 44D.

[0066] In summary, the structure illustrated in Figure 1 includes a memory device region A1 containing an internally located memory structure, which includes an SOT layer 32X and an interconnect layer 32Y located at the same metal level as the BEOL structure, where both the SOT layer 32X and the interconnect layer 32Y are composed of topological conductors, with the MTJ structure 38P located on the SOT layer 32X and the MTJ contact structure 44B located on the MTJ structure 38P. In addition to the memory device region A1, the structure also includes a non-memory device region A2 located adjacent to the memory device region A1. The non-memory device region A2 includes another interconnect layer 32Z, where this other interconnect layer 32Z is ​​located at the same metal level as both the SOT layer 32X and the interconnect layer 32Y, and this other interconnect layer 32Z is ​​composed of topological conductors.

[0067] Referring here to Figures 2 to 5, these illustrate other SOT MRAM devices according to the present application that can be used as replacements for the SOT MRAM device shown in Figure 1. In particular, the SOT MRAM device shown in Figure 2 includes an SOT layer 32X, a via structure 30 located below the SOT layer 32X, an MTJ structure 38P located on the SOT layer 32X, a contact structure 44B located on the MTJ structure 38P, a contact structure 44A located on one side of the MTJ structure 38P, and a via structure 31 connecting the contact structure 44A to the SOT layer 32X. The SOT MRAM device shown in Figure 3 includes an SOT layer 32X, an MTJ structure 38P located on the SOT layer 32X, a contact structure 44B located on the MTJ structure 38P, contact structures 44A located on both sides of the MTJ structure 38P, and a via structure 31 electrically connecting each contact structure 44A to the SOT layer 32X. The SOT MRAM device shown in Figure 4 includes a via portion V x-1 It includes an SOT layer 32X having the SOT layer 32X and via portion V. x-1 It is a single structure and is composed of the same topological conductor. The SOT MRAM device illustrated in Figure 4 further includes an MTJ structure 38P located on the SOT layer 32X, and a contact structure 44B located on the MTJ structure 38P. The SOT MRAM device illustrated in Figure 5 has a via structure 31 with via portion V x+1 It is similar to the SOT MRAM device shown in Figure 3, except that the electrical contact structure 44A and via portion V are replaced. x+1 It has a single structure and is composed of the same material, namely the conductive metal, conductive metal alloy, or topological conductor mentioned above.

[0068] Referring now to Figures 6A to 6K, a method that may be used when forming an SOT MRAM device according to one embodiment of the present application is illustrated. The method illustrated in Figures 6A to 6K is limited to the memory device region A1 depicted in Figure 1. Referring first to Figure 6A, an exemplary interconnect level that may be employed in the present application is illustrated. In particular, Figure 6A illustrates an interconnect level that includes at least one first conductive structure 22 (two of which are illustrated in Figure 6A as one example) embedded within a first interconnect dielectric layer 20.

[0069] The first dielectric layer 20 may be composed of one of the interconnect dielectric materials described above with respect to the ILD1. The first dielectric layer 20 may be formed by a deposition process such as CVD, PECVD, ALD, sputtering, or spin-on coating. The first dielectric layer 20 may have a thickness of 50 nm to 250 nm. Other thicknesses, smaller than 50 nm and larger than 250 nm, may be used in this application as the thickness of the first interconnect dielectric layer 20.

[0070] The first conductive structure 22 may be composed of a conductive metal, a conductive metal alloy, or a topological conductor. In some embodiments, a diffusion barrier liner (not shown) may be present along at least the side walls (and in some embodiments along the bottom wall) of the via structure 22. The diffusion barrier liner includes one of the diffusion barrier materials mentioned earlier.

[0071] The exemplary structure shown in Figure 6A may first be formed by depositing a first dielectric layer 20. The first deposition may include, for example, CVD, PECVD, ALD, sputtering, or spin-on coating. Next, at least one contact opening is formed within the first dielectric layer 20 by lithography and etching. Lithography includes forming a photoresist material on the surface of a material layer or structure that needs to be patterned, exposing the deposited photoresist material to a pattern of irradiation, and then developing the exposed photoresist material. The etching used to provide at least one contact opening within the first dielectric layer 20 may include a dry etching process (i.e., reactive ion etching, plasma etching, or ion beam etching) or chemical wet etching. Next, if present, a layer of diffusion barrier material may be formed within at least one via opening and on top of the first dielectric layer 20. Formation of the diffusion barrier material layer may include, for example, a deposition process such as CVD, PECVD, physical vapor deposition (PVD), or atomic layer deposition (ALD). The diffusion barrier material layer does not fill the entirety of at least one contact opening. Next, one of the conductive materials described above (e.g., Cu) is deposited on top of the diffusion barrier material layer. The deposition of the conductive material may include CVD, PECVD, PVD, ALD, sputtering, or plating. A planarization process, such as chemical mechanical polishing (CMP), is then performed to remove the diffusion barrier material layer (if present) and the conductive material or topological semimetal formed outside at least one opening and on the first dielectric layer 20. The conductive material and, if present, the diffusion barrier material layer remain in the opening after the planarization process. The conductive material remaining in the opening provides at least one first conductive structure 22, and, if present, the diffusion barrier material layer remaining in the opening provides a diffusion barrier liner (not shown in Figure 6A).In embodiments of the present application, at least one first conductive structure 22 has an uppermost surface that is at least coplanar with the uppermost surface of the first interconnect dielectric layer 20; if a diffusion barrier liner is present, the uppermost surface of at least one first conductive structure 22 may be coplanar with the uppermost surface of the diffusion barrier layer and the uppermost surface of the first dielectric layer 20.

[0072] Referring now to Figure 6B, the interconnect level shown in Figure 6A is illustrated after the dielectric capping material layer 24 and the second dielectric layer 26 have been formed on the interconnect level. As shown, the dielectric capping material layer 24 is located on both the first dielectric layer 20 and at least one conductive structure 22, while the second dielectric layer 26 is located on the dielectric capping layer 24. In some embodiments (not shown), the dielectric capping layer 24 may be omitted from being formed.

[0073] If present, the dielectric capping layer 24 includes one of the dielectric materials described above with respect to the dielectric capping layer 19. The dielectric material providing the dielectric capping layer 24 may have a thickness of 10 nm to 200 nm. Other thicknesses are possible and can be employed as the thickness of the dielectric material providing the dielectric capping layer 24. The dielectric capping layer 24 may be formed using a deposition process such as CVD, PECVD, ALD, sputtering, or spin-on coating.

[0074] A second dielectric layer 26, which may be formed directly on either the dielectric capping layer 24 (if present) or the interconnect level shown in Figure 6A (if the dielectric capping layer 24 is not present), comprises one of the dielectric materials described above with respect to ILD1. The dielectric material providing the second dielectric layer 26 may be compositionally the same as or different from the dielectric material providing the first interconnect dielectric layer 20. The dielectric material providing the second dielectric layer 26 is compositionally different from the dielectric capping layer 24. The second dielectric layer 26 may be formed using a deposition process such as CVD, PECVD, ALD, sputtering, or spin coating. The second dielectric layer 26 may have a thickness within the range described above with respect to the first dielectric layer 20.

[0075] Referring here to Figure 6C, an exemplary structure shown in Figure 6B is illustrated after at least one via opening 28 (two of which are shown as one example in Figure 6C) has been formed within the dielectric material stack of the second dielectric layer 26 and the dielectric capping layer 24. As shown, each via opening 28 physically exposes the surface of the underlying first conductive structure 22. At least one via opening 28 may be formed by lithography and etching. A cleaning step may be used to clean the physically exposed surface of the underlying metal-containing structure.

[0076] Referring here to Figure 6D, an exemplary structure shown in Figure 6C is illustrated after the via structures 30 have been formed in each of the via openings 28. In some embodiments, and in addition to the via structures 30, a diffusion barrier liner (not shown) may be present in each of the via openings 28. If a diffusion barrier liner is present, it is located along the side and bottom walls of the via structure 30. The via structure 30 comprises one of the conductive metals or metallic alloys described above with respect to at least one first conductive structure 22, and the optional diffusion barrier liner comprises one of the diffusion barrier materials described above. In some embodiments, the via structure 30 is composed of a previously defined topological conductor. The via structure 30 may be formed by utilizing the metallization process (deposition, followed by planarization) described above when forming the first conductive structure 22. Each via structure 30 has at least an upper surface that is typically coplanar with the uppermost surface of the second interconnect dielectric layer 26.

[0077] Referring here to Figure 6E, an exemplary structure shown in Figure 6D is illustrated after the formation of the topological conductor layer 32. As shown, the topological conductor layer 32 is formed on the physically exposed uppermost surface of the second interconnect dielectric layer 26 and on the physically exposed uppermost surface of each via structure 30. The topological semimetallic conductor 32 includes one of the topological materials described above. The topological conductor layer 32 may be formed using a deposition process such as CVD, PECVD, ALD, sputtering, or molecular beam epitaxy (MBE). In one example, the topological conductor layer 32 is composed of CoSi that can be sputtered from a Co-Si target at temperatures between 250°C and 550°C. The topological conductor layer 32 may have a thickness of 3 nm to 50 nm. Other thicknesses smaller than 3 nm and larger than 50 nm may be employed in this application as the thickness of the topological conductor layer 32.

[0078] Referring now to Figure 6F, an exemplary structure shown in Figure 6E is illustrated after the topological conductor layer 32 has been patterned to have an opening 34 that physically exposes the surface of the underlying second dielectric layer 26. The opening 34 can be formed by lithography and etching. One of the remaining (unetched) portions of the topological conductor layer 32 that is not located above the via structure 30 will function as an SOT layer 32X, while the other remaining portion of the topological conductor layer 32 that is located above the via structure 30 will function as an interconnect layer 32Y. The SOT layer 32X and the adjacent interconnect layer 32Y, composed of the same topological conductor, are located at the same metal level in the exemplary structure.

[0079] Referring here to Figure 6G, an exemplary structure shown in Figure 6F is illustrated after the dielectric material plug 36 has been formed within the opening 34. The dielectric material plug 36 separates the sidewall of the SOT layer 32X from the sidewall of the interconnect layer 32Y, and is formed in direct physical contact with the surface of the underlying, previously physically exposed second dielectric layer 26. The dielectric material plug 36 comprises a dielectric material that may be compositionally identical to or compositionally different from the dielectric material providing the second dielectric layer 26. Typically, the dielectric material providing the dielectric material plug 36 is compositionally identical to the dielectric material providing the second dielectric layer 26. The dielectric material plug 36 may be formed by deposition of the dielectric material (e.g., CVD, PECVD, ALD, or spin-on coating), followed by a planarization process. Sputtering cleaning may follow the planarization process. The dielectric material plug 36 typically has an uppermost surface that is coplanar with the uppermost surfaces of both the SOT layer 32X and the interconnect layer 32Y.

[0080] Referring here to Figure 6H, an exemplary structure shown in Figure 6G is illustrated after the formation of a magnetic material-containing stack 38, which includes a blanket layer of magnetic free layer material, a blanket layer of tunnel barrier material, a blanket layer of magnetic reference layer material, and a blanket layer of electrode material; the electrode material blanket layer is subsequently patterned to serve as an etching mask for the remaining blanket layers in this magnetic material-containing stack 38. Note that other magnetic and non-magnetic materials that are normally present in an MTJ structure may be formed within the magnetic material-containing stack 38 shown in Figure 6H.

[0081] Each of the magnetic free layer material, tunnel barrier material, magnetic reference layer material, and electrode material used in forming the magnetic material-containing stack 38 is described above with respect to the MTJ structure 38P shown in Figure 1. The magnetic material-containing stack 38 described above and shown in Figure 6H may be formed using one or more deposition processes, including, but not limited to, CVD, PECVD, PVD, ALD (including plasma-enhanced ALD), or sputtering.

[0082] Referring now to Figure 6I, an exemplary structure shown in Figure 6H is illustrated after the magnetic material-containing stack 38 has been patterned to provide the MTJ structure 38P. The MTJ structure 38P is located directly above the top surface of the SOT layer 32X. The MTJ structure includes the remaining (i.e., unpatterned) portion of the magnetic material-containing stack 38 described above. In other words, the MTJ structure includes the remaining portion of the blanket layer of the magnetic free layer material, the remaining portion of the blanket layer of the tunnel barrier material, the remaining portion of the blanket layer of the magnetic reference layer material, and the remaining portion of the electrode material.

[0083] Patterning of the magnetic material-containing stack 38 involves a lithography process in which a patterned resist (not shown) is formed on the uppermost surface of the top electrode material of the magnetic material-containing stack 38. The patterned resist can be formed by depositing a photoresist material, exposing the photoresist material to irradiation of a desired pattern, and developing the exposed photoresist material. The patterned resist protects a portion of the blanket layer of the electrode material, while leaving other portions of the blanket layer of the top electrode material physically exposed. The physically exposed portions of the blanket layer of the top electrode material are removed in an initial transfer etching. After the initial transfer etching, the patterned resist is removed using a conventional resist removal process, such as ashing. Patterning continues using another etching, where the remaining portion of the electrode material acts as an etching mask for the rest of the patterning process. This other etching stops on the surface of the SOT layer 32X. This other etching removes the remaining portion of the magnetic material-containing stack 38 that is not covered by the remaining portion of the top electrode material. Transfer etching and subsequent etching may include ion beam etching, reactive ion beam etching, or any combination thereof. Transfer etching may be the same as or different from the other etching used in this patterning step. For example, transfer etching may include reactive ion etching, and the other etching may include ion beam etching.

[0084] In some embodiments of the present application, the exemplary structure shown in Figure 6I may undergo an oxygen treatment process or any other gas treatment or etching process to remove any undesirable metal particles that may be redeposited on the sidewalls of the MTJ structure 38P during this patterning.

[0085] Referring here to Figure 6J, an exemplary structure shown in Figure 6I is illustrated after the formation of the encapsulation layer 40 and the third interconnect dielectric layer 42. The encapsulation layer 40 surrounds the MTJ structure 38P and is located on the SOT layer 32X, the dielectric material plug 36, and the interconnect layer 32Y. The encapsulation layer 40 comprises one of the materials previously mentioned herein with respect to the encapsulation liner 40L. The encapsulation layer 40 may have a thickness of 3 nm to 200 nm. Other thicknesses are possible and may be employed for the encapsulation layer 40.

[0086] A third dielectric layer 42 that may be formed on the encapsulation layer 40 may include one of the dielectric materials described above with respect to ILD1. The dielectric material providing the third dielectric layer 42 may be compositionally the same as or different from the dielectric material providing the first dielectric layer 20 and / or the second dielectric layer 26. The third dielectric layer 42 may be formed by utilizing one of the deposition processes described above with respect to forming the first dielectric layer 20.

[0087] Referring now to Figure 6K, an exemplary structure shown in Figure 6J is illustrated after the formation of the contact structures 44A, 44B, and 44C. In this application, contact structure 44A is in contact with the surface of the SOT layer 32X, contact structure 44B is in contact with the surface of the MTJ structure 38P (typically in contact with the remaining top electrode material portion of the MTJ structure 38P), and contact structure 44C is in contact with the surface of the interconnect layer 32Y. Each of the contact structures 44A, 44B, and 44C may include a diffusion barrier liner as previously described above. Each of the contact structures 44A, 44B, and 44C includes the conductive metal, conductive metal alloy, or topological semimetal described above. Each of the contact structures 44A, 44B, and 44C is formed using the metallization process described above when forming the first conductive structure 22. As shown in Figure 6K, contact structures 44A and 44C are V X+1 Includes the beer portion which is labeled as such.

[0088] While this application is specifically shown and described with respect to its preferred embodiments, those skilled in the art will understand that the aforementioned and other modifications in form and detail can be made without departing from the scope of this application. Accordingly, this application is not limited to the exact forms and details described and illustrated, but is intended to be included within the scope of the appended claims.

Claims

1. A spin-orbit torque (SOT) layer and an interconnect layer located at the same metal level in a wiring process (BEOL) structure, where both the spin-orbit torque (SOT) layer and the interconnect layer are composed of a topological conductor; A magnetic tunnel junction (MTJ) structure having a magnetic free layer and forming an interface with the SOT layer; and MTJ contact structure that contacts the aforementioned MTJ structure A memory structure comprising the following features.

2. The memory structure according to claim 1, wherein the topological conductor comprises a material selected from metals or metalloids, and the metal or metalloid has a conductive surface state protected by a band structure, the surface conductivity of which is greater than the bulk conductivity of the metal or metalloid.

3. The memory structure according to claim 2, wherein the topological conductor includes a Weyl semimetal, a multifold fermion semimetal, a magnetic Weyl semimetal, a Kramer-Weyl fermion semimetal, or a triple-point topological metal.

4. The memory structure according to any one of the above claims, wherein the MTJ structure has the magnetic free layer, tunnel barrier layer, magnetic reference layer, and electrode layer from bottom to top.

5. The memory structure according to any one of the above claims, wherein the MTJ structure has an electrode layer, a magnetic reference layer, a tunnel barrier layer, and the magnetic free layer from bottom to top.

6. The memory structure according to any one of the above claims, wherein the MTJ contact structure is composed of a conductive metal, a conductive metal alloy, or another topological conductor.

7. The memory structure according to any one of the above claims, wherein the SOT layer and the interconnect layer are separated by an interconnect dielectric layer.

8. The memory structure according to any one of the above claims, further comprising an SOT contact structure electrically connected to the SOT layer by a via structure.

9. The memory structure according to claim 8, wherein the SOT contact structure has a conductive metal, a conductive metal alloy, or another topological conductor, the other topological conductor being compositionally the same as or compositionally different from the topological conductor providing the SOT layer and the interconnect layer.

10. The memory structure according to any one of the above claims, further comprising an SOT contact structure that is electrically connected to the SOT layer by its via portion.

11. The memory structure according to claim 10, wherein the SOT contact structure has a conductive metal, a conductive metal alloy, or another topological conductor, the other topological conductor being compositionally the same as or compositionally different from the topological conductor providing the SOT layer and the interconnect layer.

12. The memory structure according to any one of the above claims, further comprising at least one via structure in contact with the bottom surface of the SOT layer.

13. The memory structure according to claim 12, wherein the at least one via structure is composed of a conductive metal, a conductive material alloy, or another topological conductor, the other topological conductor being compositionally the same as or compositionally different from the topological conductor providing the SOT layer and the interconnect layer.

14. The memory structure according to any one of the above claims, wherein the SOT layer further has at least one via portion located on the side of the SOT layer opposite to the side of the SOT layer that contacts the MTJ structure, and both the SOT layer and the at least one via portion are composed of the topological conductor.

15. The memory structure according to any one of the above claims, further comprising a via structure located below the interconnect layer.

16. The memory structure according to any one of the above claims, wherein the SOT layer is electrically connected to the source / drain region of a transistor.

17. It has a memory device area in which a memory structure is inherent, The aforementioned memory structure is A spin-orbit torque (SOT) layer and an interconnect layer located at the same metal level in a wiring process (BEOL) structure, wherein both the spin-orbit torque (SOT) layer and the interconnect layer are composed of topological conductors; A magnetic tunnel junction (MTJ) structure having a magnetic free layer and forming an interface with the SOT layer; and Includes an MTJ contact structure that contacts the aforementioned MTJ structure, The device further comprises a non-memory device region adjacent to the memory device region, the non-memory device region including another interconnect layer, the other interconnect layer being located at the same metal level as both the SOT layer and the interconnect layer, and the other interconnect layer being composed of the topological conductor. structure.

18. The structure according to claim 17, wherein the topological conductor comprises a material selected from metals or metalloids, and the metal or metalloid has a conductive surface state protected by a band structure, the surface conductivity of which is greater than the bulk conductivity of the metal or metalloid.

19. The structure according to claim 18, wherein the topological conductor includes a Weyl semimetal, a multifold fermion semimetal, a magnetic Weyl semimetal, a Kramer-Weyl fermion semimetal, or a triple-point topological metal.

20. The structure according to any one of the above claims, wherein the SOT layer is electrically connected to the source / drain regions of transistors located within the memory device region, and the other interconnect layer is electrically connected to the source / drain regions of transistors located within the non-memory device region.

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