Multilevel converter system

Abstract

The present invention relates to a multilevel converter system comprising a plurality of energy storage modules and transistors, wherein each energy storage module can be connected in parallel to an adjacent energy storage module, connected in series to an adjacent energy storage module, and / or bridged to an adjacent energy storage module, and at least two adjacent NPN transistors share an N-type region, and / or at least two adjacent PPN transistors share a P-type region.

Description

Technical Field

[0001] The present invention relates to a multilevel converter system including a plurality of energy storage modules and a transistor, where each energy storage module can be connected in parallel to each adjacent energy storage module, can be connected in series to each adjacent energy storage module, and / or can be bridge-connected, and each energy storage module has at least one energy storage cell.

Background Art

[0002] Conventional energy storage devices are usually loaded with a load by a direct current voltage (DC). This is due to the structure of the conventional converter system. Attempts have been made to keep the alternating voltage component, i.e., the harmonic vibration, away from the energy storage device.

[0003] In this case, since many energy storage devices need to be connected in series or in parallel, a battery management system (BMS) is required. For example, a DC link capacitor can be connected downstream of the energy storage device. This serves to further smooth the three-phase current of the converter, keep the high-frequency vibration away from the energy storage device, and block the switching overshoot. The reason is that the inductance of the energy storage device continues to drive the current. The purpose of this procedure is to load the energy storage device with direct current. The reason is that in this case, it is assumed that this contributes to the resistance of the battery cell and reduces the loss.

[0004] For example, in a conventional electric vehicle, a converter that supplies energy to the motor and returns energy to the battery during energy regeneration (recovery) during braking may be arranged on the DC bus. For example, a charging device operable with an alternating current voltage (AC) or a direct current voltage (DC) may be connected to this bus.

[0005] These converters typically take the form of a two-point converter, or a B6 bridge in the case of a three-phase design, and especially in the field of solar power generation, they take the form of a three-point converter.

[0006] As an alternative to bridge circuits, so-called multilevel converter systems are known.

[0007] Batteries, such as rechargeable batteries, can be used as energy storage devices or energy sources. These energy storage devices are not connected to each other by wiring, but are combined as individual submodules. This structure is required for each phase. Therefore, energy storage devices can be divided, for example, between these phases and permanently connected in series or parallel.

[0008] For example, lithium-ion batteries are commonly used in electric vehicles.

[0009] Current transistors are primarily manufactured as NPN semiconductors. That is, a region is negatively doped, then positively doped, and then negatively doped again. Semiconductors with these three connections (drain, gate, and source) are produced in factories.

[0010] First, a silicon wafer is used to create numerous individual semiconductors by employing different processing steps. Next, these are functionally tested and cut into individual discrete components. Each semiconductor element is then attached to a housing for external connectivity, unless it is used directly as a so-called "bare die."

[0011] This procedure is particularly advantageous in current semiconductors (for example, silicon MOSFETs, i.e., silicon metal-oxide-semiconductor field-effect transistors) because the gates of power MOSFETs used in multilevel applications are typically planar in structure.

[0012] Due to their superior switching and on-state characteristics, power MOSFETs are typically configured as so-called "superjunction MOSFETs." [Overview of the Initiative] [Problems that the invention aims to solve]

[0013] However, the power semiconductor market has been dramatically transformed over the past few years by so-called "wide bandgap devices" (WBG).

[0014] Of particular note are silicon carbide (SiC) and gallium nitride (GaN).

[0015] In the low-voltage range, for example below 650V, GaN is expected to become the dominant technology based on current trends. This is because GaN is more cost-effective and offers significantly higher output than silicon components. However, these new switches are currently configured as lateral elements rather than planar elements.

[0016] Conventional multilevel converter systems remain relatively expensive. This is due, for example, to the relatively large number of transistors they contain. Furthermore, transistors require a relatively large amount of space, resulting in relatively large chips, which negatively impacts manufacturing costs.

[0017] Therefore, the object of the present invention is to provide a multilevel converter system that reduces manufacturing costs, a method for manufacturing a multilevel converter system, and a wafer for manufacturing a multilevel converter system. [Means for solving the problem]

[0018] This objective is achieved by the subject matter and method of the independent claim.

[0019] According to the present invention, preferably, a modular multilevel converter system comprises a plurality of energy storage modules and transistors.

[0020] A multilevel converter system refers to a kind of arrangement or wiring of a plurality of energy storage modules and / or transistors.

[0021] Each energy storage module can have at least one or exactly one battery, for example, a rechargeable battery.

[0022] For example, the transistor serves as a switch that can be used to select a current and / or voltage path. As a result, the energy storage module can be incorporated into or excluded from a desired configuration, for example.

[0023] At least or exactly two, three, four, five, six, seven, eight, nine or more than ten transistors are assigned to each energy storage module.

[0024] The transistor can be designed for a voltage of less than 500V, less than 400V, less than 300V, less than 200V, less than 100V, less than 50V, less than 40V, less than 30V, less than 20V or less than 10V, for example. The transistor can preferably be designed for a voltage between 2V and 8V, for example 3V, 4V, 5V, 6V or 7V.

[0025] For example, the transistor can be a lateral type, planar type or trench type transistor. However, in principle, any type of structure is conceivable.

[0026] Preferably, the transistor is designed as a MOSFET, or the transistor comprises a MOSFET.

[0027] The MOSFET can be switched at high frequencies.

[0028] At least one transistor may have a switching frequency of at least 1 Hz, for example.

[0029] As the semiconductor material, for example, silicon, gallium nitride, gallium arsenide and / or silicon carbide may be provided.

[0030] Each energy storage module can be connected in parallel to an adjacent energy storage module and / or can be connected in series to an adjacent energy storage module and / or can be bridge-connected. Each energy storage module can preferably be connected in series to an adjacent energy storage module. The possibility of parallel connection is advantageous but not necessary.

[0031] Adjacent energy storage modules are preferably connected to each other via two current paths and / or voltage paths. A transistor can be assigned to each path.

[0032] For example, three transistors are provided between two adjacent energy storage modules. As a result, the energy storage modules can be connected in parallel or in series, for example.

[0033] Each energy storage module has at least one energy storage cell.

[0034] For example, an energy storage module can have exactly one energy storage cell. However, preferably each energy storage module has a plurality of energy storage cells, for example at least 10, 20, 30, 40, 50, 60, 70, 80, 90 or 100 energy storage cells. For example, at least 100 energy storage cells, for example 140 energy storage cells, may be provided in the energy storage module.

[0035] The energy storage cells of an energy storage module can preferably be connected in parallel to one another. Preferably, the energy storage cells of the energy storage module are selected to be supplied with the same charge as the charge supplied to the grid, for example, 230V.

[0036] Multilevel converter systems are far more versatile than bridge circuits. This allows for the creation of almost any configuration. For example, energy storage modules can be interconnected in any way, for instance, in parallel or series. Individual energy storage modules can be incorporated into or excluded from a desired configuration.

[0037] At least two adjacent NPN transistors share an N-type region. Alternatively or additionally, at least two adjacent PNP transistors share a P-type region.

[0038] Therefore, the N-type or P-type regions of adjacent transistors are coupled together.

[0039] As a result, instead of two adjacent NPN transistors, an NNPPN transistor is effectively formed, or instead of two adjacent PNP transistors, a PNPNP transistor is effectively formed.

[0040] These transistors also require protection independently of the multilevel converter system.

[0041] The preservation of either the N-type or P-type region results in an advantage in terms of the amount of semiconductor material required, particularly for adjacent switches frequently found in multilevel converter systems. This advantage is directly reflected in the price, on the one hand, and also positively impacts costs by reducing chip area.

[0042] It is remarkable that the saving and / or sharing of adjacent zones can be achieved with multilevel converter systems, leading to significant cost reductions.

[0043] Further developments of the present invention can also be understood from the dependent claims, the specification, and the accompanying drawings.

[0044] According to one embodiment, at least three NPN transistors are provided, and adjacent NPN transistors each share an N-type region.

[0045] Alternatively or additionally, at least three PNP transistors are provided, and adjacent PNP transistors each share a P-type region.

[0046] In principle, any number of transistors can be provided, and adjacent transistors share the same region.

[0047] For example, three NPN transistors can be combined to form an NPNPPN transistor, or three PNP transistors can be combined to form a PNPNPNP transistor.

[0048] According to another embodiment, adjacent NPN transistors and / or PNP transistors are arranged in parallel.

[0049] Preferably, the transistors are arranged in a straight line, i.e., in rows, and not enclosed in corners, for example.

[0050] According to other embodiments, adjacent NPN transistors and / or PPN transistors are not arranged linearly with respect to each other.

[0051] For example, adjacent transistors may be arranged at right angles to each other or at an angle.

[0052] Preferably, adjacent transistors surround each other at an angle greater than 0°.

[0053] Intermediate transistors can preferably extend in different spatial directions (for example, along the X, Y, or Z axes).

[0054] According to other embodiments, the multilevel converter system is configured as PECIN, MMSPC, M2B, or BM3.

[0055] In this case, topology PECIN stands for "Parallel Enhanced Commutation Integrated Nested," MMSPC stands for "Modular Multilevel Series Parallel Converter," and M2B stands for "Modular Multilevel Battery."

[0056] BM3 (also known as Marx topology) stands for "Battery Modular Multilevel Management".

[0057] In principle, other topologies are also possible, such as half-bridge, pre-half-bridge, cross-switched, cascaded cross-switched, CEBS, full-bridge, or ECIN.

[0058] The topologies described above are, for example, potential candidates for use in electric vehicles.

[0059] The present invention relates to a method for manufacturing a multilevel transducer system according to the present invention, comprising forming N-type conductive layers and P-type conductive layers on a wafer such that N-type conductive layers and P-type conductive layers are always arranged alternately, and / or forming P-type conductive layers and N-type conductive layers on a wafer such that P-type conductive layers and N-type conductive layers are always arranged alternately.

[0060] In this way, at least two adjacent NPN transistors share an N-type region, or two adjacent PNP transistors share a P-type region.

[0061] According to one embodiment, a wafer having an N-type conductive layer is covered with a non-conductive first protective layer.

[0062] For example, a single-crystal silicon wafer or a single-crystal gallium wafer can be used as a starting point.

[0063] The first protective layer and / or other protective layers may contain or consist of, for example, silicon dioxide and / or gallium oxide.

[0064] A first window is inserted into the first protective layer to form a P-type conductive layer.

[0065] The first window is covered with a second non-conductive protective layer.

[0066] A second window is inserted into the second protective layer to form an N-type conductive layer.

[0067] The second window is covered with a non-conductive third protective layer.

[0068] A third window is inserted into the third protective layer to form a P-type conductive layer.

[0069] The third window is covered with a non-conductive fourth protective layer.

[0070] A fourth window is inserted into the fourth protective layer to form an N-type conductive layer.

[0071] In this way, for example, an NPNPN transistor can be manufactured.

[0072] This method can, in principle, be continued as desired.

[0073] Preferably, another window is eventually inserted and a metal connector is attached, for example, by vapor deposition.

[0074] The corresponding manufacturing method is also called planing technology. Windows can be inserted, for example, by so-called masking technology, or preferably by etching.

[0075] According to another embodiment, a wafer having a P-type conductive layer is covered with a non-conductive first protective layer.

[0076] For example, a single-crystal silicon wafer or a single-crystal gallium wafer can be used as a starting point.

[0077] The first protective layer and / or other protective layers may contain, or be composed of, for example, silicon dioxide and / or gallium oxide.

[0078] A first window is inserted into the first protective layer to form an N-type conductive layer.

[0079] The first window is covered with a second non-conductive protective layer.

[0080] A second window is inserted into the second protective layer to form a P-type conductive layer.

[0081] The second window is covered with a non-conductive third protective layer.

[0082] A third window is inserted into the third protective layer to form an N-type conductive layer.

[0083] The third window is covered with a non-conductive fourth protective layer.

[0084] A fourth window is inserted into the fourth protective layer to form a P-type conductive layer.

[0085] In this way, for example, a PNPNP transistor can be manufactured.

[0086] This method can, in principle, be continued as desired.

[0087] Preferably, another window is eventually inserted and a metal connector is attached, for example, by vapor deposition.

[0088] The corresponding manufacturing method is also called planing technology. Windows can be inserted, for example, by so-called masking technology, or preferably by etching.

[0089] Furthermore, the present invention relates to a wafer for manufacturing a multilevel converter system, wherein N-type conductive layers and P-type conductive layers are always arranged alternately.

[0090] For example, the N-type conductive layer and the P-type conductive layer may be arranged to obtain an NNPPN structure.

[0091] Finally, the present invention relates to a wafer for manufacturing a multilevel transducer system, wherein P-type conductive layers and N-type conductive layers are always arranged alternately.

[0092] For example, the P-type conductive layer and the N-type conductive layer may be arranged so as to obtain a PNPNP structure.

[0093] All embodiments and components of the apparatus described herein are preferably designed to be manufactured according to one or more methods described herein. Furthermore, all embodiments of the apparatus described herein and all embodiments of the methods described herein can be combined with each other, preferably in a manner separate from the specific configuration referred to. [Brief explanation of the drawing]

[0094] The present invention will be explained by the following examples with reference to the drawings.

[0095] [Figure 1]Figure 1 shows an embodiment of a conventional multilevel converter system. [Figure 2] Figure 2 shows schematic diagrams of three NPN transistors using conventional technology. [Figure 3] Figure 3 shows a schematic diagram of an NPNPPN transistor. [Figure 4] Figure 4 shows a schematic diagram of PECIN using conventional technology. [Figure 5] Figure 5 shows a schematic diagram of PECIN according to the present invention. [Modes for carrying out the invention]

[0096] First, please note that the illustrated embodiments are illustrative only. Therefore, individual features can be realized not only in the illustrated combinations, but also individually or in other technically useful combinations. For example, features of one embodiment can be combined with features of another embodiment in any way. The illustrated energy storage modules, paths, transistor configurations, and / or numbers are illustrative and essentially arbitrary.

[0097] If a reference symbol in a figure is not explained in the directly relevant section of the specification, refer to the corresponding preceding or succeeding note in the specification. Therefore, the same reference symbol is used for identical or similar components in a figure and is not explained again.

[0098] Figure 1 shows a multilevel converter system having energy storage modules 10, 12, 14, and 16.

[0099] The adjacent energy storage modules 10, 12, 14, and 16 are each connected via multiple paths.

[0100] Each path is provided with a switch in the form of a transistor 18.

[0101] The adjacent energy storage modules 10, 12, 14, and 16 can be connected in series or in parallel. Individual energy storage modules 10, 12, 14, and 16 can also be bridged, for example, by closing the upper switch 18, thereby excluding them from the configuration.

[0102] As shown in Figures 2 and 3, according to the present invention, substantially three NPN transistors are combined to form an NPNNPPN transistor.

[0103] Neighboring NPN transistors each share an N-type region.

[0104] Therefore, N-type regions can be combined here. This slightly increases the waste rate, but enables miniaturization and cost reduction of semiconductors. This allows, for example, insertion into a housing.

[0105] This can be achieved in all topologies. However, the effect is greatest in topologies with a large number of switches, as parallel connections are also possible.

[0106] NPNPNPN transistors are preferable to be inserted into a housing as a whole, which also reduces packaging costs.

[0107] Figures 4 and 5 show the joining of adjacent regions using an example of the PECIN topology.

[0108] The two horizontally positioned NPN transistors at the top share an N-type region and form an NNPPN transistor.

[0109] Similarly, the two horizontally positioned NPN transistors at the bottom share an N-type region and form an NNPPN transistor.

[0110] The N-type region outside the horizontally oriented NPNPN transistor ultimately forms the N-type region of the two diagonally oriented NPN transistors. In this case, the dashed lines each represent an NPN connection.

[0111] Between the two horizontally arranged NPNPN transistors, an N-type transistor extends from the left end of the upper NPNPN transistor to the right end of the lower NPNPN transistor, sharing the outer N-type region. Another NPN transistor extends from the right end of the upper NPNPN transistor to the left end of the lower NPNPN transistor, also sharing the outer N-type region.

[0112] Similarly, it is also possible to provide PNP transistors in which adjacent PNP transistors share a P-type region.

[0113] Cost can be reduced by having adjacent transistors share the same region. [Explanation of symbols]

[0114] 10 Energy storage modules 12 Energy Storage Modules 14 Energy storage modules 16 Energy storage modules 18 transistors, switches

Claims

1. The system comprises a plurality of energy storage modules (10, 12, 14, 16) and a transistor (18), wherein each energy storage module (10, 12, 14, 16) can be connected in parallel to an adjacent energy storage module (10, 12, 14, 16), connected in series to an adjacent energy storage module (10, 12, 14, 16), and / or bridged to an adjacent energy storage module (10, 12, 14, 16), and each energy storage module (10, 12, 14, 16) has at least one energy storage cell. A multilevel converter system in which at least two adjacent NPN transistors (18) share an N-type region, and / or at least two adjacent PNP transistors (18) share a P-type region.

2. At least three NPN transistors (18) are provided, and adjacent NPN transistors (18) each share an N-type region, and / or The multilevel converter system according to claim 1, characterized in that at least three PNP transistors (18) are provided, and adjacent PNP transistors (18) each share a P-type region.

3. The multilevel converter system according to claim 1, characterized in that adjacent NPN transistors (18) and / or PNP transistors (18) are arranged side by side.

4. The multilevel converter system according to claim 1, characterized in that adjacent NPN transistors (18) and / or PNP transistors (18) are not arranged linearly with respect to each other.

5. The multilevel converter system according to claim 1, wherein the multilevel converter system is configured as PECIN, MMSPC, M2B, or BM3.

6. A method for manufacturing the multilevel converter system described in Claim 1, The N-type conductive layer and the P-type conductive layer are formed on a wafer such that the N-type conductive layer and the P-type conductive layer are always arranged alternately, and / or A method for forming the P-type conductive layer and the N-type conductive layer on a wafer such that the P-type conductive layer and the N-type conductive layer are always arranged alternately.

7. A wafer having an N-type conductive layer is covered with a non-conductive first protective layer. A first window is inserted into the first protective layer in order to form a P-type conductive layer. The first window is covered with a non-conductive second protective layer. A second window is inserted into the second protective layer in order to form an N-type conductive layer. The second window is covered with a non-conductive third protective layer. A third window is inserted into the third protective layer in order to form a P-type conductive layer. The third window is covered with a non-conductive fourth protective layer. The method according to claim 6, characterized in that a fourth window is inserted into the fourth protective layer in order to form an N-type conductive layer.

8. A wafer having a P-type conductive layer is covered with a non-conductive first protective layer. To form an N-type conductive layer, a first window is inserted into the first protective layer. The first window is covered with a non-conductive second protective layer. A second window is inserted into the second protective layer in order to form a P-type conductive layer. The second window is covered with a non-conductive third protective layer. A third window is inserted into the third protective layer in order to form an N-type conductive layer. The third window is covered with a non-conductive fourth protective layer. The method according to claim 6, characterized in that a fourth window is inserted into the fourth protective layer in order to form a P-type conductive layer.

9. A wafer for manufacturing a multilevel converter system according to any one of claims 1 to 5, A wafer in which N-type conductive layers and P-type conductive layers are always arranged alternately.

10. A wafer for manufacturing a multilevel converter system according to any one of claims 1 to 5, A wafer in which P-type conductive layers and N-type conductive layers are always arranged alternately.

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