Metalworking on metal silicides for CMOS devices

Abstract

A method for forming an electrical contact within a semiconductor structure comprises performing a cavity forming process on a semiconductor structure having a p-type semiconductor region for a p-type metal oxide semiconductor (p-MOS) device, the cavity forming process comprising forming a first cavity on the exposed surface of the p-type semiconductor region, performing a first selective deposition process to selectively form a first cavity contact within the first cavity, and performing a metallization process on the formed first cavity contact to remove oxide at the interface between the first cavity and the first cavity contact.

Description

[Technical Field]

[0001]

[0001] The embodiments described herein generally relate to semiconductor device manufacturing, and more specifically to systems and methods for forming electrical contacts within semiconductor structures. [Background technology]

[0002] Description of related technologies

[0002] Multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), such as complementary metal-oxide-semiconductor (CMOS) devices, present manufacturability challenges due to their three-dimensional (3D) design and small size. In advanced CMOS devices, metal silicides (e.g., molybdenum silicide (MoSi2), ruthenium silicide (RuxSiy)) are often selectively formed at the bottom of trench contacts to reduce contact resistance. However, the interface of metal silicides at the bottom of trench contacts in p-type MOS (p-MOS) regions often suffers from poor structural and electrical quality.

[0003]

[0003] Therefore, there is a need for methods and systems that can improve the structural and electrical quality of the metal silicide interface at the bottom of the trench contact. [Overview of the Initiative]

[0004]

[0004] Embodiments of the present disclosure provide a method for forming electrical contacts within a semiconductor structure. The method involves performing a cavity forming process on a semiconductor structure having a p-type semiconductor region for a p-type metal oxide semiconductor (p-MOS) device, wherein the cavity forming process includes: performing a cavity forming process which includes forming a first cavity on an exposed surface of the p-type semiconductor region; performing a first selective deposition process which includes selectively forming a first cavity contact within the first cavity; and performing a metallization process on the formed first cavity contact which includes removing oxide at the interface between the first cavity contact and the first cavity.

[0005]

[0005] Embodiments of the present disclosure also provide a method for forming electrical contacts within a semiconductor structure. The method involves performing a pre-cleaning process on a semiconductor structure having an n-type semiconductor region for an n-type metal oxide semiconductor (n-MOS) device, a p-type semiconductor region for a p-type metal oxide semiconductor (p-MOS) device, and a dielectric layer having a first trench above the p-type semiconductor region and a second trench above the p-type semiconductor region; performing a cavity forming process to form a second cavity on the exposed surface of the n-type semiconductor region in the first trench and a first cavity on the exposed surface of the p-type semiconductor region in the second trench; and performing a first selective deposition process to selectively form a first cavity contact within the first cavity. The process includes: performing a metallization process on the formed first cavity contact to remove oxides at the interface between the first cavity and the first cavity contact; performing a second selective deposition process to selectively form a second cavity contact within the second cavity; performing a blanket deposition process to form a barrier layer on the exposed inner surfaces of the first and second trenches and on the exposed surfaces of the dielectric layer; and performing a metal filling process to form a first contact plug in the first trench and a second contact plug in the second trench.

[0006]

[0006] Embodiments of the present disclosure further provide a processing system. The processing system includes a first processing chamber, a second processing chamber, a third processing chamber, and a system controller configured to cause a cavity forming process to be performed in the first processing chamber, on a semiconductor structure having an n-type semiconductor region for an n-type metal oxide semiconductor (n-MOS) device and a p-type semiconductor region for a p-type metal oxide semiconductor (p-MOS) device, including forming a second cavity on the exposed surface of the n-type semiconductor region and a first cavity on the exposed surface of the p-semiconductor region; causing a first selective deposition process to be performed in the second processing chamber to selectively form a first cavity contact within the first cavity; and causing a metallizing process to be performed in the third processing chamber on the formed first cavity contact to remove oxide at the interface between the first cavity contact and the first cavity, wherein the metallizing process includes a capacitively coupled plasma (CCP) chemical etching process with ion collisions using a processing gas containing hydrogen (H2) and argon (Ar).

[0007]

[0007] To better understand the features of the Disclosure described above, a more detailed description of the Disclosure, which has been briefly summarized above, can be obtained by referring to the embodiments. Some embodiments are shown in the accompanying drawings. However, it should be noted that the accompanying drawings merely illustrate typical embodiments of the Disclosure and should not be considered to limit the scope of the Disclosure, as the Disclosure may also permit other equally valid embodiments. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure. [Figure 2] The following is a process flow diagram of a method for forming a contact layer within a semiconductor structure according to one or more embodiments of the present disclosure. [Figure 3A-3F]Figure 2 shows a cross-sectional view of a portion of the semiconductor structure corresponding to various states of the method. [Modes for carrying out the invention]

[0009]

[0011] For ease of understanding, the same reference numerals are used to indicate identical elements common to the figures where possible. It is assumed that elements and features of one embodiment may be usefully incorporated into other embodiments without further description.

[0010]

[0012] Embodiments described herein provide a method and system for forming electrical contacts containing metal silicides (e.g., molybdenum silicide (MoSi2), ruthenium silicide (RuxSiy)) on selected portions of a structure used to form a CMOS device (e.g., on the exposed surface of a silicon-germanium layer), and for further improving the structural and electrical quality of the metal silicides at the interface. The method and system comprises a region containing silicon, a region containing silicon-germanium, a dielectric layer formed thereon, and metal silicide contacts (e.g., molybdenum silicide (MoSi2), ruthenium silicide (RuxSiy)) selectively formed on the exposed surface of the silicon-germanium material within an opening or feature (e.g., a contact trench) in the dielectric layer. The process described herein is configured to form a cavity within the opening or feature (e.g., a contact trench), the surface of which is optimized for selective deposition of metal silicides, and oxides are removed at the interface between the metal silicide contact and the cavity.

[0011]

[0013] Figure 1 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 having transfer robots 112, 114 respectively, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, substrates in the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the substrates to the ambient environment outside the processing system 100 (e.g., the atmospheric environment that may be present in the factory). For example, substrates can be processed in various chambers and transferred between various chambers during various processes performed on the substrates in the processing system 100, without disrupting the low-pressure or vacuum environment, while being maintained in a low-pressure (e.g., about 300 Torr or less) or vacuum environment. Therefore, the processing system 100 can provide an integrated solution for processing a portion of the substrate.

[0012]

[0014] Examples of processing systems that can be appropriately modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems, commercially available from Applied Materials, Inc. in Santa Clara, California, or other suitable processing systems. It is assumed that other processing systems (including those from other manufacturers) can be adapted to benefit from the embodiments described herein.

[0013]

[0015] In the illustrated example in Figure 1, the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate the transfer of substrates. The docking station 132 is adapted to receive one or more forward-opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 located at one end of the factory interface robot 134, adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0014]

[0016] The load lock chambers 104 and 106 each have ports 140 and 142 connected to the factory interface 102, and ports 144 and 146 connected to the transfer chamber 108. The transfer chamber 108 further has ports 148 and 150 connected to the holding chambers 116 and 118, and ports 152 and 154 connected to the processing chambers 120 and 122. Similarly, the transfer chamber 110 has ports 156 and 158 connected to the holding chambers 116 and 118, and ports 160, 162, 164, and 166 connected to the processing chambers 124, 126, 128, and 130. Ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, and 166 may be slit valve openings having slit valves for sealing the spaces between chambers to prevent gas from passing between them, for example, when substrates are passed through by transfer robots 112 and 114. Generally, any port is open for the transfer of substrates. Otherwise, the port is closed.

[0015]

[0017] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 can be fluidically connected to a gas and pressure control system (not shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), a gas source, various valves, and fluidly connected conduits to the various chambers. During operation, the factory interface robot 134 transfers the substrate from the FOUP 136 to the load lock chamber 104 or 106 via port 140 or 142. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, pumping down the load lock chamber 104 or 106 facilitates the passage of the substrate between, for example, the atmospheric environment of the factory interface 102 and the low-pressure or vacuum environment of the transfer chamber 108.

[0016]

[0018] With the substrate in the load lock chamber 104 or 106 pumped down, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 through port 144 or 146 into the transfer chamber 108. The transfer robot 112 can then transfer the substrate to either the processing chambers 120 or 122 via their respective processing ports 152 or 154, and / or to the holding chambers 116 or 118 via their respective ports 148 or 150 to hold awaiting further transfer. Similarly, the transfer robot 114 can access the substrate in the holding chamber 116 or 118 via port 156 or 158, and transfer the substrate to either the processing chambers 124, 126, 128, or 130 via their respective ports 160, 162, 164, or 166, and / or to the holding chambers 116 or 118 via their respective ports 156 or 158 to hold awaiting further transfer. The transfer and holding of substrates within and between various chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0017]

[0019] Processing chambers 120, 122, 124, 126, 128, and 130 can be any suitable chamber for processing the substrate. In some embodiments, processing chamber 120 can perform an etching process, processing chamber 122 can perform a cleaning process, processing chamber 124 can perform a selective removal process, and processing chambers 126, 128, and 130 can perform their respective epitaxial growth processes. Processing chamber 120 is available from Selectra, which is available from Applied Materials in Santa Clara, California. TM It may also be an etching chamber. The processing chamber 122 is made of SiCoNi, which is available from Applied Materials in Santa Clara, California. TM A pre-wash chamber may also be used. Processing chambers 126, 128, or 130 are available from Centura, which is available from Applied Materials in Santa Clara, California. TM Epi chamber is also acceptable.

[0018]

[0020] The system controller 168 is coupled to the processing system 100 to control the processing system 100 or its components. For example, the system controller 168 can control the operation of the processing system 100 by using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130 of the processing system 100, or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130. During operation, the system controller 168 enables data collection and feedback from each chamber to adjust the performance of the processing system 100.

[0019]

[0021] The system controller 168 generally includes a central processing unit (CPU) 170, a memory 172, and a support circuit 174. The CPU 170 can be any form of general-purpose processor that can be used in an industrial setting. The memory 172, or non-transitory computer-readable medium, is accessible by the CPU 170 and can be one or more of the memories such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or other forms of digital storage, local or remote. The support circuit 174 is connected to the CPU 170 and can include a cache, a clock circuit, an input / output subsystem, a power supply, etc. The various methods disclosed herein can generally be implemented by executing computer instruction codes by the CPU 170 stored in the memory 172 (or the memory of a specific process chamber), for example, as software routines, under the control of the CPU 170. When the computer instruction codes are executed by the CPU 170, the CPU 170 controls the chamber to execute a process according to various methods.

[0020]

[0022] Other processing systems can be configured differently. For example, more or fewer processing chambers can be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110, and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) can be implemented as the transfer device within the processing system.

[0021]

[0023] FIG. 2 shows a process flow diagram of a method 200 for forming a contact layer on a semiconductor structure 300 according to some embodiments of the present disclosure. FIGS. 3A, 3B, 3C, 3D, 3E, and 3F are cross-sectional views of a part of the semiconductor structure 300 corresponding to various states of the method 200. FIGS. 3A, 3B, 3C, 3D, 3E, and 3F show only partial schematic views of the semiconductor structure 300, and it should be understood that the semiconductor structure 300 may include any number of transistor sections and additional materials having aspects as shown in the figures. Also, although the method shown in FIG. 2 is described in order, other process sequences including one or more steps that are omitted and / or added and / or rearranged in a different desired order are within the scope of the embodiments of the disclosure provided herein.

[0022]

[0024] Referring to FIGS. 3A, 3B, 3C, 3D, 3E, and 3F, the semiconductor structure 300 may include an n-type MOS device 302 and a p-type MOS device 304 formed on a substrate (not shown).

[0023]

[0025] As used herein, the term "substrate" refers to a layer of material that functions as a base for subsequent processing operations and includes a surface to be cleaned. The substrate can be a silicon-based material or any suitable insulating or conductive material as needed. The substrate can include materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0024]

[0026] As shown in FIG. 3A, a part of the n-type MOS device 302 of a plurality of n-type transistor devices formed on a substrate includes an n-type semiconductor region 306 formed of a first material such as silicon (Si). A part of the p-type MOS device 304 of a plurality of p-type transistor devices formed on the substrate includes a p-type semiconductor region 308 formed of a second material such as silicon germanium (SiGe). The first material and the second material include materials having different compositions such that the second material can be selectively etched with respect to the first material (that is, the etching rate of the second material is faster than the etching rate of the first material). The etching selectivity of the second material (that is, the ratio of the etching rate of the second material to the etching rate of the first material) is between about 10:1 and 500:1. Other exemplary combinations of the first material and the second material include silicon (Si) / silicon germanium (SiGe), germanium (Ge) / silicon germanium (SiGe), or silicon (Si) / germanium tin (GeSn), respectively.

[0025]

[0027] The n-type semiconductor region 306 may be doped with an n-type dopant such as phosphorus (P) or antimony (Sb) according to the desired conductive characteristics of the n-type MOS device 302, and about 10 20 cm -3 and 5×10 21 cm -3 The concentration is between. The p-type semiconductor region 308 may be doped with a p-type dopant such as boron (B) or gallium (Ga) at a concentration of about 10 20 cm -3 to about 5×10 21 cm -3 The concentration of.

[0026]

[0028] The semiconductor structure 300 further includes a dielectric layer 310 having a first trench 312 formed on the n-type semiconductor region 306 and a second trench 314 formed on the p-type semiconductor region 308. The dielectric layer 310 may be formed of a dielectric material such as silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0027]

[0029] The n-type semiconductor region 306 and the p-type semiconductor region 308 may be formed using any suitable deposition technique such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the first and second trenches 312 and 314 are formed by patterning techniques such as lithography and etching processes.

[0028]

[0030] Method 200 begins with a pre-cleaning process of block 210. The pre-cleaning process can be performed in a processing chamber, such as the processing chamber 122 shown in Figure 1. The pre-cleaning process of block 210 can be performed in a multi-chamber processing system, such as the multi-chamber processing system 100 shown in Figure 1, without disrupting the vacuum environment.

[0029]

[0031] The pre-cleaning process is configured to remove contaminants such as carbon-containing contaminants (e.g., patterning residue) or oxide-containing contaminants (e.g., native oxide layer) formed on the exposed surface of the n-type semiconductor region 306 in the first trench 312 and the exposed surface of the p-type semiconductor region 308 in the second trench 314.

[0030]

[0032] The pre-cleaning process for removing carbon-containing contaminants may include an anisotropic remote plasma-assisted dry etching process, such as a reactive ion etching (RIE) process, which uses a plasma formed from a gas containing hydrogen (H), argon (Ar), helium (He), or a combination thereof. The plasma ejecta directionally impact and remove the dielectric layers remaining in the first trench 312 and the second trench 314.

[0031]

[0033] The pre-cleaning process for removing oxide-containing contaminants is an isotropic plasma etching process such as a dry chemical etching process using hydrofluoric acid (HF) and ammonia (NH3), or a SiCoNi process using a plasma formed from a gas containing ammonia (NH3) and nitrogen trifluoride (NF3). TMThis includes a dry etching process. The dry etching process is selective to oxide layers and therefore does not readily etch silicon, germanium, or nitride layers, regardless of whether the layers are amorphous, crystalline, or polycrystalline. The selectivity of the dry etching process for silicon or germanium over oxides is at least about 3:1, usually 5:1 or higher, and sometimes 10:1. The dry etching process also has high selectivity for oxides over nitrides. The selectivity of the dry etching process over nitrides is at least about 3:1, usually 5:1 or higher, and sometimes 10:1.

[0032]

[0034] In block 220, as shown in Figure 3B, a cavity forming process is performed to form an n-MOS cavity 306C on the exposed surface of the n-type semiconductor region 306 in the first trench 312, and a p-MOS cavity 308C on the exposed surface of the p-type semiconductor region 308 in the second trench 314. The cavity forming process can be carried out in an etching chamber (such as the processing chamber 120 shown in Figure 1). The cavity forming process in block 220 can be carried out in a multi-chamber processing system, such as the multi-chamber processing system 100 shown in Figure 1, without disrupting the vacuum environment.

[0033]

[0035] The cavity forming process for block 220 includes an etching process using an etching gas that includes a halogen-containing gas such as chlorine (Cl2), hydrogen chloride (HCl), or hydrogen fluoride (HF), and a carrier gas such as argon (Ar) or helium (He). The etching process using chlorine (Cl2) and hydrogen (H2) is sensitive to the amount of germanium (Ge), and therefore this cavity forming process exhibits different reactions to the n-type semiconductor region 306 (e.g., silicon (Si)) and the p-type semiconductor region 308 (e.g., SiGe). This difference can lead to a difference in the deposition rate of metallic material on the exposed surface on the n-MOS cavity 306C (e.g., silicon (Si)) and the exposed surface on the p-MOS cavity 308C (e.g., silicon germanium (SiGe)) in the subsequent selective deposition process.

[0034]

[0036] The n-MOS and p-MOS cavities 306C and 308C have a V-shape, U-shape, or any other shape with a width between approximately 5 nm and 15 nm and a depth between approximately 5 nm and 15 nm, thereby increasing the contact area between the p-type semiconductor region 308 and the contact plug formed in the second trench 314, reducing parasitic resistance and improving device performance.

[0035]

[0037] The cavity forming process is used to refresh the pure, uncontaminated exposed surfaces of n-MOS cavities 306C and 308C (e.g., surface etching of approximately a few nanometers that could potentially be contaminated with residual oxygen, nitrogen, or carbon) so that a contact (e.g., metal silicide) can be selectively formed within the p-MOS cavity 308C during the subsequent deposition process. The cavity forming process is also used to optimize device stress.

[0036]

[0038] In block 230, as shown in Figure 3C, a first selective deposition process is performed to selectively form a p-MOS cavity contact 316 within the p-MOS cavity 308C. The first selective deposition process may be performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1. The first selective deposition process in block 230 can be performed in a multi-chamber processing system such as the multi-chamber processing system 100 shown in Figure 1 without disrupting the vacuum environment.

[0037]

[0039] The p-MOS cavity contact 316 may be formed from a first metallic material such as molybdenum (Mo), ruthenium (Ru), or a silicide thereof. The p-MOS cavity contact 316 connects to the p-type semiconductor region 308 and to a contact plug formed in the second trench 314, providing an electrical connection between them.

[0038]

[0040] In some embodiments, the first selective deposition process includes deposition processes such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). The selectivity in the first selective deposition process may arise from differences in the reaction between the deposition precursor of a first metallic material (e.g., molybdenum (Mo), ruthenium (Ru)) and the exposed surfaces of the n-MOS cavity 306C (e.g., silicon (Si), passivated silicon (Si) surface) and the exposed surfaces of the p-MOS cavity 308C (e.g., silicon germanium (SiGe)). During the deposition process, the deposition precursor preferentially reacts with the exposed surface of the p-MOS cavity 308C (e.g., silicon germanium (SiGe)) and the exposed surface of the n-MOS cavity 306C (e.g., silicon (Si), passivated silicon (Si) surface). Therefore, the growth of the first metallic material can occur at a faster rate on the exposed surface of the p-MOS cavity 308C than on the exposed surface of the n-MOS cavity 306C.

[0039]

[0041] In some embodiments, the deposition gas used in the deposition process includes a molybdenum (Mo)-containing halide precursor or a metal source such as a ruthenium (Ru)-containing organometallic agent. The first selective deposition process may be carried out at a temperature between about 240°C and about 450°C and a pressure between 3 Torr and 300 Torr. During the deposition process, argon (Ar) gas is supplied at a flow rate between approximately 0 sccm and approximately 1000 sccm, and hydrogen (H2) gas can be supplied at a flow rate between approximately 500 sccm and approximately 15000 sccm, for example.

[0040]

[0042] The first selective deposition process cycle may be repeated as needed to obtain a desired thickness of the p-MOS cavity contact 316, for example, a thickness of about 5 to about 1000 times.

[0041]

[0043] In block 240, a metallizing process is performed to remove oxides at the interface between the p-MOS cavity contact 316 (e.g., molybdenum (Mo), ruthenium (Ru), or their silicides) and the p-MOS cavity 308C (e.g., SiGe:B). In some embodiments, the metallizing process removes oxides at the interface between the n-MOS cavity contact 318 (e.g., titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), lanthanum (La), yttrium (Y), hafnium (Hf), zirconium (Zr), or their silicides) and the n-MOS cavity 306C (e.g., Si:P).

[0042]

[0044] The metal processing process may include a capacitively coupled plasma (CCP) or inductively coupled plasma (ICP) chemical etching process with ion collisions using a processing gas containing hydrogen (H2) and argon (Ar). The processing chamber is the Preclean XT chamber available from Applied Materials in Santa Clara, California, or processing chamber 122 shown in Figure 1. The metal processing process of block 240 can be carried out without disrupting the vacuum environment in a multi-chamber processing system, such as the multi-chamber processing system 100 shown in Figure 1. The metal processing process may be carried out for a period of about 90 seconds under a pressure of about 2 mTorr, with an ICP power of about 900 W and a bias power between 0 W and about 200 W. During the metal processing process, the argon (Ar) gas may be supplied at a flow rate of about 20 sccm, and the hydrogen (H2) gas at a flow rate of about 20 sccm.

[0043]

[0045] The inventors observed that metallization of a molybdenum silicide (MoSix) layer formed on a cavity within a SiGe:B region improves the structural quality of the molybdenum silicide (MoSix) layer at the interface with the cavity (e.g., reduction of defects and impurities).

[0044]

[0046] Although not intended to be bound by theory, during metal processing, hydrogen radicals (H * The oxygen diffuses through the molybdenum silicide (MoSix) layer and reacts with the interface with the cavity (MoSix / SiGe:B interface), thus removing oxygen at the interface.

[0045]

[0047] In block 250, a second selective deposition process is optionally performed to selectively form n-MOS cavity contacts 318 within the n-MOS cavity 306C, as shown in Figure 3D. The second selective deposition process may be performed in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1. The second selective deposition process in block 250 can be performed in a multi-chamber processing system such as the multi-chamber processing system 100 shown in Figure 1 without disrupting the vacuum environment.

[0046]

[0048] The n-MOS cavity contact 318 may be formed from a second metallic material such as titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), lanthanum (La), yttrium (Y), hafnium (Hf), zirconium (Zr), or silicides thereof. The n-MOS cavity contact 318 interfaces with the n-type semiconductor region 306 and contact plug formed within the first trench 312, providing an electrical connection between them.

[0047]

[0049] In some embodiments, the second selective deposition process includes deposition processes such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). The selectivity in the second selective deposition process may arise from differences in the reaction between the deposition precursor of a second metallic material (e.g., titanium (Ti)) and the exposed surfaces of the n-MOS cavity 306C (e.g., silicon (Si)) and the p-MOS cavity contact 316 (e.g., molybdenum (Mo), ruthenium (Ru)). During the deposition process, the deposition precursor preferentially reacts with the exposed surfaces of the n-MOS cavity 306C (e.g., silicon (Si)) and the p-MOS cavity contact 316 (e.g., molybdenum (Mo), ruthenium (Ru)), and the growth of the second metallic material can occur at a faster rate on the exposed surfaces of the n-MOS cavity contact 306C than on the exposed surfaces of the p-MOS cavity contact 316 (e.g., molybdenum (Mo), ruthenium (Ru)).

[0048]

[0050] In some embodiments, the deposition gas used in the deposition process includes a metal source such as a precursor containing titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), or combinations thereof. The second selective deposition process may be carried out at a temperature between approximately 300°C and approximately 800°C, and a pressure between 1° Torr and 50° Torr.

[0049]

[0051] In block 260, as shown in Figure 3E, a blanket deposition process is performed to form a barrier metal layer 320 on the exposed inner surfaces of the first trench 312 and the second trench 314, as well as on the exposed surface of the dielectric layer 310. The barrier metal layer 320 protects the p-MOS cavity contacts 316 and n-MOS cavity contacts 318 and allows for the nucleation and growth of contact plugs in the first trench 312 and the second trench 314. The barrier metal layer 320 may be formed from a barrier metal material which is titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the n-MOS cavity contacts 318 are silicide layers formed from a portion of the barrier metal layer 320 using a spike annealing process. The blanket deposition process for block 260 can be performed in a multi-chamber processing system, such as the multi-chamber processing system 100 shown in Figure 1, without disrupting the vacuum environment.

[0050]

[0052] In block 270, a metal filling process is performed to form a first contact plug 322 in a first trench 312 and a second contact plug 324 in a second trench 314, as shown in Figure 3F. The first and second contact plugs 322 and 324 may be formed from contact plug metal materials such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The first and second contact plugs 322 and 324 may contain metals having a desired work function. The metal filling process in block 270 may include a chemical vapor deposition (CVD) process using a tungsten-containing precursor such as WF6 or a cobalt-containing precursor in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1.

[0051]

[0053] After the metal filling process, the semiconductor structure 300 can be planarized using a chemical mechanical planarization (CMP) process.

[0052]

[0054] Embodiments described herein provide a method and system for forming electrical contacts containing a metal silicide (e.g., molybdenum silicide (MoSi2)) in trenches on selected portions of a transistor structure, further improving the structural and electrical properties of the metal silicide at the interface with the trench. The contact trench structure includes a metal contact plug formed in a trench between adjacent device modules, and an electrical contact that interfaces between the contact plug and a silicon-based channel in the device module, reducing parasitic resistance. The electrical contact is formed by selective deposition, and oxides within the electrical contact are removed by a CCP chemical etching process with ion collisions using a processing gas containing hydrogen (H2) and argon (Ar). The electrical contact may be a metal silicide (e.g., molybdenum silicide MoSi2), ruthenium silicide (RuxSiy), or a metal silicide (e.g., TiSi2) selectively formed in a trench of a p-type MOS device (e.g., silicon-germanium), or a metal silicide (e.g., TiSi2) selectively formed in a trench of an n-type MOS device.

[0053]

[0055] While the above description applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure can be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is defined by the following claims.

Claims

1. A method for forming an electrical contact within a semiconductor structure, Performing a cavity forming process on a semiconductor structure having a p-type semiconductor region for a p-type metal oxide semiconductor (p-MOS) device, wherein the cavity forming process includes forming a first cavity on the exposed surface of the p-type semiconductor region, Performing a first selective deposition process to selectively form a first cavity contact within the first cavity, A metal treatment process is performed on the formed first cavity contact to remove oxides at the interface between the first cavity contact and the first cavity, Methods that include...

2. The aforementioned metal treatment process involves hydrogen (H ２ The method according to claim 1, comprising a capacitively coupled plasma (CCP) chemical etching process with ion collisions using a processing gas containing ) and argon (Ar).

3. The method according to claim 1, wherein the first cavity contact comprises a material selected from molybdenum (Mo) silicide and ruthenium (Ru) silicide.

4. The semiconductor structure further includes an n-type semiconductor region for an n-type metal oxide semiconductor (n-MOS) device, The cavity forming process further includes forming a second cavity on the exposed surface of the n-type semiconductor region. The method according to claim 1.

5. The aforementioned n-type semiconductor region contains silicon doped with an n-type dopant, The p-type semiconductor region includes silicon germanium doped with a p-type dopant. The cavity forming process described above is Chlorine (Cl ２ ) and hydrogen (H ２ This includes etching processes that use The method according to claim 4.

6. After the metal treatment process, a second selective deposition process is performed to selectively form a second cavity contact within the second cavity. The second cavity contact contains titanium silide (Ti), The method according to claim 4.

7. Prior to the cavity forming process, A dry etching process using hydrogen (H) plasma removes carbon-containing contaminants from the exposed surfaces of the n-type semiconductor region and the p-type semiconductor region, The dry etching process removes oxide-containing contaminants from the exposed surfaces of the n-type semiconductor region and the p-type semiconductor region. Performing a pre-washing process, including The method according to claim 4, further comprising:

8. The method according to claim 1, wherein the cavity forming process, the first selective deposition process, and the metal treatment process are performed without disrupting the vacuum environment.

9. A method for forming an electrical contact within a semiconductor structure, Performing a pre-cleaning process on a semiconductor structure having an n-type semiconductor region for an n-type metal oxide semiconductor (n-MOS) device, a p-type semiconductor region for a p-type metal oxide semiconductor (p-MOS) device, and a dielectric layer having a first trench on the n-type semiconductor region and a second trench on the p-type semiconductor region, A cavity forming process is performed to form a second cavity on the exposed surface of the n-type semiconductor region in the first trench, and a first cavity on the exposed surface of the p-type semiconductor region in the second trench. To selectively form a first cavity contact within the first cavity, a first selective deposition process is performed. A metal treatment process is performed on the formed first cavity contact to remove oxides at the interface between the first cavity contact and the first cavity, To selectively form a second cavity contact within the second cavity, a second selective deposition process is performed. A blanket deposition process is performed to form a barrier layer on the exposed inner surfaces of the first trench and the second trench and on the exposed surface of the dielectric layer. A metal filling process is performed to form a first contact plug in the first trench and a second contact plug in the second trench. Methods that include...

10. The method according to claim 9, wherein the pre-cleaning process, the cavity forming process, the first selective deposition process, the metal treatment process, the second selective deposition process, and the blanket deposition process are performed without disrupting the vacuum environment.

11. The aforementioned metal treatment process involves hydrogen (H ２ The method according to claim 9, comprising a capacitively coupled plasma (CCP) chemical etching process with ion collisions using a processing gas containing ) and argon (Ar).

12. The aforementioned n-type semiconductor region contains silicon doped with an n-type dopant, The p-type semiconductor region includes silicon germanium doped with a p-type dopant. The cavity forming process described above is Chlorine (Cl ２ ) and hydrogen (H ２ This includes etching processes that use The method according to claim 9.

13. The method according to claim 9, wherein the first cavity contact comprises a material selected from molybdenum (Mo) silicide and ruthenium (Ru) silicide, and the second cavity contact comprises titanium (Ti) silicide.

14. The aforementioned pre-cleaning process, A dry etching process using hydrogen (H) plasma removes carbon-containing contaminants from the exposed surfaces of the n-type semiconductor region and the p-type semiconductor region, The dry etching process removes oxide-containing contaminants from the exposed surfaces of the n-type semiconductor region and the p-type semiconductor region. The method according to claim 9, including the method described in claim 9.

15. The method according to claim 9, wherein the barrier layer comprises titanium nitride (TiN) or tantalum nitride (TaN).

16. The method according to claim 9, wherein the first contact plug and the second contact plug contain tungsten (W).

17. A processing system, The first processing chamber, A second processing chamber, A third processing chamber, A system controller, wherein in the processing system, The invention provides a cavity forming process to be performed in the first processing chamber on a semiconductor structure having an n-type semiconductor region for an n-type metal oxide semiconductor (n-MOS) device and a p-type semiconductor region for a p-type metal oxide semiconductor (p-MOS) device, wherein the cavity forming process includes forming a second cavity in the exposed surface of the n-type semiconductor region and a first cavity in the exposed surface of the p-type semiconductor region. In the second processing chamber, a first selective deposition process is performed to selectively form a first cavity contact within the first cavity. In a third processing chamber, a metallizing process is performed on the formed first cavity contact to remove oxides at the interface between the first cavity contact and the first cavity, wherein the metallizing process involves hydrogen (H ２ The process involves performing a metal processing procedure, including a capacitively coupled plasma (CCP) chemical etching process with ion collisions using a processing gas containing ) and argon (Ar). The system controller is configured as follows: A processing system that includes this.

18. A fourth processing chamber, wherein the system controller Prior to the cavity forming process, in the fourth processing chamber, A dry etching process using hydrogen (H) plasma removes carbon-containing contaminants from the exposed surfaces of the n-type semiconductor region and the p-type semiconductor region, The dry etching process removes oxide-containing contaminants from the exposed surfaces of the n-type semiconductor region and the p-type semiconductor region. Pre-washing process, including It is further configured to perform The processing system according to claim 17, further comprising a fourth processing chamber.

19. A fifth processing chamber, wherein the system controller The system is further configured to perform a second selective deposition process in the fifth processing chamber after the metal treatment process to selectively form a second cavity contact within the second cavity. The processing system according to claim 17, further comprising a fifth processing chamber.

20. The processing system according to claim 17, wherein the system controller is further configured to cause the processing system to perform the cavity forming process, the first selective deposition process, and the metal processing without disrupting the vacuum environment.

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