Multi-threshold voltage integration scheme for semiconductor devices

Abstract

Methods for manufacturing electronic devices are described. Embodiments of this disclosure include reducing thickness, reducing leakage current, reducing thermal balance, and V t Requirements (Multi-V t The present invention provides an advantageous method for manufacturing electronic devices that satisfy (including) the requirements and improve the performance and reliability of the devices. The method comprises depositing an interface layer (e.g., silicon oxide (SiOx)) on the upper surface of a channel; depositing a hafnium-containing layer containing hafnium oxide (HfOx) and having a thickness of 5 Å or less on the interface layer; and depositing a dipole layer containing lanthanum nitride (LaN) on the hafnium-containing layer to form a p-type dipole stack and an n-type dipole stack on a semiconductor substrate.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of electronic device manufacturing, particularly transistors. More specifically, embodiments of the present disclosure are directed to FinFET devices and GAA devices, and methods of manufacturing such FinFET devices and GAA devices.

Background Art

[0002] Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors, and resistors on a single chip. In the process of the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) generally increases, while the feature size (i.e., the smallest component (or line) that can be generated using a manufacturing process) decreases.

[0003] Transistors are components or elements that are often formed on semiconductor devices. Depending on the circuit design, many transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Integrated circuits incorporate planar field-effect transistors (FETs) in which current flows through a semiconductor channel between a source and a drain in response to a voltage applied to a control gate.

[0004] As the dimensions of devices shrink, it has become difficult to maintain switching speed without causing failures in the feature size and materials of the devices. Several new technologies have emerged to enable chip designers to further reduce the gate length. Controlling the dimensions of device structures is an important issue for current and future technology generations.

[0005] The scaling down of the materials currently used as negative metal oxide semiconductor (n-type MOS) transistors and positive metal oxide semiconductor (p-type MOS) transistors has led to a threshold voltage (V tThis presents challenges due to changes in fundamental characteristics such as ). In addition, transitioning transistor technology from planar FETs to FinFETs and then to GAA devices requires multiple threshold voltages (multi-V). t A conformal work function sheath corresponding to ) is required. t The adjustment range will be limited by changes in film thickness as the device size is further reduced.

[0006] There are also challenges associated with conventional dipole engineering techniques. To achieve the desired dipole effect, the desired element is driven out of a film deposited by spike annealing and then removed after being driven in. Spike annealing can cause a penalty to the equivalent oxide thickness (EOT) and a high heat balance because free oxygen atoms in the gate dielectric layer and the upper dipole stack diffuse downward and oxidize the underlying silicon layer.

[0007] In addition, precise control of the amount of dipole species in metal gate stacks, such as high dielectric constant metal gate stacks, is essential for achieving the desired voltage of a transistor. t (or MultiV) tis essential to achieve. Conventional processes include "dipole first" processes and "dipole last" processes. Usually, the dipole first process involves flowing a metal-containing precursor and reactants onto an interface layer to deposit metal atoms on the interface layer (forming a treated interface layer), achieving the desired dipole effect, and subsequently depositing a high-k dielectric layer on the treated interface layer. The dipole last process typically includes forming an interface layer on a substrate, forming a high-k dielectric layer on the interface layer, flowing a metal-containing precursor and reactants onto the high-k dielectric layer to deposit metal atoms on the high-k dielectric layer, and annealing the substrate to drive the metal atoms into the interface between the interface layer and the high-k dielectric layer to achieve the desired dipole effect. In the dipole last process, instead of forming an ultrathin surface adsorption layer, an atomic layer deposition (ALD) process is implemented to deposit a dipole layer having a thickness in the range of 3 Å to 20 Å and containing metal atoms, usually in the form of oxides or nitrides. To prevent the regrowth of silicon oxide during the annealing process, a capping material is usually required on top of the dipole oxide / nitride layer.

[0008] In the conventional dipole first process, V exceeding about 200 millivolts (mV) t can be adjusted, but in the conventional dipole last process, V less than about 200 mV t can be adjusted. Therefore, in the conventional dipole last process, to achieve the high V t such as that achieved in the conventional dipole first process t would require multiple annealing steps. To switch to the conventional dipole first process for higher V t adjustability, an etching process capable of selectively removing the dipole material without removing a part of the silicon oxide (SiOx) interface layer is not currently known, so the multi-V t function is lost. Also, especially in the dipole first process, there are also issues related to V t shift and leakage current.

[0009] Therefore, the reduction in thickness, the reduction in leakage current, the reduction in heat balance, and V t Requirements (Multi-V t An improved method is needed for manufacturing electronic devices that meet the following criteria (including) and have minimal or no EOT penalty. [Overview of the project]

[0010] One or more embodiments of this disclosure relate to a method for manufacturing an electronic device. The method includes forming a p-type dipole stack and an n-type dipole stack on a semiconductor substrate. Each of the p-type and n-type dipole stacks is formed on the upper surface of a channel located between a source and a drain on the semiconductor substrate. In some embodiments, forming each of the p-type and n-type dipole stacks includes depositing an interface layer on the upper surface of the channel; depositing a hafnium-containing layer on the interface layer, wherein the hafnium-containing layer has a thickness of 5 Å or less; and depositing a dipole layer on the hafnium-containing layer.

[0011] Further embodiments of the present disclosure relate to methods for manufacturing electronic devices. The method includes forming a p-type dipole stack and an n-type dipole stack on a semiconductor substrate. Each of the p-type and n-type dipole stacks is formed on the upper surface of a channel located between a source and a drain on the semiconductor substrate. In some embodiments, forming each of the p-type and n-type dipole stacks includes depositing an interface layer (e.g., silicon oxide (SiOx)) on the upper surface of the channel; depositing a hafnium-containing layer on the interface layer, wherein the hafnium-containing layer contains hafnium oxide (HfOx) and has a thickness of 5 Å or less; and depositing a dipole layer containing lanthanum nitride (LaN) on the hafnium-containing layer.

[0012] A more detailed description of the Disclosure, which is briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings, so that the above features of the Disclosure can be understood in more detail. However, it should be noted that the accompanying drawings show only typical embodiments of the Disclosure and should not be considered to limit its scope, as the Disclosure may also permit other equally valid embodiments. The embodiments described herein are shown as examples and are not limited to the drawings in the accompanying drawings, where similar references show similar elements. [Brief explanation of the drawing]

[0013] [Figure 1] Process flow diagram of a method for manufacturing an electronic device according to one or more embodiments of the present disclosure. [Figure 2A] Cross-sectional view of a semiconductor substrate according to one or more embodiments of the present disclosure [Figure 2B] Cross-sectional view of a semiconductor substrate according to one or more embodiments of the present disclosure [Figure 2C] Cross-sectional view of a semiconductor substrate according to one or more embodiments of the present disclosure [Figure 2D] Cross-sectional view of a substrate according to one or more embodiments of the present disclosure [Figure 2E] Cross-sectional view of a semiconductor substrate according to one or more embodiments of the present disclosure [Figure 2F] Cross-sectional view of a semiconductor substrate according to one or more embodiments of the present disclosure [Figure 3] Figure illustrating a cluster tool according to one or more embodiments of this disclosure. [Modes for carrying out the invention]

[0014] Before describing some exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the configuration or process step details described below. Other embodiments of this disclosure are possible and can be implemented or performed in a variety of ways.

[0015] As used herein, the term "approximately" means roughly or nearly, and in the context of the given numbers or ranges, it means a variation of ±15% or less of the number. For example, values ​​that differ by ±14%, ±10%, ±5%, ±2%, or ±1% would satisfy the definition of approximately.

[0016] As used herein and in the appended claims, the terms “substrate” or “wafer” refer to the surface or portion of a surface on which the processing is performed. It will also be understood by those skilled in the art that a reference to a substrate may refer to only a portion of the substrate unless otherwise explicitly stated in the context. Furthermore, when a reference is made to deposition on a substrate, it may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0017] As used herein, “substrate” means any substrate or material surface formed on such substrate on which a film treatment is performed during the manufacturing process. For example, substrate surfaces that may be treated include, depending on the application, materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes for polishing, etching, reduction, oxidation, hydroxylation, annealing, and / or baking of the substrate surface. In addition to direct film treatment of the substrate surface itself, any disclosed film treatment process may also be performed on underlying layers formed on the substrate, as will be disclosed in more detail below, and the term “substrate surface” is intended to include such underlying layers as the context indicates. Therefore, for example, if a film / layer or partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0018] The term "on" indicates that there is direct contact between elements. The term "directly on" indicates that there is direct contact between elements without an intervening element.

[0019] As used herein and in the appended claims, terms such as “precursor,” “reactant,” and “reactive gas” are interchangeable to refer to any gaseous species capable of reacting with the substrate surface.

[0020] As used herein, “atomic layer deposition” or “periodic deposition” refers to the deposition of a layer of material on a substrate surface by sequential exposure to two or more reactive compounds. The substrate or a portion of the substrate is exposed separately to two or more reactive compounds introduced into the reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay, allowing each compound to adhere to and / or react with the substrate surface before being purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, different portions of the substrate surface or material on the substrate surface are simultaneously exposed to two or more reactive compounds such that no given point on the substrate is substantially exposed to more than one reactive compound at the same time. As used herein and in the appended claims, the term “substantially” in this regard means, as understood by those skilled in the art, that small portions of the substrate may be simultaneously exposed to multiple reactive gases by diffusion, but simultaneous exposure is not intended.

[0021] In one embodiment of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compounds or reaction byproducts from the reaction zone. Alternatively, the purge gas may be continuously flowed throughout the entire deposition process so that only the purge gas flows during the time delays between pulses of the reactive compound. Alternatively, the reactive compound is pulsed until a desired film or thickness is formed on the substrate surface. In either scenario, one cycle consists of compound A, purge gas, compound B, and the ALD process of pulsed purge gas. A cycle can be started with either compound A or compound B, and each sequence of cycles can be continued until a film of a predetermined thickness is achieved.

[0022] One or more of the substrate or layers deposited on the substrate surface are continuous. As used herein, the term “continuous” refers to a layer that covers the entire exposed surface without gaps or exposed areas that expose the material beneath the deposited layer. Continuous layers may have gaps or exposed areas having a surface area of ​​less than approximately 15% or less than approximately 10% of the total surface area of ​​the layer.

[0023] In one embodiment of the spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are simultaneously supplied to the reaction zone but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas supply device so that any given point on the substrate is exposed to the first and second reactive gases.

[0024] A transistor is a component or element that is often formed on a semiconductor device. Depending on the circuit design, a transistor is formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive wires, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doping regions of a substrate, such as a semiconductor substrate, which exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric sandwiched between the gate electrode and the channel region in the semiconductor substrate.

[0025] As used herein, the term “field-effect transistor” or “FET” refers to a transistor that uses an electric field to control the electrical behavior of a device. A field-effect transistor is a voltage-controlled device whose current-conducting ability changes when an electric field is applied. Field-effect transistors generally exhibit very high input impedance at low temperatures. Conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by the voltage difference between the device body and the gate. The three terminals of an FET are the source (S) where carriers enter the channel; the drain (D) where carriers exit the channel; and the gate (G), which is the terminal that adjusts the conductivity of the channel. Typically, the current entering the channel at the source (S) is I S It is specified that the current entering the channel at the drain (D) is I D It is specified as follows. The voltage from drain to source is V DS It is specified as follows. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D ) can be controlled.

[0026] Metal oxide semiconductor field-effect transistors (MOSFETs) are a type of field-effect transistor (FET) used in integrated circuits and high-speed switching applications. MOSFETs have an insulated gate, and the device's conductivity is determined by the voltage applied to it. This ability to change conductivity depending on the applied voltage is used for amplifying or switching electronic signals. MOSFETs are based on the modulation of charge concentration by metal oxide semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to MOS capacitors, MOSFETs have two additional terminals (source and drain), each connected to a separate, highly doped region separated by the body region. These regions are either p-type or n-type, both being the same type but opposite to the body region. The source and drain are highly doped (unlike the body), and the doping type is indicated by a "+" sign.

[0027] If the MOSFET is an n-type channel or nMOS FET, the source and drain are the n+ region, and the body is the p-type substrate region. If the MOSFET is a p-channel or pMOS FET, the source and drain are the p+ region, and the body is the n-type substrate region. The source is so called because it is the source of charge carriers (electrons in the case of an n-type channel, and holes in the case of a p-channel) flowing through the channel; similarly, the drain is where the charge carriers exit the channel.

[0028] An nMOS FET consists of an n-type source, a drain, and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are pushed out of the gate. This creates an n-type channel between the source and the drain, and current is carried by electrons from the source to the drain through the induced n-type channel. Logic gates and other digital devices implemented using NMOS are said to have NMOS logic. NMOS has three operating modes called cutoff, triode, and saturation. Circuits with NMOS logic gates consume static power when the circuit is idling because DC current flows through the logic gate when the output is low.

[0029] A pMOS FET consists of a p-type source, a drain, and an n-type substrate. When a positive voltage is applied between the source and the gate (and a negative voltage between the gate and the source), a p-type channel with opposite polarity is formed between the source and the drain. Current is carried from the source to the drain by holes through the induced p-type channel. A PMOS does not conduct when a high voltage is applied to the gate, but it does conduct when a low voltage is applied to the gate. Logic gates and other digital devices implemented using PMOS are said to have PMOS logic. PMOS technology is low-cost and has good noise immunity.

[0030] In NMOS, the carriers are electrons, while in PMOS, the carriers are holes. When a high voltage is applied to the gate, NMOS conducts, but PMOS does not. Furthermore, when a low voltage is applied to the gate, NMOS will not conduct, while PMOS will. Because electrons, the carriers in NMOS, move twice as fast as holes, the carriers in PMOS, NMOS is considered to be faster than PMOS. However, PMOS devices are less susceptible to noise than NMOS devices. Moreover, because NMOS can only provide half the impedance that PMOS (with the same shape and operating conditions) provides, NMOS ICs will be smaller than PMOS ICs (providing the same functionality).

[0031] As used herein, the term “Fin-field-effect transistor (FinFET)” refers to a substrate-built MOSFET transistor in which the gate is located on two, three, or four sides of the channel, or is wound around the channel to form a double-gate structure. FinFET devices are given the common name FinFET because the source / drain regions form “fins” on the substrate. FinFET devices have fast switching times and high current densities.

[0032] As used herein, the term “gate all around (GAA)” is used to refer to an electronic device, such as a transistor, in which the gate material surrounds the channel region on all sides. The channel region of a GAA transistor may include nanowires, or nanoslabs, or nanosheets, bar-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of vertically spaced horizontal nanowires or horizontal bars, and the GAA transistor becomes a stacked horizontal gate all around (hGAA) transistor.

[0033] As used herein, the term "nanowire" refers to a wire with a diameter of nanometers (10⁻¹⁰-9 This refers to nanostructures of about 1000 nanometers in size. Nanowires can also be defined as structures where the ratio of length to width is greater than 1000. Alternatively, nanowires can be defined as structures whose thickness or diameter is limited to tens of nanometers or less, and whose length is not limited. Nanowires are used in transistors and some laser applications, and in one or more embodiments, they are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in logic CPUs, GPUs, MPUs, and transistors for volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term “nanosheet” refers to a two-dimensional nanostructure having a thickness on a scale ranging from about 0.1 nm to about 1000 nm, or 0.5 nm to 500 nm, or 0.5 nm to 100 nm, or 1 nm to 500 nm, or 1 nm to 100 nm, or 1 nm to 50 nm.

[0034] Embodiments of this disclosure reduce thickness, reduce leakage current, reduce heat balance, and V t Requirements (Multi-V t The present disclosure provides an advantageous method for manufacturing electronic devices that satisfy (including) and improve device performance and reliability. Embodiments of this disclosure provide a novel integration scheme that enables V without an EOT penalty. t This significantly improves the EOT increase while reducing the V to at least 300mV. Embodiments of this disclosure minimize the increase in EOT. t Includes an integration scheme that provides adjustability.

[0035] In some embodiments, V is used in one or more p-type or n-type dipole stacks in an electronic device. t It provides an advantageous way to increase the leakage current (J) in an electronic device. Several embodiments provide an advantageous way to increase the leakage current (J) in an electronic device. g ) provides a favorable way to reduce.

[0036] Embodiments of this disclosure are characterized by increased V t and MultiV tThe present invention provides an improved dipole-first process that enables enhanced adjustment capabilities. Embodiments of the present disclosure provide an improved dipole-first process that increases the density of the high-dielectric constant dielectric layer and reduces the number of annealing steps for driving in metal atoms from the deposited dipole layer. Embodiments of the present disclosure provide an improved dipole-first process that, compared to conventional dipole-first processes and conventional dipole-last processes, for example, a flat-band voltage (V fb This relates to metal gate stacks with improved band-edge performance, such as p-type and n-type dipole stacks.

[0037] Embodiments of the present disclosure are illustrated by drawings showing devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The illustrated processes are merely illustrative possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated uses.

[0038] Figure 1 shows a process flow diagram of a method 100 for manufacturing an electronic device according to one or more embodiments of the present disclosure. Method 100 includes forming a p-type dipole stack and an n-type dipole stack on a semiconductor substrate. Each of the p-type and n-type dipole stacks is formed on the upper surface of a channel located between the source and drain on the semiconductor substrate. Forming each of the p-type and n-type dipole stacks includes depositing an interface layer on the upper surface of the channel (operation 110); depositing a hafnium-containing layer having a thickness of 5 Å or less on the interface layer (operation 120); and depositing a dipole layer on the hafnium-containing layer to a predetermined thickness (operation 130).

[0039] In some embodiments, during operation 110, the interface layer is deposited on the semiconductor substrate using a deposition technique, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In one or more embodiments, the interface layer includes a silicon oxide (SiOx) layer formed on doped or undoped silicon. In one or more embodiments, the interface layer can be formed by etching and oxide formation on the surface.

[0040] In some embodiments, a wet chemical technique is performed in operation 110 to form an interface layer. The wet chemical technique may be any suitable technique known to those skilled in the art. In some embodiments, the wet chemical technique includes a pre-cleaning process. In some embodiments, the pre-cleaning process includes using an SC-1 solution containing one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, the pre-cleaning process includes using an SC-1 solution that does not contain ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, after using the SC-1 solution, the pre-cleaning process includes etching off native oxides on the substrate and forming a hydrophobic surface (i.e., interface layer) using dilute hydrofluoric acid (diluted HF), including a dilution of HF greater than 100:1, for example, 130:1.

[0041] In some embodiments, in operation 110, rapid heat treatment (RTP) is used to form an interfacial layer. RTP can be any suitable process known to those skilled in the art. In some embodiments, in operation 110, RTP is a thermal oxidation process in which a silicon oxide (SiOx) layer is grown on a semiconductor substrate.

[0042] In some embodiments, during operation 120, the hafnium-containing layer is deposited on the interface layer using a deposition technique, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, during operation 120, the hafnium-containing layer is conformally deposited by ALD.

[0043] In some embodiments, the hafnium-containing layer comprises one or more of the following: hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), nitrogen-doped hafnium oxide (HfOx), or nitrogen-doped hafnium zirconium oxide (HfZrOx). In some embodiments, the hafnium-containing layer comprises hafnium oxide (HfOx).

[0044] Embodiments of the present disclosure advantageously provide a thin hafnium-containing layer that functions as a buffer layer between an interface layer and a dipole layer. Advantageously, in contrast to conventional dipole-first processes, a thin hafnium-containing layer is provided, such as a hafnium-containing layer having a thickness of 5 Å or less. In one or more embodiments, the hafnium-containing layer is continuous, and a hafnium-containing layer having a thickness of 5 Å or less covers the entire exposed surface (e.g., interface layer) without gaps or exposed portions that expose the material beneath the hafnium-containing layer.

[0045] The hafnium-containing layer may have any suitable thickness of 5 Å or less, as described herein, so that the hafnium-containing layer maintains continuity and prevents etching of the interface layer during the removal of the dipole layer in subsequent operations.

[0046] In some embodiments, during operation 130, the dipole layer is deposited on the hafnium-containing layer using a deposition technique, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. The dipole layer comprises one or more of the following: a metal layer, a metal oxide layer, or a metal nitride layer.

[0047] In some embodiments, in operation 130, depositing the dipole layer involves exposing a semiconductor substrate to pulses of a metal-containing precursor and pulses of a hydrogen-containing reactant by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In some embodiments, the semiconductor substrate is purged after each pulse.

[0048] In some embodiments, in operation 130, depositing the dipole layer involves exposing a semiconductor substrate to pulses of a metal-containing precursor and pulses of an oxygen-containing reactant by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In some embodiments, the semiconductor substrate is purged after each pulse.

[0049] In some embodiments, in operation 130, depositing the dipole layer involves exposing a semiconductor substrate to pulses of a metal-containing precursor and pulses of a nitrogen-containing reactant by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In some embodiments, the semiconductor substrate is purged after each pulse.

[0050] In some embodiments, the metal-containing precursor includes one or more of the following: titanium (Ti), tantalum (Ta), aluminum (Al), niobium (Nb), antimony (Sb), tellurium (Te), germanium (Ge), gallium (Ga), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), or boron (B).

[0051] In some embodiments, the reactants are hydrogen reactants for forming a dipole layer containing a pure metal layer. In some embodiments, the reactants are oxygen-containing reactants for forming a dipole layer containing a metal oxide layer. In some embodiments, the reactants are nitrogen-containing reactants for forming a dipole layer containing a metal nitride layer.

[0052] In some embodiments, the hydrogen-containing reactant is hydrogen (H2) or deuterium ( 2 Includes one or more of the following (H):

[0053] In some embodiments, the oxygen-containing reactant includes one or more of oxygen (O2), ozone (O3), or water (H2O).

[0054] In some embodiments, the nitrogen-containing reactants are nitrogen (N2), ammonia (NH3), hydrazine (N2H4), and nitrogen radical (N2 * ) and hydrogen radical (H * ) co-flow with nitrogen radicals (N2 * ) and co-flow with hydrogen (H2) gas, or nitrogen radicals (N2 * ) and deuterium ( 2 H) Includes one or more of the following: co-flow with gas.

[0055] In some embodiments, the nitrogen-containing reactant comprises substituted or unsubstituted alkylhydrazines. In some embodiments, the alkylhydrazine comprises atoms ranging from one to six carbon atoms. In one or more embodiments, the alkylhydrazine is t-butylhydrazine. In some embodiments, the nitrogen-containing reactant comprises plasma. In some embodiments, the nitrogen-containing reactant comprises ammonia (NH3).

[0056] In one or more embodiments, the dipole layer on an n-type dipole stack comprises lanthanum nitride (LaN). In one or more embodiments, the dipole layer on a p-type dipole stack comprises aluminum nitride (AlN).

[0057] The dipole layer can be deposited as a single layer or as a multilayer film. The dipole layer can be deposited to a predetermined thickness.

[0058] Method 100 optionally includes selectively etching the dipole layer in operation 140. In one or more embodiments, the method applies a plurality of threshold voltages (multiple V) to the electronic device. t This includes selectively etching the dipole in operation 140 in order to form ).

[0059] Advantageously, in contrast to conventional dipole-first processes, operation 140 allows for the selective removal of the dipole layer without removing a portion of the interface layer. In one or more embodiments, method 100 selectively etches the dipole layer deposited from one of a p-type dipole stack or an n-type dipole stack in operation 140, and increases the thickness of the dipole layer on the other of the p-type dipole stack or n-type dipole stack to achieve multiple threshold voltages (multi-V). t This includes forming an electronic device having ).

[0060] The etching process of operation 140 may be any suitable etching process known to those skilled in the art. In some embodiments, the etching process includes a wet etching process or a dry etching process. In some embodiments, the etching process includes a wet etching process. In some embodiments, the wet etching process includes a pre-washing process. In some embodiments, the pre-washing process includes using one or more of ammonium hydroxide (NH4OH) or water (H2O). In some embodiments, water (H2O) is deionized water (DI). In some embodiments, the pre-washing process includes using a DI:NH4OH ratio in the range of 100:1 to 5:1.

[0061] In some embodiments, the pre-cleaning process includes using either SC-1 solution or SC-2 solution. In one or more embodiments, SC-1 solution includes one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In one or more embodiments, SC-2 solution includes one or more of hydrochloric acid or hydrogen peroxide. It has been found that using either SC-1 solution or SC-2 solution in operation 140 is advantageous for selectively etching the deposited dipole layer from either a p-type dipole stack or an n-type dipole stack without etching any portion of the interfacial layer.

[0062] In operation 140, the deposited dipole layer is selectively etched from either a p-type dipole stack or an n-type dipole stack, thereby increasing the thickness of the dipole layer on the other of the p-type or n-type dipole stack, and the multi-V of the electronic device is increased. t It was found to be advantageous to have a way to adjust it.

[0063] For example, if the work function is shifted at either the p-type or n-type dipole band edge after dipole engineering, the band edge can be shifted in the opposite direction using the method herein. For example, the method described herein shifts the band edge to the most p-type and / or n-type dipole band edge, respectively, at the very low V t (ULV t ) from the very low V, which is the most p-type dipole and / or n-type dipole band edge. t (ULV t ), low V t (LV t ) or standard V t (SV t ), or intermediate gap: high V t (HV t ) can be shifted to ULV. In some embodiments, t This can be achieved by using p-type dipoles and p-type metals in a p-type dipole stack, and by using n-type dipoles and n-type metals in an n-type dipole stack. In some embodiments, the thickness of the dipole layer is selected to form the maximum dipole density at the interface between the interface layer and the hafnium-containing layer.

[0064] While I don't intend to be bound by theory, by selectively etching the dipole layer deposited on either a p-type or n-type dipole stack, and increasing the thickness of the dipole layer on the other of the p-type or n-type dipole stack, multiple threshold voltages (multi-V) can be achieved. tIt is thought that an electronic device having ) can be formed. In other words, if a dipole layer on a p-type dipole stack or an n-type dipole stack has a first thickness, and a dipole layer on the other of the p-type dipole stack or n-type dipole stack has a second thickness, and the first and second thicknesses are different, then multiple threshold voltages (multiple V) can be formed. t ) is formed.

[0065] In some embodiments, LV t This can be achieved by using a p-type metal or p-type dipole (thinner dipole layer) and a p-type metal in a p-type dipole stack, and by using an n-type metal or n-type dipole (thinner dipole layer) and an n-type metal in an n-type dipole stack. In some embodiments, SV t This can be achieved by using a thin p-type metal layer in a p-type dipole stack, or by using a thin n-type metal layer in an n-type dipole stack, or by using a combination of p-type and n-type dipoles of a predetermined thickness. In some embodiments, HV t This can be achieved by a combination of a p-type metal and an n-type metal or an intermediate gap work function metal. In some embodiments, the intermediate gap work function metal includes any suitable metallic material having a work function of 4.4 to 4.6 eV. Depending on the selected metal precursor, the methods described herein have been found to be advantageous in that they can lower or raise the effective work function (eWF) of a film stack in a semiconductor device (e.g., a p-type dipole stack and / or an n-type dipole stack). Therefore, the adjustment of eWF can be achieved by using different intermediate gap work function metals. Intermediate gap work function metals are multi-V t The selection can be made based on the adjustment of requirements.

[0066] Referring to Figures 1 and 2E, Method 100 optionally includes, in Operation 150, depositing a high dielectric layer having a thickness in the range of 10 Å to 20 Å on a dipole layer using a deposition technique, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, in Operation 150, the high dielectric layer is deposited conformally by ALD.

[0067] The high dielectric layer includes one or more of the following: hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx). In one or more embodiments, the electronic device includes a hafnium-containing layer on the interface layer containing hafnium oxide (HfOx) (having a thickness of 5 Å or less) and a high dielectric layer on the dipole layer containing hafnium oxide (HfOx) (having a thickness in the range of 10 Å to 20 Å).

[0068] Referring again to Figures 1 and 2E, Method 100 optionally includes, in Operation 160, annealing (indicated by arrows) the p-type and n-type dipole stacks at a temperature of 1000°C or less to drive metal atoms from the dipole layer and increase the density of the high dielectric layer to form an annealed high dielectric layer. In some embodiments, in Operation 160, Method 100 includes annealing the p-type and n-type dipole stacks at a temperature of 950°C or less. In some embodiments, the temperature is in the range of 500°C to 1000°C, including the range of 600°C to 1000°C, the range of 700°C to 1000°C, the range of 750°C to 950°C, or the range of 800°C to 900°C.

[0069] While not intended to be bound by theory, it is believed that annealing a semiconductor substrate according to operation 160 drives a greater number of atoms from the dipole layer to the interface between the interfacial layer and the hafnium-containing layer compared to a method in which annealing is not performed. In one or more embodiments, annealing the semiconductor substrate in operation 160 includes rapid thermal treatment (RTP). RTP can be any suitable process known to those skilled in the art. While not intended to be bound by theory, it is believed that RTP increases the density of the deposited dipole layer and improves its physical properties. While not intended to be bound by theory, if in operation 160 method 100 includes annealing the semiconductor substrate at a temperature of 1000°C or less to drive atoms from the dipole layer to the interface between the interfacial layer and the hafnium-containing layer, then the interface between the interfacial layer and the hafnium-containing layer includes the properties of the dipole layer.

[0070] While not intending to be bound by theory, a dipole region containing a channel with n-type or p-type material and the aforementioned dipole layer is thought to simplify existing integration flows and reduce integration costs. In addition, when atoms from the dipole layer (such as metal atoms) are embedded in the interface layer and / or hafnium-containing layer, a dipole region is formed, and oxidation may be reduced, which may lower the required annealing temperature.

[0071] Referring to Figures 1 and 2F, Method 100 optionally includes, in Operation 170, depositing a work function layer or an intermediate gap filling layer on an annealed high-dielectric-constant dielectric layer. In some embodiments, in Operation 170, the work function layer is deposited on the annealed high-dielectric-constant dielectric layer using a deposition technique, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0072] The work function layer may contain any suitable metal known to those skilled in the art. In some embodiments, the work function layer contains one or more p-type metals or n-type metals. In some embodiments, the work function layer contains a p-type metal. In embodiments where the work function layer contains a p-type metal, the p-type metal contains any suitable high electronegativity metal nitride material. In some embodiments, the p-type metal contains one or more titanium nitride (TiN), titanium oxynitride (TiON), molybdenum nitride (MoN), molybdenum oxynitride (MoON), or niobium nitride (NbN).

[0073] In some embodiments, the work function layer includes an n-type metal. In embodiments where the work function layer includes an n-type metal, the n-type metal includes any suitable electropositive high-melting-point (refractive) metal. In some embodiments, the n-type metal includes lanthanides, their carbides, their nitrides, alloys thereof with electropositive high-melting-point metals, titanium aluminum (TiAl), tantalum aluminum (TaAl), niobium aluminum (NbAl), or zirconium aluminum (ZrAl).

[0074] In one or more embodiments, the work function layer has a thickness in the range of 2 nm or less to 3 nm or less.

[0075] Figures 2A to 2F are cross-sectional views of an electronic device (e.g., a transistor such as a FinFET or GAA) 200 according to one or more embodiments. The electronic devices 200 shown in Figures 2A to 2F can be manufactured by the method 100 shown in Figure 1.

[0076] Referring to Figures 2A and 2B, in one or more embodiments, the electronic device 200 includes a semiconductor substrate 202 having an upper surface 203. The semiconductor substrate 202 can be any suitable substrate material. In one or more embodiments, the semiconductor substrate 202 includes semiconductor materials such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphate (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), other semiconductor materials, or any combination thereof. In one or more embodiments, the semiconductor substrate 202 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), or selenium (Se). While some examples of materials that can form the substrate 202 are described herein, any material that can serve as a basis for constructing passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) is within the spirit and scope of this disclosure.

[0077] In one or more embodiments, the semiconductor substrate 202 is a p-type or n-type substrate. As used herein, the term “n-type” refers to a semiconductor produced by doping an intrinsic semiconductor with an electron donor element during manufacturing. The term n-type derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. As used herein, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration greater than the electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers.

[0078] In one or more embodiments, the source region 204a is located on the upper surface 203 of the semiconductor substrate 202. In one or more embodiments, the source region 204a has a source and a source contact (not shown). The drain region 204b is located on the upper surface 203 of the semiconductor substrate 202 opposite to the source region 204a. In one or more embodiments, the drain region 204b has a drain and a drain contact (not shown).

[0079] In one or more embodiments, the source region 204a and / or the drain region 204b may be any suitable material known to those skilled in the art. In one or more embodiments, the source region 204a and / or the drain region 204b may have more than one layer. For example, the source region 204a and / or the drain region 204b may independently comprise three layers. In one or more embodiments, the source region 204a and the drain region 204b may independently comprise one or more of the following: copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorus (P), germanium (Ge), silicon (Si), aluminum (Al), or zirconium (Zr). In some embodiments, the source region 204a and the drain region 204b may independently include a bottom layer of silicon doped with epitaxial material (e.g., SiGe, SiP), a second layer of silicide which may include nickel (Ni), titanium (Ti), aluminum (Al), etc., and a third or top layer which may be a metal such as cobalt, tungsten, or ruthenium, but are not limited to these. In some embodiments, the source region 204a and the drain region 204b may be raised source / drain regions formed by epitaxial growth.

[0080] In one or more embodiments, the source contact and / or drain contact can be independently selected from one or more of the following: nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In one or more embodiments, the formation of the source contact and / or drain contact can be carried out by any suitable process known to those skilled in the art, including but not limited to ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0081] In one or more embodiments, the channel 206 is located between the source 204a and the drain 204b. In one or more embodiments, during operation 110, the interface layer 210 is deposited on the upper surface 205 of the channel 206. In one or more embodiments, the interface layer 210 can be any suitable material known to those skilled in the art. For example, in one or more embodiments, the interface layer 210 includes a silicon oxide (SiOx) layer formed on doped or undoped silicon. In one or more embodiments, the interface layer 210 includes silicon dioxide (SiO2). In other embodiments, the dielectric material is a low dielectric constant material. In one or more embodiments, the interface layer 210 can be formed on the upper surface 205 of the channel 206 by any of the processes described herein with respect to operation 110. In one or more embodiments, the interface layer 210 has a thickness ranging from 1 Å to 10 Å.

[0082] In one or more embodiments, during operation 120, the hafnium-containing layer 212 is deposited on the upper surface 211 of the interface layer 210 using a deposition technique, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, during operation 120, the hafnium-containing layer 212 is deposited conformally by ALD.

[0083] In some embodiments, the hafnium-containing layer 212 contains one or more of the following: hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), nitrogen-doped hafnium oxide (HfOx), or nitrogen-doped hafnium zirconium oxide (HfZrOx). In some embodiments, the hafnium-containing layer 212 contains hafnium oxide (HfOx).

[0084] Embodiments of the present disclosure advantageously provide a thin hafnium-containing layer 212 that functions as a buffer layer between the interface layer 210 and the dipole layer 214. Advantageously, in contrast to conventional dipole-first processes, a thin hafnium-containing layer is provided, such as a hafnium-containing layer 212 having a thickness of 5 Å or less. In one or more embodiments, the hafnium-containing layer 212 is continuous, and a hafnium-containing layer 212 having a thickness of 5 Å or less covers the entire exposed surface (e.g., the interface layer 210) without gaps or exposed portions that expose the material beneath the hafnium-containing layer 212.

[0085] The hafnium-containing layer 212 may have any suitable thickness of 5 Å or less, as described herein, so that the hafnium-containing layer 212 maintains continuity and prevents etching of the interface layer 210 during the removal of the dipole layer 214 in subsequent operations.

[0086] In some embodiments, during operation 130, the dipole layer 214 is deposited on the upper surface 213 of the hafnium-containing layer 212 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0087] The dipole layer 214 includes one or more of the following: a metal layer, a metal oxide layer, or a metal nitride layer.

[0088] In some embodiments, in operation 130, depositing the dipole layer 214 involves exposing the semiconductor substrate 202 to pulses of metal-containing precursors and reactants by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In some embodiments, the semiconductor substrate 202 is purged after each pulse.

[0089] In some embodiments, the reactants are hydrogen reactants for forming a dipole layer 214 containing a pure metal layer. In some embodiments, the reactants are oxygen-containing reactants for forming a dipole layer 214 containing a metal oxide layer. In some embodiments, the reactants are nitrogen-containing reactants for forming a dipole layer 214 containing a metal nitride layer.

[0090] In one or more specific embodiments, the dipole layer 214 is deposited by atomic layer deposition (ALD). In one or more embodiments, the dipole layer 214 is deposited by atomic layer deposition (ALD) at temperatures ranging from about 200°C to about 600°C. In one or more embodiments, the dipole layer 214 is deposited by atomic layer deposition (ALD) at temperatures below about 450°C. In one or more embodiments, the dipole layer has a thickness ranging from 1 Å to 10 Å, or from 2 Å to 5 Å. In one or more specific embodiments, the dipole layer has a thickness ranging from 3 Å to 4 Å.

[0091] Figure 2B shows an n-type dipole stack and a p-type dipole stack. In one or more embodiments, the stack on the left side of Figure 2B is an n-type dipole stack, and the stack on the right side of Figure 2B is a p-type dipole stack. Those skilled in the art will recognize that either the left or right side may include either an n-type dipole stack or a p-type dipole stack, and this disclosure is not limited to the embodiments shown in Figure 2B.

[0092] In one or more embodiments, the channel 206 comprises an n-type material, and the dipole layer 214 comprises one or more of the following: lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), magnesium (Mg), scandium (Sc), strontium (Sr), yttrium (Y), zirconium (Zr), or cesium (Cs).

[0093] In one or more embodiments, the channel 206 comprises a p-type material, and the dipole layer 214 comprises one or more of the following: aluminum (Al), titanium (Ti), gallium (Ga), germanium (Ge), selenium (Se), indium (In), tin (Sn), antimony (Sb), tellurium (Te), tantalum (Ta), tungsten (W), or molybdenum (Mo).

[0094] In some embodiments, the metal-containing precursor includes one or more of the following: titanium (Ti), tantalum (Ta), aluminum (Al), niobium (Nb), antimony (Sb), tellurium (Te), germanium (Ge), gallium (Ga), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), or boron (B).

[0095] In some embodiments, the hydrogen-containing reactant is hydrogen (H2) or deuterium ( 2 Includes one or more of the following (H):

[0096] In some embodiments, the oxygen-containing reactant includes one or more of oxygen (O2), ozone (O3), or water (H2O).

[0097] In some embodiments, the nitrogen-containing reactants are nitrogen (N2), ammonia (NH3), hydrazine (N2H4), and nitrogen radical (N2 * ) and hydrogen radical (H *) co-flow with nitrogen radicals (N2 * ) and co-flow with hydrogen (H2) gas, or nitrogen radicals (N2 * ) and deuterium ( 2 H) Includes one or more of the following: co-flow with gas.

[0098] In some embodiments, the nitrogen-containing reactant comprises substituted or unsubstituted alkylhydrazines. In some embodiments, the alkylhydrazine comprises atoms ranging from one to six carbon atoms. In one or more embodiments, the alkylhydrazine is t-butylhydrazine. In some embodiments, the nitrogen-containing reactant comprises plasma. In some embodiments, the nitrogen-containing reactant comprises ammonia (NH3).

[0099] In one or more embodiments, the channel 206 comprises an n-type material, and the dipole layer 214 comprises lanthanum nitride (LaN) on an n-type dipole stack. In one or more embodiments, the channel 206 comprises a p-type material, and the dipole layer 214 comprises aluminum (Al) on a p-type dipole stack.

[0100] The dipole layer 214 can be deposited as a single layer or as a multilayer film. The dipole layer 214 can be deposited to a predetermined thickness.

[0101] Referring to Figure 2C, in one or more embodiments, the dipole layer 214 on the PFET side 250 is removed by a selective etching process in operation 140 of method 100. Advantageously, in contrast to conventional dipole-first processes, operation 140 allows for the selective removal of the dipole layer 214 without removing any portion of the interface layer 210.

[0102] In one or more embodiments, Method 100 selectively etches the deposited dipole layer 214 from one of the p-type dipole stacks or the n-type dipole stack in operation 140, and increases the thickness of the dipole layer 214 on the other of the p-type dipole stacks or the n-type dipole stack (forming dipole layer 214A and dipole layer 214B) to achieve multiple threshold voltages (multi-V). t This includes forming an electronic device having ).

[0103] The etching process of operation 140 may be any suitable etching process known to those skilled in the art. In some embodiments, the etching process includes a wet etching process or a dry etching process. In some embodiments, the etching process includes a wet etching process. In some embodiments, the wet etching process includes a pre-washing process. In some embodiments, the pre-washing process includes using one or more of ammonium hydroxide (NH4OH) or water (H2O). In some embodiments, water (H2O) is deionized water (DI). In some embodiments, the pre-washing process includes using a DI:NH4OH ratio in the range of 100:1 to 5:1.

[0104] In some embodiments, the pre-cleaning process includes using either SC-1 solution or SC-2 solution. In one or more embodiments, SC-1 solution includes one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In one or more embodiments, SC-2 solution includes one or more of hydrochloric acid or hydrogen peroxide. It has been found that using either SC-1 solution or SC-2 solution in operation 140 is advantageous for selectively etching the dipole layer 214 deposited from either a p-type dipole stack or an n-type dipole stack without etching any portion of the interface layer 210.

[0105] In operation 140, the dipole layer deposited on one of the p-type dipole stacks or the n-type dipole stack is selectively etched, increasing the thickness of the dipole layer on the other of the p-type or n-type dipole stacks (forming dipole layer 214A and dipole layer 214B), thereby enabling multi-V of the electronic device. t It was found to be advantageous to have a way to adjust it.

[0106] Figure 2D shows multiple threshold voltages (multiple V) t The diagram shows an electronic device 200 having ). In one or more embodiments, the stack on the left side of Figure 2D is an n-type dipole stack, and the stack on the right side of Figure 2D is a p-type dipole stack. Those skilled in the art will recognize that either the left or right side may include either an n-type dipole stack or a p-type dipole stack, and the disclosure is not limited to the embodiments shown in the drawings.

[0107] In Figure 2D, the dipole layer 214A on the n-type dipole stack has a first thickness, and the dipole layer 214B on the p-type dipole stack has a second thickness. The first thickness of dipole layer 214A and the second thickness of dipole layer 214B are different. In the embodiments illustrated in Figure 2D, the first thickness of dipole layer 214A is greater than the second thickness of dipole layer 214B. In one or more embodiments, the first thickness is in the range of 10 Å to 20 Å, and the second thickness is in the range of 1 Å to 10 Å. The embodiments illustrated in Figure 2D show the thicknesses of two dipole layers, i.e., the first thickness of dipole layer 214A and the second thickness of dipole layer 214B, but the disclosure is not limited thereto. In other words, the electronic device 200 has any suitable number of different dipole layer thicknesses and multiple threshold voltages (multi-V). t ) may include. In one or more embodiments not shown, the electronic device 200 has three different dipole layer thicknesses and three multiple threshold voltages (multi-V). t ) includes. In one or more embodiments not shown, the electronic device 200 has four different dipole layer thicknesses and four multiple threshold voltages (multiple V t ) and include.

[0108] Embodiments of this disclosure are characterized by increased V t and MultiV t This provides an improved dipole-first process that allows for enhanced adjustment capabilities. In certain embodiments, the electronic device 200 has two different dipole layer thicknesses and two multiple threshold voltages (multiple V) t ) and. In one or more embodiments, method 100 comprises lanthanum nitride (LaN) and 400 mV V t This is carried out to form a dipole layer having lanthanum nitride (LaN) and 400 mV. In one or more specific embodiments, it comprises lanthanum nitride (LaN) and 400 mV. t The thickness of the dipole layer having a first thickness is defined, and the dipole last process forms a dipole layer having a second thickness different from the first thickness, resulting in multi-V t It will be implemented to achieve this.

[0109] In operation 140, the deposited dipole layer 214 is selectively etched from one of the p-type dipole stacks or the n-type dipole stack, increasing the thickness of the dipole layer on the other of the p-type or n-type dipole stacks (forming dipole layer 214A and dipole layer 214B), thereby increasing the multi-V rating of the electronic device 200. t It was found to be advantageous to have a way to adjust it.

[0110] Referring to Figures 1 and 2E, in one or more embodiments, Method 100 optionally includes, in Operation 150, depositing a high dielectric constant dielectric layer 216 having a thickness ranging from 10 Å to 20 Å on the upper surface 215 of a dipole layer 214, such as dipole layer 214A and / or dipole layer 214B, using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, in Operation 150, the high dielectric constant dielectric layer 216 is deposited conformally by ALD. The high dielectric constant dielectric layer 216 contains one or more of the following: hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx). In one or more embodiments, the electronic device 200 includes a hafnium-containing layer 212 containing hafnium oxide (HfOx) (having a thickness of 5 Å or less) on an interface layer 210, and a high dielectric constant dielectric layer 216 containing hafnium oxide (HfOx) (having a thickness ranging from 10 Å to 20 Å) on a dipole layer 214.

[0111] Figures 1 and 2E also show operation 160 (indicated by arrows), which includes annealing the p-type and n-type dipole stacks at a temperature below 1000°C to drive metal atoms from the dipole layer 214 and densifying the high dielectric layer 216 to form the annealed high dielectric layer 216A (shown in Figure 2F). The metal atoms from the dipole layer 214 (indicated by ellipses in Figure 2F) are formed at the interface between the interface layer 210 and the hafnium-containing layer 212 (for example, on the upper surface 213 of the hafnium-containing layer 212).

[0112] Referring to Figures 1 and 2F, Method 100 optionally includes, in Operation 170, depositing a work function layer 218 on the annealed high dielectric constant layer 216A.

[0113] In some embodiments, during operation 170, a work function layer 218 is deposited on the annealed high dielectric constant dielectric layer 216A using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0114] The work function layer 218 may contain any suitable metal known to those skilled in the art. In some embodiments, the work function layer 218 contains one or more p-type metals or n-type metals. In some embodiments, the work function layer 218 contains a p-type metal. In embodiments where the work function layer 218 contains a p-type metal, the p-type metal contains any suitable high electronegativity metal nitride material. In some embodiments, the p-type metal contains one or more titanium nitride (TiN), titanium oxynitride (TiON), molybdenum nitride (MoN), molybdenum oxynitride (MoON), or niobium nitride (NbN).

[0115] In some embodiments, the work function layer 218 includes an n-type metal. In embodiments where the work function layer 218 includes an n-type metal, the n-type metal includes any suitable electropositive high-melting-point metal. In some embodiments, the n-type metal includes lanthanides, their carbides, their nitrides, alloys thereof with electropositive high-melting-point metals, titanium aluminum (TiAl), tantalum aluminum (TaAl), niobium aluminum (NbAl), or zirconium aluminum (ZrAl).

[0116] In one or more embodiments, the work function layer 218 has a thickness in the range of 2 nm or less to 3 nm or less.

[0117] Additional embodiments of the present disclosure, as shown in Figure 3, relate to a processing tool (i.e., a cluster tool) 900 for forming the described logic / memory devices and methods. The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are positioned within the central transfer stations 921, 931 and configured to move robot blades and wafers to each of the multiple sides.

[0118] The cluster tool 900 includes a number of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also called processing stations, connected to the central transfer stations 921 and 931. The various processing chambers provide separate processing areas isolated from adjacent processing stations. The processing chambers may include, but are not limited to, any suitable chambers, including pre-cleaning chambers, buffer chambers, (one or more) transfer spaces, wafer-orienter / degassing chambers, cryogenic cooling chambers, deposition chambers, annealing chambers, etching chambers, heat treatment (RTP) chambers, plasma oxidation chambers, plasma nitriding chambers, and atomic layer deposition (ALD) chambers. In one or more embodiments, the ALD chamber comprises a single chamber for depositing an interface layer on the upper surface of the channel (operation 110); depositing a hafnium-containing layer having a thickness of 5 Å or less on the interface layer (operation 120); and depositing a dipole layer on the hafnium-containing layer to a predetermined thickness (operation 130), without vacuum breaking during these operations.

[0119] In one or more embodiments, the ALD chamber comprises a single chamber for each of the following operations: depositing an interface layer on the upper surface of the channel (operation 110); depositing a hafnium-containing layer having a thickness of 5 Å or less on the interface layer (operation 120); and depositing a dipole layer on the hafnium-containing layer to a predetermined thickness (operation 130), with vacuum breaking occurring between at least one of the operations.

[0120] The specific arrangement of the processing chamber and its components may be modified depending on the cluster tool and should not be construed as limiting the scope of this disclosure.

[0121] In one or more embodiments, the cluster tool 900 includes a silicon dioxide (SiO2) chamber for depositing silicon dioxide (SiO2). The silicon dioxide (SiO2) deposit chamber in some embodiments includes an atomic layer deposit chamber, a plasma-enhanced atomic layer deposit chamber, or a space atomic layer deposit chamber. In one or more embodiments, the cluster tool 900 includes a pre-cleaning chamber connected to a central transfer station.

[0122] In the embodiment shown in Figure 3, the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of the factory interface 950. The loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, but those skilled in the art will understand that this is merely representative of one possible configuration.

[0123] The size and shape of the loading chamber 954 and the unloading chamber 956 may vary, for example, depending on the substrate being processed in the cluster tool 900. In the shown embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette in which multiple wafers are positioned within the cassette.

[0124] Robot 952 is located within the factory interface 950 and can move between the loading chamber 954 and the unloading chamber 956. Robot 952 can transfer wafers from a cassette in the loading chamber 954 to the load lock chamber 960 via the factory interface 950. Robot 952 can also transfer wafers from the load lock chamber 962 to a cassette in the unloading chamber 956 via the factory interface 950. As will be understood by those skilled in the art, the factory interface 950 may have multiple robots 952. For example, the factory interface 950 may have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960, and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.

[0125] The cluster tool 900 shown in Figure 3 has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 via load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 in which at least one robot 925 is positioned. The robot 925 is also called a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally located with respect to the load lock chambers 960, 962, processing chambers 902, 904, 916, 918, and buffer chambers 922, 924. In some embodiments, the robot 925 is a multi-arm robot capable of independently moving multiple wafers at once. In one or more embodiments, the first transfer chamber 921 includes multiple robotic wafer transfer mechanisms. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Each wafer is carried on a wafer transport blade located at the distal end of the first robotic mechanism.

[0126] After processing the wafer in the first section 920, the wafer can be passed through a passage chamber to the second section 930. For example, chambers 922, 924 may be unidirectional or bidirectional passage chambers. Passage chambers 922, 924 can be used, for example, to cool the wafer to a low temperature before processing in the second section 930, or to allow cooling or post-processing of the wafer before returning it to the first section 920.

[0127] The system controller 990 communicates with the first robot 925, the second robot 935, the first set of processing chambers 902, 904, 916, 918, and the second set of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 can be a computer including a central processing unit, memory, appropriate circuitry, and storage.

[0128] Generally, when executed by a processor, the process can be stored in the memory of the system controller 990 as a software routine that causes a processing chamber to execute the process of the present disclosure. The software routine can also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure can also be executed in hardware, such as method 100. Thus, the process may be implemented in software, and may also be executed by using, for example, a computer system in hardware as an implementation of an application-specific integrated circuit or other types of hardware, or a combination of software and hardware. When executed by a processor, the software routine transforms a general-purpose computer into an application-specific computer (controller) that controls the operation of the chamber so that the process can be executed.

[0129] Embodiments of this disclosure relate to non-temporary computer-readable media. In one or more embodiments, the non-temporary computer-readable media includes instructions, when executed by a controller of a processing chamber, that cause the processing chamber to perform an operation of one of the methods described herein. In one or more embodiments, the controller causes the processing chamber to perform an operation of method 100.

[0130] In one or more embodiments, the processing tool 900 comprises: central transfer stations 921, 931 including at least one robot 925, 935 configured to move wafers; one or more fast heat treatment (RTP) stations, decoupled plasma oxidation (DPO), or decoupled plasma nitriding (DPN) stations connected to the central transfer stations; an atomic layer deposition (ALD) station connected to the central transfer stations; an optional pre-cleaning station connected to the central transfer stations; and at least one controller connected to one or more of the central transfer stations, RTP stations, DPO stations, DPN stations, ALD stations, or optional pre-cleaning stations. In one or more embodiments, the at least one controller has at least one configuration selected from: a configuration for moving wafers between stations using robots; a configuration for performing fast heat treatment; a configuration for performing a decoupled plasma process; a configuration for controlling the flow rate of oxidation gas to the RTP or DPO station; a configuration for controlling the flow rate of nitriding gas to the RTP or DPN station; a configuration for depositing silicon oxide films by atomic layer deposition; and a configuration for pre-cleaning wafers.

[0131] To facilitate explanation, spatially relative terms such as “directly below,” “down,” “downward,” “up,” and “above” can be used to describe the relationship between one or more elements or features shown in the figure and another (one or more) elements or features. It will be understood that spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figure. For example, if the device in the figure is turned over, the element described as “below” or “directly below” the other element or feature would be oriented “above” the other element or feature. Thus, the exemplary term “down” can encompass both up and down orientations. The device may be oriented in a different direction (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used herein will be interpreted accordingly.

[0132] The terms “a,” “an,” and “the,” and similar references in the context describing the materials and methods discussed herein (in particular, in the context of the following claims), should be interpreted as encompassing both singular and plural forms unless otherwise stated herein or unless clearly contradicted by the context. The enumeration of value ranges herein is intended merely as a simple way to refer individually to each individual value falling within the range, unless otherwise stated herein, and each individual value is incorporated herein as if it were individually stated herein. All methods described herein may be carried out in any suitable order unless otherwise stated herein or unless clearly contradicted by the context. Any and all examples or illustrative language provided herein (e.g., “etc.”) are intended merely to further clarify the materials and methods and do not impose limitations on the claims unless specifically stated otherwise. Nothing in the specification should be interpreted as indicating that non-claimed elements are essential to the carrying out of the disclosed materials and methods.

[0133] Throughout this specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiments” means that any particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this disclosure. Therefore, any other expression such as “in one or more embodiments,” “in one embodiment,” “in one embodiment,” or “in an embodiment” found elsewhere in this specification does not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, the particular features, structure, material, or property are combined in any suitable manner.

[0134] Next, the present disclosure will be described with reference to the following examples. Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configuration or process steps described below. The present disclosure can also be in other embodiments and can be implemented or performed in a variety of ways. [Examples]

[0135] Comparative Example 1 A dipole rust process was performed. The dipole rust process involved forming an interface layer containing silicon oxide (SiOx) with a thickness of 8 Å on a silicon (Si) substrate, and forming a high-dielectric-constant dielectric layer containing hafnium oxide (HfOx) with a thickness of 20 Å on the interface layer. Next, a lanthanum-containing precursor and a nitrogen-containing reactant were flowed onto the surface of the high-dielectric-constant dielectric layer to deposit a lanthanum nitride (LaN) dipole layer with a thickness of 10 Å on the high-dielectric-constant dielectric layer. A capping layer containing amorphous silicon (a-Si) with a thickness of 10 Å was deposited on the dipole layer. Next, the substrate was annealed at a temperature of 1050°C to drive metal atoms into the dipole layer. Then, the capping layer and dipole layer were removed from the substrate. The formed electronic device exhibited low V and V t An increase in V and V below 200mV t Achieving adjustability required multiple annealing processes.

[0136] Comparative Example 2 A dipole-first process was performed. The dipole-first process involved forming an interface layer containing silicon oxide (SiOx) with a thickness of 8 Å on a silicon (Si) substrate. Next, a lanthanum-containing precursor and a nitrogen-containing reactant were flowed onto the surface of the interface layer, depositing a lanthanum nitride (LaN) dipole layer with a thickness ranging from 1 Å to 5 Å on the interface layer. A high-dielectric constant dielectric layer containing hafnium oxide (HfOx) with a thickness of 20 Å was deposited on the dipole layer, and the substrate was annealed at 700°C in a nitrogen (N2) atmosphere for 15 seconds using rapid thermal treatment (RTP). The formed electronic device exhibited V values ​​exceeding 200 mV. t It exhibited insufficient etch selectivity as a tunable dipole material, failing to selectively remove the silicon oxide (SiOx) interface layer without removing a portion of it, resulting in high leakage current.

[0137] Comparative Example 3 Multi-V t A dipole last process was performed. Multi-V tThe dipole last process involved forming an interface layer containing silicon oxide (SiOx) with a thickness of 8 Å on a silicon (Si) substrate, and forming a high-dielectric-constant dielectric layer containing hafnium oxide (HfOx) with a thickness of 20 Å on the interface layer. The high-dielectric-constant dielectric layer was densified using rapid heat treatment (RTP) at a temperature of 700°C in a nitrogen (N2) atmosphere for 15 seconds. Next, a lanthanum-containing precursor and a nitrogen-containing reactant were flowed onto the surface of the densified high-dielectric-constant dielectric layer, and a lanthanum nitride (LaN) dipole layer with a thickness of 10 Å was deposited on the densified high-dielectric-constant dielectric layer. A capping layer containing amorphous silicon (a-Si) with a thickness of 10 Å was deposited on the dipole layer. The capping layer and the dipole layer were removed from either the NFET side or the PFET side of the substrate, exposing the surface of the densified high-dielectric-constant dielectric layer. Dipole layers of different thicknesses were deposited on the high-dielectric-constant dielectric layers on the NFET and PFET sides of the substrate, respectively, and a capping layer was deposited on each dipole layer. Next, the substrate was annealed again at a temperature of 1050°C to drive metal atoms in from the dipole layers. Then, the capping layer and dipole layers were removed from the substrate, and a work function layer was deposited on the high-dielectric-constant dielectric layer. The formed electronic device exhibited low V and V t An increase in V and V below 200mV t Achieving adjustability required multiple annealing processes.

[0138] Example 1 A process following the operation of Method 100 was carried out. This process involved forming a p-type dipole stack and an n-type dipole stack on a semiconductor substrate. Each of the p-type and n-type dipole stacks was formed on the upper surface of a channel located between the source and drain on the semiconductor substrate. Each of the p-type and n-type dipole stacks was formed by: depositing an interface layer (silicon oxide (SiOx) layer) on the upper surface of the channel; depositing a hafnium oxide (HfOx) layer having a thickness of 5 Å or less on the interface layer; and depositing a lanthanum nitride (LaN) dipole layer on the hafnium oxide (HfOx) layer. The hafnium oxide (HfOx) layer having a thickness of 5 Å or less is continuous. Next, the deposited dipole layers were selectively etched from one of the p-type or n-type dipole stacks to increase the thickness of the dipole layer on the other of the p-type or n-type dipole stack, and multiple threshold voltages (multi-V) were applied. t An electronic device having a high dielectric constant (V) was formed. This process involved depositing a high dielectric constant (Hafnium Oxide (HfOx)) layer with a thickness ranging from 10 Å to 20 Å on a lanthanum nitride (LaN) dipole layer. The p-type and n-type dipole stacks were annealed at a temperature of 1000°C or less to drive metal atoms into the dipole layer, thereby increasing the density of the high dielectric constant layer and forming an annealed high dielectric constant layer. Finally, a work function layer was deposited on the annealed high dielectric constant layer. The formed electronic device showed an improved threshold voltage (V) compared to methods that did not involve forming a hafnium-containing layer with a thickness of 5 Å or less on the interface layer (Comparative Examples 1-3). t ) was shown. In addition, the process of Example 1 showed a flat band voltage (V) even after one cycle compared to Comparative Examples 1-3. fb The leakage current (J) showed an increase of 300mV. The formed electronic device showed a lower leakage current (J) compared to methods that do not involve forming a hafnium-containing layer with a thickness of 5Å or less on the interface layer (Comparative Examples 1-3). g The study also showed a reduction in ).

[0139] While the disclosures herein are described with reference to specific embodiments, these embodiments should be understood as merely illustrative examples of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Accordingly, the disclosure is intended to include modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. In a method for manufacturing electronic devices, The method involves forming a p-type dipole stack and an n-type dipole stack on a semiconductor substrate, wherein each of the p-type dipole stack and the n-type dipole stack is formed on the upper surface of a channel located between the source and drain on the semiconductor substrate, and the formation of each of the p-type dipole stack and the n-type dipole stack is as follows: Depositing an interface layer on the upper surface of the channel, Depositing a hafnium-containing layer on the aforementioned interface layer, wherein the hafnium-containing layer has a thickness of 5 Å or less, and Depositing a dipole layer on the aforementioned hafnium-containing layer Forming a p-type dipole stack and an n-type dipole stack on a semiconductor substrate, including A method for manufacturing electronic devices, including [a specific component].

2. The method according to claim 1, wherein the interface layer includes a silicon oxide (SiOx) layer formed on doped silicon or undoped silicon.

3. The method according to claim 1, wherein the hafnium-containing layer comprises one or more of the following: hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), nitrogen-doped hafnium oxide (HfOx), or nitrogen-doped hafnium zirconium oxide (HfZrOx).

4. The method according to claim 1, wherein the hafnium-containing layer has a thickness of 3 Å or less.

5. The method according to claim 1, wherein the deposition of the dipole layer comprises exposing the semiconductor substrate to pulses of a metal-containing precursor and pulses of reactants by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process.

6. The method according to claim 5, wherein the metal-containing precursor comprises one or more of titanium (Ti), tantalum (Ta), aluminum (Al), niobium (Nb), antimony (Sb), tellurium (Te), germanium (Ge), gallium (Ga), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), or boron (B).

7. The reactant is ammonia (NH ３ The method according to claim 5, including )

8. The method according to claim 5, wherein the dipole layer comprises lanthanum nitride (LaN) or aluminum nitride (AlN).

9. Selectively etching the deposited dipole layer from one of the p-type dipole stacks or the n-type dipole stack, and increasing the thickness of the dipole layer of the other of the p-type dipole stacks or the n-type dipole stack, thereby generating multiple threshold voltages (multiple V) ｔ The method according to claim 1, further comprising forming an electronic device having ).

10. The method according to claim 1, further comprising depositing a high dielectric constant layer having a thickness in the range of 10 Å to 20 Å on the dipole layer.

11. The method according to claim 10, wherein the high dielectric constant dielectric layer comprises one or more of the following: hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx).

12. The method according to claim 10, further comprising annealing the p-type dipole stack and the n-type dipole stack at a temperature of 1000°C or less to drive metal atoms into the dipole layer, thereby increasing the density of the high dielectric constant dielectric layer and forming an annealed high dielectric constant dielectric layer.

13. The method according to claim 12, further comprising depositing a work function layer on the annealed high dielectric constant layer.

14. Compared to a method that does not involve forming a hafnium-containing layer having a thickness of 5 Å or less on the interface layer, the threshold voltage (V) of the electronic device is higher. ｔ The method according to claim 1, which improves ).

15. Compared to a method that does not involve forming a hafnium-containing layer having a thickness of 5 Å or less on the interface layer, the leakage current (J) of the electronic device is lower. ｇ The method according to claim 1, which reduces the following:

16. In a method for manufacturing electronic devices, The method involves forming a p-type dipole stack and an n-type dipole stack on a semiconductor substrate, wherein each of the p-type dipole stack and the n-type dipole stack is formed on the upper surface of a channel located between the source and drain on the semiconductor substrate, and the formation of each of the p-type dipole stack and the n-type dipole stack is as follows: Depositing an interface layer on the upper surface of the channel, wherein the interface layer contains silicon oxide (SiOx). Depositing a hafnium-containing layer on the interface layer, wherein the hafnium-containing layer contains hafnium oxide (HfOx) and has a thickness of 5 Å or less, and Depositing a dipole layer containing lanthanum nitride (LaN) on the aforementioned hafnium-containing layer. Forming a p-type dipole stack and an n-type dipole stack on a semiconductor substrate, including A method for manufacturing electronic devices, including [a specific component].

17. The method according to claim 16, further comprising depositing a high dielectric constant dielectric layer on the dipole layer, wherein the high dielectric constant dielectric layer comprises one or more of the following: hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx).

18. The method according to claim 17, further comprising annealing the p-type dipole stack and the n-type dipole stack at a temperature of 1000°C or less to drive metal atoms into the dipole layer, thereby increasing the density of the high dielectric layer and forming an annealed high dielectric layer.

19. The method according to claim 18, further comprising depositing a work function layer on the annealed high dielectric constant layer.

20. Compared to a method that does not involve forming a hafnium-containing layer having a thickness of 5 Å or less on the interface layer, the leakage current (J) of the electronic device is lower. ｇ The method according to claim 16, which reduces )

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