Non-conductive edge termination structure for semiconductor devices, and method for manufacturing the same.

Abstract

A method for forming an edge termination structure in a semiconductor device is provided. The method includes forming an epitaxial layer on a semiconductor substrate, wherein the epitaxial layer extends laterally across an active region and an edge termination region in the device; forming a plurality of active trenches in the active region and at least one outer trench in the edge termination region, wherein each of the outer trenches and the active trenches extends vertically through at least a portion of the epitaxial layer; at least partially filling each of the outer trenches and the active trenches with a first insulating material; forming a trench by etching a region of the epitaxial layer in the edge termination region adjacent to the last of the plurality of active trenches in the active region; and at least partially filling the trench with a second insulating material to form a trench structure as an edge termination structure in the semiconductor device.

Description

[Technical Field]

[0001] References to related applications This application claims priority under 35 U.S. SC § 119 to U.S. Provisional Application No. 63 / 498,962, “Non-conducting Edge Termination Structures for a Semiconductor Device and Methods of Fabricating the Same,” filed on 28 April 2023, and the disclosures of this application are incorporated by reference in their entirety for all purposes. [Background technology]

[0002] The present invention relates to semiconductor devices and methods for manufacturing the same, and more particularly to enhanced edge termination structures used in semiconductor devices, and methods for manufacturing such structures.

[0003] Vertically conducting semiconductor devices within integrated circuits (ICs) have an active region surrounded by an edge termination region. In such vertical devices, the edges of the die always have the same or similar voltage potential as the bottom of the device, primarily due to saw damage during device singulation or the lack of a blocking junction at the edge of the device. Therefore, the edge termination region is a critical part of the device design to ensure lateral blocking of potential voltages between the active region and the edges of the die.

[0004] While the active region must withstand vertical blocking voltage, the edge termination region must withstand blocking voltage in both the lateral and vertical directions. Because the edge termination region must maintain voltage blocking capability in both the vertical and lateral directions, the design of the device's edge termination region is a critical factor in determining the device's performance and cost-effectiveness. [Overview of the project] [Problems that the invention aims to solve]

[0005] In the case of a semiconductor device that balances the charge in its active region, the requirement of "charge balance" for the last active cell of the device further complicates the design of the edge termination region. [Means for solving the problem]

[0006] The present invention significantly provides an enhanced edge termination structure for use in charge-balanced semiconductor devices, as shown in one or more embodiments. In one or more embodiments, the edge termination structure is configured to isolate the active region in the semiconductor device by surrounding it with an insulating material. Furthermore, while planar edge termination structures are more conventional, the conceptual viewpoint of the present invention provides beneficial voltage blocking in both vertical and lateral directions.

[0007] Embodiments of the present invention provide a method for forming an edge termination structure in a semiconductor device. The method includes forming an epitaxial layer on a semiconductor substrate, wherein the epitaxial layer extends laterally across an active region and an edge termination region in the device; forming a plurality of active trenches within the active region and at least one outer trench in the edge termination region, wherein each of the outer trench and the active trench extends vertically through at least a portion of the epitaxial layer; at least partially filling each of the outer trench and the active trench with a first insulating material; forming a moat by etching a region of the epitaxial layer in the edge termination region adjacent to the last of the plurality of active trenches in the active region; and at least partially filling the moat with a second insulating material to form a moat structure as an edge termination structure in the semiconductor device.

[0008] According to another embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising an active region and an edge-terminating region, wherein the edge-terminating region is laterally adjacent to the active region. The semiconductor device comprises an epitaxial layer formed on a semiconductor substrate, wherein the epitaxial layer extends laterally across the active region and the edge-terminating region. The semiconductor device further comprises a plurality of active trench structures formed within the active region and at least one active device, wherein each of the plurality of active trench structures extends vertically through at least a portion of the epitaxial layer and is at least partially filled with a first insulating material. At least one outer trench structure is formed in the edge-terminating region of the semiconductor device, wherein the outer trench structure extends vertically through at least a portion of the epitaxial layer and is at least partially filled with the first insulating material. The outer trench structure is adjacent to the last of the plurality of active trench structures in the active region. The semiconductor device further comprises a trench structure extending vertically through at least a portion of the epitaxial layer in the edge-terminating region, wherein the trench structure has sidewalls defined by the at least one outer trench structure, and the trench structure is at least partially filled with a second insulating material. The trench structure forms an edge-terminating structure in the semiconductor device configured to laterally isolate the active region from reverse voltage in the semiconductor device.

[0009] Where the term “facilitate” is used herein, an action includes performing the action, facilitating the action, assisting in the performance of the action, or causing the action to be performed. Therefore, in the context of processor implementations, an instruction executed on one processor may facilitate an action performed by an instruction executed on a remote processor by transmitting appropriate data or commands to cause or assist in the action. To avoid doubt, even if an actor facilitates an action by means other than performing the action, the action is still performed by some entity or combination of entities.

[0010] The technology of the present invention can provide substantial beneficial technical effects. While not limited to illustrative purposes, technologies according to embodiments of the present invention may provide one or more of the following advantages, among others: • To provide a compact edge termination region that minimizes additional semiconductor area consumption; To minimize additional process steps, thereby reducing overall cost and manufacturing complexity, and improving yield; To provide an edge termination region that achieves a high breakdown voltage matching the breakdown voltage in the active region and can balance the charge of the last cell in the edge termination region; · Compatibility with other edge termination features (such as inner field plates, outer field plates, junction termination extensions (JTE), variable lateral diffusion (VLD), and charged or resistive layers on the surface) used to improve the effect of the edge termination structure; · Maximizing the breakdown voltage of the edge termination region.

[0011] These and other features and advantages of the present invention will become apparent from the following detailed description of its exemplary embodiments, which should be read with reference to the accompanying drawings.

[0012] The following drawings are presented for illustrative purposes only and are not limiting. The same reference numerals, if used, indicate corresponding elements throughout the several drawings.

Brief Description of the Drawings

[0013] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating at least a portion of an exemplary integrated circuit (IC) die according to one or more embodiments of the concepts of the present invention. [Figure 2] FIG. 2 is a flow diagram illustrating at least a portion of an intermediate process step in an exemplary method for manufacturing an edge termination structure for use in a semiconductor device according to one or more embodiments of the concepts of the present invention. [Figure 3A] FIG. 3A is a schematic cross-sectional view illustrating at least a portion of an intermediate process for manufacturing an exemplary semiconductor device using a non-conducting edge termination structure according to one or more embodiments of the concepts of the present invention. [Figure 3B] Figure 3B is a schematic cross-sectional view illustrating at least a portion of an intermediate process for manufacturing an exemplary semiconductor device using a non-conducting edge termination structure, according to one or more embodiments of the concept of the present invention. [Figure 3C] Figure 3C is a schematic cross-sectional view illustrating at least a portion of an intermediate process for manufacturing an exemplary semiconductor device using a non-conducting edge termination structure, according to one or more embodiments of the concept of the present invention. [Figure 3D] Figure 3D is a schematic cross-sectional view illustrating at least a portion of an intermediate process for manufacturing an exemplary semiconductor device using a non-conducting edge termination structure, according to one or more embodiments of the concept of the present invention. [Figure 3E] Figure 3E is a schematic cross-sectional view illustrating at least a portion of an intermediate process for manufacturing an exemplary semiconductor device using a non-conducting edge termination structure, according to one or more embodiments of the concept of the present invention. [Figure 4A] Figure 4A is a schematic cross-sectional view illustrating at least some exemplary semiconductor devices using inner and / or outer field plates in various configurations, according to exemplary embodiments of the concept of the present invention. [Figure 4B] Figure 4B is a schematic cross-sectional view illustrating at least some exemplary semiconductor devices using inner and / or outer field plates in various configurations, according to exemplary embodiments of the concept of the present invention. [Figure 4C] Figure 4C is a schematic cross-sectional view illustrating at least some exemplary semiconductor devices using inner and / or outer field plates in various configurations, according to exemplary embodiments of the concept of the present invention. [Figure 4D]Figure 4D is a schematic cross-sectional view illustrating at least some exemplary semiconductor devices using inner and / or outer field plates in various configurations, according to exemplary embodiments of the concept of the present invention. [Figure 5] Figure 5 is a schematic cross-sectional view conceptually illustrating the charge balancing within a semiconductor device shown in Figure 4A, with the field plate removed, according to one or more embodiments of the present invention. [Figure 6A] Figure 6A is a schematic plan view illustrating at least a portion of the corner structure in a semiconductor device using a moat edge termination structure, and conceptually showing a method by which the capacitance of the moat structure at the corner can be determined. [Figure 6B] Figure 6B is a schematic plan view illustrating at least a portion of the corner structure in a semiconductor device using a moat edge termination structure, and conceptually showing a method by which the capacitance of the moat structure at the corner can be determined. [Figure 7A] Figure 7A is a schematic plan view conceptually illustrating at least a portion of an exemplary configuration of a corner structure in a semiconductor device using a pitted edge termination structure according to an embodiment of the present invention. [Figure 7B] Figure 7B is a schematic plan view conceptually illustrating at least a portion of an exemplary configuration of a corner structure in a semiconductor device using a pitted edge termination structure according to an embodiment of the present invention. [Figure 7C] Figure 7C is a schematic plan view conceptually illustrating at least a portion of an exemplary configuration of a corner structure in a semiconductor device using a pitted edge termination structure according to an embodiment of the present invention. [Figure 8]Figure 8 is a schematic plan view illustrating at least a portion of an exemplary corner of a semiconductor device using a pitted edge termination structure and a chamfered inner boundary trench according to one or more embodiments of the present invention. [Figure 9] Figure 9 is a schematic plan view illustrating at least some non-limiting examples of exemplary corner structures that may be used in the edge termination region of a semiconductor device using a pitted edge termination structure according to an embodiment of the present invention. [Figure 10] Figure 10 is a schematic plan view illustrating at least some non-limiting examples of exemplary corner structures that may be used in the edge termination region of a semiconductor device using a pitted edge termination structure according to an embodiment of the present invention. [Figure 11] Figure 11 is a schematic plan view illustrating at least some non-limiting examples of exemplary corner structures that may be used in the edge termination region of a semiconductor device using a pitted edge termination structure according to an embodiment of the present invention. [Figure 12] Figure 12 is a schematic plan view illustrating at least some non-limiting examples of exemplary corner structures that may be used in the edge termination region of a semiconductor device using a pitted edge termination structure according to an embodiment of the present invention. [Figure 13] Figure 13 is a schematic plan view illustrating at least some non-limiting examples of exemplary corner structures that may be used in the edge termination region of a semiconductor device using a pitted edge termination structure according to an embodiment of the present invention. [Figure 14] Figure 14 is a schematic plan view illustrating at least some non-limiting examples of exemplary corner structures that may be used in the edge termination region of a semiconductor device using a pitted edge termination structure according to an embodiment of the present invention. [Figure 15A] Figure 15A is a schematic plan view illustrating at least some non-limiting examples of exemplary corner structures that may be used in the edge termination region of a semiconductor device using a pitted edge termination structure according to an embodiment of the present invention. [Figure 15B] Figure 15B is a schematic plan view illustrating at least some non-limiting examples of exemplary corner structures that may be used in the edge termination region of a semiconductor device using a pitted edge termination structure according to an embodiment of the present invention. [Figure 16] Figure 16 is a schematic plan view illustrating at least some non-limiting examples of exemplary corner structures that may be used in the edge termination region of a semiconductor device using a pitted edge termination structure according to an embodiment of the present invention.

[0014] Please note that the elements in the figures are shown for simplification and clarity. Common, but well-known, elements that may be useful or necessary in commercially viable embodiments are not necessarily shown so as not to hinder the understanding of the illustrated embodiments. [Modes for carrying out the invention]

[0015] The principles of the present invention will be described herein in the context of exemplary edge termination structures configured to withstand blocking voltages in both lateral and vertical directions, as shown in one or more embodiments thereof, and methods for manufacturing such structures. Novel edge termination structures according to embodiments of the present invention are suitable for use in charge-balanced semiconductor devices and may have beneficial applications in power devices or power system environments for providing, for example, direct current (DC)-DC or alternating current (AC)-DC conversion. However, it should be understood that the present invention is not limited to the specific structures and / or methods illustrated and described herein. Rather, it will be apparent to those skilled in the art from the teachings herein that numerous modifications can be made to the illustrated embodiments within the scope of the claimed invention. That is, no limitations are intended, and no such limitations should be inferred, with respect to the illustrated and described embodiments herein.

[0016] Figure 1 is a schematic cross-sectional view illustrating at least a portion of an exemplary integrated circuit (IC) die 100 according to one or more embodiments of the concept of the present invention. The IC die 100 may comprise one or more vertically conducting devices and may comprise an active region 102 surrounded by an edge termination region 104. In one or more embodiments, the active region 102 may comprise an n-type epitaxial layer 106, wherein a layer of p-type material (not explicitly shown) is preferably formed adjacent to the upper surface of the epitaxial layer (depending on the type of device formed), but embodiments of the present invention are not limited to this particular configuration. For example, in some embodiments, a p-type epitaxial layer 106 may be used. As is known to those skilled in the art, the n-type material used to form the epitaxial layer 106 (which may be referred to herein as the drift region) can be formed by doping a semiconductor material (e.g., silicon) with n-type (donor) dopant elements, such as phosphorus and arsenic, at a predetermined doping concentration. Similarly, the p-type material layer can be formed by doping a semiconductor material with p-type (acceptor) dopant elements, such as boron, at a predetermined doping concentration.

[0017] In vertical conductive devices, the edges of the IC die 100 always have the same or similar voltage potential as the bottom surface of the device, primarily due to saw damage during singulation (i.e., separation) of the device, or the lack of a blocking junction at the edge of the device. Therefore, it is necessary to block not only the voltage between the top and bottom surfaces of the vertical device, but also the lateral voltage between the active region 102 of the device and the edge of the IC die 100. The edge termination region 104 is the region within the device that provides this lateral voltage blocking capability.

[0018] The active region 102 may comprise a plurality of active trench structures 108. Each of the plurality of active trench structures 108 may extend at least partially through the epitaxial layer 106 substantially vertically (in the z-direction). In one or more embodiments, the plurality of active trench structures 108 may extend through at least 25% of the epitaxial layer 106. In some embodiments, the plurality of active trench structures 108 may extend completely through the epitaxial layer 106 and within the underlying substrate (not explicitly stated but implied) on which the epitaxial layer can be formed. The first metal layer 110 may be formed above the upper surface of the plurality of active trench structures 108. In one or more embodiments, the plurality of active trench structures 108 may be used to balance the charge in at least a portion of the active region 102.

[0019] The edge termination region 104 may comprise at least one outer trench structure 112. The outer trench structure 112 may be formed substantially vertically (z-direction) through the epitaxial layer 106 at least partially, and may extend along the y-direction perpendicular to the z-direction. Preferably, the same trenching process, which may include etching, trench filling, etc., although not essential, is used to form both the multiple active trench structures 108 and the outer trench structures 112. That is, the same mask and trench etching process can be used to form both the active trench structures 108 and the outer trench structures 112, thus reducing costs.

[0020] Optionally, one or more boundary trench structures 114 may be formed in the edge termination region 104 substantially vertically (z-direction) through the epitaxial layer 106 at least partially. The boundary trench structures 114 may be spaced laterally (e.g., in the x-direction) from the outer trench structure 112 by “moat” structures 118 formed between the boundary trench structures 114 within the epitaxial layer 106. As used herein, the term “moat” is intended to broadly mean a region adjacent to an active region (e.g., 102) in which a portion of the epitaxial silicon has been removed and which is at least partially filled with insulating material. As used herein, the term “filled” (or similar terms such as “filling,” “filling,” etc.) is intended to broadly mean either completely filling a defined space (e.g., the moat structure 118) or partially filling the defined space. In other words, the defined space does not need to be completely filled; for example, it may be partially filled, or it may have voids or other spaces throughout. In one or more embodiments, the trench structure 118 may be formed as a RESURF (reduced surface field) structure.

[0021] Generally, the trench surrounds the active area, but configurations are envisioned in which the trench may exist on only some (e.g., only a few sides) of the active area, rather than on all sides. Where used herein, “surround” (plural subject) (or similar terms such as “surrounds” (singular subject)) is intended to broadly refer to an element, structure, or layer that extends around, encloses, or surrounds another element, structure, or layer, although breaks or gaps may also exist. Thus, for example, a material layer (having voids or gaps within the material layer) may “surround” another layer that surrounds it. Although not required, in one or more embodiments, the width (in the x-direction) of the outer trench structure 112 and the boundary trench structure 114 may be relatively large compared to the width (in the x-direction) of the multiple active trench structures 108. For example, in some embodiments, the width of the outer trench structure 112 is about twice (2×) the width of the plurality of active trench structures 108. Preferably, the width of the outer trench structure 112 is about 2 micrometers (μm), and the width of each of at least a subset of the plurality of active trench structures 108 is about 1 μm, but embodiments are not limited to these. This allows the outer trench structure 112 to be etched more deeply, thereby providing a beneficial process margin when forming the edge termination structure. The spacing (i.e., pitch) between adjacent active trench structures 108 may be about 4 μm, but embodiments of the present invention are not limited to these.

[0022] The trench structure 118 may be defined by a trench 120 between the outer trench structure 112 and one of the plurality of boundary trench structures 114 (the trench may be formed by removing a portion of the epitaxial layer 106 in the edge termination region 104). The vertical depth of the trench 120 in the z-direction (relative to the upper surface of the epitaxial layer 106) may generally be about the same as the vertical depth of the active trench, and preferably less than the depth of the outer trench structure 112 (e.g., 20 μm). As an example, in an exemplary IC die 100, the trench 120 and the trench structure 108 may be formed to a depth of about 20 μm, and the trench structures 112 and 114 may be formed to a depth of about 22 μm, but the embodiment is not limited thereto. An insulating layer 122 may be formed on at least the side walls and bottom surface of the trench 120. The insulating layer 122 may conformally cover the inner surface of the trench 120. Where used herein in the context of material layers or coatings, the word “conformally” (or “conformal,” or similar) is intended to mean a material layer or coating having a substantially uniform cross-sectional thickness with respect to the contour of the surface to which the material layer is applied. Where used herein, the word “covering” (or “covering,” or similar) is intended to mean an element, structure, or layer that is directly on or over another element, structure, or layer, or through one or more other intervening elements, structures, or layers.

[0023] The insulating layer 122 may extend along the sidewall of the trench 120 and may extend at least partially into the active region 102, for example, through at least one subset of the plurality of active trench structures 108. In addition or alternatively, the insulating layer 122 may extend at least partially into the edge termination region 104, for example, through a subset of at least one of the plurality of boundary trench structures 114. In one or more embodiments, the insulating layer 122 may be, for example, silicon oxynitride (SiO x N y), may also include silicon nitride (SiN), etc., but the embodiments are not limited to these.

[0024] The trench 120 may be at least partially filled with an insulating material 124, such as polyimide, another polymer, or an organic material, to finally form the trench structure 118. A standard deposition process is used to fill the trench 120. The insulating material 124 may at least partially extend over the upper surface of the IC die 100, above the upper ends of one or more active trench structures 108 of the plurality of active trench structures 108 in the active region 102 and / or one or more boundary trench structures 114 of the plurality of boundary trench structures 114 in the edge termination region 104.

[0025] The trench structure 118, comprising the insulating layer 122 and the insulating material 124, works in conjunction with the outer trench structure 112 and the boundary trench structure 114 to beneficially form an edge capacitor that can be used for edge termination. The outer trench structure 112 and the boundary trench structure 114, adjacent to the opposing side walls of the trench structure 118, enclose the edge capacitor in the edge termination region 104. The edge termination is generally either capacitive (i.e., a voltage blocked through an insulator) or may use a blocking junction in the semiconductor (e.g., a pn diode). In some embodiments, a combination of these two options may be used, where a portion of the voltage is dropped laterally (i.e., horizontally parallel to the top surface of the substrate) through a depletion region / blocking junction, and the remaining voltage is blocked by the trench structure.

[0026] The edge termination in the IC die 100 may be configured to minimize the induced charge from the edge capacitor. Charge balance in the IC die 100 may be achieved by configuring the width of the last active mesa 126 (i.e., the region of the epitaxial layer 106 between the last of the multiple active trench structures 108 in the active region 102 and the first (or only) outer trench structure 112 in the edge termination region 104) to compensate for any additional charge from the edge capacitor and the charge in the insulating material 124. The electrodes of the edge capacitor may include the sidewall of the outer trench structure 112 adjacent to the trench structure 118 and the sidewall of the boundary trench structure 114 adjacent to the trench structure 118, where the insulating material 124 serves as a dielectric layer between the two capacitor plates.

[0027] In one or more embodiments, the IC die 100 may include a second metal layer forming an inner field plate 128, which is located on at least a portion of the upper surface of the first metal layer 110 and above at least a portion of the upper surface of the insulating layer 124 of the groove (e.g., resurf) structure 118. The inner field plate 128 may include a conductive material, such as a metal. In some embodiments, the first metal layer 110 and the inner field plate 128 may be formed of the same material, but in other embodiments, they may be formed of different materials. Although the exemplary IC die 100 is shown to include two levels of metal, it should be understood that in one or more alternative embodiments, the inner field plate 128 may be formed from the second metal layer, and the inner field plate 128 may be formed as an extension of the first metal layer.

[0028] The inner electric field plate 128 may be electrically connected to at least one subset of the plurality of active trench structures 108 and / or to a voltage source (e.g., ground) and configured to control the electric field distribution in the edge termination region 104. Specifically, the inner electric field plate 128 may be configured as an electrode positioned above at least a portion of the trench structure 118 to redistribute the electric field away from the active region 102 and to mitigate electric field peaking in the edge termination region 104 and in the active region 102 adjacent to the edge termination region 104, for example, in or near the last active mesa 126. Generally speaking, the electric field plate helps to reduce the maximum electric field, achieve a desired electric field profile discernible in a defined region (e.g., trench structure 118), and increase the breakdown voltage of the device. The amount of lateral (i.e., horizontal) extension of the inner electric field plate 128 above the trench structure 118 in the x and / or y directions may be adjusted to control the electric field distribution profile in the edge termination region 104 and in the active area adjacent to the trench structure 118.

[0029] Optionally, the IC die 100 may further include an outer field plate 130 formed above at least a portion of the upper surface of the insulating layer 124, adjacent to the plurality of boundary trench structures 114. The outer field plate 130 may be electrically connected to one or more of the plurality of boundary trench structures 114 and may be configured to confine the electric field within the insulating material (e.g., insulating layer 124) of the trench structure 118. In a manner consistent with the configuration of the inner field plate 128, the amount of extension of the outer field plate 130 above the trench structure 118 (in the x and / or y directions) may be adjusted to control the electric field distribution in the edge termination region 104.

[0030] Figure 2 is a flowchart illustrating at least a portion of the intermediate processes carried out in an exemplary method 200 for manufacturing an edge termination structure for use in a semiconductor device, according to one or more embodiments of the present invention. The processes carried out in exemplary method 200 may be described herein in a particular order, but it should be understood that embodiments of the present invention are not necessarily limited to the particular order described. Furthermore, additional processes (not expressly shown) may be carried out when manufacturing a finished semiconductor device, and such additional processes may be carried out before, after, or between the processes used to form the edge termination structure according to an embodiment of the concept of the present invention.

[0031] Referring to Figure 2, the exemplary manufacturing method 200 may include processes 202 relating to the creation of one or more active region devices and / or structures, for example, processes 202 including high thermal budget processes (e.g., ion implantation, rapid thermal processing (RTP), annealing, etc.). These processes, or at least a portion of such processes, used in manufacturing the active region devices may be performed before the processes involved in manufacturing the edge-terminal structures are initiated. Next, a high aspect ratio (e.g., about 20:1) deep trench etch process 204 may be performed, followed by a process 206 including an etch stop layer. The deep trench etching process 204 and trench filling process may be used to form an active trench structure in the active region of the device (e.g., 108 in Figure 1), and / or an outer trench defining the sidewall of the trench structure (e.g., 118 in Figure 1), and optionally a boundary trench structure in the edge termination region of the device (e.g., 114 in Figure 1). Subsequently, one or more additional processes 208 involved in manufacturing the active region device and / or structure may be performed.

[0032] Next, a first metal layer process 210 may be performed. The first metal layer process 210 is used to form electrodes for providing electrical connections to the active region device. In process step 212, etching may be performed outside the last active trench structure in the active region (adjacent to the edge termination region of the device) to subsequently form a broad trench (e.g., 120 in Figure 1) which will be used as a trench edge termination structure in the device. In process 214, one or more insulating layers may be added to the edge termination region trench by conformally forming one or more insulating layers on the side walls and / or bottom surface of the edge termination region trench, for example. Next, at least a second metal layer process 216 may be optionally performed to manufacture one or more metal layers above at least a portion of the trench edge termination structure in the edge termination region of the device. These additional metal layers can be used to form an inner field plate (e.g., 128 in Figure 1) and / or an outer field plate (e.g., 130 in Figure 1) in the device.

[0033] The exemplary manufacturing method 200 can be usefully used for various different types of active-region devices (e.g., metal-oxide-semiconductor (MOS) transistors, Schottky devices, etc.). Therefore, it should be understood that the integration of edge-terminated structures with various active-region devices in accordance with the conceptual view of the present invention may include, depending on the type of active device to be formed, some of the processes required for the manufacture of the novel edge-terminated structure, which may be inserted between the processes required for the manufacture of the novel edge-terminated structure.

[0034] For example, one or more implants requiring a high thermal budget (e.g., above approximately 1000°C) may be performed at the start of the manufacturing process. The gate trench formation process may be performed either before or after the deep trench etching and filling process. Shallow implants requiring a minimum thermal budget (e.g., less than approximately 1000°C) (e.g., those that may be used to create source and drain regions in the active region of the device) may be performed after the trench filling process. Forming an active trench (e.g., 108 in Figure 1) typically has a high thermal budget (at least in part due to sacrificial oxidations and film deposition that may occur within the trench). Therefore, some of the formation of a device requiring a low thermal budget (e.g., shallow junctions) should be performed after the active trench has been formed. Deep junctions that may require a high thermal budget can be performed beforehand.

[0035] Figures 3A to 3E are schematic cross-sectional views illustrating at least a portion of an intermediate process for manufacturing a semiconductor die 300 using a non-conductive edge-terminated structure according to one or more embodiments of the present invention. While Figures 3A to 3E may be directed toward the manufacture of a Schottky device, it should be understood that embodiments of the present invention are not limited to the formation of Schottky devices. Rather, as will be apparent to those skilled in the art from the teachings herein, conceptual aspects of the present invention can be used to form a variety of other semiconductor devices, including MOS transistors and the like.

[0036] Referring to Figure 3A, an exemplary deep trench etch process according to one or more embodiments is shown. More specifically, the semiconductor die 300 may include a substrate 302, which may be doped with n-type or p-type impurities at known dopant concentration levels. An epitaxial layer 304 (including, for example, silicon (Si), silicon carbide (SiC), etc.), which may also be referred to herein as a drift region, may be formed on at least a portion of the substrate 302. The epitaxial layer 304 may be formed using a standard epitaxial process. For example, an n-type epitaxial layer 304 may be formed by doping a semiconductor material (e.g., silicon) with an n-type (donor) dopant element at a predetermined doping concentration. Similarly, a p-type epitaxial layer 304 can be formed by doping a semiconductor material with a p-type (acceptor) dopant element at a predetermined doping concentration.

[0037] The semiconductor die 300 may include an edge termination region 306 on which an edge termination structure according to an embodiment of the present invention is formed, and an active region 308 on which one or more active devices (e.g., Schottky devices, MOSFETs, etc.) may be formed. The edge termination region 306 preferably includes at least one outer trench 310 and optionally at least one boundary trench 312. The active region 308 may include a plurality of active trenches 313. Each of the plurality of trenches extends at least partially substantially vertically (i.e., perpendicular to the upper surface of the substrate 302) into or through the drift region 304, and in one or more embodiments, may partially extend into the substrate 302.

[0038] The outer trench 310 may also be considered a “boundary” trench because it is located in the edge-terminal region of the device. Therefore, in this specification, the outer trench 310 may be referred to as an “inner boundary trench,” and the boundary trench 312 may be referred to as an “outer boundary trench.” These terms may be used interchangeably throughout the specification.

[0039] In one or more embodiments, the trenches 310, 312, and 313 may be formed using a high aspect ratio deep trench etching process, such as deep reactive ion etching (DRIE). Advantageously, the same trench mask and etching process may be used to form trenches in both the edge-terminal region 306 and the active region 308. In the case of the trench etching process, a trench mask including a photoresist mask or a hard mask (e.g., a thin film of silicon dioxide (SiO2) and / or silicon nitride (SiN) patterned using a standard photolithography process) may be used. The outer trench 310 may be formed to the same dimensions as the active trench 313, but in one or more embodiments, the outer trench 310 (and the boundary trench 312, if present) may be formed wider (horizontally) than the active trench 313. This allows the outer trench 310 to be etched more deeply, resulting in a larger process margin for forming the trench structure used in the edge termination structure, since the trench structure must not be deeper than the outer trench 310. For example, in some embodiments, the width (in the horizontal direction) of each of at least one subset of the plurality of active trenches 313 may be about 1 μm, and the width of the outer trench 310 may be about 2 μm, but the concept of the present invention is not limited to any particular dimensions of the trench.

[0040] The last mesa 314 in the active region 308 may be defined as the region of the epitaxial layer 304 between the last active trench of the plurality of active trenches 313 and the outer trench 310 in the edge-terminal region 306. In one or more embodiments, the width of the last mesa 314 is configured to beneficially control (i.e., optimize) the charge balance within the last mesa so as to compensate for the difference in charge resulting from the trench structure (to be formed between the outer trench 310 and the boundary trench 312) in the edge-terminal region 306. Optionally, the boundary trench 312 defines the outer boundary of the trench structure. If the boundary trench 312 is omitted, the outer trench of an adjacent die (before dicing) formed on the same wafer substantially becomes the boundary trench for defining the width of the trench structure. Although only one boundary trench 312 is shown in the exemplary embodiment of Figure 3A, it should be understood that, according to several embodiments, one or more additional “dummy” boundary trenches may be formed outside the boundary trench adjacent to the edge 315 of the semiconductor die 300.

[0041] Referring to Figure 3B, an exemplary trench filling process according to one or more embodiments is illustrated. Specifically, on the sidewall and bottom surfaces of each of the semiconductor die 300 and at least one subset of the plurality of active trenches 313, the outer trench 310 and the boundary trench 312 may be smoothed, preferably with a sacrificial oxide film, to remove etch damage or other defects. The trenches are then at least partially filled with one or more insulating layers 316 (e.g., SiO2) which may include air gaps. Note that the first insulating layer 316 deposited in the trench may be used as an etch stop layer for the subsequent etching process.

[0042] Although not explicitly stated (but implied), the trench filling process may also incorporate the deposition of layers introducing fixed charges to form a charge balance structure. That is, one or more insulating layers 316 may include one or more fixed charge layers. For example, alumina (Al2O3) with a net negative static charge may be deposited in at least one subset of the multiple active trenches 313, for example, using an atomic layer deposition (ALD) process. Alternatively, in the case of a device using an n-type epitaxial layer 304, a thinly doped epitaxial layer may be grown on the sidewalls of the trenches before filling, or p-type seeds (i.e., dopants) may be diffused through the trench sidewalls into mesas (e.g., mesa 314) between adjacent active trenches 313 prior to the trench filling process.

[0043] The outer trench 310 and the boundary trench 312 may be formed simultaneously in the active trench 313 using the same process. In this configuration, the outer trench 310 and the boundary trench 312 may have the same fixed charge as the active trench 313. Using the same process to form the outer trench 310 and the boundary trench 312 as the active trench 313 may have advantages, at least from a cost standpoint. However, it should be understood that embodiments in which the outer trench 310 and the boundary trench 312 are treated differently from the active trench 313 are conceivable, particularly when it is desirable to avoid adding a fixed charge to the outer trench 310 and the boundary trench 312, or when it is desirable to form the outer trench 310 and the boundary trench 312 having different fixed charges (or no fixed charge) relative to the active trench 313. Once filled, each of the trenches 310, 312, and 313 may be referred to herein as a “trench structure,” which may be used interchangeably with the word “trench” depending on the context in which the word is used.

[0044] After the trench filling process, a portion of the insulating layer material 316 may extend laterally (i.e., horizontally) over at least a portion of the upper surface of the epitaxial layer 304. This portion of the insulating layer material extending over the upper surface of the epitaxial layer 304 may be removed, for example, by chemical mechanical polishing (CMP) and / or etching (wet etching and / or dry etching), so that the upper surface of the semiconductor die 300 is substantially flat. Alternatively, the insulating layer 316 extending over the upper surface of the epitaxial layer 304 may be patterned and partially etched (for example, using photolithography) according to one or more embodiments, and used as part of the device structure.

[0045] Referring to Figure 3C, a metallization process according to one or more embodiments is shown. The metallization process may be used to complete the active region structure by providing electrical connections (e.g., electrodes, wiring traces, etc.) to one or more devices formed in the active region 308. As used herein, the word “connect” (or “connect” or similar words, e.g., “contact” or “contact”) is intended to mean a physical and / or electrical connection between two or more elements, which may include other intervening elements. As used herein, the word “and / or” encompasses any and all combinations of one or more of the associated enumeration items.

[0046] For illustrative purposes only and not limited thereto, when forming a Schottky device, the metallization process may include depositing a first metal layer 318 on the upper surface of the active region 308 (e.g., including the upper surface of the active trench structure 313 and the upper surface of the mesa (e.g., 314) between adjacent active trench structures). At least a portion of the first metal layer 318 may be patterned and configured to function as a Schottky barrier layer of the device. In one or more embodiments, the first metal layer 318 may extend (horizontally) over a portion of the upper surface of the epitaxial layer 304 in the edge termination region 306 (including the upper surface of the outer trench structure 310). However, in the illustrated exemplary embodiment, the first metal layer 318 does not extend above the boundary trench structure 312, and therefore at least a portion of the upper surface of the epitaxial layer 304 between the outer trench 310 and the boundary trench 312 is exposed. In this specification, the term “exposed” (or “exposed” or similar) may be used to describe the relationships between elements and / or intermediate processes in the manufacturing of a semiconductor device, but does not necessarily require that a particular element be exposed in the finished device. Similarly, the term “not exposed” may be used to describe the relationships between elements and / or intermediate processes in the manufacturing of a semiconductor device, but does not necessarily require that a particular element be not exposed in the finished device.

[0047] A thin insulating layer 320 (for example, about 0.1 μm thick, but the embodiments are not limited thereto) may be formed above the upper surface of the die 300 (including at least a portion of the upper surface of the first metal layer 318 in the active region 308, and at least a portion of the upper surface of the epitaxial layer 304 and the first metal layer 318 in the edge termination region 306). This thin insulating layer 320 may include silicon dioxide (or an alternative insulating material) formed by, for example, a deposition process, and may be used to protect the first metal layer 318 from subsequent processing and / or as an adhesion layer or stress relief layer for subsequent layers that may be provided on the first metal layer.

[0048] The first metal layer 318 and the thin insulating layer 320 may act as masks to protect the active area 308 during subsequent etching of the trench structure, as further detailed. During the trench etching process, the outer trench 310 and the boundary trench 312 preferably act as etch stops to define the sidewalls of the trench structure. When isotropic etching (i.e., a process that selectively etches in both the transverse and longitudinal directions) is used, the isotropic etching removes silicon beneath the metal layer and does not stop until the etchant reaches the outer trench 310, so the first metal layer 318 can be partially extended into the edge termination area 306 between the outer trench 310 and the boundary trench 312 to form an electric field plate. When isotropic etching is used, the first metal layer 318 will preferably cover all or at least part of the last mesa 314 and the outer trench 310. It should be noted that it is possible to form the trench structure before the metallization process, provided that a suitable trench-filling material is used that can withstand the processes associated with the deposition and etching of the metal.

[0049] Referring to Figure 3D, an exemplary trench etching process is shown according to one or more embodiments. Specifically, a trench 322 may be etched within the edge termination region 306. The trench 322 may be formed by removing a portion of the epitaxial layer 304 between the outer trench 310 and the boundary trench 312, preferably using an isotropic deep trench etching process. Typically, deep trench etching uses anisotropic etching to prevent lateral (i.e., lateral or horizontal) etching when a feature is etched into silicon. However, when forming the trench 322 in the semiconductor die 300, the outer trench 310 and the boundary trench 312 act as etch stops to ensure that the dimensions of the trench are precisely defined, thereby providing a beneficial option for using isotropic etching. By forming the groove 322 using isotropic etching, a portion of the first metal layer 318 extending above the upper surface of the edge termination region 306 remains, thereby making it possible to form a metal electric field plate in the edge termination region where a portion of the groove 322 overlaps.

[0050] It should be noted that the width and depth of the trench 322 are functions of one or more factors, such as the desired voltage blocking requirement of the device, the length of the electric field plate above the trench 322 (i.e., extension), and the properties of one or more materials used to line and / or fill the trench 322. Preferably, the depth of the trench 322 (in the vertical direction) may be close to the depth of the outer trench 310 and the boundary trench 312. When an isotropic etch is used to form the trench 322, the etch may remove the lower part of the outer trench 310, which is undesirable, and therefore the depth of the trench should not be greater than the depth of the outer trench 310. At least for this reason, it is advantageous (though not strictly necessary) to make the outer trench 310 and the boundary trench 312 deeper than the active trench 313. As previously stated, the outer trench 310 and the boundary trench 312 can be etched deeper by widening them. In one or more embodiments, the width of the outer trench 310 and the boundary trench 312 is at least twice the width of the active trench 313 (for example, about 1 μm for the active trench 313 and at least about 2 μm for the outer trench 310 and the boundary trench 312), but embodiments are not limited to any specific arbitrary ratio of the width of the outer trench 310 and the boundary trench 312 to the width of the active trench 313.

[0051] In one or more exemplary embodiments, the extension of the first metal layer 318 above the (horizontal) trench 322 may be approximately equal to the (vertical) depth of the trench 322. For example, the depth of the trench 322 may be approximately 20 μm, and the extension of the first metal layer 318 above the trench 322 may be approximately 18 μm, but the concept of the present invention is not limited to any particular dimensions of the trench 322 and / or the horizontal extension of the first metal layer 318 above the trench 322. The trench 322 may extend vertically through the epitaxial layer 304 into the substrate 302 and be partially etched into the substrate 302, but embodiments of the present invention envision a case where only the epitaxial layer 304 is partially etched without the trench 322 extending into the substrate 302.

[0052] Referring to Figures 3D and 3E, exemplary trench filling processes are shown according to one or more embodiments. Specifically, a first insulating layer or dielectric layer 324 may be formed on the exposed inner surface of the trench 322 (including the side walls and bottom surface of the trench 322) and on the exposed surfaces of the extended portions of the first metal layer 318 and the thin insulating layer 320, for example, by a deposition process. The first insulating layer 324 may conformally cover the exposed surfaces of the trench 322, the first metal layer 318, and the thin insulating layer 320. The first insulating layer 324 may include, for example, silicon oxynitride. The trench 322 may then be at least partially filled with a second insulating layer 326 on at least a portion of the exposed surfaces of the first insulating layer 324. The second insulating layer 326 may be formed not only within the trench 322, but also on the upper surface of the first insulating layer 324 which extends horizontally outside the defined trench 322, for example, above the first metal layer 318, so as to partially extend within the active region 308. The second insulating layer 326 may include, for example, polyimide, but embodiments of the present invention are not limited thereto. In one or more embodiments, the first insulating layer 324 and the second insulating layer 326 may include the same one or more materials, but in some embodiments, the first insulating layer 324 and the second insulating layer 326 may include different materials.

[0053] In the case of a typical power device, it may be known to have a silicon dioxide layer on a metal, followed by a silicon nitride or silicon oxynitride layer, followed by polyimide. These same materials may be used in integration according to the conceptual viewpoint of the present invention. For example, in some embodiments, silicon dioxide may be deposited before the etching process (however, the silicon dioxide layer may also be deposited after the etching). After the etching process, a layer of silicon oxynitride may be deposited, followed by the deposition of polyimide.

[0054] As shown in Figure 3E, an optional second metal layer 328 may be formed on at least a portion of the first metal layer 318 in the active region 308 and on at least a portion of the upper surface of the second insulating layer 326, extending laterally within the edge termination region 306. The extended portion of the second metal layer 328 may be used to form a second electric field plate 330 above the trench 322. In embodiments where the first metal layer 318 does not extend above the trench 322, this second metal layer 328 may function as the sole electric field plate. By using two electric field plates 318 and 330, with the upper electric field plate 330 further extending above the trench region in the edge termination region 306, it is possible to improve the curvature of the electric field as it transitions from the vertical direction in the active region 308 to the lateral direction (i.e., horizontal direction) across the trench 322 in the edge termination region 306.

[0055] The upper surface of the second insulating layer 326 above the trench 322 is shown to be planar with the upper surface of the second insulating layer outside the trench area, but there may be depressions on the upper surface of the second insulating layer 326, represented by the dotted contour line 332. These depressions 332 on the upper surface of the second insulating layer 326 above the trench 322 may be caused, for example, by the trench filling process. That is, the upper surface of the second insulating layer 326 in the trench 322 is not necessarily flat, and therefore the second metal layer 328, which may follow the contour of the upper surface of the second insulating layer 326, may be non-flat. Consequently, the edges of the second metal layer forming the second electric field plate 330 may follow these depressions 332 on the upper surface of the second insulating layer 326, thereby affecting the electric field distribution in the trench area to some extent. Forming such depressions 322 in the trench filling process to reduce the height of the metal electric field plate can be beneficial in optimizing the electric field curvature.

[0056] As further described in conjunction with the exemplary embodiments shown in Figures 4B to 4D, the conceptual aspect of the present invention envisions forming an electric field plate on the outer surface of the trench 322 adjacent to the boundary trench 310 using the first metal layer 318 and / or the second metal layer 328.

[0057] For illustrative purposes only and without limitation or generality, Figures 4A–4D are schematic cross-sectional views illustrating at least a portion of exemplary semiconductor devices using various configurations of inner and / or outer field plates in the edge termination region of the device according to embodiments of the present invention. Certain elements provided in the semiconductor device, such as active trench structures, edge trench structures, external trench structures, etc., may be formed in a manner consistent with corresponding elements already described herein, and therefore further details are omitted for clarity of the description.

[0058] Figure 4A illustrates an exemplary semiconductor device 400, according to several embodiments, configured such that the second metal layer 328 forms a single inner electric field plate. Specifically, the semiconductor device 400 includes the first metal layer 318 formed adjacent to the upper surface of the active region 308. Unlike the exemplary semiconductor device 300 shown in Figure 3E, the first metal layer 318 does not extend into the edge-terminating region 306, but rather terminates in the outer trench 310 at the edge of the active region 308. The second metal layer 328 may be formed on at least a portion of the upper surface of the first metal layer 318 and is configured to extend laterally on the second insulating layer 326 above a portion of the trench structure in the edge-terminating region 306 (defined, for example, by the trench 322 shown in Figure 3D). This extension of the second metal layer 328 above the trench structure functions as a first inner electric field plate in the absence of the extension of the first metal layer 318 above the trench structure.

[0059] Referring to Figure 4B, an exemplary semiconductor device 420 is shown, comprising an inner and outer field plate formed from a second metal layer 328 extending laterally from both the outer trench 310 and both ends of the boundary trench 312 of the trench, according to several embodiments. More specifically, the semiconductor device 420 is configured such that, similar to the semiconductor device 400 in Figure 4A, the first metal layer 318 does not extend into the edge termination region 306, but rather terminates in the active region 308 adjacent to the outer trench 310. A first portion of the second metal layer 328 may be formed on at least a portion of the first metal layer 318 and extend laterally (i.e. horizontally) on the second insulating layer 326 above a portion of the trench structure adjacent to the outer trench 310 in the edge termination region 306, forming a first inner field plate.

[0060] In a similar manner, the semiconductor device 420 may be further configured such that a second portion of the second metal layer 328 is formed on at least a portion of the epitaxial layer 304 in the edge termination region 306 and above the second insulating layer 326 adjacent to the boundary trench 312. Preferably, the second portion of the second metal layer 328 extends laterally above the trench structure from the end of the boundary trench 312 toward the end of the outer trench 310 of the trench structure. The extension of the second metal layer 328 above the trench structure forms a first outer electric field plate. The amount of extension of the first and second portions of the second metal layer 328 above the trench structure may be controlled to achieve a desired electric field distribution in the trench structure. However, the first and second portions of the second metal layer 328 are not electrically connected to each other.

[0061] Figure 4C illustrates an exemplary semiconductor device 440 comprising a first inner field plate and a first outer field plate formed from the first metal layer 318 and a second inner field plate formed from the second metal layer 328, according to several embodiments. Specifically, the semiconductor device 440 is configured such that the first metal layer 318 is formed above the active trench 313 in the active region 308 and above at least a portion of the epitaxial layer 304 in the edge termination region 306. In this exemplary embodiment, a first portion of the first metal layer 318 extends laterally (i.e., horizontally) from the active region 308 above the outer trench 310 and above a portion of the trench structure in the edge termination region 306 to form the first inner field plate. Similarly, the second portion of the first metal layer 318 extends laterally above the epitaxial layer 304, above the boundary trench 312, and above a portion of the trench structure in the edge termination region 306, forming a first outer electric field plate. Thus, the first metal layer 318 forms a first inner electric field plate and a first outer electric field plate above portions of the trench structure, originating from the ends of the outer trench 310 and the boundary trench 312, respectively. A portion of the upper surface of the second insulating layer 326 in the trench structure may be left without any superimposed electric field plates. The amount of extension of the first and second portions of the first metal layer 318 above the trench structure may be selectively varied to optimize the electric field distribution in the trench structure.

[0062] The semiconductor device 440 may be further configured to have a second metal layer 328 formed on at least a portion of the first metal layer 318 and extending laterally over the second insulating layer 326 above a portion of the trench structure in the edge termination region 306, in a manner consistent with the arrangement of the second metal layer 328 shown in Figure 3E. This extension of the second metal layer 328 above the trench structure may function as a second inner field plate. In this exemplary embodiment, the second metal layer 328 does not extend over the second insulating layer 326 from the end of the boundary trench 312 of the trench structure, but this arrangement is similarly envisioned in other embodiments of the present invention.

[0063] Referring to Figure 4D, an exemplary semiconductor device 460 is shown having a first outer field plate formed from the second metal layer 328, and a first inner field plate and a second inner field plate formed from the first metal layer 318 and the second metal layer 328, respectively. Specifically, the semiconductor device 460 may be configured such that the first metal layer 318 is formed above the active trench 313 in the active region 308, and extends laterally (i.e., horizontally) from the active region 308 above the outer trench 310 and above a portion of the trench structure in the edge termination region 306 to form the first inner field plate. This is similar to the formation of the first inner field plate shown in the semiconductor device 440 in Figure 4C. In the exemplary semiconductor device 460, the first metal layer 318 does not extend above the trench structure from the boundary trench 312 side.

[0064] In the semiconductor device 460, the first portion of the second metal layer 328 may be formed on at least a portion of the first metal layer 318, and may extend laterally on the second insulating layer 326 above a portion of the trench structure in the edge termination region 306 adjacent to the outer trench 310, forming a second inner field plate. The semiconductor device 460 may further be configured such that the second portion of the second metal layer 328 is formed on at least a portion of the epitaxial layer 304 in the edge termination region 306 and above the second insulating layer 326 adjacent to the boundary trench 312. Preferably, the second portion of the second metal layer 328 extends laterally above the trench structure from the end of the boundary trench 312 toward the end of the outer trench 310. The extension of the second portion of the second metal layer 328 above the trench structure forms a first outer electric field plate. The amount of extension of the first and second portions of the second metal layer 328 above the trench structure may be selectively varied to achieve a desired electric field distribution in the trench structure.

[0065] By using a moat termination structure (e.g., including a moat 322 and material lining and / or filling the moat) created either by a single trench 310 or by a boundary of multiple separate trenches 310, 312, a charge imbalance may occur in the last mesa 314 (see Figure 3E) of the active region 308. This charge imbalance may reduce the breakdown capability of the device. One solution to this charge imbalance, according to one or more aspects of the concept of the present invention, is to selectively vary the width of the last mesa 314 (i.e., the epitaxial layer 304 between the last of the multiple active trench structures (313 in Figure 4C) in the active region 308 and the first (or only) outer trench 310 in the edge termination region 306 adjacent to the active region 308) to compensate for the different charge received by this last mesa 314.

[0066] Generally, in a charge balanced device, there is a charge balance region 、 The charge Q in the charge balance region P is the same as the charge Q in the mesa region N FIG. 5 is a schematic cross-sectional view showing at least a portion of the exemplary semiconductor device of FIG. 4A without an electric field plate, where each of the plurality of active trench structures 313 incorporates therein a fixed charge Q N that is the same as Q P in the mesa region, thereby achieving charge balance within the device. However, the last mesa 314 adjacent to the trench structure is no longer surrounded by the trench having the charge Q P and rather 、 may have a different charge Q PE associated therewith. The boundary trench charge Q PE may be the same as the charge Q P associated with the other active trench structures 313, but this is not necessarily the case due to differences in process, dimensions, or other factors. Moreover, the one or more insulating layers filling the trench 322 may also have a fixed charge associated with the insulating layer that is specific to itself depending on the type of material filling the trench. As a result of these other factors, the last mesa 314 in the active region 308 may have a charge Q N different from the charge Q NE associated with the other mesas in the active region.

[0067] The charge Q in the boundary trench 310 PE and the fixed charge Q in the trench moat are not equal to the charge Q NE in the last mesa 314, charge balance may not be achieved, and there is a high likelihood that the breakdown voltage will decrease as a result (i.e., QPE +Q moat ≠Q NE ) 。 In this case, the charge Q of the last mesa NE The charge in can be modified according to one or more embodiments to adjust this difference in charge. This can be achieved in several ways, including changing the width (in the horizontal (x) direction or lateral direction) of the last mesa 314, among other approaches (e.g., changing the material in the last mesa 314 or trench structure, changing the dimensions of the trench structure, etc.). For example, Q PE +Q moat >Q NE In this case, the width of the last mesa 314 can be increased, thereby increasing the charge associated with the last mesa. Similarly, Q PE +Q moat NE In this case, the width of the last mesa 314 can be reduced to decrease the charge associated with the last mesa.

[0068] A further consideration is that the trench structure essentially functions as a capacitor that can induce an additional charge on the inside edge of the outer trench 310. This induced charge is proportional to the applied voltage according to the equation Q=CV (where Q is the charge in coulombs, C is the capacitance in farads, and V is the potential difference in volts between the electrodes of the capacitor). The capacitance is proportional to the width of the trench structure (in the horizontal (x) direction) and the relative dielectric constant of one or more insulating materials within the trench (e.g., the first insulating layer 324 and the second insulating layer 326), and the following equation can be obtained:

number

[0069] At the device corner, the area of ​​the trench increases with respect to the active area, and therefore the capacitive effect (and the influence of fixed charges within the trench) increases. Capacitance C at the device corner CORNER This can be determined according to the following formula:

number

[0070] Figure 6B is a simplified schematic plan view illustrating a magnified corner of an exemplary semiconductor device using a pitted edge termination structure according to one or more embodiments of the present invention. Referring to Figure 6B, the capacitance of the pit 322 is preferably reduced in order to reduce the effect of charge at the corner of the device. That is, the ln(R2 / R1) term in equation (2) above may be increased, which can be achieved by increasing R2 and / or decreasing R1 (i.e., the ratio of R2 / R1 should be maximized). This essentially means that a larger pit width "w" is required. Since increasing the width of the pit 322 increases the die area, thereby increasing the overall size and cost of the die, it may be more effective to offset the capacitance effect of the pit structure by changing the width of the final mesa 314 instead.

[0071] Without limitation or loss of generality, as an example, Figures 7A–7C are plan views conceptually illustrating at least some of different exemplary configurations of corner structures in semiconductor devices using a trench edge termination structure according to embodiments of the present invention. In Figures 7A–7C, at least one outer boundary trench structure (e.g., 312 in Figures 4A–4D) is not shown for clarity. However, it is assumed that one or more outer boundary trench structures may be optionally used in actual devices.

[0072] Generally, a series of parallel active trench structures 313 may be formed in the active region 308 of the device, as shown in Figure 7A, and may be surrounded (i.e., extending around) an inner boundary trench structure 702. The inner boundary trench structure 702 may be configured to have a straight section facing the end of the semiconductor device 700 and a chamfered section 724 at the corner of the device, as in the embodiment of the semiconductor device 720 shown in Figure 7B. As described later in conjunction with Figure 11, in a top view, the chamfered inner boundary trench structure 702 allows the horizontal width WC of the last mesa 726 at the corner (i.e., the epitaxial layer / drift region between the last active trench structure 722 and the inner boundary trench structure 702), adjacent to the chamfered portion 724, to be narrower than the horizontal width WD along the edge of the last mesa 726 in order to at least partially compensate for the charge imbalance caused by the trench 322. Alternatively, although not explicitly shown in Figure 7B, the semiconductor device 720 may be configured such that the last mesa 726 has a substantially constant horizontal width along the side and corner regions, as further described in conjunction with Figure 12.

[0073] In this embodiment, the last active trench structure 722 extends close to the inner end of the inner boundary trench structure 702 in both a first and a second direction, where the first and second directions are parallel to the upper surface of the substrate of the semiconductor device 720 (i.e., horizontal plane), and the second direction intersects the first direction. The other active trench structures 313 may be parallel to one another, and all extend in either the first or the second direction.

[0074] Figure 7C illustrates an exemplary semiconductor device 730 according to one or more embodiments of the present invention. The semiconductor device 730 may utilize multiple rings of active mesa 314 defined by concentric rings of active trench structures 722, 732, 734, and 736 formed in the active region 308 and adjacent to the inner boundary trench structure 702. A pair of adjacent active trench structures (e.g., 732 and 734) has an active mesa 314 between them. Four concentric active trench structures are illustrated, but the embodiments are not limited thereto. The innermost ring of an active trench structure 736 may at least partially enclose (i.e., extend around) a second plurality of active area trench structures (internal active area trench structures) 313. Each of the second plurality of active area trench structures 313 may be parallel to one another.

[0075] One or more of the concentric rings of active trench structures 722, 732, 734, and 736 may optionally have breaks or gaps 738 formed therein, which may be beneficial in the manufacturing and / or charge balancing of the device. Specifically, the use of long trenches puts stress on the device, resulting in wafer warping and other manufacturing difficulties; therefore, this stress can be reduced by providing gaps 738 in the trench structure. A further advantage of the gaps 738 in the plurality of active trench structures 722, 732, 734, and / or 736 is that they help facilitate the flow of current between the active trench structures, thereby mitigating current concentration and potentially reducing hot spots in the device, because heat can dissipate more effectively (since the plurality of active trench structures may be filled with insulating materials that may have poor thermal conductivity). In extreme cases, islands of charge equilibrium regions are superior to striped structures.

[0076] Figure 8 is a schematic plan view illustrating at least a portion of the corners of a semiconductor device 800 using a trench edge termination structure according to one or more non-limiting embodiments of the present invention. As shown in Figure 8, the semiconductor device 800 comprises an inner boundary trench structure having a straight portion 802 along the edge of the device 800 and one or more chamfered portions 804 located at one or more corresponding corners of the device 800. The dimensions indicated in Figure 8 are illustrative and should be understood to mean that embodiments of the concept of the present invention are not limited to any particular dimensions.

[0077] Figures 9–16 are schematic plan views illustrating at least some non-limiting examples of exemplary corner structures that may be used in the edge termination region of a semiconductor device using a pitted edge termination structure according to embodiments of the present invention. It should be understood that these corner structure designs are provided only to demonstrate different ways of adapting pitted edge termination technology in accordance with the conceptual views of the present invention for implementing enhanced charge balance within a semiconductor device in various applications and systems. Various other designs of corner structures used in the edge termination region of a semiconductor device using a pitted edge termination structure will be apparent to those skilled in the art in light of the teachings herein.

[0078] Referring to Figure 9, a semiconductor device 900 using a pit edge termination structure 902 according to one or more embodiments is shown. Note that the outer boundary of the pit edge termination structure 902 is omitted in Figure 9 for clarity. In this embodiment, the horizontal width WB of the last active mesa 904 (i.e., the material between the inner boundary trench structure 702 and the last active trench structure 722) can be smaller than the horizontal width WA of the mesa 314 between the other active area trench structures 313, taking into account the effects of charges in the pit edge termination structure 902 and / or fixed charges associated with the inner boundary trench structure 702.

[0079] In this exemplary embodiment, the active area trench structures 313 are parallel to each other in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction. The active area trench structures 313 extend continuously into the inner boundary trench structure 702 without gaps in the first horizontal direction, but the embodiment is not limited thereto. 、 Charge Q at wider edge termination PE This may be most suitable when there is no other option.

[0080] Referring to Figure 10, the trench structure in the semiconductor device 1000 according to several embodiments may have a certain capacitive charge and associated fixed charge Q PE Considering that this may be the case, it may be desirable to provide a gap (e.g., gaps "C" and "D") between the end of each / last active trench structure 722 of at least one subset of the multiple active area trench structures 313 and the inner boundary trench structure 702, and / or change the width WB of the last mesa 904 with respect to the width WA of the active mesa 1002 adjacent to the last mesa 904.

[0081] It should be noted that because the corners of the semiconductor device 1000 may have different compensating charges, the horizontal width of the gap "D" between the end of the last active area trench structure 722 (i.e., the active trench structure closest to the corner) and the inner boundary trench structure 702 may differ from the horizontal width of the gap "C" between the other active area trench structures 313 and the inner boundary trench structure 702.

[0082] In Figure 11, semiconductor devices 1100 according to several embodiments may be configured to have edge curvature (which can be defined as the radius of curvature of the outer boundary trench structure 312 at the corner of the semiconductor device 1000, defining the outer edge of the trench structure 1102), and this edge curvature can be increased by using a small chamfered section 1104 joining adjacent sides of the inner boundary trench structure 702. In some embodiments, the chamfered section 1104 may be configured to have an angle of about 45 degrees (i.e., angle θ = 45 degrees) with respect to the adjacent sides of the inner boundary trench structure 702, but embodiments of the present invention are not limited to this particular angle or shape. For example, the chamfered portion 1104 may be configured to have an angle θ of less than 45 degrees (e.g., about 40 degrees, about 30 degrees, or less), or the chamfered portion 1104 may be configured to have an angle θ greater than 45 degrees (e.g., about 50 degrees, about 60 degrees, or greater). This embodiment is similar to the exemplary embodiment of the corner structure 800 in the exemplary semiconductor device 800 shown in Figure 8.

[0083] According to one or more embodiments, the widths of the gaps "C" and "D" between the active area trench structures 313, 722 and the inner boundary trench structure 702, when viewed in a plan view (i.e., horizontal plane), can be adjusted to optimize the charge balance in the semiconductor device 1100. Alternatively or additionally, the horizontal width WB of the last mesa 904 can be adjusted relative to the horizontal width WA of the mesas 314 between the other active area trench structures 313 to optimize the charge balance in the semiconductor device 1100.

[0084] In Figure 12, at least a portion of the exemplary semiconductor device 1200 is shown according to one or more embodiments. The semiconductor device 1200 includes a corner structure arrangement, where the horizontal width WB of the last mesa 904 (i.e., the material between the last active trench structure 722 and the inner boundary trench structure 702) is substantially constant. Note that with this configuration, all four sides are identical, at least in terms of charge balance.

[0085] The multiple active trench structures 313, 722 may be configured such that the last active trench structure 722 extends along the inner edge of the inner boundary trench structure 702 in both the first and second horizontal directions, similar to the multiple active trench structures 313 shown in Figure 7B, while the remaining active trench structures 313 may be configured to be parallel to each other and extend in either the first or second horizontal direction when viewed from above.

[0086] Referring to Figure 13, at least a portion of the exemplary semiconductor device 1300 is shown according to one or more embodiments. The semiconductor device 1300 has a corner structure arrangement, where the horizontal width WB of the last mesa 904 between the last active trench structure 1302 and the inner boundary trench structure 702 is substantially constant along the straight edge sections of the last mesa. At the corner of the semiconductor device 1300, the width WC of the last mesa 904 may be narrower at the corner compared to the width WB of the last mesa 904 in the straight edge sections in order to compensate for the different charge balances that may be required at the corner. Furthermore, the widths WB and WC of the last mesa 904 may differ from the widths WA of other mesas 314 in the active region between other adjacent active trench structures 313.

[0087] In the embodiment shown in FIG. 14, a semiconductor device 1400 according to one or more embodiments is configured such that the last mesa 904 adjacent to the inner boundary trench structure 702 in the edge termination region has a constant width WB along the straight edge of the die and a narrowed width WC (i.e., WC < WB) at the corner of the die joining the adjacent straight edges. In this embodiment, the width WC of the last mesa 904 at the corner can be narrowed by using an inner boundary trench structure 702 configured to have a chamfer at the corner rather than a rounded corner. In some embodiments, the chamfer can have an angle of about 45 degrees, although embodiments are not limited thereto. The width WC of the last mesa 904 at the corner of the semiconductor device 1400 and the width WB of the last mesa 904 along the straight edge of the device 1400 can be different from the width WA of the mesa 314 between other active trench structures 313 in the active region of the semiconductor device 1400.

[0088] FIGS. 15A and 15B are top plan views illustrating semiconductor devices 1500 and 1550, respectively, according to embodiments of the present invention. The semiconductor devices 1500 and 1550 each include a corner structure configured to have a chamfer of about 45 degrees at the corner, although embodiments are not limited to any particular shape or angle of the chamfer portion of the corner structure. The semiconductor devices 1500 and 1550 further include a plurality of active trench structures 313 that extend parallel to each other and within or adjacent to the inner boundary trench structure 702. That is, there may or may not be a gap between the ends of the plurality of active trench structures 313 and the inner boundary trench structure 702. Note that the gap in the chamfered portion of the inner boundary trench structure 702 can be different compared to the straight portion of the inner boundary trench structure 702.

[0089] In the semiconductor device 1500 shown in Figure 15A, the plurality of active trench structures 313 may extend in a first horizontal direction parallel to the upper surface of the substrate of the semiconductor device 1500. In the semiconductor device 1550 shown in Figure 15B, the plurality of active trench structures 313 may extend in a second horizontal direction parallel to the upper surface of the substrate of the semiconductor device 1550, where the second horizontal direction intersects the first horizontal direction (for example, vertically).

[0090] The inner boundary trench structure 702 may be a linear structure having a predetermined inclination (e.g., about 45 degrees), as illustrated in the semiconductor device 1500 of Figure 15A. Alternatively, the inner boundary trench structure 702 may be configured to have stepped (i.e., zigzag) ends at the corners, and may have a predetermined inclination (e.g., about 45 degrees) overall with respect to adjacent sides of the inner boundary trench structure 702. Embodiments of the present invention are not limited to a specific shape or angle at the corners of the inner boundary trench structure 702, although 45 degrees may be preferred in some embodiments.

[0091] Referring to Figures 15A and 15B, the chamfered corner configuration of the inner boundary trench structure 702 may be implemented such that it has a smooth end that is angled at the corner (e.g., about 45 degrees) with respect to the adjacent side of the inner boundary trench structure 702 joined at the corner, as shown, for example in Figure 15A. Alternatively, the chamfered corner configuration of the inner boundary trench structure 702 may be implemented such that it has a stepped (i.e., zigzag) end that approximates the angled end at the corner with respect to the adjacent side of the inner boundary trench structure 702, as shown, for example in Figure 15B. The steps forming the corner of the inner boundary trench structure 702 in Figure 15B may be of equal size. That is, for each of the steps forming the corner of the inner boundary trench structure 702, the tread dimension d1 may be equal to the riser dimension d2, but the embodiment is not limited thereto.

[0092] Figure 16 illustrates an exemplary semiconductor device 1600 according to one or more embodiments of the present invention. The semiconductor device 1600 may comprise an inner boundary trench structure 702 and a plurality of active trench structures 313, the plurality of active trench structures 313 extending parallel to each other and within or adjacent to the inner boundary trench structure 702. That is, there may or may not be gaps between the ends of the plurality of active trench structures 313 and the inner boundary trench structure 702.

[0093] Referring to Figure 16, the trench structure in the semiconductor device 1600 in Figure 16 may be configured to have chamfered corners as shown in Figures 15A and 15B, and may also be rounded at the corners (e.g., corners with a large radius of curvature). Similar to the embodiment shown in Figure 15B, the rounded corner of the inner boundary trench structure 702 may be configured to have a stepped edge that approximates a predetermined radius of curvature that substantially matches the contour of the inner end of the trench structure at the corner. The steps forming the corner of the inner boundary trench structure 702 in Figure 16 do not necessarily have to be of equal size. That is, the tread dimension d3 and riser dimension d4 of one step may differ from the tread dimension d3 and riser dimension d4 of another step forming the corner of the inner boundary trench structure 702. Furthermore, for any given step forming the corner of the inner boundary trench structure 702, the tread dimension d3 does not have to be equal to the riser dimension d4, but d3 and d4 may be equal to each other in some part along the curved corner.

[0094] This disclosure provides several non-limiting examples of exemplary edge termination structures for use in charge-balanced semiconductor devices, but various modifications and changes can be made without departing from the scope of the disclosure set forth in the appended claims, as will be apparent to those skilled in the art from the teaching herein. Accordingly, the specification and drawings should be understood as illustrative, not limiting, and all such modifications are intended to be within the scope of this disclosure. No advantage, benefit, or solution described herein with respect to a particular example is intended to be construed as an essential, necessary, or indispensable feature or element in any or all of the claims.

[0095] While the overall manufacturing method and the resulting structures are entirely novel, certain individual processing steps required to implement this method can utilize conventional semiconductor manufacturing techniques and tools. These techniques and tools are already known to those skilled in the art in light of the teachings herein. Furthermore, many processing steps and tools used to manufacture semiconductor devices are also described in numerous available publications, for example: P.Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008; and R.K.Willardson et al., Processing and Properties of Compound Semiconductors, Academic Press, 2001. These publications are incorporated herein by reference in their entirety for all purposes. While several individual processing steps are described herein, these are merely illustrative, and it should be emphasized that those skilled in the art may know of several equivalent alternatives that are also included within the scope of the present invention.

[0096] It should be noted that the various layers and / or regions shown in the attached drawings are not necessarily depicted to actual size. Furthermore, in a given drawing, one or more semiconductor layers of a type commonly used in such semiconductor devices may not be explicitly shown in order to facilitate clearer explanation. This does not mean that one or more semiconductor layers that are not explicitly shown are omitted in the actual device.

[0097] In one or more embodiments, the formation of the exemplary device structures described herein may involve the deposition of a material and a layer by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or various variations thereof (e.g., plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), electron-beam physical vapor deposition (EB-PVD), plasma-enhanced atomic layer deposition (PE-ALD)). The deposition may be an epitaxial process, and the deposited material may be crystalline. In one or more embodiments, layer formation can be achieved using a single deposition process or multiple deposition processes, where, for example, a conformal layer is formed by a first process (e.g., ALD, PE-ALD, etc.), and a packed layer is formed by a second process (e.g., CVD, electrodeposition, PVD, etc.). The multiple deposition processes may be the same or different.

[0098] In this specification, the term "semiconductor" may broadly refer to a doped semiconductor material, i.e., a semiconductor material into which a doping agent has been introduced to give it different electrical properties from the original semiconductor material, or it may refer to an undoped semiconductor material. Doping may include adding dopant atoms to the original semiconductor material, thereby changing the electron and hole carrier concentrations of the original semiconductor material in thermal equilibrium. The dominant carrier concentration in the extrinsic semiconductor material determines the conductivity type of the semiconductor material.

[0099] As used herein, the term “metal” is intended to mean any electrically conductive material, whether or not it is technically defined as a metal from a chemical standpoint. Therefore, as used herein, the term “metal” encompasses materials such as aluminum, copper, silver, and gold, and also includes such materials such as graphene, germanium, gallium arsenide, and highly doped polysilicon (commonly used in most MOSFET devices). This is distinct from the physical definition of “metal,” which typically refers to an element having a partially filled conduction band and lower resistance at lower temperatures.

[0100] As used herein, the term "insulating" generally means about 10 -10 (Ω-m) -1This may refer to materials having a room-temperature conductivity of less than 1 / 2. Suitable insulating materials may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, high dielectric constant (high k) materials, or any combination of these materials. Non-limiting examples of high-k materials include oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, scandium tantalum lead oxide, and zinc niobate. This may include materials such as niobate and ceramics. High-k materials may further include dopants, such as lanthanum and aluminum.

[0101] As used herein, "p-type" may broadly refer to the addition of impurities that cause valence electron depletion to an impurity-doped semiconductor material. In silicon-containing materials, non-exclusive examples of p-type dopants (i.e., impurities) include boron, aluminum, gallium, and indium.

[0102] As used herein, "n-type" may broadly refer to the addition of impurities to supply free electrons to a semiconductor material without impurities. In silicon-containing materials, non-limiting examples of n-type dopants include antimony, arsenic, and phosphorus.

[0103] When an element, such as a layer, region, or substrate, is referred to as being "on top of," "on top of," "directly above," or "above" another element, it is also understood that it is broadly intended that the element is in direct contact with the other element or that an intermediate element may also be present. In contrast, when an element is referred to as being "directly on" or "directly above" another element, it is intended that no intervening element is present. When an element is referred to as being "connected" or "joined" to another element, it will also be understood that there may be a directly connected or joined element, or that an intervening element may be present. In contrast, when an element is referred to as being "directly connected" or "directly joined" to another element, there is no intervening element. Furthermore, as used herein, terms relating to position (i.e., direction), such as "on top," "below," "upper side," "lower side," "below," and "above," are intended to indicate relative positions between elements or structures, not absolute positions.

[0104] At least a portion of the technology of the present invention can be implemented in an integrated circuit. When forming an integrated circuit, identical dies are typically manufactured in a repeating pattern on the surface of a semiconductor wafer. Each die comprises the devices described herein and may also comprise other structures and / or circuits. Individual dies are cut or diced from a wafer and then packaged as an integrated circuit. Those skilled in the art know methods for dicing wafers and packaging dies for manufacturing integrated circuits. All or part of the exemplary structures illustrated in the accompanying drawings may be part of an integrated circuit. An integrated circuit manufactured in this manner is considered part of the present invention.

[0105] Those skilled in the art will understand that the exemplary structures described above can be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), as bare dies, or in packaged form, or incorporated as part of an intermediate or final product that enjoys the benefits of having an enhanced edge-terminating structure (e.g., a power IC device) formed according to one or more embodiments of the present invention.

[0106] Integrated circuits conforming to the aspects of this disclosure can be used in essentially any application and / or electronic system with enhanced breakdown voltage structures (including, but not limited to, power metal-oxide semiconductor field-effect transistors (MOSFETs), Schottky diodes, etc.). Suitable systems and applications for implementing embodiments of the present invention include, but are not limited to, AC-DC and DC-DC conversion, motor control, and power supply OR-ing (where "OR-ing" is a specific application in redundant power system architectures where multiple power supplies are connected in parallel to a single common power bus). Systems incorporating such integrated circuits are considered part of the present invention. Based on the disclosures described herein, those skilled in the art may devise other implementations and applications of embodiments of the present invention.

[0107] The examples of embodiments of the present invention described herein are intended to provide a general understanding of various embodiments and are not intended to provide a complete description of all elements and features of equipment and systems that may utilize the structures and semiconductor manufacturing methods described herein. Many other embodiments will become apparent to those skilled in the art in light of the teachings herein. These other embodiments are utilized and derived from this specification and can therefore be structurally and logically substituted and modified without departing from the scope of this specification. The drawings are also conceptual and not necessarily drawn to actual size. Therefore, the specification and drawings should be interpreted as illustrative, not restrictive.

[0108] Embodiments of the present invention are referred to individually and / or collectively by the term “embodiments” for convenience, but this is not intended to limit the scope of this application to a single embodiment or inventive concept, even if multiple embodiments are actually shown. Therefore, while certain embodiments are illustrated and described herein, it should be understood that configurations achieving the same objective can be used in place of one or more specific embodiments shown. That is, this disclosure is intended to encompass any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those skilled in the art in light of the teachings herein.

[0109] The terms used herein are for the sole purpose of describing specific embodiments and are not intended to limit the invention. Where used herein, the singular forms “one” (a), “an” and “the” are intended to also include the plural form unless the context clearly indicates otherwise. Where used herein, the words “equipped with” and / or “equipped with” indicate the presence of the described feature, integer, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0110] The corresponding structures, materials, actions, and equivalents of elements that add function to all means or steps in the following claims are intended to encompass any structures, materials, or actions for performing such function in combination with other explicitly claimed elements. The description of the present invention is presented for illustrative and explanatory purposes only and is not intended to be exhaustive or to limit the invention to the disclosed forms. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The embodiments have been selected and described to best illustrate the principles and practical applications of the invention and to enable those skilled in the art to understand the invention with respect to various embodiments, along with various modifications suitable for specific intended uses.

[0111] The abstract is provided in accordance with 37 CFR §1.72(b), which requires an abstract that allows readers to quickly grasp the nature of the technical disclosure. It is submitted on the premise that it will not be used to interpret or limit the scope or meaning of the claims. In addition, as can be seen in the detailed description above, various features have been grouped into a single embodiment for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting the intent required by the claimed embodiment, beyond features explicitly stated in each claim. Rather, as the attached claims indicate, the subject matter of the invention lies in fewer features than all the features of a single embodiment. Accordingly, the attached claims are incorporated within the detailed description of the invention, and each claim exists independently as individually claimed subject matter.

[0112] In light of the teaching of embodiments of the invention described herein, those skilled in the art will be able to consider other implementations and applications of the technology of embodiments of the present invention. Although exemplary embodiments of the present invention are described herein with reference to the accompanying drawings, it should be understood that embodiments of the present invention are not limited to these exact embodiments, and that various other changes and modifications can be made by those skilled in the art without departing from the scope of the appended claims.

Claims

1. A method for forming an edge termination structure in a semiconductor device, wherein the semiconductor device includes an active region where one or more active structures are formed, and an edge termination region where the edge termination structure is formed, the edge termination region being laterally adjacent to the active region, and the method is Forming an epitaxial layer on a semiconductor substrate, wherein the epitaxial layer extends laterally across the active region and the edge termination region; To form a plurality of active trenches within the active region and at least one outer trench in the edge termination region, wherein each of the outer trenches and the active trenches extends vertically through at least a portion of the epitaxial layer; Each of the outer trench and the active trench is filled at least partially with the first insulating material; Forming a trench by etching a region of the epitaxial layer in the edge termination region adjacent to the last trench of the plurality of active trenches in the active region; and, The trench is filled at least partially with a second insulating material to form a trench structure as a non-conductive edge termination structure in a semiconductor device. The method, including the method described above.

2. The method described above is To form at least one boundary trench in the edge termination region, wherein the boundary trench extends vertically through at least a portion of the epiaxial layer and is spaced laterally from the at least one outer trench; and, Filling at least one boundary trench with the first insulating material at least partially. It further includes, Here, the trench structure is positioned between the outer trench and the boundary trench, and therefore a given side wall of the trench structure is defined by one of the outer trench and the boundary trench. The method according to claim 1.

3. The method according to claim 2, wherein the outer trench, the boundary trench, and the active trench are formed simultaneously using the same mask and in the same processing step.

4. The method according to claim 1, wherein the first width of at least one outer trench is greater than the second width of each of the plurality of active trenches.

5. The method according to claim 4, wherein the first width is at least twice the second width.

6. The method according to claim 2, wherein each of the at least one outer trench, the at least one boundary trench, and the plurality of active trenches is formed using a deep trench etch process having an aspect ratio greater than approximately 10:

1.

7. The method according to claim 1, further comprising forming a first metal layer on at least the upper surface of the active region, wherein the first metal layer is configured to extend laterally above the at least one outer trench and above a portion of the trench structure in the edge termination region, and the extension of the first metal layer above the trench structure forms an electric field plate in the edge termination region.

8. The method according to claim 7, further comprising controlling the amount of extension of the first metal layer above the trench structure in the edge termination region to optimize the electric field distribution in the trench structure.

9. Forming a first metal layer at least on the upper surface of the active region; and, A second metal layer is formed on the upper surface of the first metal layer and extending laterally above the at least one outer trench and above a portion of the second insulating layer in the trench structure, thereby forming an electric field plate in the edge termination region. The method according to claim 1, further comprising:

10. The method according to claim 9, further comprising controlling the amount of extension of the second metal layer above the trench structure in the edge termination region to optimize the electric field distribution in the trench structure.

11. The method involves forming a first metal layer that is located at least on the upper surface of the active region and extends laterally above the at least one outer trench and a portion of the trench structure in the edge termination region, wherein the extension of the first metal layer above the trench structure forms a first electric field plate in the edge termination region; To form a second metal layer on the upper surface of the first metal layer and extending laterally above a portion of the second insulating layer in the trench structure, thereby forming a second electric field plate in the edge termination region; and, The amount of extension of at least one of the first and second metal layers above the trench structure in the edge termination region is controlled to optimize the electric field distribution in the trench structure. The method according to claim 1, further comprising:

12. A first metal layer is formed on at least the upper surface of the active region to form a first inner electric field plate in the edge termination region, wherein a first portion of the first metal layer extends laterally from the active region above the at least one outer trench and above a portion of the trench structure; and, A second portion of the first metal layer is formed above the epitaxial layer, extending laterally above at least one boundary trench and above a portion of the trench structure, thereby forming a first outer electric field plate in the edge termination region. The method according to claim 2, further comprising:

13. A first metal layer is formed on at least the upper surface of the active region to form a first outer electric field plate in the edge termination region, wherein a portion of the first metal layer extends laterally above the epitaxial layer, above the at least one boundary trench, and above a portion of the trench structure adjacent to the at least one outer trench; and, A second metal layer is formed on the upper surface of the first metal layer and extending laterally above a portion of the second insulating layer in the trench structure adjacent to at least one outer trench, thereby forming a secondary outer electric field plate in the edge termination region. The method according to claim 2, further comprising:

14. Forming a first metal layer at least on the upper surface of the active region; To form an inner electric field plate in the edge termination region by forming a first portion of a second metal layer that is located on the upper surface of the first metal layer and extends laterally above the at least one outer trench and a portion of the second insulating layer in the trench structure adjacent to the at least one outer trench; and, A second portion of the second metal layer on the second insulating layer is formed above the at least one boundary trench and a portion of the trench structure adjacent to the at least one boundary trench, thereby forming an outer electric field plate in the edge termination region. The method according to claim 2, further comprising:

15. The method according to claim 14, further comprising controlling the amount of extension of the first and second portions of the second metal layer above the trench structure in the edge termination region to optimize the electric field distribution in the trench structure.

16. The method according to claim 1, further comprising forming the at least one outer trench and the moat such that the depth of the at least one outer trench is greater than the depth of the moat in the edge termination region.

17. The method according to claim 1, further comprising controlling the width of the mesa region between the last of the plurality of active trenches in the active region and the outer trench in the edge termination region to adjust the difference in charge between the trench structure and the plurality of active trenches.

18. A semiconductor device comprising an active region and an edge termination region, wherein the edge termination region is laterally adjacent to the active region, and the semiconductor device is An epitaxial layer formed on a semiconductor substrate, wherein the epitaxial layer extends laterally across the active region and the edge termination region; A plurality of active trench structures formed within the active region and at least one active device, wherein each of the plurality of active trench structures extends vertically through at least a portion of the epitaxial layer and is at least partially filled with a first insulating material; At least one outer trench structure formed in the edge termination region, wherein the outer trench structure extends vertically through at least a portion of the epitaxial layer and is at least partially filled with the first insulating material, and the outer trench structure is adjacent to the last trench of the plurality of active trench structures in the active region; and, A trench structure extending vertically through at least a portion of the epitaxial layer in the edge termination region, wherein the trench structure has side walls defined by at least one outer trench structure, the trench structure is at least partially filled with a second insulating material, and the trench structure forms an edge termination structure in the semiconductor device configured to laterally isolate the active region from reverse voltage in the semiconductor device. The semiconductor device including the above.

19. The aforementioned semiconductor device is At least one boundary trench structure formed in the edge termination region It further includes, The boundary trench structure extends vertically through at least a portion of the epitaxial layer and is at least partially filled with the first insulating material, and the boundary trench structure is spaced laterally from the at least one outer trench structure. Here, the trench structure is positioned between the outer trench structure and the boundary trench structure, and therefore a given side wall of the trench structure is defined by one of the outer trench structure and the boundary trench structure. The semiconductor device according to claim 18.

20. A first metal layer located on at least the upper surface of the plurality of active trench structures in the active region; A second metal layer on the second insulating layer extending over at least a portion of the trench structure, wherein the second metal layer forms an electric field plate for controlling the electric field distribution in the trench structure. The semiconductor device according to claim 18, further comprising the above.

21. The aforementioned semiconductor device is A first metal layer located on at least the upper surface of the plurality of active trench structures in the active region, wherein the first metal layer extends laterally above the outer trench structure and above at least a portion of the trench structure, and the extension of the first metal layer above the trench structure forms a first electric field plate in the edge termination region; and, A second metal layer is disposed on the second insulating layer above at least a portion of the trench structure, wherein the second metal layer forms a second electric field plate in the edge termination region. It also has the following features: Here, the amount of extension of at least one of the first and second metal layers above the trench structure in the edge termination region is configured to control the electric field distribution in the trench structure. The semiconductor device according to claim 18.

22. The semiconductor device according to claim 18, wherein each of at least one subset of the plurality of active trench structures in the active region is at least partially filled with a material having a fixed charge associated with the material, and so the plurality of active trench structures are configured to balance the charge of at least a portion of the active region.

23. The semiconductor device according to claim 19, wherein the at least one boundary trench structure is at least partially filled with a material having a fixed charge associated with the material, and so the at least one boundary trench structure is configured to balance the charge of at least a portion of the edge termination region.

24. The semiconductor device according to claim 18, wherein the width of the mesa region between the last of the plurality of active trenches in the active region and the outer trench in the edge termination region is configured to adjust the difference in charge between the trench structure and the plurality of active trenches.

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