Improved materials and methods for complementary field-effect transistors having an intermediate dielectric insulating layer

Abstract

Embodiments of the present disclosure advantageously provide, in particular, semiconductor devices CFETs and methods for manufacturing such devices having a fully strained superlattice structure having a substantially defect-free channel layer and a release layer protected from material loss during the removal of the intermediate sacrificial layer. The CFET described herein comprises a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising a first hGAA structure on the substrate, an intermediate sacrificial layer on top of the first hGAA structure, an intermediate sacrificial layer containing silicon germanium (SiGe), and a second hGAA structure on top of the sacrificial layer. Each of the first and second hGAA comprises alternating layers of silicon (Si) nanosheet channel layers and silicon germanium (SiGe) nanosheet release layers. The intermediate sacrificial layer and the nanosheet release layer may contain silicon germanium (SiGe) having the same or substantially the same geranium content.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic device manufacturing, particularly to transistors. More specifically, embodiments of the present disclosure are directed to complementary field effect transistors (CFETs), and methods of forming the same.

Background Art

[0002]

[0002] Transistors are important components in most integrated circuits. Since the drive current, and thus the speed, of a transistor is proportional to the gate width of the transistor, generally a larger gate width is required for a faster transistor. Therefore, there is a trade-off between the size and speed of a transistor, and "fin" field effect transistors (finFETs) have been developed to address the conflicting goals of maximum drive current and minimum size. FinFETs are characterized by a fin-type channel region that can significantly increase the size of a transistor without significantly increasing the transistor's implementation area, and are currently applied to many integrated circuits. However, finFETs also have drawbacks.

[0003]

[0003] To achieve improvements in circuit density and high performance, the feature size of transistor devices has been continuously reduced, and improvements in transistor device structures are required to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and leakage current in the off state. Examples of transistor device structures include planar structures, fin field effect transistor (FinFET) structures, and gate all around (GAA) structures. The GAA device structure includes several lattice-matched channels that are suspended in a stacked configuration and connected by source / drain regions. The GAA structure provides good electrostatic control and can be widely adopted in complementary metal oxide semiconductor (CMOS) wafer manufacturing.

[0004]

[0004] An example of gate-all-around (GAA) technology is a complementary field-effect transistor (CFET), in which nFET and pFET nanowires / nanosheets are stacked vertically on top of each other. Compared to GAA transistors, CFET transistors have increased on-chip device density and reduced area consumption. When nFETs and pFETs are stacked monolithically, the n and p superlattices are continuously deposited in an intermediate sacrificial layer during processing and selectively removed and replaced by an intermediate dielectric insulating (MDI) layer. The MDI layer serves to electrically isolate the lower level GAA from the upper level GAA.

[0005]

[0005] Each n or p superlattice of the CFET includes alternating layers of channel layers and release layers. The release layers typically contain silicon germanium (SiGe) with a low concentration of germanium (Ge). For etching contrast between the intermediate sacrificial layer and the channel layer, the intermediate sacrificial layer contains SiGe with a high concentration of Ge.

[0006]

[0006] However, providing a structure with such a high concentration of Ge in the intermediate sacrificial layer relaxes the superlattice, reducing strain and mobility, and decreasing the drive current, thus degrading transistor performance. Furthermore, while providing an intermediate sacrificial layer with a relatively high concentration of Ge provides etching contrast and selective removal of the intermediate sacrificial layer, undesirable losses of SiGe occur in the release layer, resulting in a roughened and damaged release layer. In addition, the Si channel layer can become rounded while the intermediate sacrificial layer is removed. As a result, the superlattice is given a non-uniform profile, which adversely affects device performance and leads to device variability.

[0007]

[0007] Therefore, there is a need for semiconductor devices, in particular CFETs, and methods for manufacturing such devices having a perfectly distorted superlattice structure with a uniform, defect-free or substantially defect-free channel layer. There is a further need for semiconductor devices, in particular CFETs, and methods for manufacturing such devices having a channel layer and a release layer that are protected from damage and loss during the removal of the intermediate sacrificial layer. [Overview of the Initiative]

[0008]

[0008] One aspect of the present disclosure relates to a method for forming a semiconductor device, said method is A superlattice structure stacked vertically on a substrate, The first horizontal gate all-around (hGAA) structure is formed on a substrate, wherein the first hGAA structure includes alternating layers of nanosheet channel layers and nanosheet release layers; Forming an intermediate sacrificial layer on the upper surface of the first hGAA structure; The method involves forming a second horizontal gated all-around (hGAA) structure on the upper surface of the intermediate sacrificial layer, wherein the second hGAA structure comprises alternating layers of nanosheet channel layers and nanosheet release layers; Depositing encapsulating material to fill one or more trenches within the vertical stacked superlattice structure, thereby surrounding the vertical stacked superlattice structure; Remove a portion of the encapsulation material to expose the second hGAA structure; Depositing a protective liner onto the second hGAA structure; Removing part of the encapsulation material to expose the intermediate sacrificial layer; and Removing the intermediate sacrificial layer; Including being formed by, The first hGAA structure is covered with an encapsulation material, and the second hGAA structure is covered with a protective liner during the removal of the intermediate sacrificial layer.

[0009]

[0009] Another aspect of the present disclosure relates to a method for forming a semiconductor device, the method being A superlattice structure stacked vertically on a substrate, The first horizontal gate all-around (hGAA) structure is formed on a substrate, wherein the first hGAA structure includes alternating layers of nanosheet channel layers and nanosheet release layers; Forming an intermediate sacrificial layer on the upper surface of the first hGAA structure; Forming a second horizontal gated all-around (hGAA) structure on the upper surface of the sacrificial layer, wherein the second hGAA structure includes alternating layers of nanosheet channel layers and nanosheet release layers; and Etching the intermediate sacrificial layer; Including being formed by, The alternating layers of nanosheet release layers in the first hGAA structure and the nanosheet release layers in the second hGAA structure, as well as the intermediate sacrificial layer, contain the same material. The second hGAA structure is shielded by a protective liner while the intermediate sacrificial layer is being etched, and the first hGAA structure is shielded by an encapsulation material while the intermediate sacrificial layer is being etched. Etching the intermediate sacrificial layer prevents material loss in forming the alternating layers of nanosheet release layers in the first and second hGAA structures.

[0010]

[0010] To enable a detailed understanding of the above-described features of the Disclosure, a more specific description of the Disclosure, which has been briefly summarized above, can be obtained by reference to embodiments. Some of these embodiments are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the Disclosure and therefore should not be considered to limit its scope, as the Disclosure may allow for other equally valid embodiments. Embodiments described herein are shown in the figures of the accompanying drawings as examples, not limitations, and similar reference numerals indicate similar elements. [Brief explanation of the drawing]

[0011] [Figure 1] A process flow diagram of a method for manufacturing a complementary field-effect transistor (CFET) according to one or more embodiments is shown. [Figure 2] A schematic cross-sectional view of a vertically stacked superlattice structure on a semiconductor substrate, according to one or more embodiments, is shown. [Figure 3A-3E] This shows a series of processing steps for manufacturing a CFET having an intermediate dielectric insulating (MDI) layer using conventional technology. [Figure 4] Two cross-sectional views of a vertically stacked superlattice structure according to one or more embodiments after post-gate spacer deposition are shown. [Figure 5A] This shows the desired vertically stacked superlattice structure after selectively removing the intermediate sacrificial layer. [Figure 5B] This shows the vertically stacked superlattice structure after selective removal of the intermediate sacrificial layer using conventional techniques. [Figure 6] The diagram shows a cross-sectional view of a vertically stacked superlattice structure after post-gate spacer deposition, according to one or more embodiments. [Figure 7] The diagram shows a double cross-sectional view of a vertically stacked superlattice structure after global etching of the source / drain according to one or more embodiments. [Figure 8] The diagram shows a double cross-sectional view of a vertically stacked superlattice structure after a carbon spin-on or CVD gap-filling and planarization process according to one or more embodiments. [Figure 9] The diagram shows a cross-sectional view of a vertically stacked superlattice structure after a carbon etching back process to expose an upper horizontal gate all-around (hGAA) structure, according to one or more embodiments. [Figure 10]A cross-sectional view of a vertically stacked superlattice structure after deposition of a protective liner covering the top and side surfaces of a gate, the side surfaces of an upper hGAA structure, and the top surface of a carbon spin-on or CVD gap-fill material, according to one or more embodiments. [Figure 11] A cross-sectional view of a vertically stacked superlattice structure after etching the protective liner to expose the top surface of a carbon spin-on or CVD gap-fill material, according to one or more embodiments. [Figure 12] Two cross-sectional views of a vertically stacked superlattice structure after a carbon pullback process to expose an intermediate sacrificial layer, according to one or more embodiments. [Figure 13] A cross-sectional view of a vertically stacked superlattice structure after removing the intermediate sacrificial layer, according to one or more embodiments. [Figure 14] A cross-sectional view of a vertically stacked superlattice structure after deposition of an intermediate dielectric isolation (MDI) layer material, according to one or more embodiments. [Figure 15] A cross-sectional view of a vertically stacked superlattice structure after removing the MDI layer material from the top and side surfaces of the gate, the side surfaces of the upper hGAA structure, and the trenches of the upper hGAA structure, according to one or more embodiments. [Figure 16] Two cross-sectional views of a vertically stacked superlattice structure after removing the remaining carbon from a carbon spin-on or CVD gap-fill to expose a lower horizontal gate all-around (hGAA) structure, and a process for densifying the MDI layer material to form an MDI layer, according to one or more embodiments. [Figure 17] A cross-sectional view of a vertically stacked superlattice structure after removing the protective liner, according to one or more embodiments. [Figure 18] Two cross-sectional views of a CFET having an upper stack separated from a bottom stack having a fabricated MDI layer, according to one or more embodiments.

DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0030] Before describing some exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the configuration or process step details described below. Other embodiments of this disclosure are possible and can be practiced or implemented in various ways.

[0013]

[0031] As used in this book, the term "approximately" means roughly or nearly, and refers to a variation of no more than ±15% of a given number or range. For example, values ​​that differ by only ±14%, ±13%, ±12%, ±11%, ±10%, ±9%, ±8%, ±7%, ±6%, ±5%, ±4%, ±3%, ±2%, or ±1% satisfy the definition of approximately.

[0014]

[0032] Spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used here to describe the relationship between one element or feature shown in the drawing and another, for the sake of clarity. It will be understood that spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the drawing. For example, if the device in the drawing is upside down, an element described as “below” or “directly below” another element or feature will therefore be oriented “above” the other element or feature. Thus, the exemplary term “below” may encompass both up and down orientations. The device may be oriented in ways other than those described (it may be rotated 90 degrees or rotated to other orientations), and the spatially relative descriptions used herein shall be interpreted accordingly.

[0015]

[0033] In the context of describing the materials and methods discussed herein (in particular in the context of the following claims), the use of “a” and “an,” “the,” and similar referents should be interpreted as encompassing both singular and plural, unless otherwise indicated herein or unless clearly contradicted by the context. The enumeration of ranges of values ​​herein is merely intended to serve as a shorthand notation for referring individually to each individual value within the range, unless otherwise indicated herein, and each individual value is incorporated into the specification as if it were individually stated herein. All methods described herein may be performed in any appropriate order, unless otherwise indicated herein or unless clearly contradicted by the context. Any and all examples or illustrative language provided herein (e.g., “such as”) is merely intended to better describe the materials and methods and does not impose any limitation of scope unless specifically asserted otherwise. Nothing in this specification should be interpreted as indicating any unclaimed element essential to the practice of the disclosed materials and methods.

[0016]

[0034] Throughout this Specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiment” means that any particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this Disclosure. Therefore, any other occurrences of the phrases “in one or more embodiments,” “in a particular embodiment,” “in one embodiment,” or “in an embodiment” throughout this Specification do not necessarily refer to the same embodiment of this Disclosure. In one or more embodiments, the particular feature, structure, material, or property is combined in any suitable manner.

[0017]

[0035] As used herein and in the appended claims, the terms “substrate” or “wafer” refer to a surface or portion of a surface on which a process is performed. Furthermore, when a substrate is referred to, it will be understood by those skilled in the art that unless otherwise explicitly stated in the context, it may refer only to a portion of the substrate. In addition, when a deposition on a substrate is referred to, it may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed. In this specification, “substrate” means any substrate on which a film treatment is performed during a manufacturing process, or any material surface formed on a substrate. For example, substrate surfaces on which treatment may be performed include, depending on the application, silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. A substrate includes, but is not limited to, a semiconductor wafer. The substrate can be subjected to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to direct film treatment on the surface of the substrate itself, any of the disclosed film treatment steps may be performed on an underlying layer formed on the substrate, as will be disclosed in more detail below. The term “substrate surface” is intended to include any underlying layer as indicated in the context. Thus, for example, if a film / layer or partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0018]

[0036] The term "on" indicates direct contact between elements. The term "directly on" indicates direct contact between elements without an intervening element.

[0019]

[0037] As used herein and in the appended claims, terms such as “precursor,” “reactant,” and “reactive gas” are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0020]

[0038] Epitaxy is a process in which a deposited film is required to be in a high degree of crystallographic alignment with the substrate. Epitaxial growth is broadly defined as the condensation of a gaseous precursor to form a film on a substrate. Liquid precursors can also be used. Vapor precursors can be obtained by chemical vapor deposition (CVD) and laser ablation. Several epitaxy techniques have become available, such as molecular beam epitaxy (MBE), epitaxial CVD, or atomic layer epitaxy (ALE).

[0021]

[0039] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive wires, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric interposed between the gate electrode of the substrate and the channel region.

[0022]

[0040] As used herein, the term “field-effect transistor” or “FET” refers to a transistor that uses an electric field to control the electrical behavior of a device. A field-effect transistor is a voltage-controlled device whose current-transmitting ability changes when an electric field is applied. Field-effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by the voltage difference between the body and the gate of the device. The three terminals of an FET are the source (S) through which carriers enter the channel, the drain (D) through which carriers exit the channel, and the gate (G), which is the terminal that regulates the conductivity of the channel. Traditionally, the current entering the channel from the source (S) is denoted as IS, and the current entering the channel from the drain (D) is denoted as ID. The voltage between the drain and source is called VDS. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., ID) can be controlled.

[0023]

[0041] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a type of field-effect transistor (FET) used in integrated circuits and high-speed switching applications. MOSFETs have an insulated gate, and the voltage applied to it determines the device's conductivity. This ability to change conductivity in response to the applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the modulation of charge concentration by metal-oxide-semiconductor (MOS) capacitance between the body electrodes and the gate electrode, which is located above the body and insulated from all other device regions by the gate dielectric layer. Compared to MOS capacitors, MOSFETs include two additional terminals (source and drain), each connected to a separate, highly doped region separated by the body region. These regions can be p-type or n-type, but both are the same type and are the opposite type to the body region. The source and drain (unlike the body) are highly doped, and the doping type is followed by a "+" symbol.

[0024]

[0042] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions, and the body is a p-type substrate region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions, and the body is an n-type substrate region. The source is so named because it is the source of charge carriers (electrons in the case of n-channels, and holes in the case of p-channels) flowing through the channel. Similarly, the drain is where charge carriers exit the channel.

[0025]

[0043] An nMOS FET consists of an n-type source / drain and a p-type substrate. When a voltage is applied to the gate, the holes in the body (p-type substrate) are driven away from the gate. This allows for the formation of an n-type channel between the source and drain, and current is carried by electrons from the source to the drain through the induced n-type channel. Logic gates and other digital devices implemented using NMOS are said to have NMOS logic. NMOS has three operating modes called cutoff, triode, and saturation. Circuits with NMOS logic gates dissipate electrostatic force when the circuit is idling because DC current flows through the logic gate when the output is low.

[0026]

[0044] A pMOS FET consists of a p-type source and drain and an n-type substrate. When a positive voltage is applied between the source and gate (a negative voltage between the gate and source), a p-type channel is formed between the source and drain with opposite polarity. Current is carried through the induced p-type channel and the holes from the source to the drain. sLogic gates and other digital devices implemented using PMOS are said to have PMOS logic. PMOS technology is low-cost and has good noise immunity.

[0027]

[0045] In NMOS, the carriers are electrons, while in PMOS, the carriers are pores. When a high voltage is applied to the gate, NMOS conducts, but PMOS does not. Furthermore, when a low voltage is applied to the gate, NMOS does not conduct, but PMOS does. Because the electron carriers in NMOS move twice as fast as the pore carriers in PMOS, NMOS is considered faster than PMOS. However, PMOS devices are more resistant to noise than NMOS devices. In addition, NMOS can provide half the impedance offered by PMOS (with the same shape dimensions and operating conditions), so NMOS ICs will be smaller than PMOS ICs (providing the same functionality).

[0028]

[0046] As used herein, the term “Fin-field-effect transistor (FinFET)” refers to a substrate-built MOSFET transistor in which the gate is located on two, three, or four sides of the channel, or wrapped around the channel, forming a double-gate structure. FinFET devices are given the common name FinFET because the source / drain regions form “fins” on the substrate. FinFET devices have fast switching times and high current density.

[0029]

[0047] As used herein, the term “gate all around (GAA)” is used to refer to electronic devices such as transistors in which the gate material completely surrounds the channel region. The channel region of a GAA transistor may include nanowires or nanoslabs or nanosheets, rod-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of vertically spaced horizontal nanowires or horizontal bars, making the GAA transistor a stacked horizontal gate all around (hGAA) transistor.

[0030]

[0048] As used herein, the term "complementary field-effect transistor (CFET)" refers to a transistor comprising NMOS FET devices and PMOS FET devices stacked together. Each of the NMOS FET devices and PMOS FET devices forming the CFET is a GAA transistor or an hGAA transistor.

[0031]

[0049] As used herein, the term "nanowire" refers to a nanometer (10⁻¹⁰) -9 This refers to nanostructures having a diameter in units of meters. Nanowires can also be defined as structures with a length-to-width ratio greater than 1000. Alternatively, nanowires can be defined as structures whose thickness or diameter is limited to tens of nanometers or less, but whose length is not limited. Nanowires are used in transistors and some laser applications, and in one or more embodiments, they are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in logic CPUs, GPUs, MPUs, and transistors for volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term “nanosheet” refers to two-dimensional nanostructures having a thickness in the range of about 0.1 nm to about 1000 nm, or 0.5 nm to 500 nm, or 0.5 nm to 100 nm, or 1 nm to 500 nm, or 1 nm to 100 nm, or 1 nm to 50 nm.

[0032]

[0050] In this specification, “material loss” in a layer, and in particular “material loss” in a nanosheet release layer and / or nanosheet channel layer, refers to the loss or removal of a portion of the material forming these layers. Specifically, “material loss” in a nanosheet release layer and / or nanosheet channel layer is described herein in relation to the loss or removal of a portion of the material forming these layers during the removal of an intermediate sacrificial layer. For example, in embodiments having an intermediate sacrificial layer formed from SiGe, a nanosheet release layer formed from SiGe (having the same or different concentrations of Ge), and a nanosheet channel layer formed from Si, a removal process performed to remove the intermediate sacrificial layer (such as etching or another suitable removal process) results in the unintentional loss or removal of a portion of the SiGe forming the nanosheet release layer and / or the loss or removal of a portion of the Si forming the nanosheet channel layer.

[0033]

[0051] Generally, removing the intermediate sacrificial layer within a CFET superlattice by an etching process without etching the nanosheet release layer requires a tricolor selectivity of >10:1. In a typical patterned wafer, the selectivity between SiGe and Si (e.g., the intermediate sacrificial layer and nanosheet release layer, both formed of SiGe, relative to the nanosheet channel layer formed of SiGe) is very high, satisfying the >10:1 requirement. However, the selectivity of SiGe with a low germanium content (i.e., 15-20% on an atomic basis) is much lower than that of SiGe with a high germanium content (i.e., over 30% on an atomic basis), failing to meet the >10:1 requirement. Therefore, monolithic CFETs have been manufactured by relying on a relatively high germanium content in the intermediate sacrificial layer compared to the germanium content in the nanosheet release layer.

[0034]

[0052] While not intended to be bound by any particular operating theory, relying on a selective etching process based on a relatively high germanium content in the intermediate sacrificial layer relative to the germanium content in the nanosheet release layer of a vertically stacked superlattice structure is thought to result in defects because some material loss occurs even within the nanosheet release layer. While not intended to be bound by any particular operating theory, a selective etching process may cause material loss to form the nanosheet channel layer, resulting in a nanosheet channel layer with a rounded profile after etching the intermediate sacrificial layer. Embodiments of this disclosure advantageously provide a vertically stacked superlattice structure in which material loss forming the nanosheet release layer and nanosheet channel layer is minimized or prevented while the intermediate sacrificial layer is removed. In some embodiments, for example, by coating the upper hGAA structure with a protective liner and surrounding the lower hGAA structure with a protective gap-filling material, material loss forming the nanosheet release layer and nanosheet channel layer is minimized or prevented by etching the exposed intermediate sacrificial layer while protecting both the upper and lower hGAA structures. In some embodiments, selective etching of the intermediate sacrificial layer can be achieved independently of the etching selectivity of the material forming the intermediate sacrificial layer relative to the material forming the nanosheet release layer.

[0035]

[0053] According to one or more embodiments, any material can be used to form the intermediate sacrificial layer and the nanosheet release layer, and selective etching of the intermediate sacrificial layer can be performed while minimizing or preventing etching of the nanosheet release layer. According to one or more embodiments, the material forming the intermediate sacrificial layer may have higher etching selectivity than the material forming the nanosheet release layer. According to one or more embodiments, the material forming the intermediate sacrificial layer may have the same or substantially the same etching selectivity as the material forming the nanosheet release layer. According to one or more embodiments, the same or substantially the same material can be used to form the intermediate sacrificial layer and the nanosheet release layer. According to one or more embodiments, the nanosheet channel layer contains Si, and the intermediate sacrificial layer and the nanosheet release layer independently contain SiGe. According to one or more embodiments, a layer in which nanosheet layers containing Si and nanosheet release layers are alternately stacked can have an intermediate sacrificial layer containing SiGe and form a vertically stacked superlattice structure that is strained and free of crystal lattice defects. According to one or more embodiments, the material forming the intermediate sacrificial layer is the same as the material forming the nanosheet release layer, simplifying the fabrication of the vertical superlattice structure because fewer material compositions are required to form the various layers. Furthermore, although not bound by theory, it is believed that using the same material composition (e.g., the same SiGe material) to form the intermediate sacrificial layer and the nanosheet release layer not only enables a simpler manufacturing process, but also reduces potential defects that may occur during the manufacturing process by using different materials.

[0036]

[0054] Embodiments of the present disclosure are illustrated by diagrams showing devices (e.g., transistors) and processes for forming devices according to one or more embodiments of the present disclosure. The illustrated processes are merely illustrative examples of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0037]

[0055] Figure 1 shows a process flow diagram of a method 100 for manufacturing a complementary field-effect transistor (CFET) according to one or more embodiments of the present disclosure. Method 100 includes forming a vertically stacked superlattice structure on a substrate in step 102. In one or more embodiments, the superlattice is distorted and free of crystalline lattice defects. In step 104, a vertically stacked superlattice structure is formed on the substrate by placing a first or lower horizontal gate-all-around (hGAA) structure on the substrate. The first or lower hGAA is formed of alternating layers of nanosheet channel layers and nanosheet release layers. In step 106, an intermediate sacrificial layer is formed on the upper surface of the first or second hGAA structure. In step 108, a second or upper horizontal gate-all-around (hGAA) structure is formed on the upper surface of the sacrificial layer. The second hGAA is formed of alternating layers of nanosheet channel layers and nanosheet release layers. After forming a gate structure on the upper surface of the second hGAA, step 110 deposits a spacer layer on the outer surface of the gate structure and on the upper surface of the hGAA not covered by the gate structure. In step 112, a series of trenches are etched within the vertically stacked superlattice structure to form source / drain regions. In step 114, the entire vertical superlattice structure is enclosed with encapsulating material from the upper surface of the substrate up to the top of the gate structure, and then spin-on, CVD carbon gap filling, or other appropriate process is performed for planarization. In step 116, the encapsulating material is etched to expose the gate structure and the second hGAA. In step 118, a protective liner is deposited on the exposed upper surfaces of the gate structure, the second hGAA, and the etched encapsulating material. In step 120, the protective liner is removed from the upper surface of the etched encapsulating material. In step 122, method 100 includes etching the encapsulating material to expose an intermediate sacrificial layer. In step 124, the intermediate sacrificial layer is removed, and an intermediate separation layer may be formed during subsequent processing.

[0038]

[0056] Figure 2 shows a simplified diagram of a CFET device 200 including a substrate 210 having a top surface 212. The substrate 210 can be any suitable substrate material known to those skilled in the art. In one or more embodiments, the substrate 210 includes semiconductor materials (e.g., silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe)), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 210 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), or selenium (Se). While several examples of materials that can form the substrate 210 are described herein, any material that can serve as a basis on which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be constructed falls within the spirit and scope of this disclosure.

[0039]

[0057] In one or more embodiments, the substrate 210 is a p-type or n-type substrate. In this specification, the term “n-type” refers to a semiconductor produced by doping an intrinsic semiconductor with an electron donor element during manufacturing. The term “n-type” derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and pores are minority carriers. In this specification, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a pore concentration greater than the electron concentration. In p-type semiconductors, pores are majority carriers and electrons are minority carriers.

[0040]

[0058] In one or more embodiments, the vertically stacked superlattice structure 260 includes one or more horizontal gate-all-around (hGAA) structures on the substrate 210. In some embodiments, the vertically stacked superlattice structure 260 includes a first or lower horizontal gate-all-around (hGAA) structure 215 on the upper surface 212 of the substrate 210. In some embodiments, the vertically stacked superlattice structure 260 includes a second or upper horizontal gate-all-around (hGAA) structure 255. Although not intended to be bound to any particular operating theory, the first hGAA 215 or second hGAA 215 and the second hGAA 255 or second hGAA 255 may independently comprise the same structure having the same layers. According to one or more embodiments, the vertically stacked superlattice structure 260 includes a first hGAA structure 215 on the upper surface 212 of a substrate 210, an intermediate sacrificial layer 240 on the upper surface 225 of the first hGAA structure 215, and a second hGAA structure 255 on the upper surface 245 of the intermediate sacrificial layer 240.

[0041]

[0059] In some embodiments, each of the first hGAA215 and the second hGAA255 includes alternating layers of nanosheet channel layers 230 and nanosheet release layers 220. In some embodiments, the multiple nanosheet release layers 220 and the multiple nanosheet channel layers 230 may include any number of lattice-matched material pairs suitable for forming a vertically stacked superlattice structure 260. In some embodiments, each of the first hGAA215 and the second hGAA255 has alternating layers of nanosheet channel layers 230 and nanosheet release layers 220 ranging from 1 to 5 pairs.

[0042]

[0060] The nanosheet release layer 220 may have any suitable thickness. In one or more embodiments, each nanosheet release layer 220 has a thickness in the range of about 5 nm to about 15 nm. The nanosheet channel layer 230 may have any suitable thickness. In one or more embodiments, each nanosheet channel layer 230 has a thickness in the range of about 4 nm to about 15 nm.

[0043]

[0061] In some embodiments, each of the nanosheet channel layers 230 independently contains silicon (Si). In some embodiments, each of the nanosheet release layers 220 independently contains silicon germanium (SiGe). In one or more embodiments, the nanosheet release layer 220 contains silicon germanium (SiGe) having a germanium content ranging from more than 0% to about 50% on an atomic basis. In certain embodiments, the nanosheet release layer 220 comprises silicon germanium (SiGe) having a germanium content ranging from about 10% to about 40% on an atomic basis, including 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30%, 31%, 32%, 33%, 34%, 35%, 36%, 37%, 38%, 39%, and 40% on an atomic basis.

[0044]

[0062] In one or more embodiments, the sacrificial layer 240 is formed between the first or lower hGAA 215 and the second or upper hGAA 255. In one or more embodiments, the intermediate sacrificial layer 240 is selectively removed and replaced with an intermediate dielectric insulating (MDI) layer 340 during subsequent processing. The intermediate dielectric insulating (MDI) layer 340 serves to electrically insulate the source / drain region of the lower hGAA 215 from the source / drain region of the upper hGAA 255. In one or more embodiments, the intermediate sacrificial layer 240 contains silicon germanium (SiGe) having a germanium content of more than 0% to about 65% on an atomic basis. In certain embodiments, the intermediate sacrificial layer 240 comprises silicon germanium (SiGe) having a germanium content ranging from about 10% to about 65% on an atomic basis, including 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, and 2% on an atomic basis. This includes 8%, 29%, 30%, 31%, 32%, 33%, 34%, 35%, 36%, 37%, 38%, 39%, 40%, 41%, 42%, 43%, 44%, 45%, 46%, 47%, 48%, 49%, 50%, 51%, 52%, 53%, 54%, 55%, 56%, 57%, 58%, 59%, 60%, 61%, 62%, 63%, 64%, and 65%.

[0045]

[0063] According to one or more embodiments, the intermediate sacrificial layer 240 is made of silicon germanium (SiGe) having a relatively higher germanium content than the germanium content in the nanosheet release layer 220. According to one or more embodiments, the nanosheet release layer 220 and the intermediate sacrificial layer 240 each contain silicon germanium (SiGe) individually having substantially the same germanium content. "Substantially the same" content means that the germanium content in the nanosheet release layer 220 is within approximately ±1% to 5% of the germanium content in the intermediate sacrificial layer 240 on an atomic basis. According to one or more embodiments, the nanosheet release layer 220 and the intermediate sacrificial layer 240 each contain silicon germanium (SiGe) individually having the same germanium content.

[0046]

[0064] In one or more embodiments, the sacrificial layer 240 may have any suitable thickness. In some embodiments, the sacrificial layer 240 has thicknesses including the ranges of about 15 nm to about 90 nm, about 15 nm to about 80 nm, about 20 nm to about 75 nm, about 15 nm to about 60 nm, about 15 nm to about 50 nm, about 15 nm to about 75 nm, and about 20 nm to about 50 nm.

[0047]

[0065] As will be recognized by those skilled in the art, during subsequent processing, the intermediate sacrificial layer 240 can be removed and replaced with an intermediate dielectric insulating (MDI) layer 340. Selective removal of the intermediate sacrificial layer 240 can be carried out by any suitable means known to those skilled in the art. In some embodiments, selective removal of the intermediate sacrificial layer 240 includes an etching process that removes the intermediate sacrificial layer 240 without causing material loss in the nanosheet release layer 220. In some embodiments, the etching process includes one or more of a wet etching process or a dry etching process. In some embodiments, the etching process is directional etching.

[0048]

[0066] As illustrated in Figures 3A to 3E, a general process for forming the CFET 200 is shown, where a vertically stacked superlattice structure 260 comprises a first or lower hGAA 215 on a substrate 210, an intermediate sacrificial layer 240 located on the lower hGAA 215, and a second or upper hGAA 255 stacked on top of the intermediate sacrificial layer 240, the superlattice structure 260 having a gate structure 270 on the upper surface of the second or upper hGAA 255 and a spacer layer 280 deposited on the outer surface of the gate structure 270. A series of trenches 290 are etched down to the upper surface 212 of the substrate within the vertically stacked superlattice structure 260 to form the source / drain region. Next, the intermediate sacrificial layer 240 is selectively removed, for example, by an etching process. Then, an intermediate dielectric insulating (MDI) material is deposited on top of the entire structure to fill the void left by the removed intermediate sacrificial layer 240. Finally, the MDI material is removed so that it remains only in the cavities left by the removed intermediate sacrificial layer 240, thus forming the intermediate dielectric insulating (MDI) layer 340.

[0049]

[0067] Figure 4 shows an enlarged view of an embodiment of the vertically stacked superlattice structure 260 after the deposition of the spacer layer 280, corresponding to Figure 3A. As shown, the first or lower hGAA 215 and the second or upper hGAA 255 each contain alternating layers of nanosheet channel layers 230 and nanosheet release layers 220. In this embodiment, each nanosheet channel layer 230 contains silicon (Si), and each nanosheet release layer 230 contains silicon germanium (SiGe). The intermediate sacrificial layer 240 contains silicon germanium (SiGe). As shown in the embodiments in Figures 3A to 3E and Figure 4, the intermediate sacrificial layer 240 is made of silicon germanium (SiGe) having a relatively higher germanium content than the germanium content in the nanosheet release layer 220 in order to selectively remove the intermediate sacrificial layer 240 while maintaining the nanosheet release layer 220.

[0050]

[0068] As shown in Figure 5A, the desired superlattice profile after selective removal of the intermediate sacrificial layer 240 is smooth and uniform. As illustrated, the surfaces of the alternating nanosheet channel layer 230 and nanosheet release layer 220 are uniform and coplanar along the stack, with no surface defects. However, it has been found that selective removal based on the relatively high germanium content in the intermediate sacrificial layer 240 results in undesirable material loss in one or more additional layers of the material. For example, as shown in Figure 5B, selective etching of the intermediate sacrificial layer 240, which has a relatively high germanium content compared to the nanosheet release layer 220, results in material loss from the nanosheet release layer 220. Instead of providing the desired smooth and uniform superlattice profile through the selective removal of only the intermediate sacrificial layer 240, portions of the nanosheet release layer 220 are also removed. As a result, a superlattice profile with alternating nanosheet channel layer 230 and nanosheet release layer 220 is provided, where the outer surface of the nanosheet release layer 220 has concave, indented, and / or surface roughness due to the removed portions of the material. As a result, after selectively removing the intermediate sacrificial layer 240, the nanosheet release layer 220 is not coplanar with the outer surface of the otherwise nanosheet channel layer 230. This material loss from the nanosheet release layer 220 negatively impacts the subsequent removal process of the nanosheet release layer 220. For example, material loss from the nanosheet release layer 220 results in a rough and non-uniform surface of the nanosheet release layer 220. This can lead to random and non-uniform spacer cavities between the nanosheet channel layers 230, potentially causing fluctuations in Vt control. In addition, as shown in Figure 5B, material loss (i.e., Si loss) has also been found in the nanosheet channel layer 220, which generates smaller and more rounded shapes (relative to the size of the nanosheet channel layer 230 before selective etching of the intermediate sacrificial layer 240). This material loss in the nanosheet channel layer 230 negatively impacts source / drain growth and device performance.

[0051]

[0069] Referring to Figures 6 to 17, according to one or more embodiments, the CFET has a vertically stacked superlattice structure 260 having a smooth profile along the upper and lower stacked hGAA structures 215, 255 after the removal of the intermediate sacrificial layer 240, and the nanosheet channel layer 230 is separated from each other by uniform spacer cavities after the nanosheet release layer 220 is subsequently removed. According to one or more embodiments, a CFET and a method for manufacturing such a device are provided, in which the nanosheet release layer 220 and the channel layer 230 are protected from damage and material loss during the removal of the intermediate sacrificial layer 240. Furthermore, according to one or more embodiments, the removal of the intermediate sacrificial layer 240 is achieved without material loss in either the nanosheet channel layer 230 or the nanosheet release layer 220, regardless of the materials used to form the intermediate sacrificial layer 240, the nanosheet channel layer 230, and the nanosheet release layer 220.

[0052]

[0070] As shown in Figure 6, according to one or more embodiments, a vertically stacked superlattice structure 260 is provided on a substrate 210. The vertically stacked superlattice structure 260 has a first or lower horizontal hGAA structure 215 on the upper surface 212 of the substrate, an intermediate sacrificial layer 240 disposed on the upper surface 225 of the first or lower hGAA structure 215, and a second or upper hGAA structure 25555 disposed on the upper surface 245 of the sacrificial layer 240. According to one or more embodiments, the first or lower hGAA structure 215 and the second or upper hGAA structure 255 each individually include alternating layers of nanosheet channel layers 230 and nanosheet release layers 220. A gate structure 270 is disposed on the upper surface of the second hGAA structure or the upper hGAA structure 255. Furthermore, the spacer layer 280 is deposited on the outer surface of the gate structure 270 and on the exposed upper surface of the second or upper hGAA structure 255 (i.e., the surface not covered by the gate structure 270). In the embodiments shown in Figures 6 to 17, six gates are shown, but it should be noted that the methods and structures are not limited to this number.

[0053]

[0071] According to one or more embodiments, a series of vertical trenches 290 are etched along the sides of the gate structure 270 within a vertically stacked superlattice structure 260. The trenches extend through a second or upper hGAA structure 255, an intermediate sacrificial layer 240, and a first or lower hGAA structure 215, and terminate at the top surface 212 of the substrate. A source / drain region is further formed. The resulting structure is shown in Figure 7.

[0054]

[0072] As shown in Figure 8, a material deposition process was performed following planarization. According to one or more embodiments, the encapsulation material 300 is deposited to surround the structure (e.g., the structure shown in Figure 7). The encapsulation material is any suitable material that can protect the underlying first or lower hGAA structure 255 during the subsequent removal of the intermediate sacrificial layer 240 (e.g., by etching or other suitable removal process). According to one or more embodiments, the encapsulation material 300 contains carbon. As shown, according to one or more embodiments, the encapsulation material 300 fills the voids throughout the vertical superlattice structure, including the trenches 290, and is deposited to surround the vertically stacked superlattice structures 260 and gate structures 270 from the substrate top surface 212 to the top of the gate structures 270. The encapsulation material 300 can be deposited by using spin-on, CVD carbon gap filling, or other suitable processes.

[0055]

[0073] According to one or more embodiments, as shown in Figure 9, a portion of the encapsulation material 300 is removed, for example, by etching. As illustrated, the encapsulation material 300 is removed from around the gate structure 270 and the second hGAA structure or the upper hGAA structure 255. As a result, as shown in Figure 9, only the substrate 210, the first or lower hGAA structure 215, and the intermediate sacrificial layer 240 remain surrounded by the encapsulation material 300.

[0056]

[0074] Figure 10 shows a protective liner 310 deposited on the exposed upper surface of the gate structure 270, the second or upper hGAA structure 255, and the encapsulation material 300 according to one or more embodiments. The protective liner 310 can be formed of any suitable material that can protect the upper or second hGAA structure 255 of the underlying layer during subsequent removal of the intermediate sacrificial layer 240 (e.g., by etching or other suitable removal treatment). According to one or more embodiments, the protective liner 310 includes a layer of AlOx or SiN having a thickness of at least about 0.5 nm to about 4 nm, including ranges of about 0.6 nm to about 3.9 nm, about 0.7 nm to about 3.8 nm, about 0.8 nm to about 3.7 nm, about 0.9 nm to about 3.6 nm, and about 1 nm to about 3.5 nm. In a particular embodiment, the protective liner 310 includes a layer of AlOx or SiN having a thickness in the range of approximately 1 nm to approximately 3 nm, which includes 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, and 3 nm.

[0057]

[0075] After the deposition of the protective liner 310, a bottom open etching process is performed to remove the protective liner 310 from the upper surface of the encapsulation material 300. As shown in Figure 11, according to one or more embodiments, the bottom open etching process exposes the sides of the trenches 290 of the vertically stacked superlattice structure 260 and the upper surface of the encapsulation material 300 located within the trenches 290, above the upper surface 245 of the intermediate sacrificial layer.

[0058]

[0076] Next, as shown in Figure 12, a portion of the encapsulation material 300 is removed to expose the intermediate sacrificial layer 240. According to one or more embodiments, carbon pullback etching is performed to expose the intermediate sacrificial layer 240. As shown in Figure 12, a vertically stacked superlattice structure 260 is provided, where (a) the substrate 210 and the first or lower hGAA structure 215 are completely enclosed and protected by the encapsulation material 300, (b) the gate structure 270 and the second or upper hGAA structure 255 are enclosed and protected by a protective liner 310, and (c) the intermediate sacrificial layer 240 is exposed for a subsequent etching or removal process.

[0059]

[0077] As shown in Figure 13, according to one or more embodiments, the intermediate sacrificial layer 240 is removed using etching or other suitable process. Once the intermediate sacrificial layer 240 is removed, the substrate 210, the first or lower hGAA structure 215, the gate structure 270, and the second or upper hGAA structure 255 are protected from the removal process (e.g., etching) and material loss.

[0060]

[0078] In Figure 14, the intermediate dielectric insulating (MDI) material 320 is deposited on top of the entire structure, filling the voids left by the removed intermediate sacrificial layer 240 and trench 290, and covering the outer surface of the device from above with the encapsulation material 300. Advantageously, depositing the MDI material 320 while the encapsulation material 300 covers the first hGAA structure or the lower hGAA structure 215 results in a lower aspect ratio, which facilitates the deposition process.

[0061]

[0079] According to one or more embodiments shown in Figure 15, the MDI material 320 is trimmed and returned so that it remains only in the cavity left by the removed intermediate sacrificial layer 240. The trim-back process is facilitated by the reduction in aspect ratio provided by the encapsulating material 300. The MDI material 320 is then densified to form the intermediate dielectric insulating (MDI) layer 340.

[0062]

[0080] As shown in Figure 16, according to one or more embodiments, the remainder of the encapsulation material 300 is removed. For example, in embodiments where the encapsulation material 300 is carbon, radical ash may be performed to remove the carbon material and expose the first or lower hGAA structure 215.

[0063]

[0081] In Figure 17, the protective liner 310 is removed, exposing the gate structure 270 and the second hGAA structure or upper hGAA structure 255.

[0064]

[0082] With the first and second hGAA structures 215, 255 exposed, further processing steps can be performed, including a selective etching process to remove the nanosheet release layer 220 and form a uniform cavity separating the nanosheet channel layer 230. A CFET formed according to one or more embodiments after the further processing steps is shown, for example, in Figure 18.

[0065]

[0083] According to one or more embodiments, a method and structure for forming an electronic device, in particular a CFET, is provided, in which shallow trench isolation (STI) oxide loss is reduced or prevented. In particular, during typical etching and cleaning procedures, STI loss can be induced, resulting in the complete exposure of the Si fin base. Subsequent epitaxial growth of the source / drain can result in growth from the bottom Si fin sidewalls, potentially inducing an electrical failure. While not bound by theory, according to one or more embodiments, the encapsulation material 300 provides a shield that protects the underlying components from cleaning, removal, and etching steps throughout the entire manufacturing process, including during etching of the intermediate sacrificial layer 240 and the MDI layer 340. By providing the encapsulation material 300 according to one or more embodiments, the underlying components are shielded, and consequently, STI loss is reduced or prevented.

[0066]

[0084] While the disclosures herein are described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and uses of the disclosure. It will be obvious to those skilled in the art that various modifications and variations can be made to the methods and apparatus of the disclosure without departing from the essence and scope of the disclosure. Therefore, the disclosure is intended to include modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor device, wherein the method is A superlattice structure stacked vertically on a substrate, The method involves forming a first horizontal gate all-around (hGAA) structure on the substrate, wherein the first hGAA structure includes alternating layers of nanosheet channel layers and nanosheet release layers. Forming an intermediate sacrificial layer on the upper surface of the first hGAA structure, The method involves forming a second horizontal gate all-around (hGAA) structure on the upper surface of the intermediate sacrificial layer, wherein the second hGAA structure includes alternating layers of nanosheet channel layers and nanosheet release layers. The encapsulating material is deposited to fill one or more trenches within the vertical stacked superlattice structure, surrounding the vertical stacked superlattice structure. By removing a portion of the aforementioned encapsulating material, the second hGAA structure is exposed. Depositing a protective liner on the second hGAA structure, Removing a portion of the aforementioned encapsulating material to expose the intermediate sacrificial layer, and Removing the aforementioned intermediate sacrificial layer, This includes forming by A method wherein the first hGAA structure is covered with the encapsulating material, and the second hGAA structure is covered with the protective liner during the removal of the intermediate sacrificial layer.

2. The method according to claim 1, wherein depositing the encapsulating material to fill one or more trenches within the vertical stacked superlattice structure and surrounding the vertical stacked superlattice structure is performed by carrying out a spin-on or chemical vapor deposition (CVD) carbon gap filling process.

3. The method according to claim 1, wherein the protective liner includes a layer of AlOx or SiN.

4. The method according to claim 3, wherein depositing the protective liner includes depositing a layer of AlOx or SiN having a thickness in the range of about 0.5 nm to about 4 nm.

5. The method according to claim 1, wherein removing the intermediate sacrificial layer includes etching the intermediate sacrificial layer.

6. The method according to claim 5, wherein the encapsulating material and the protective liner shield the first hGAA structure and the second hGAA structure, and prevent material loss in the alternating layers of the nanosheet release layer and the nanosheet channel layer during etching.

7. The method according to claim 1, further comprising: removing the intermediate sacrificial layer; depositing an intermediate dielectric insulating (MDI) material in at least the cavity formed by removing the intermediate sacrificial layer; removing the deposited excess MDI material so that the MDI material remains only in the cavity; and densifying the MDI material to form an MDI layer.

8. The method according to claim 7, further comprising: densifying the MDI material, then removing the encapsulation material and the protective liner to expose the first hGAA structure and the second hGAA structure; and performing selective etching to remove alternating layers of nanosheet release layers from the first hGAA structure and the second hGAA structure.

9. The method according to claim 1, wherein the alternating layers of the nanosheet channel layer contain silicon (Si), the alternating layers of the nanosheet release layer contain silicon germanium (SiGe), and the intermediate sacrificial layer contains silicon germanium (SiGe).

10. The method according to claim 9, wherein the alternating layers of the nanosheet release layer contain silicon germanium (SiGe) having an atomic germanium content of about 10% to about 40%, and the intermediate sacrificial layer contains silicon germanium (SiGe) having an atomic germanium content of about 10% to about 65%.

11. The method according to claim 10, wherein the alternating layers of the nanosheet release layer contain silicon germanium (SiGe) having an atomic germanium content of about 15% to about 35%, and the intermediate sacrificial layer contains silicon germanium (SiGe) having an atomic germanium content of about 15% to about 35%.

12. The method according to claim 9, wherein the alternating layers of the nanosheet release layer and the intermediate sacrificial layer are manufactured from the same material.

13. The method according to claim 1, wherein the etching selectivity of the material forming the alternating layers of the nanosheet release layer is the same as that of the material forming the intermediate sacrificial layer.

14. The method according to claim 7, wherein the MDI material is deposited while the first hGAA structure is covered with the encapsulating material, and the deposited excess MDI material is removed, thereby providing a low aspect ratio for depositing and removing the MDI material.

15. The method according to claim 7, wherein the density of the MDI material is increased by increasing the density of the MDI material while the first hGAA structure is covered with the encapsulating material and while the second hGAA structure is covered with the protective liner.

16. A method for forming a semiconductor device, wherein the method is A superlattice structure stacked vertically on a substrate, The method involves forming a first horizontal gate all-around (hGAA) structure on the substrate, wherein the first hGAA structure includes alternating layers of nanosheet channel layers and nanosheet release layers. Forming an intermediate sacrificial layer on the upper surface of the first hGAA structure, The method involves forming a second horizontal gate all-around (hGAA) structure on the upper surface of the sacrificial layer, wherein the second hGAA structure includes alternating layers of nanosheet channel layers and nanosheet release layers, and Etching the aforementioned intermediate sacrificial layer, Including being formed by, The alternating layers of the nanosheet release layer in the first hGAA structure and the nanosheet release layer in the second hGAA structure, and the intermediate sacrificial layer, comprise the same material. The second hGAA structure is shielded by a protective liner while the intermediate sacrificial layer is being etched, and the first hGAA structure is shielded by an encapsulating material while the intermediate sacrificial layer is being etched. A method by which no material loss occurs in the alternating layers of nanosheet release layers in the first hGAA structure and the second hGAA structure by etching the intermediate sacrificial layer.

17. The method according to claim 16, wherein the encapsulating material is carbon and is deposited on the first hGAA structure using a spin-on or chemical vapor deposition (CVD) carbon void-filling process.

18. The method according to claim 16, wherein the protective liner includes a layer of AlOx or SiN.

19. The method according to claim 16, wherein the alternating layers of the nanosheet channel layer contain silicon (Si), the alternating layers of the nanosheet release layer contain silicon germanium (SiGe), and the intermediate sacrificial layer contains silicon germanium (SiGe).

20. The method according to claim 19, wherein the alternating layers of the nanosheet release layer and the intermediate sacrificial layer each contain silicon germanium (SiGe) having the same germanium content.

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