N-channel linked to P-channel and method for manufacturing the same

Abstract

A logic device and a method for manufacturing a logic device are provided. The semiconductor logic device is an n-channel gate all-around (n-GAA) field-effect transistor on a substrate, and includes an n-channel gate all-around (n-GAA) field-effect transistor integrated with a p-channel gate all-around (p-GAA) field-effect transistor on a substrate adjacent to an n-channel gate all-around (p-GAA) field-effect transistor. The n-channel gate all-around (n-GAA) field-effect transistor has a structure comprising a plurality of layers comprising silicon and a corresponding plurality of layers comprising at least 25% germanium, these layers being arranged alternately in stacked pairs extending between a source region and a drain region, and the p-channel gate all-around (p-GAA) field-effect transistor has a plurality of layers comprising germanium in the range of 5% to 15% and a corresponding plurality of layers comprising at least 25% germanium, these layers being arranged alternately in stacked pairs.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic devices, and methods and apparatuses for manufacturing electronic devices. More specifically, embodiments of the present disclosure provide methods for forming logic devices and transistors, such as gate-all-around devices (GAA), fin field-effect transistors (FinFETs), and complementary field-effect transistors (CFETs), having an n-channel connected to a p-channel.

Background Art

[0002]

[0002] Integrated circuits have evolved into complex devices that can house millions of transistors, capacitors, and resistors on a single chip. In the process of the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the feature size (i.e., the smallest component (or line) that can be fabricated using a manufacturing process) has decreased.

[0003]

[0003] Transistors are important components in most integrated circuits. Since the drive current, and thus the speed, of a transistor is proportional to the gate width of the transistor, generally a larger gate width is required for a faster transistor. Therefore, there is a trade-off between the size and speed of a transistor, and "fin" field-effect transistors (FinFETs) have been developed to address the conflicting goals of maximum drive current and minimum size. FinFETs are characterized by a fin-shaped channel region that can significantly increase the size of a transistor without significantly increasing the implementation area of the transistor, and are currently applied to many integrated circuits. However, FinFETs have their own drawbacks.

[0004]

[0004] In order to improve circuit density and achieve higher performance, the characteristic size of transistor devices continues to shrink, and improvements in transistor device structure are required to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and leakage current in the off state. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and gate-all-around (GAA) structures.

[0005]

[0005] The GAA device structure includes several lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. The GAA structure provides good electrostatic control and can be widely adopted in complementary metal oxide semiconductor (CMOS) wafer manufacturing. Post-high dielectric constant (HK) nitriding is one of the attractive features of CMOS equivalent oxide thickness (EOT) scaling, enabling high-performance transistors. However, HK post-nitriding degrades the end-of-line (EOL) negative bias temperature instability (NBTI) of p-channel metal oxide semiconductor (PMOS) transistors, resulting in a trade-off with EOT scaling gain.

[0006]

[0006] Therefore, in the art, there is a need for a logic device that enables MOS EOT scaling with improved RO performance without reducing performance reliability. Furthermore, in the art, there is a need for a method and apparatus for forming a logic device. [Overview of the Initiative]

[0007]

[0007] One or more embodiments of the present disclosure relate to methods for forming semiconductor logic devices. In one or more embodiments, the method for forming a semiconductor logic device is to form a first superlattice structure on a substrate, the first superlattice structure comprising a plurality of first layers containing silicon and a plurality of corresponding second layers containing at least 25% germanium, arranged alternately in a plurality of stacked pairs extending between a source region and a drain region; The method involves forming a second superlattice structure on a substrate, wherein the second superlattice structure comprises a plurality of third layers containing germanium in the range of 5% to 15%, and a plurality of corresponding fourth layers containing at least 25% germanium, arranged alternately in a plurality of stacked pairs extending between a source region and a drain region; The process involves selectively etching multiple second layers and multiple fourth layers simultaneously to form nMOS transistors and pMOS transistors. Includes.

[0008]

[0008] Further embodiments of the present disclosure relate to semiconductor logic devices. In one embodiment, the semiconductor logic device comprises an n-channel gate all-around (n-GAA) field-effect transistor on a substrate; and a p-channel gate all-around (p-GAA) field-effect transistor on a substrate adjacent to the n-channel gate all-around (n-GAA) field-effect transistor; Equipped with, An n-channel gate all-around (n-GAA) field-effect transistor includes a first superlattice structure comprising a plurality of first layers containing silicon and a plurality of corresponding second layers containing at least 25% germanium, arranged alternately in a plurality of stacked pairs extending between a source region and a drain region. A p-channel gate all-around (p-GAA) field-effect transistor includes a second superlattice structure comprising a plurality of third layers containing germanium in the range of 5-15% and a plurality of corresponding fourth layers containing at least 25% germanium, arranged alternately in a plurality of stacked pairs extending between a source region and a drain region.

[0009]

[0009] Further embodiments of the present disclosure relate to a non-temporary computer-readable medium containing instructions, which, when executed by a controller of a processing chamber, causes the processing chamber to perform the following actions: The first superlattice structure is formed on a substrate, wherein the first superlattice structure comprises a plurality of first layers containing silicon and a plurality of corresponding second layers containing at least 25% germanium, arranged alternately in a plurality of stacked pairs extending between a source region and a drain region. The method involves forming a second superlattice structure on the substrate, wherein the second superlattice structure comprises a plurality of third layers containing germanium in the range of 5% to 15% and a plurality of corresponding fourth layers containing at least 25% germanium, arranged alternately in a plurality of stacked pairs extending between the source region and the drain region. The process involves selectively etching multiple second layers and multiple fourth layers simultaneously to form nMOS transistors and pMOS transistors. This includes an order to perform the action.

[0010]

[0010] To enable a more detailed understanding of the features of the Disclosure described above, a more detailed description of the Disclosure, which has been briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the Disclosure, and therefore the Disclosure may allow for other equally valid embodiments and should not be considered to limit its scope. Embodiments described herein are illustrated for illustrative purposes and are not limited to the figures in the accompanying drawings, where similar reference numerals indicate similar elements. [Brief explanation of the drawing]

[0011] [Figure 1] This document shows a process flow diagram of one or more methods according to the embodiments described herein. [Figure 2] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2A] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2B] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2C] Shows a cross-sectional view of a device according to one or more embodiments. [Figure 3A] Shows a cross-sectional view of a device according to one or more embodiments. [Figure 3B] Shows a cross-sectional view of a device according to one or more embodiments. [Figure 3C] Shows a cross-sectional view of a device according to one or more embodiments. [Figure 4] Shows a cross-sectional view of a device according to one or more embodiments. [Figure 5] Shows a cross-sectional view of a device according to one or more embodiments. [Figure 6A] Shows a cross-sectional view of a device according to one or more embodiments. [Figure 6B] Shows a cross-sectional view of a device according to one or more embodiments. [Figure 7] Is a schematic top view of an exemplary multi-chamber processing system according to one or more embodiments.

Mode for Carrying Out the Invention

[0012]

[0024] For ease of understanding, wherever possible, the same reference numbers are used to denote the same elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without further description.

[0013]

[0025] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or process steps described in the following description. The present disclosure can have other embodiments and can be practiced or executed in various ways.

[0014]

[0026] As used herein, the term "about" means approximately or nearly and, in reference to a stated numerical value or range, means a variation of up to ±15% of that numerical value. For example, values that differ by up to ±14%, ±10%, ±5%, ±2%, ±1%, ±0.5%, or ±0.1% satisfy the definition of about.

[0015]

[0027] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element to another element, to facilitate description, or as shown in the figures. It is to be understood that spatially relative terms are intended to encompass different orientations of a device, such as a semiconductor device in use or operation, in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, an element described as "beneath" or "directly below" another element or feature would be oriented "above" the other element or feature. Thus, the exemplary term "below" can encompass both an upward and a downward orientation. The device may be oriented in other orientations (rotated 90 degrees or otherwise), and the spatially relative descriptions used herein are to be interpreted accordingly.

[0016]

[0028] As used in this specification and the appended claims, the term "substrate" or "wafer" refers to the surface or a portion of the surface on which a process acts. When reference is made to a substrate, one of ordinary skill in the art should understand that, unless otherwise explicitly stated in the context, it may refer to only a portion of the substrate. Further, when reference is made to deposition on a substrate, it may mean both a bare substrate and a substrate on which one or more films or features have been deposited or formed.

[0017]

[0029] As used herein, “substrate” refers to any substrate or material surface formed on a substrate on which a film treatment is performed during the manufacturing process. For example, substrate surfaces that may be treated include, depending on the application, materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. A substrate includes, but is not limited to, a semiconductor wafer. A substrate may be subjected to a pretreatment process, and the substrate surface may be polished, etched, reduced, oxidized, hydroxylated (or otherwise to create or graft target chemical moieties to impart chemical functionality), annealed, and / or baked. In addition to direct film treatment on the surface of the substrate itself, any of the disclosed film treatment steps may also be performed on underlying layers formed on the substrate, as will be disclosed in more detail below. Furthermore, the term "substrate surface," as the context indicates, is intended to include such underlying layers. Therefore, for example, if a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What constitutes a given substrate surface depends on the type of film deposited and the specific chemical properties used.

[0018]

[0030] A substrate surface may have one or more features formed therein, one or more layers formed thereon, and combinations thereof. The shape of a feature may be any suitable shape, including, but not limited to, trenches, holes, and vias (circular or polygonal). The term “feature” as used herein refers to any intentional irregular portion of a surface. Suitable examples of features include, but are not limited to, trenches having a top, two sidewalls, and a bottom extending into the substrate, vias having one or more sidewalls extending into the substrate, and slot vias. Features described herein may have any preferred aspect ratio (ratio of feature depth to feature width). In one or more embodiments, the aspect ratio of features described herein is about 1:1, 2:1, 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, or 40:1 or greater.

[0019]

[0031] The term "on" indicates direct contact between elements. The term "directly on" indicates direct contact between elements without an intervening element.

[0020]

[0032] As used herein and in the appended claims, terms such as “precursor,” “reactant,” and “reactive gas” are interchangeable and refer to any gas species that can react with the substrate surface.

[0021]

[0033] Sputtering is a physical vapor deposition (PVD) process in which high-energy ions collide with and erode a solid target, depositing the target material onto the surface of a substrate such as a semiconductor substrate. In semiconductor manufacturing, the sputtering process is typically carried out in a semiconductor manufacturing chamber, also known as a PVD processing chamber or sputtering chamber. Sputtering has long been used for depositing metals and related materials in the manufacture of semiconductor integrated circuits.

[0022]

[0034] Typically, a sputtering chamber comprises a housing wall surrounding a processing zone into which a processing gas is introduced, a gas exciter that energizes the processing gas, and an exhaust port that exhausts the processing gas from the chamber and controls its pressure. The chamber is used to sputter deposit material onto a semiconductor substrate from a sputtering target. In the sputtering process, the sputtering target is bombarded by energy ions such as plasma, knocking off the material from the target and depositing it as a film onto the semiconductor substrate.

[0023]

[0035] A typical semiconductor manufacturing chamber has a target assembly that includes a disc-shaped target made of a solid metal or other material, supported by a backing plate that holds the target. To facilitate uniform deposition, the PVD chamber may have an annular concentric metal ring, often called a shield, that surrounds the disc-shaped target in a circumferential direction.

[0024]

[0036] Plasma sputtering can be achieved using either DC sputtering or radio frequency sputtering. Plasma sputtering typically involves a magnetron positioned behind the sputtering target, which contains two magnets with opposing poles magnetically coupled at its back through a magnetic yoke, emitting a magnetic field into the processing space to increase the plasma density and the sputtering rate from the front of the target. The magnets used in the magnetron are typically closed-loop in DC sputtering and open-loop in radio frequency sputtering.

[0025]

[0037] As used herein, “atomic layer deposition” or “periodic deposition” refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate or a portion of the substrate is exposed separately to two or more reactive compounds introduced into the reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay, so that each compound can adhere to and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, various portions of the substrate surface, or material on the substrate surface, are exposed simultaneously to two or more reactive compounds such that no given point on the substrate is substantially exposed to multiple reactive compounds at the same time. As used herein and in the appended claims, the term “substantially” as used in this respect means, as understood by those skilled in the art, that a small portion of the substrate may be exposed simultaneously by diffusion to multiple reactive gases, but simultaneous exposure is not intended.

[0026]

[0038] In one embodiment of time-domain ALD processing, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction area, or otherwise remove any residual reactive compounds or reactive byproducts from the reaction area. Alternatively, the purge gas may flow continuously throughout the entire deposition process so that only the purge gas flows during the time delays between pulses of the reactive compounds. The reactive compounds are pulsed alternately until a desired film or thickness is formed on the substrate surface. In either case, one cycle consists of compound A, purge gas, compound B, and the ALD processing with pulsed purge gas. A cycle may begin with either compound A or compound B, and each stage of the cycle may continue until a film of a predetermined thickness is achieved.

[0027]

[0039] In one embodiment of spatial ALD processing, a first reactive gas and a second reactive gas (e.g., hydrogen gas) are supplied simultaneously to the reaction zone but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas supply device so that any given point on the substrate is exposed to the first and second reactive gases.

[0028]

[0040] One or more of the layers deposited on the substrate or the substrate surface are continuous. As used herein, the term “continuous” refers to a layer that covers the entire exposed surface without gaps or bare spots that expose the material beneath the deposited layer. A continuous layer may have gaps or bare spots having a surface area of ​​less than about 15% or less than 10% of the total surface area of ​​the layer.

[0029]

[0041] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive wires, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric interposed between the gate electrode of the substrate and the channel region.

[0030]

[0042] As used herein, the term “field-effect transistor” or “FET” refers to a transistor that uses an electric field to control the electrical behavior of a device. Enhancement-mode field-effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by the voltage difference between the body and the gate of the device. The three terminals of an FET are the source (S) through which carriers enter the channel, the drain (D) through which carriers exit the channel, and the gate (G), which is the terminal that modulates the conductivity of the channel. Conventionally, the source (S) through which carriers enter the channel is IS The current entering the channel at the drain (D) is specified as follows: ID This is specified. The voltage between the drain and source is called VDS. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., ID) can be controlled.

[0031]

[0043] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the voltage applied to it determines the device's conductivity. This ability to change conductivity in response to the applied voltage is used to amplify or switch electronic signals. A MOSFET is based on the modulation of charge concentration by metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a separate, highly doped region separated by the body region. These regions can be p-type or n-type, but both are the same type, and are the opposite type to the body region. The source and drain (unlike the body) are highly doped, and the doping type is followed by a "+" symbol.

[0032]

[0044] If a MOSFET is an n-channel or nMOS FET, the source and drain are in the n+ region, and the body is in the p region. If a MOSFET is a p-channel or pMOS FET, the source and drain are in the p+ region, and the body is in the n region. The source is so named because it is the source of charge carriers (electrons in the case of an n-channel, and holes in the case of a p-channel) flowing through the channel. Similarly, the drain is where charge carriers exit the channel.

[0033]

[0045] As used herein, the term "Fin-field-effect transistor (FinFET)" refers to a MOSFET transistor built on a substrate in which the gate is located on two or three sides of the channel, forming a double or triple-gate structure. FinFET devices are given the common name FinFET because the channel region forms "fins" on the substrate. FinFET devices have fast switching times and high current density.

[0034]

[0046] As used herein, the term “gate all around (GAA)” is used to refer to electronic devices such as transistors in which the gate material completely surrounds the channel region. The channel region of a GAA transistor may include nanowires or nanoslabs, or nanosheets, rod-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of vertically spaced horizontal nanowires or horizontal bars, making the GAA transistor a stacked horizontal gate all around (hGAA) transistor. A stacked horizontal gate all around (hGAA) transistor may include any suitable number of stacked horizontal gate all around (hGAA) channels. In some embodiments, a stacked horizontal gate all around (hGAA) transistor includes a range of 2 to 10 stacked horizontal gate all around (hGAA) channels.

[0035]

[0047] An example of gate-all-around (GAA) technology is the complementary field-effect transistor (CFET). As used herein, the term “complementary field-effect transistor (CFET)” refers to a transistor comprising NMOS FET devices and PMOS FET devices stacked together. Each of the NMOS FET and PMOS FET devices forming the CFET is a GAA transistor or hGAA transistor. Compared to GAA transistors, CFET transistors offer increased on-chip device density and reduced area consumption.

[0036]

[0048] As used herein, the term “nanowire” refers to a nanostructure having a diameter in units of nanometers (10⁻⁹ meters). A nanowire may also be defined as having a length-to-width ratio greater than 1000. Alternatively, a nanowire may be defined as a structure whose thickness or diameter is limited to tens of nanometers or less, but whose length is not limited. Nanowires are used in transistors and certain laser applications and, in one or more embodiments, are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in logic CPUs, GPUs, MPUs, and transistors for volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term “nanosheet” refers to a two-dimensional nanostructure having a thickness ranging from about 0.1 nm to about 1000 nm.

[0037]

[0049] Embodiments of the present disclosure are illustrated by diagrams illustrating devices (e.g., gate-all-around devices, FinFETs, and CFETs) and processes for forming transistors according to one or more embodiments of the present disclosure. The illustrated processes are merely illustrative examples of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0038]

[0050] The following description includes numerous specific details, such as particular materials, chemical properties, and element dimensions, in order to provide a complete understanding of one or more embodiments of this disclosure. However, it will be apparent to those skilled in the art that one or more embodiments of this disclosure can be implemented without these specific details. In other examples, semiconductor manufacturing processes, techniques, materials, and equipment are not described in detail to avoid unnecessarily obscuring this description. Those skilled in the art will be able to implement appropriate functionality using the information contained herein without conducting unnecessary experiments.

[0039]

[0051] While certain exemplary embodiments of this disclosure are described and shown in the accompanying drawings, such embodiments are merely illustrative and not limiting to this disclosure. Modifications may occur in the art, so please understand that this disclosure is not limited to the specific configurations and arrangements shown and described.

[0040]

[0052] One or more embodiments of this disclosure are described with reference to the drawings. In one or more embodiments, an n-channel field-effect transistor is coupled or integrated with a p-channel field-effect transistor to form a semiconductor logic device. In one or more embodiments, an n-channel gate-all-around field-effect transistor is coupled or integrated with a p-channel gate-all-around field-effect transistor to form a semiconductor logic device. In certain embodiments, a silicon-germanium (SiGe) channel is used to improve the EOT scaling performance of a PMOS device and, in combination with a silicon (Si) channel NMOS device, to form a gate-all-around nanosheet CMOS device. In other specific embodiments, a silicon-germanium (SiGe) channel is used to improve the EOT scaling performance of a PMOS device and, in combination with a silicon (Si) channel NMOS device, to form a CMOS device. In one or more embodiments, the combination of an n-channel gate-all-around field-effect transistor and a p-channel gate-all-around field-effect transistor results in improved EOT scaling in the range of over 5 Å to 1.5 Å and an overall CMOS RO speed gain of over 5% without causing a decrease in reliability performance. In one or more embodiments, SiGe channel PMOS may contribute to other advantages, including, but not limited to, a reduction in threshold voltage (Vt) and improved hole mobility. In other embodiments, the formed semiconductor logic devices are compatible with FinFET and CFET (hybrid-coupled monolithic / sequential) technologies, in addition to compatibility with GAA nanosheet technology.

[0041]

[0053] Figure 1 shows a process flow diagram of Method 10 for forming semiconductor logic devices such as gate-all-around devices, FinFETs, and CFETs according to some embodiments of the present disclosure. Figures 2A to 7 show the manufacturing steps of a semiconductor logic structure according to some embodiments of the present disclosure. In one or more embodiments, silicon germanium (SiGe) channels are integrated with the optimization of interlayer dielectric and high dielectric constant dielectric stack nitridation for PMOS.

[0042]

[0054] Method 10 is described below with reference to Figures 1 to 7. Figures 1 to 7 are cross-sectional views of an electronic device (e.g., GAA, FinFET, CFET) according to one or more embodiments. Method 10 may be part of a multi-stage manufacturing process for semiconductor devices. Thus, Method 10 may be carried out in any suitable process chamber coupled to a cluster tool. The cluster tool may include processing chambers for manufacturing semiconductor devices, such as etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in the manufacture of semiconductor devices.

[0043]

[0055] Figures 2 to 7 show the manufacturing steps of operations 12 to 24 in Figure 1. Referring to Figure 1, method 10 for forming device 100 begins in operation 12, providing a substrate 102 and forming a superlattice structure on the substrate 102. In some embodiments, the substrate 102 may be a bulk semiconductor substrate. In this specification, the term “bulk semiconductor substrate” refers to a substrate whose entirety is made of semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor material may include one or more materials, such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 102 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 102 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While some examples of materials that can form substrates are described herein, any material that can function as a basis on which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be constructed is included in the spirit and scope of this disclosure.

[0044]

[0056] In some embodiments, the semiconductor material may be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. Herein, the term “n-type” refers to a semiconductor made by doping an intrinsic semiconductor with an electron donor element during manufacturing. The term “n-type” derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and pores are minority carriers. Herein, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a pore concentration greater than the electron concentration. In p-type semiconductors, pores are majority carriers and electrons are minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof.

[0045]

[0057] Referring to Figure 2, in one or more embodiments, a first superlattice structure 114 is formed on the upper surface of the substrate 102, and a second superlattice structure 108 is formed on the upper surface of the substrate 102 adjacent to the first superlattice structure 114. In one or more embodiments, the first superlattice structure 114 forms the NMOS region of the semiconductor memory device 100, and the second superlattice structure 108 forms the PMOS region of the semiconductor memory device 100.

[0046]

[0058] In one or more embodiments, the first superlattice structure 114 comprises a plurality of first layers 112 containing silicon and a plurality of corresponding second layers containing at least 25% germanium, these layers being alternately arranged in a plurality of stacked pairs extending between a source region 116a and a drain region 116b. In one or more embodiments, the plurality of second layers 110 contain silicon germanium (SiGe) having at least 25% germanium (Ge). In some embodiments, the amount of germanium (Ge) in the plurality of second layers is in the range of greater than 25% to 100%, greater than 25% to 90%, greater than 25% to 75%, or greater than 25% to 50%.

[0047]

[0059] In one or more embodiments, the second superlattice structure 108 comprises a plurality of third layers 106 containing germanium in the range of 5% to 15%, and a corresponding plurality of fourth layers 104 containing at least 25% germanium, wherein these layers are alternately arranged in a plurality of stacked pairs extending between a source region 116a and a drain region 116b. In one or more embodiments, the plurality of fourth layers 104 contain silicon germanium (SiGe) having at least 25% germanium (Ge). In some embodiments, the amount of germanium (Ge) in the plurality of fourth layers 104 is in the range of greater than 25% to 100%, greater than 25% to 90%, greater than 25% to 75%, or greater than 25% to 50% germanium. In one or more embodiments, the plurality of third layers 106 include silicon germanium (SiGe) having germanium in the range of 5% to 15%, including germanium in the range of 5% to 10%, and germanium in the range of 5% to 15%.

[0048]

[0060] In one or more embodiments, the first superlattice structure 114 may be formed by any suitable means known to those skilled in the art. In some embodiments, the first superlattice structure 114 is formed by epitaxial growth of a plurality of first layers 112 and a corresponding plurality of second layers 110.

[0049]

[0061] In one or more embodiments, the second superlattice structure 108 can be formed by any suitable means known to those skilled in the art. In some embodiments, the second superlattice structure is formed by bottom-up growth of a plurality of fourth layers 104, followed by bottom-up growth of a plurality of third layers 106, or by HCl sidewall etch-back, as shown in Figures 2A to 2C, where HCl is an etching chemical performed in-situ in an EPI chamber.

[0050]

[0062] In other embodiments, as shown in Figures 3A to 3C, the second superlattice structure 108 may be formed by bottom-p growth of a plurality of fourth layers 104 followed by conformal deposition of a plurality of third layers 106.

[0051]

[0063] Referring to Figures 2 to 7, in one or more embodiments, the plurality of fourth layers 104 and the corresponding plurality of third layers 106 may include any number of lattice-matched pairs suitable for forming a superlattice structure 108. In one or more embodiments, the plurality of second layers 110 and the corresponding plurality of first layers 112 may include any number of lattice-matched pairs suitable for forming a superlattice structure 114. In some embodiments, the plurality of third layers 106 and the corresponding plurality of fourth layers 104 include about 4 to about 20 pairs of lattice-matched material. In some embodiments, the plurality of first layers 112 and the corresponding plurality of second layers 110 include about 4 to about 20 pairs of lattice-matched material.

[0052]

[0064] In one or more embodiments, the thickness t1 of a plurality of first layers 112, a plurality of second layers 110, a plurality of third layers 106, and a plurality of fourth layers 104 is independently in the range of about 2 nm to about 30 nm, a range of about 3 nm to about 20 nm, or a range of about 2 nm to about 11111.

[0053]

[0065] Referring to Figures 1 and 4, in operation 16, in one or more embodiments, a dummy gate structure 120 is formed on a first superlattice structure 114 and a second superlattice structure 108. The dummy gate structure 120 defines the channel region of the transistor device. The dummy gate structure 120 defines the channel region 118 of the transistor device. The dummy gate structure 120 can be formed using any suitable conventional deposition and patterning process known in the art. In one or more embodiments, the dummy gate structure 120 includes one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and N-doped polysilicon. In one or more embodiments, the channel region 118 separates the dummy gate structure 120 from adjacent dummy gate structures.

[0054]

[0066] Referring to Figures 1 and 4-6, in some embodiments, during operation 18, the sidewall spacers 122 are formed on the superlattices 108, 114 along the outer sidewalls of the dummy gate structure 120. The sidewall spacers 122 may include any suitable insulating material known in the art, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. In some embodiments, the sidewall spacers are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma atomic layer deposition, plasma chemical vapor deposition, low-pressure chemical vapor deposition, or isotropic deposition.

[0055]

[0067] In operation 20, the channel region 118 is recessed to form a source trench 116a and a drain trench 116b. In one or more embodiments, the source trench 116a and the drain trench 116b are formed adjacent to (i.e., on either side of) the first superlattice structure 114 and the second superlattice structure 108. In one or more embodiments, the source trench or region 116a is adjacent to the first end of the first superlattice structure 114, and the drain trench or region 116b is adjacent to the second opposite end of the first superlattice structure 114.

[0056]

[0068] Referring to Figure 1, in operation 22, the formation of a semiconductor device, for example, a GAA, continues according to a conventional procedure involving the release of nanosheets and the formation of a substituted metal gate (operation 24). Specifically, as shown in Figure 5, in one or more embodiments, a plurality of second layers 104 and a plurality of fourth layers 110 selectively recess from the sides of the superlattice structure 108, 114 to form a recessed region 124.

[0057]

[0069] Referring to Figure 6A, silicon germanium (SiGe) layers containing more than 25% germanium (i.e., multiple second layers 104 and multiple fourth layers 110) are selectively etched to form channel nanowires. The silicon germanium (SiGe) layers containing more than 25% germanium (i.e., multiple second layers 104 and multiple fourth layers 110) may also be removed using any well-known etchant that is selective to the multiple first layers 106 and multiple third layers 112, by which the silicon germanium (SiGe) layers containing more than 25% germanium (i.e., multiple second layers 104 and multiple fourth layers 110) are etched at a significantly higher rate than the multiple first layers 106 and multiple third layers 112. In some embodiments, selective dry etching or wet etching may be used. In some embodiments, silicon germanium layers containing more than 25% germanium can be selectively removed using wet etchants such as, but not limited to, carboxylic acid / nitric acid / HF aqueous solutions and citric acid / nitric acid / HF aqueous solutions. Removal of silicon germanium (SiGe) layers containing more than 25% germanium (i.e., a plurality of second layers 104 and a plurality of fourth layers 110) leaves voids 126 between a plurality of first layers 106 and a plurality of third layers 113. The voids 126 between the plurality of first layers 106 and a plurality of third layers 113 independently have thicknesses ranging from about 3 nm to about 20 nm. The remaining plurality of first layers 106 and a plurality of third layers 113 form a vertical array of channel nanowires 130 bonded 132 to source / drain regions 116a, 116b. The channel nanowires 130 run parallel to the upper surface of the substrate 102 and align with each other to form a single row of channel nanowires.

[0058]

[0070] The etching process of operation 22 may include any suitable etching process that is selective for the spacer material 122. In some embodiments, the etching process of operation 22 includes one or more wet etching processes or dry etching processes.

[0059]

[0071] In some embodiments, the dry etching process may include any conventional plasma etching or any suitable remote plasma-assisted dry etching process known to those skilled in the art. In one or more embodiments, the etching process includes a device exposed to H2, NF3, and / or NH3 plasma species, e.g., plasma-excited hydrogen and fluorine species. For example, in some embodiments, the device may be simultaneously exposed to H2, NF3, and NH3 plasmas. The etching process may be performed in any suitable pre-cleaning chamber that can be incorporated into one of various multi-processing platforms known to those skilled in the art. The wet etching process may include a hydrofluoric acid (HF) final process, i.e., a so-called "HF final" process in which HF etching of the surface is performed, leaving a hydrogen termination on the surface. Alternatively, any other liquid-based pre-cleaning treatment before epitaxial growth may be employed. In some embodiments, the treatment includes sublimation etching for the removal of native oxides. The etching treatment may be plasma or heat-based. The plasma treatment may be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0060]

[0072] Referring to Figure 6B, in one or more embodiments not shown, a high dielectric constant dielectric material 134 is deposited. The high dielectric constant dielectric material 134 can be any suitable high dielectric constant dielectric material deposited by any suitable deposition technique known to those skilled in the art. In some embodiments, the high dielectric constant dielectric material 134 contains hafnium oxide. In some embodiments, conductive materials (not shown), such as titanium nitride (TiN), tungsten (W), cobalt (Co), and aluminum (Al), are deposited on the high dielectric constant dielectric to form a substitutional metal gate. The conductive material can be formed using any suitable deposition process, not limited to atomic layer deposition (ALD), for reliable formation.

[0061]

[0073] In some embodiments, method 10 is integrated so as not to cause vacuum breakage. In one or more embodiments, the formation of superlattice structures 108, 114 (operation 12), nanosheet patterning (operation 14), dummy gate patterning (operation 16), spacer formation (18), source / drain formation (operation 20), nanosheet release (operation 22), and substitution gate formation (operation 24) can be integrated so as not to cause vacuum breakage between operations.

[0062]

[0074] Additional embodiments of this disclosure, as shown in Figure 7, relate to processing tools 300 and the described methods for forming gate-all-around (GAA) devices, FinFETs, and CFETs. Figure 7 shows a schematic top view of an example of a multi-chamber processing system 700 according to embodiments of this disclosure. The processing system 700 generally includes a factory interface 702, load lock chambers 704, 706, transfer chambers 708, 710 having transfer robots 712, 714 respectively, holding chambers 716, 718, and processing chambers 720, 722, 724, 726, 728, 730. As detailed herein, wafers in the processing system 700 can be processed in various chambers and transferred between various chambers without exposing the wafers to the ambient environment outside the processing system 700 (e.g., an atmospheric environment that may be present in a factory). For example, wafers can be processed in various chambers under low pressure (e.g., below approximately 300 Torr) or vacuum conditions, and transferred between various chambers, without disrupting the low-pressure or vacuum environment during the various processes performed on the wafers within the processing system 700. Thus, the processing system 700 can provide an integrated solution for several wafer processing operations.

[0063]

[0075] Examples of processing systems that can be appropriately modified in accordance with the teachings provided herein include any integrated processing system or other suitable commercially available processing systems.

[0064]

[0076] In the illustrated example in Figure 7, the factory interface 702 includes a docking station 740 and a factory interface robot 742 to facilitate wafer transfer. The docking station 740 is configured to receive one or more front-opening unified pods (FOUPs) 744. In some embodiments, each factory interface robot 742 generally includes a blade 748 located at one end of the factory interface robot 742, configured to transfer wafers from the factory interface 702 to the load lock chambers 704, 706.

[0065]

[0077] Load lock chambers 704 and 706 have ports 750 and 752 connected to the factory interface 702, respectively, and ports 754 and 756 connected to the transfer chamber 708, respectively. Transfer chamber 708 further has ports 758 and 760 connected to the holding chambers 716 and 718, respectively, and ports 762 and 764 connected to the processing chambers 720 and 722, respectively. Similarly, transfer chamber 710 has ports 766 and 768 connected to the holding chambers 716 and 718, respectively, and ports 770, 772, 774, and 776 connected to the processing chambers 724, 726, 728, and 730, respectively. Ports 754, 756, 758, 760, 762, 764, 766, 768, 770, 772, 774, and 776 can be slit valve openings, for example, that have slit valves to allow wafers to pass through by transfer robots 712 and 714 and to prevent gas from passing between the respective chambers. Generally, any port is open for wafer transfer. Otherwise, the port is closed.

[0066]

[0078] The load lock chambers 704, 706, transfer chambers 708, 710, holding chambers 716, 718, and processing chambers 720, 722, 724, 726, 728, 730 may be fluid-coupled to a gas and pressure control system (not shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), a gas source, various valves, and fluid-coupled conduits to the various chambers. During operation, the factory interface robot 742 transfers wafers from FOUP 744 through port 750 or 752 to the load lock chamber 704 or 706. The gas and pressure control system then pumps down the load lock chamber 704 or 706. The gas and pressure control system further maintains the transfer chambers 708, 710 and the holding chambers 716, 718 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, pumping down the load lock chamber 704 or 706 facilitates, for example, passing the wafer between the atmospheric environment of the factory interface 702 and the low-pressure or vacuum environment of the transfer chamber 708.

[0067]

[0079] With the wafer in load lock chamber 704 or 706 pumped down, the transfer robot 712 transfers the wafer from load lock chamber 704 or 706 through port 754 or 756 into transfer chamber 708. The transfer robot 712 can then transfer the wafer to either processing chamber 720 or 722 via ports 762 or 764 for processing, and / or to holding chambers 716 or 718 via ports 758 or 760 for holding awaiting further transfer. Similarly, the transfer robot 714 can access the wafer in holding chamber 716 or 718 via port 766 or 768 and transfer the wafer to any processing chamber, and / or between these processing chambers, to any processing chamber 724, 726, 728, or 730 via ports 770, 772, 774, or 776 for processing, and can process and hold chambers 716 or 718 via ports 766 or 768 for holding awaiting further transfer. Wafer transfer and holding within and between various chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0068]

[0080] Processing chambers 720, 722, 724, 726, 728, and 730 can be any suitable chamber for processing wafers. In some embodiments, processing chamber 720 can perform an annealing process, processing chamber 722 can perform a cleaning process, and processing chambers 724, 726, 728, and 730 can perform epitaxial growth processes. In some embodiments, processing chamber 722 can perform a cleaning process, processing chamber 720 can perform an etching process, and processing chambers 724, 726, 728, and 730 can perform their respective epitaxial growth processes. Processing chamber 722 may be any suitable pre-cleaning chamber known to those skilled in the art. Processing chamber 720 may be any suitable etching chamber known to those skilled in the art.

[0069]

[0081] A system controller 790 is connected to the processing system 400 to control the processing system 700 or its components. For example, the system controller 790 can control the operation of the processing system 700 by using direct control of the chambers 704, 706, 708, 716, 718, 710, 720, 722, 724, 726, 728, and 730 of the processing system 700, or by controlling the controllers associated with the chambers 704, 706, 708, 716, 718, 710, 720, 722, 724, 726, 728, and 730. During operation, the system controller 790 enables data collection and feedback from each chamber to adjust the performance of the processing system 700.

[0070]

[0082] The system controller 790 generally includes a central processing unit (CPU) 792, memory 794, and support circuitry 796. The CPU 792 may be one of any form of general-purpose processor available for use in an industrial environment. The memory 794 or non-temporary computer-readable medium is accessible by the CPU 792 and may be one or more of the following: random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital storage. The support circuitry 796 is connected to the CPU 792 and may include a cache, clock circuitry, input / output subsystems, power supply, etc. The various methods disclosed herein can generally be implemented by the CPU 792 executing, for example, computer instruction code stored in memory 794 (or the memory of a particular processing chamber) as a software routine under the control of the CPU 792. Once the computer instruction code is executed by the CPU 792, the CPU 792 controls each chamber to perform processing according to various schemes.

[0071]

[0083] Other processing systems can also be configured in other ways. For example, more or fewer processing chambers may be connected to the transfer device. In the illustrated example, the transfer device includes transfer chambers 708, 710 and holding chambers 716, 718. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as transfer devices within the processing system.

[0072]

[0084] In the context of describing the materials and methods discussed herein (in particular in the context of the following claims), the use of “a” and “an,” “the,” and similar referents should be interpreted as encompassing both singular and plural, unless otherwise indicated herein or unless clearly contradicted by the context. The enumeration of ranges of values ​​herein is merely intended to serve as a shorthand notation for referring individually to each individual value within the range, unless otherwise indicated herein, and each individual value is incorporated into the specification as if it were individually stated herein. All methods described herein may be performed in any appropriate order, unless otherwise indicated herein or unless clearly contradicted by the context. Any and all examples or illustrative language provided herein (e.g., “such as”) is merely intended to better describe the materials and methods and does not impose any limitation of scope unless specifically asserted otherwise. Nothing in this specification should be interpreted as indicating any unclaimed element essential to the practice of the disclosed materials and methods.

[0073]

[0085] Throughout this Specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiment” means that a particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this Disclosure. Therefore, any other reference to “in one or more embodiments,” “a particular embodiment,” “in one embodiment,” or “in an embodiment” in various parts of this Specification does not necessarily refer to the same embodiment of this Disclosure. Furthermore, a particular feature, structure, material, or property may be combined in any suitable manner in one or more embodiments.

[0074]

[0086] While the disclosures herein have been described with reference to specific embodiments, those skilled in the art will understand that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be obvious to those skilled in the art that various modifications and alterations can be made to the methods and apparatus of the disclosure without departing from the essence and scope of the disclosure. Accordingly, the disclosure may include modifications and alterations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor logic device, The first superlattice structure is formed on a substrate, wherein the first superlattice structure comprises a plurality of first layers containing silicon and a plurality of corresponding second layers containing at least 25% germanium, arranged alternately in a plurality of stacked pairs extending between a source region and a drain region. The method involves forming a second superlattice structure on the substrate, wherein the second superlattice structure includes a plurality of third layers containing germanium in the range of 5% to 15% and a plurality of corresponding fourth layers containing at least 25% germanium, arranged alternately in a plurality of stacked pairs extending between the source region and the drain region. The plurality of second layers and the plurality of fourth layers are selectively etched simultaneously to form nMOS transistors and pMOS transistors, Methods that include...

2. The method according to claim 1, wherein each of the plurality of third layers comprises silicon germanium having germanium in the range of 5% to 10%.

3. The method according to claim 1, wherein each of the plurality of second layers comprises silicon germanium having at least 25% germanium.

4. The method according to claim 1, wherein each of the plurality of fourth layers comprises silicon germanium having at least 25% germanium.

5. The method according to claim 1, wherein forming the second superlattice structure includes bottom-up growth of the plurality of fourth layers and bottom-up growth of the plurality of third layers.

6. The method according to claim 1, wherein forming the second superlattice structure includes bottom-up growth of the plurality of fourth layers and etch-back of the HCL sidewalls to grow the plurality of third layers.

7. The method according to claim 1, wherein forming the second superlattice structure includes bottom-up growth of the plurality of fourth layers and conformal deposition of the plurality of third layers.

8. The method according to claim 1, further comprising forming a first gate structure on the first superlattice structure and forming a second gate structure on the second superlattice structure.

9. The method according to claim 1, further comprising forming the source region adjacent to the first end of the first superlattice structure and the drain region adjacent to the second opposing end of the first superlattice structure.

10. The method according to claim 8, further comprising forming side wall spacers on the outer side walls of the first gate structure and the second gate structure.

11. The method according to claim 10, further comprising depositing an interlayer dielectric (ILD) layer on the semiconductor logic device.

12. The method according to claim 8, further comprising recessing the plurality of second layers and recessing the plurality of fourth layers from the second superlattice structure.

13. The method according to claim 8, wherein the first gate structure and the second gate structure independently comprise one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), and titanium aluminum (TiAl).

14. The method according to claim 1, wherein the process is carried out in a processing chamber without disrupting the vacuum.

15. The method according to claim 1, wherein the semiconductor logic device has gates around its entire circumference.

16. An n-channel gate all-around (n-GAA) field-effect transistor on a substrate, A p-channel gate all-around (p-GAA) field-effect transistor on the substrate adjacent to the n-channel gate all-around (n-GAA) field-effect transistor, A semiconductor logic device that is equipped with the following features: The n-channel gate all-around (n-GAA) field-effect transistor includes a first superlattice structure comprising a plurality of first layers containing silicon and a corresponding plurality of second layers containing at least 25% germanium, arranged alternately in a plurality of stacked pairs extending between a source region and a drain region, and the p-channel gate all-around (p-GAA) field-effect transistor includes a second superlattice structure comprising a plurality of third layers containing germanium in the range of 5 to 15% and a corresponding plurality of fourth layers containing at least 25% germanium, arranged alternately in a plurality of stacked pairs extending between the source region and the drain region, wherein the semiconductor logic device.

17. The semiconductor logic device according to claim 16, wherein each of the plurality of third layers comprises silicon germanium having germanium in the range of 5% to 10%.

18. The semiconductor logic device according to claim 16, wherein each of the plurality of second layers comprises silicon germanium having at least 25% germanium.

19. The semiconductor logic device according to claim 16, wherein each of the plurality of fourth layers comprises silicon germanium having at least 25% germanium.

20. When executed by the controller of the processing chamber, the processing chamber performs the following operations: The first superlattice structure is formed on a substrate, wherein the first superlattice structure comprises a plurality of first layers containing silicon and a plurality of corresponding second layers containing at least 25% germanium, arranged alternately in a plurality of stacked pairs extending between a source region and a drain region. The method involves forming a second superlattice structure on the substrate, wherein the second superlattice structure comprises a plurality of third layers containing germanium in the range of 5% to 15% and a plurality of corresponding fourth layers containing at least 25% germanium, arranged alternately in a plurality of stacked pairs extending between the source region and the drain region. The process involves selectively etching multiple second layers and multiple fourth layers simultaneously to form nMOS transistors and pMOS transistors. A non-temporary computer-readable medium containing instructions to perform an action.

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