Memory device formed on a silicon-on-insulator substrate and method for manufacturing the same

Abstract

The memory device includes an SOI substrate comprising bulk silicon, an insulating layer vertically above the bulk silicon, and a silicon layer vertically above the insulating layer. The memory cell includes a source region and a drain region formed in the bulk silicon, with a channel region of bulk silicon extending between the source region and the drain region, and a floating gate comprising a first portion of the silicon layer disposed vertically above a first portion of the channel region and insulated from the first portion of the channel region by the insulating layer. The first portion of the silicon layer is epitaxially thickened, or a polysilicon layer is formed on the first portion of the silicon layer. A selection gate is disposed vertically above a second portion of the channel region and insulated from the second portion of the channel region. A control gate is disposed vertically above the floating gate and insulated from the floating gate. An erase gate is disposed vertically above the source region and insulated from the source region.

Description

Technical Field

[0001] (Related Applications) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 466,821, filed May 16, 2023, and U.S. Patent Application No. 18 / 228,414, filed Jul. 31, 2023.

[0002] (Field of the Invention) This disclosure relates to non-volatile memory devices.

Background Art

[0003] Non-volatile memory devices (i.e., devices including at least non-volatile memory cells) formed on a bulk silicon semiconductor substrate are well known. For example, U.S. Pat. Nos. 6,747,310, 7,868,375, and 7,927,994 disclose memory cells having four gates (floating gate, control gate, select gate, and erase gate) formed on a bulk semiconductor substrate. Source and drain regions are formed as diffusion implantation regions into the substrate, defining a channel region therebetween in the substrate. The floating gate is disposed vertically above a first portion of the channel region and insulated from the first portion of the channel region (i.e., there is no intervening gate between the floating gate and the first portion of the channel region) to directly control the conductivity of the first portion of the channel region, the select gate is disposed vertically above a second portion of the channel region and insulated from the second portion of the channel region (i.e., there is no intervening gate between the select gate and the second portion of the channel region) to directly control the conductivity of the second portion of the channel region, the control gate is disposed vertically above the floating gate and insulated from the floating gate to capacitively couple with the floating gate, and the erase gate is disposed vertically above the source region and insulated from the source region. The bulk substrate is optimal for these types of memory devices because deep diffusion into the substrate can be used to form the source and drain region junctions. These three patents are hereby incorporated by reference in their entirety for all purposes.

[0004] Silicon-on-insulator (SOI) devices are also well-known in the field of microelectronics. SOI devices differ from bulk silicon substrate devices in that they are not made of solid silicon (i.e., bulk silicon), but rather a substrate and an embedded insulating layer are laminated beneath the silicon surface (i.e., silicon-insulator-silicon). In an SOI substrate, there is a thin silicon layer vertically above the insulating layer, and the insulating layer is located vertically above the bulk silicon. In SOI devices, silicon junctions (e.g., source and drain regions) are formed in the thin silicon layer. The insulating layer is typically silicon dioxide (oxide). This substrate configuration reduces the capacitance of parasitic devices and improves performance. SOI substrates can be manufactured by SIMOX (separation by oxygen implantation using oxygen ion beam implantation; see U.S. Patents No. 5,888,297 and No. 5,061,642), wafer bonding (bonding silicon oxide to a second substrate and removing most of the second substrate; see U.S. Patent No. 4,771,016), or seeding (growing the top layer of silicon directly into an insulating layer; see U.S. Patent No. 5,417,180). These four patents are incorporated herein by reference for all purposes.

[0005] Forming source and drain regions on a thin silicon layer limits the depth of these regions and negatively impacts memory cell performance, making SOI substrates unsuitable for non-volatile memory devices. However, other devices typically formed on the same substrate, such as CMOS logic devices and HV devices, benefit from being formed on SOI substrates because their source / drain regions do not need to have the same depth as the memory cell's source / drain region, and therefore are better suited to the thin silicon layer of the SOI substrate. The advantages of SOI substrates need to be combined with non-volatile memory devices that are better suited to being formed on bulk silicon substrates. [Overview of the project]

[0006] The aforementioned problems and needs are addressed by a memory device comprising a SOI substrate including bulk silicon, an insulating layer vertically above the bulk silicon, a silicon layer vertically above the insulating layer, and memory cells disposed in the memory cell region of the SOI substrate. The memory cell includes a source region and a drain region formed in bulk silicon, with a channel region of bulk silicon extending between the source region and the drain region, a floating gate, a selection gate, a control gate, and an erase gate. The floating gate includes a first portion of a silicon layer disposed vertically above a first portion of the channel region and insulated from the first portion of the channel region by the insulating layer, and a polysilicon layer of the first portion of the silicon layer. The selection gate is disposed vertically above a second portion of the channel region and insulated from the second portion of the channel region. The control gate is disposed vertically above the floating gate and insulated from the floating gate. The erase gate is disposed vertically above the source region and insulated from the source region.

[0007] A method for forming a memory device includes the steps of providing an SOI substrate comprising bulk silicon, an insulating layer vertically above the bulk silicon, and a silicon layer vertically above the insulating layer, and forming a memory cell in a memory cell region of the SOI substrate. Memory cell formation includes the steps of: forming a source region and a drain region in bulk silicon, wherein a channel region of bulk silicon extends between the source region and the drain region; forming a floating gate which includes a first portion of a silicon layer disposed vertically above a first portion of the channel region and insulated from the first portion of the channel region by an insulating layer, wherein the step of forming the floating gate includes the step of epitaxially growing silicon on the first portion of the silicon layer, or the step of forming a polysilicon layer on the first portion of the silicon layer; forming a selection gate which is disposed vertically above a second portion of the channel region and insulated from the second portion of the channel region; forming a control gate which is disposed vertically above the floating gate and insulated from the floating gate; and forming an erase gate which is disposed vertically above the source region and insulated from the source region.

[0008] Other purposes and features of this disclosure will become apparent upon careful reading of the specification, claims, and accompanying drawings.

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Brief Description of the Drawings

[0022] [Figure 1] It is a perspective view of a silicon-on-insulator (SOI) substrate. [Figure 2A] It is a side sectional view of a memory cell by a memory device of the first example. [Figure 2B] It is a side sectional view of a logic device by a memory device of the first example. [Figure 2C] It is a side sectional view of a high-voltage device by a memory device of the first example. [Figure 3A] It is a side sectional view of a memory cell by a memory device of the second example. [Figure 3B] It is a side sectional view of a logic device by a memory device of the second example. [Figure 3C] It is a side sectional view of a high-voltage device by a memory device of the second example. [Figure 4A] It is a side sectional view of a memory cell by a memory device of the third example. [Figure 4B] It is a side sectional view of a logic device by a memory device of the third example. [Figure 4C] It is a side sectional view of a high-voltage device by a memory device of the third example. [Figure 4D] It is a side sectional view of a memory cell by a memory device of the fourth example. [Figure 5A] It is a partial perspective view showing the formation of a memory device of the first example. [Figure 5B] It is a partial perspective view showing the formation of a memory device of the first example. [Figure 5C] It is a partial perspective view showing the formation of a memory device of the first example. [Figure 5D]This is a partial perspective view showing the formation of a memory device in the first example. [Figure 5E] This is a partial perspective view showing the formation of a memory device in the first example. [Figure 5F] This is a partial perspective view showing the formation of a memory device in the first example. [Figure 5G] This is a partial perspective view showing the formation of a memory device in the first example. [Figure 5H] This is a partial perspective view showing the formation of a memory device in the first example. [Figure 6A] This is a partial perspective view showing the formation of a memory device in the second example. [Figure 6B] This is a partial perspective view showing the formation of a memory device in the second example. [Figure 6C] This is a partial perspective view showing the formation of a memory device in the second example. [Figure 6D] This is a partial perspective view showing the formation of a memory device in the second example. [Figure 6E] This is a partial perspective view showing the formation of a memory device in the second example. [Figure 7A] This is a partial perspective view showing the formation of a memory device in the third example. [Figure 7B] This is a partial perspective view showing the formation of a memory device in the third example. [Figure 7C] This is a partial perspective view showing the formation of a memory device in the third example. [Figure 7D] This is a partial perspective view showing the formation of a memory device in the third example. [Figure 7E] This is a partial perspective view showing the formation of a memory device in the third example. [Figure 7F] This is a partial perspective view showing the formation of a memory device in the third example. [Modes for carrying out the invention]

[0023] This disclosure relates to non-volatile memory cells formed on a silicon-on-insulator substrate (also referred to herein as an SOI substrate), wherein a thin layer of silicon on the SOI substrate is used for at least a portion of the floating gate of the memory cell, an insulating layer on the SOI substrate is used as an insulating layer between the floating gate and its respective channel region, and the source and drain regions of the memory cell are formed in the bulk silicon region of the SOI substrate. A logic device can be formed on the same SOI substrate along with a source and drain region formed in a thin silicon layer, and a high-voltage device can be formed in a region of the SOI substrate from which the thin silicon layer and insulating layer have been removed, resulting in the source and drain regions of the high-voltage device being formed in bulk silicon.

[0024] Figure 1 shows a silicon-on-insulator (SOI) substrate 10, which comprises three parts: a bulk silicon layer 12 at the bottom, an insulating layer 14 vertically above the bulk silicon 12 (for example, called an oxide-buried oxide-BOX), and a thin silicon layer 16 vertically above the insulating layer 14. The formation of SOI substrates is well known in the art as described above and in the U.S. patents specified above, and is therefore not described further herein. The SOI substrate 10 may have three regions: a memory cell region MC where memory cells are formed, a logic device region LG where logic devices are formed, and a high-voltage device region HV where high-voltage devices are formed.

[0025] Figures 2A to 2C show a first example of a memory device formed on the SOI substrate 10, the memory device including a memory cell 20 formed in the memory cell region MC (as shown in Figure 2A), a logic device 22 formed in the logic device region LG (as shown in Figure 2B), and a high-voltage device 24 formed in the high-voltage device region HV (as shown in Figure 2C).

[0026] The memory cell 20 includes a source region 30 and a drain region 32 formed in bulk silicon 12, with a channel region 34 of bulk silicon 12 between the source region 30 and the drain region 32. A floating gate 36 is positioned vertically above a first portion of the channel region 34 and is isolated from the first portion of the channel region 34; a selection gate 38 is positioned vertically above a second portion of the channel region 34 and is isolated from the second portion of the channel region 34; a control gate 40 is positioned vertically above the floating gate 36 and is isolated from the floating gate 36; and an erase gate 42 is positioned vertically above the source region 30 and is isolated from the source region 30. The memory cells 20 can be formed in pairs, and as shown in Figure 2A, a pair of memory cells 20 can share a common source region 30 and a common erase gate 42. Multiple pairs of memory cells can be formed end-to-end and share a common drain region.

[0027] The floating gate 36 includes a first portion of the silicon layer 16 of the SOI substrate 10, which is insulated from the bulk silicon 12 by the insulating layer 14 of the SOI substrate 10. Specifically, when forming the memory cell 20, the silicon layer 16 and insulating layer 14 of the SOI substrate remain with respect to the floating gate 36, but are removed from the rest of the memory cell 20. The second portion of the silicon layer 16 and insulating layer 14 of the SOI substrate remains with respect to the logic device region LG, in which the logic device 22 includes a logic source region 46 and a logic drain region 48 formed in the second portion of the silicon layer 16, with the logic channel region 50 of the second portion of the silicon layer 16 extending between the logic source region 46 and the logic drain region 48. The logic gate 52 is positioned vertically above the logic channel region 50 to directly control its conductivity and is insulated from the logic channel region 50. Using selective epitaxial growth, the vertical thickness of the logic source region 46 and the logic drain region 48 can be increased, as shown in Figure 2B. Finally, the silicon layer 16 and the insulating layer 14 of the SOI substrate are removed from the high-voltage device region HV, in which the high-voltage device 24 includes an HV source region 54 and an HV drain region 56 formed in the bulk silicon 12, with an HV channel region 58 of the bulk silicon 12 extending between the HV source region 54 and the HV drain region 56. The HV gate 60 is positioned vertically above the HV channel region 60 to directly control its conductivity and is isolated from the HV channel region.

[0028] The selection gate 38, control gate 40, erase gate 42, logic gate 52, and HV gate 60 may be high-k metal gates. Non-limiting examples of such high-k metal gates include a high-k insulating layer 66 (i.e., a layer of a material having a dielectric constant K greater than that of silicon dioxide, such as HfO2), a metal layer 68 such as TiAlN, and a polysilicon layer 70. High-k metal gates can have higher conductivity and provide better performance than gates formed solely of polysilicon. The erase gate 42 may have a first portion laterally adjacent to the floating gate 36 and a second portion extending vertically upward from the floating gate 36, such that the erase gate 42 has a notch 42a facing the edge 36a of the floating gate 36, in order to enable good tunneling during the erase operation.

[0029] The process flow used to form the memory device can be greatly simplified by using a first portion of the silicon layer 16 as a floating gate 36 for the memory cell 20 and a first portion of the insulating layer 14 as a floating gate insulator for the bulk silicon 12, and by using a second portion of the silicon layer 16 and a second portion of the insulating layer 14 for the logic device 22. In this configuration, the silicon layer 16 of the SOI substrate 10 is used as a gate (i.e., a floating gate 36) in the memory cell region MC and as the source region, drain region, and channel region in the logic device region LG.

[0030] The inventors have found that using a first portion of the silicon layer 16 of the SOI substrate 10 (which may have a thickness of approximately 80-100 Å) as the floating gate 36 may present performance problems because the silicon layer 16 may be too thin to function as an effective floating gate. Therefore, as shown in Figure 2A, a polysilicon layer 62 is formed on the silicon layer 16 of the memory cell region MC, and the silicon layer 16 and the polysilicon layer 62 are combined to form the floating gate 36. The polysilicon layer 62 can be dopanted to enhance its conductivity. A non-limiting example is the inclusion of n+ doping of the polysilicon layer. The combined thickness of the silicon layer 16 and the polysilicon layer 62 allows for better doping control as a single floating gate 36 and avoids programming problems associated with ballistic electron transport.

[0031] Figures 3A to 3C show a second example of a memory device formed on the SOI substrate 10, which is the same as the example in Figures 2A to 2C, except that the thickness of the floating gate 36 is increased by epitaxially growing silicon 64 on the silicon layer 16 instead of forming a polysilicon layer, so that the thickness of the floating gate 36 is the sum of the thickness of the silicon layer 16 and the epitaxially grown silicon 64. Increasing the vertical thickness of the floating gate 36 by epitaxial growth of the silicon layer 16, and increasing the vertical thickness of the logic source region 46 and the logic drain region 48, can be done using the same epitaxial growth process steps.

[0032] Figures 4A to 4C show a third example of a memory device formed on the SOI substrate 10, which is the same as the second example in Figures 3A to 3C, except that the selection gate 38 has a first portion 38a that is laterally adjacent to the floating gate 36 and a second portion 38b that extends vertically upward from the floating gate 36, and the spacing between the selection gate 38 and the control gate 40 can be reduced for better performance and better control of the isolation between the selection gate 38 and the floating gate 36, which may be important for programming.

[0033] Figure 4D shows a fourth example, which is the same memory cell 20 as in the third example in Figure 4A, except that the floating gate 36 includes a silicon layer 16 and a polysilicon layer 62. The logic device 22 shown in Figure 4B and the high-voltage device 24 shown in Figure 4C for the third example in Figure 4A may be the same for the fourth example in Figure 4D.

[0034] Figures 1 and 5A to 5H illustrate the process for forming the memory device shown in Figures 2A to 2C. This process begins with an SOI substrate 10 having bulk silicon 12, an insulating layer 14, and a silicon layer 16, as shown in Figure 1. As shown in Figure 5A, an insulating layer 72, such as silicon dioxide (i.e., oxide), is formed on the silicon layer 16. A mask layer 74, such as photoresist or silicon nitride, is formed on the structure and then selectively removed from the memory cell region MC, leaving the insulating layer 72 exposed in the memory cell region MC. Oxide etching is used to remove the exposed portion of the insulating layer 72 in the memory cell region MC, exposing the silicon layer 16 in the memory cell region MC, as shown in Figure 5B, but not in the logic device region LC or high-voltage device region HV. As shown in Figure 5C, after the mask layer 74 is removed, a polysilicon layer 62 is formed on top of the structure. A mask layer 76 is formed on the structure and selectively removed outside the memory cell region MC. Using etching, the polysilicon layer 62 exposed from the logic device region LG and the high-voltage device region HV is removed, as shown in Figure 5D (the polysilicon layer 62 is maintained in the memory cell region MC below the mask layer 76, and the polysilicon layer 62 eventually forms part of the floating gate together with the underlying silicon layer 16).

[0035] After removing the mask layer 76, the structure is patterned using a patterned mask layer 78, where the polysilicon layer 62, insulating layer 72, silicon layer 16, a portion of the insulating layer 14, and a portion of the bulk silicon 14 are selectively removed to form the device structure in the memory cell region MC, the logic device region LG, and the high-voltage device region HV, respectively, as shown in Figure 5E. The structure is covered with an STI insulator 80, which may be an oxide, and the STI insulator 80 is planarized by chemical mechanical polishing, which removes the mask layer 78 and exposes the polysilicon layer 62 in the memory cell region MC, as shown in Figure 5F. The structure is selectively etched, leaving the polysilicon layer 62 and the separated floating gates 36 of the underlying silicon layer 16 in the memory cell region MC, as shown in Figure 5G. Using etching and deposition, the silicon layer 16 and insulating layer 14 are removed from the high-voltage device region HV, and different gate oxides are formed in the three regions MC / LG / HV. Subsequently, a high-k insulating layer 66 such as HfO2, a metal layer 68 such as TiAlN, and a polysilicon layer 70 are deposited and patterned (i.e., selectively removed) to form the aforementioned selective gate 38, control gate 40, erase gate 42, logic gate 52, and HV gate 60 for the memory cell 20, logic device 22, and high-voltage device 24, respectively, as shown in Figure 5H, completing the device structure shown in Figures 2A to 2C.

[0036] Figures 6A to 6E illustrate the process of forming the memory device shown in Figures 3A to 3C. This process begins with the structure shown in Figure 5B. However, instead of directly depositing the polysilicon layer onto the exposed portion of the silicon layer 16, selective epitaxy is performed in the memory cell region MC to epitaxially grow silicon 64 onto the silicon layer 16 (effectively thickening the silicon layer 16), as shown in Figure 6A. Although silicon 64 is shown separately in Figures 4A and 6A, silicon 64 is not a separate layer of silicon, but rather silicon 64 that grows on the silicon layer 16, thickening the silicon layer 16 with the additionally grown silicon 64. The same steps described above are performed with respect to Figures 5D to 5H to complete the structure, namely, forming the device structure using the patterned mask layer 78 and etching (Figure 6B), forming and planarizing the STI insulator 80 to leave the silicon 64 (i.e., the thickened silicon layer 16) exposed (Figure 6C), selectively etching the structure to leave the isolated floating gate 36 of the thickened silicon layer 16 (Figure 6D), performing etching and deposition to remove the silicon layer 16 and insulating layer 14 from the high-voltage device region HV, forming different gate oxides in the three regions MC / LG / HV, and then performing deposition and patterning (i.e., selective removal) of the high-k insulating layer 66, metal layer 68, and polysilicon layer 70 to form the complete device structure shown in Figures 3A to 3C (Figure 6E).

[0037] Figures 7A to 7F show the process of forming the memory device shown in Figures 4A to 4C. This process begins with the structure shown in Figure 6D. After etching and deposition to remove the silicon layer 16 and insulating layer 14 from the high-voltage device region HV, forming different gate oxides in the three regions MC / LG / HV, and depositing the high-k insulating layer 66, metal layer 68, and polysilicon layer 70, the resulting structure in the memory cell region MC is shown in Figure 7A. As shown in Figure 7B, a first mask layer 82, which may be an oxide, is formed on the polysilicon layer 70. The first mask layer 82 is patterned (i.e., selectively removed) using a photoresist 84, leaving an opening 86 in the first mask layer 82 that exposes a portion of the polysilicon layer 70 vertically above the floating gate 36, as shown in Figure 7C. The opening 86 may have a first width W1. After removing the photoresist 84, a second mask layer 88, which may be the same material as the first mask layer 82, is formed on the structure. The second mask layer 88 may have a thickness that narrows the opening 86, as shown in Figure 7D, and the second mask layer 88 is positioned at the bottom of the opening 86. Anisotropic etching is then performed, which removes the second mask layer 88 from the bottom of the opening 86, while leaving a spacer of layer 88 along the vertical sidewalls of layer 82 of the opening 86, extending downward to the polysilicon layer 70, as shown in Figure 7E, resulting in an opening 86 having a second width W2 smaller than the first width W1. Using one or more etchings, portions of the polysilicon layer 70, metal layer 68, and high-k insulating layer 66 below the opening 86 are removed, extending the opening 86 through the polysilicon layer 70, metal layer 68, and high-k insulating layer 66 with a width W2. As shown in Figure 7F, this creates a gap 86a of width W2 between the control gate 40 and the selection gate 38, and a gap 86b of width W2 between the control gate 40 and the erase gate 42, and the second width W2 is smaller than the first width W1 defined by lithography as shown in Figure 7C. This makes the second width W2 gap between the control gate 40 and the adjacent selection gate 38 and erase gate 42 smaller than the lithography resolution limit used to initially form the opening 86 having width W1.Furthermore, by positioning the gaps 86a and 86b between the control gate 40 and the adjacent selection gate 38 and erase gate 42 vertically above the floating gate 36, it is possible to avoid low-density CMOS spacer material between the floating gate 36 and the selection gate 38, which are in direct proximity to the silicon substrate 12 and could lead to charge trapping during programming and associated reliability problems.

[0038] Regarding Figures 7A to 7F, which show the process for forming the memory devices in Figures 4A to 4C, please note that the memory device in Figure 4D can be formed using the process described above. The only change might be to start with the structure in Figure 5G instead of the structure in Figure 6D.

[0039] The aforementioned technologies have many advantages. The same material layer is used to form the gates of these devices, excluding the floating gate, thereby simplifying the manufacturing process and making it more reliable. These technologies improve the functionality and reliability of memory cells as well as their manufacturing. Increasing the thickness of the floating gate leads to better doping control and avoids programming problems associated with ballistic electron transport. Spacer-enhanced patterning technology allows for a reduction in the gap between the floating gate and the selection gate, thereby improving the conditions for programming by hot electron injection. Spacer-enhanced patterning technology provides a gap between the control gate and the selection gate that should be positioned vertically above the floating gate, making the gap between the selection gate and the floating gate and the gap between the control gate and the selection gate uncorrelated, thereby avoiding the presence of low-density spacer material in the separation gap between the selection gate 38 and the floating gate 36 adjacent to the substrate 12, and thus limiting undesirable charge traps during programming and improving durability.

[0040] This disclosure is not limited to the embodiments illustrated herein and should be understood to encompass any modifications that fall within the scope of any claim. For example, reference in this disclosure or to the invention or embodiments is not intended to limit any claim or the scope of any claim terminology, but rather to one or more features that may be covered by one or more claims. The examples of materials, processes, and numerical structures described above are illustrative and should not be considered to limit the scope of any claim. A single material layer can be formed as a number of layers composed of such or similar materials, and vice versa. Finally, as used herein, the terms “formed” and “created” include material deposition, material formation, or any other technique in providing the disclosed or claimed material.

Claims

1. A memory device, An SOI substrate comprising bulk silicon, an insulating layer located vertically above the bulk silicon, and a silicon layer located vertically above the insulating layer, The SOI substrate comprises a memory cell disposed in the memory cell region, and the memory cell is Source region and drain region formed in the bulk silicon, wherein the channel region of the bulk silicon extends between the source region and the drain region, It is a floating gate, The first portion of the silicon layer is disposed vertically above the first portion of the channel region and is insulated from the first portion of the channel region by the insulating layer, A floating gate comprising a polysilicon layer in the first portion of the silicon layer, A selection gate is disposed vertically above the second portion of the channel region and is isolated from the second portion of the channel region, A control gate is disposed vertically above the floating gate and is insulated from the floating gate, A memory device comprising: an erase gate disposed vertically above the source region and isolated from the source region.

2. The SOI substrate comprises a logic device disposed in the logic device region, and the logic device is A logic source region and a logic drain region formed in a second portion of the silicon layer, wherein the logic channel region of the silicon layer extends between the logic source region and the logic drain region, The memory device according to claim 1, comprising a logic gate disposed vertically above the logic channel region and isolated from the logic channel region.

3. The SOI substrate comprises a high-voltage device disposed in the high-voltage device region, and the high-voltage device is The HV source region and HV drain region formed in the bulk silicon, wherein the HV channel region of the bulk silicon extends between the HV source region and the HV drain region, The memory device according to claim 2, comprising an HV gate disposed vertically above the HV channel region and isolated from the HV channel region.

4. The memory device according to claim 1, wherein the erase gate includes a notch facing the edge of the floating gate.

5. The memory device according to claim 3, wherein the selection gate, the control gate, the erase gate, the logic gate, and the HV gate each include a high-k insulating layer, a metal layer, and a polysilicon layer.

6. A method for forming a memory device, The steps of providing an SOI substrate comprising bulk silicon, an insulating layer located vertically above the bulk silicon, and a silicon layer located vertically above the insulating layer, The step includes forming a memory cell in the memory cell region of the SOI substrate, The step of forming a memory cell in the memory cell region of the SOI substrate is: The steps of forming a source region and a drain region in the bulk silicon, wherein the channel region of the bulk silicon extends between the source region and the drain region. A step of forming a floating gate, comprising: a step of epitaxially growing silicon on the first portion of the silicon layer, or a step of forming a polysilicon layer on the first portion of the silicon layer, wherein the floating gate is disposed vertically above the first portion of the channel region and is insulated from the first portion of the channel region by the insulating layer, the floating gate is formed by epitaxially growing silicon on the first portion of the silicon layer, or a step of forming a polysilicon layer on the first portion of the silicon layer. A step of forming a selection gate that is disposed vertically above the second portion of the channel region and is isolated from the second portion of the channel region, The steps include forming a control gate that is disposed vertically above the floating gate and is insulated from the floating gate, and The step of forming an erase gate that is disposed vertically above the source region and isolated from the source region, A method for forming memory cells in the memory cell region of the SOI substrate.

7. The method according to claim 6, wherein the step of forming the erase gate includes the step of forming a notch in the erase gate that faces the edge of the floating gate.

8. The step of forming the selection gate, the control gate, and the erase gate is: The steps include forming a high-k insulating layer in the memory cell region, The steps include forming a metal layer on the high-k insulating layer in the memory cell region, The steps include forming a polysilicon layer on the metal layer in the memory cell region, The steps include forming a first mask layer on the polysilicon layer in the memory cell region, The steps include forming an opening having a first width in the first mask layer, The steps include forming a second mask layer on the first mask layer and within the opening, The step of removing a portion of the second mask layer such that the opening extends downward to the polysilicon layer and has a second width smaller than the first width, The method according to claim 6, comprising the step of removing a portion of the polysilicon layer, the metal layer, and the high-k insulating layer vertically below the opening, thereby leaving a first gap of the second width between the control gate and the selection gate, and a second gap of the second width between the control gate and the erase gate.

9. The method according to claim 8, wherein the first gap and the second gap are arranged vertically above the floating gate.

10. The steps of forming a logic source region and a logic drain region in a second portion of the silicon layer, wherein the logic channel region of the first portion of the silicon layer extends between the logic source region and the logic drain region, and The step of forming a logic gate that is disposed vertically above the logic channel region and isolated from the logic channel region, The method according to claim 6, comprising the step of forming a logic device in the logic device region of the SOI substrate.

11. The steps of forming an HV source region and an HV drain region in the bulk silicon, wherein the HV channel region of the bulk silicon extends between the HV source region and the HV drain region, and The step of forming an HV gate that is disposed vertically above the HV channel region and is insulated from the HV channel region, The method according to claim 10, further comprising the step of forming a high-voltage device in the high-voltage device region of the SOI substrate.

12. The method according to claim 11, wherein the step of forming the selection gate, the control gate, the erase gate, the logic gate, and the HV gate includes the step of forming a high-k insulating layer, a metal layer, and a polysilicon layer.

13. The step of forming the selection gate, the control gate, the erase gate, the logic gate, and the HV gate is: The steps include forming a high-k insulating layer in the memory cell region, the logic device region, and the high-voltage device region, The steps include forming a metal layer on the high-k insulating layer in the memory cell region, the logic device region, and the high-voltage device region, The steps include forming a polysilicon layer on the metal layer in the memory cell region, the logic device region, and the high-voltage device region, The method according to claim 11, comprising the steps of selectively removing the high-k insulating layer, the metal layer, and the polysilicon layer in the memory cell region, the logic device region, and the high-voltage device region, leaving the selection gate, the control gate, the erase gate, the logic gate, and the HV gate of the high-k insulating layer, the metal layer, and the polysilicon layer.

14. The method according to claim 11, wherein the step of forming the floating gate includes the step of epitaxially growing silicon on the first portion of the silicon layer.

15. The step of forming the floating gate is, The steps include forming an insulating layer on the silicon layer in the memory cell region, the logic device region, and the high-voltage device region, The method according to claim 14, comprising the step of removing the insulating layer from at least a portion of the memory cell region to expose the first portion of the silicon layer, prior to the step of epitaxially growing silicon on the first portion of the silicon layer.

16. The method according to claim 6, wherein the step of forming the floating gate includes the step of forming the polysilicon layer on the first portion of the silicon layer.

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