Back contact for source / drain area

Abstract

The semiconductor structure comprises a first transistor and a second transistor. The first transistor has a first input source / drain region and a first output source / drain region, and the second transistor has a second input source / drain region and a second output source / drain region. The first input source / drain region and the second input source / drain region are connected to a first source / drain contact, and the first output source / drain region and the second output source / drain region are connected to a second source / drain contact. The first source / drain contact and the second source / drain contact are on the same side of the semiconductor structure.

Description

Technical Field

[0001] This application relates to semiconductors, and more particularly, to techniques for forming semiconductor structures. Semiconductors and integrated circuit chips have become ubiquitous in many products, especially as their cost and size continue to decrease. It is continuously desired to reduce the size of structural features and / or provide a greater amount of structural features for a given chip size. Miniaturization generally enables performance improvements at lower power levels and lower costs. Current technology is at or near the atomic-level scaling of certain microdevices such as logic gates, field-effect transistors (FETs), and capacitors.

[0002] A field-effect transistor (FET) is a transistor having a source, a gate, and a drain and having an action that depends on the flow of carriers (electrons or holes) along a channel extending between the source and the drain. The current flowing through the channel between the source and the drain can be controlled by a lateral electric field under the gate.

[0003] FETs are widely used for switching, amplification, filtering, and other tasks. Examples of FETs include metal-oxide-semiconductor (MOS) FETs (MOSFETs). Complementary MOS (CMOS) devices are also widely used, where both n-type and p-type transistors (nFETs and pFETs) are used to fabricate logic and other circuits. The source and drain regions of an FET are typically formed by adding a dopant to a target region of the semiconductor body on either side of the channel, with the gate formed above the channel. The gate includes a gate dielectric covering the channel and a gate conductor covering the gate dielectric. The gate dielectric is an insulating material that prevents high leakage current from flowing into the channel when a voltage is applied to the gate conductor, while allowing the applied gate voltage to generate a lateral electric field within the channel.

[0004] Various techniques can be used to reduce the size of FETs. One technique is through the use of fin-shaped channels in FinFET devices. Before the advent of FinFET configurations, CMOS devices were typically substantially flat along the surface of the semiconductor substrate, except for the FET gate which was positioned covering the top of the channel. FinFETs utilize a vertical channel structure, increasing the surface area of ​​the channel exposed to the gate. Therefore, in a FinFET structure, the gate extends across multiple sides or surfaces of the channel, allowing the gate to control the channel more effectively. In some FinFET configurations, the gate surrounds three surfaces of a three-dimensional channel, rather than being located only on the top surface of a conventional flat channel.

[0005] Another technique useful for reducing the size of FETs is through the use of stacked nanosheet channels formed on a semiconductor substrate. These stacked nanosheets may be two-dimensional nanostructures, such as sheets with thicknesses ranging from 1 to 100 nanometers (nm). Nanosheets and nanowires are viable options for scaling to 7 nm and beyond. A typical process flow for forming nanosheet stacks involves removing a sacrificial layer, which may be formed from silicon germanium (SiGe), between sheets of channel material, which may be formed from silicon (Si).

[0006] Using conventional methods, the connection from the back-side power rail to the source / drain region of the FET is typically established by through-vias extending from the back to the front of the semiconductor device. As a result, the semiconductor manufacturing process is unnecessarily complex. In addition, the resulting structure, due to the need to accommodate through-vias, hinders size reduction and further miniaturization. [Overview of the project]

[0007] Embodiments of the present invention provide a technique for forming an efficient connection to a back-side power supply by using back-side contacts directly.

[0008] In one embodiment, the semiconductor structure comprises a first transistor and a second transistor. The first transistor has a first input source / drain region and a first output source / drain region, and the second transistor has a second input source / drain region and a second output source / drain region. The first input source / drain region and the second input source / drain region are connected to a first source / drain contact, and the first output source / drain region and the second output source / drain region are connected to a second source / drain contact. The first source / drain contact and the second source / drain contact are on the same side of the semiconductor structure.

[0009] In combination with the preceding paragraph, the same side of the semiconductor structure may include the back side of the semiconductor structure. The first source / drain contact and the second source / drain contact may be connected to a first wire and a second wire located on the back side of the semiconductor structure, respectively. At least one edge of the first source / drain contact may be self-aligned with at least one edge of the first input source / drain region, and at least one edge of the second source / drain contact may be self-aligned with at least one edge of the second output source / drain region. The first wire may be in contact with the first source / drain contact, and the second wire may be in contact with the second source / drain contact.

[0010] In combination with the preceding paragraph, the semiconductor structure may further comprise at least one gate structure common to the first and second transistors. The first and second transistors may have the same doping type. The semiconductor structure may further comprise a third transistor adjacent to the second transistor. The third transistor may have a different doping type than that of the first and second transistors.

[0011] Advantageously, the semiconductor structure includes efficient connection to a back-side power supply through a direct back-side contact. For example, the input source / drain regions of multiple transistors are commonly connected to a direct back-side contact, and the output source / drain regions of multiple transistors are commonly connected to another direct back-side contact. The back-side contact is connected to a back-side power rail and may be self-aligned with the edges of the input and output source / drain regions. The transistors may have a common gate structure and the same doping type. As an additional advantage, the back-side source / drain contact may be formed on part or the entire surface of the source / drain region. In the case where the back-side source / drain contact is formed on the entire surface of the source / drain region, vias may be formed between the back-side source / drain contact and the back-side power rail.

[0012] In another embodiment, the semiconductor structure comprises a plurality of input source / drain regions connected to a first wire through a first contact, and a plurality of output source / drain regions connected to a second wire through a second contact. The first and second wires are on the same side of the semiconductor structure.

[0013] In combination with the preceding paragraph, the same side of the semiconductor structure may include the back side of the semiconductor structure. The first and second contacts may be on the back side of the semiconductor structure. Multiple input source / drain regions and multiple output source / drain regions may correspond to a merged transistor, the merged transistor including the first and second transistors. The same side of the semiconductor structure may include the back sides of the first and second transistors. The semiconductor structure may include a third transistor adjacent to the merged transistor and at least one gate structure common to the merged transistor and the third transistor. The first and second transistors may have the same doping type. The third transistor may have a different doping type than the first and second transistors.

[0014] In another embodiment, the semiconductor structure comprises a first input source / drain region and a first output source / drain region, and a second input source / drain region and a second output source / drain region. The first and second input source / drain regions are connected to a first source / drain contact. The first and second output source / drain regions are connected to a second source / drain contact. The first source / drain contact is connected to a first wire through a first via, and the second source / drain contact is connected to a second wire through a second via. The first source / drain contact, the second source / drain contact, the first wire, and the second wire are on the same side of the semiconductor structure.

[0015] In combination with the preceding paragraph, the same side of the semiconductor structure may include the back side of the semiconductor structure. The first input source / drain region and the first output source / drain region may correspond to the first transistor, and the second input source / drain region and the second output source / drain region may correspond to the second transistor. The first and second transistors may gate the voltage input for the core power supply.

[0016] In another embodiment, the semiconductor structure comprises a plurality of transistors, the plurality of transistors comprising a first transistor, a second transistor located next to the first transistor, and a third transistor located next to the second transistor. The first and second transistors have the same doping type, and the third transistor has a different doping type than the first and second transistors. The semiconductor structure further comprises at least one gate structure common to the first, second, and third transistors. The first input source / drain region and the first output source / drain region correspond to the first transistor, and the second input source / drain region and the second output source / drain region correspond to the second transistor. The first input source / drain region and the second input source / drain region are connected to the first source / drain contact. The first output source / drain region and the second output source / drain region are connected to the second source / drain contact.

[0017] In combination with the preceding paragraph, the first and second source / drain contacts may be located on the back of multiple transistors and may be connected to the first and second wires, respectively, located on the back of the multiple transistors. At least one edge of the first source / drain contact may be self-aligned with at least one edge of the first input source / drain region, and at least one edge of the second source / drain contact may be self-aligned with at least one edge of the second output source / drain region. The first wire may be in contact with the first source / drain contact, and the second wire may be in contact with the second source / drain contact.

[0018] In another embodiment, the method comprises the steps of forming a first sacrificial layer and a second sacrificial layer within a semiconductor layer, and forming a plurality of first source / drain regions and a plurality of second source / drain regions on the semiconductor layer. At least one of the plurality of first source / drain regions is formed on the first sacrificial layer, and at least one of the plurality of second source / drain regions is formed on the second sacrificial layer. The first sacrificial layer is replaced by a first contact, and the second sacrificial layer is replaced by a second contact. The method further comprises the steps of forming a first wire on the first contact and forming a second wire on the second contact. The first wire and the second wire are on the same side of the plurality of first and second source / drain regions as the first and second contacts.

[0019] In combination with the preceding paragraph, the method may further comprise the step of connecting the first and second wires to a back-side power supply network. At least one edge of the first contact may be self-aligned with at least one edge of at least one first source / drain region, and at least one edge of the second contact may be self-aligned with at least one edge of at least one second source / drain region.

[0020] These and other features and advantages of the embodiments described in this specification will become more apparent from the accompanying drawings and the following detailed description.

Brief Description of the Drawings

[0021] [Figure 1-1] FIG. 1A is a circuit diagram showing a transistor structure having backside power distribution according to an embodiment of the present invention.

[0022] FIG. 1B is a top view of the transistor structure according to the circuit diagram of FIG. 1A according to an embodiment of the present invention, in which the source / drain regions of adjacent transistors are connected to a common backside contact.

[0023] FIG. 1C is a circuit diagram showing a transistor structure having an output signal to the backside according to an embodiment of the present invention.

[0024] FIG. 1D is a top view of the transistor structure corresponding to the circuit diagram of FIG. 1C according to an embodiment of the present invention, in which the source / drain regions of adjacent transistors are connected to a common backside contact.

[0025] [Figure 1-2] FIG. 1E is a schematic circuit diagram of the transistor structure of FIG. 1A according to an embodiment of the present invention, in which the source / drain regions of adjacent transistors are connected to a common backside contact.

[0026] [Figure 2] FIG. 2A is a circuit diagram showing a transistor structure having backside power distribution according to an embodiment of the present invention.

[0027] FIG. 2B is a top view of the transistor structure according to the circuit diagram of FIG. 2A according to an embodiment of the present invention, in which the source / drain regions of merged transistors are connected to a common backside contact.

[0028] Figure 2C is a circuit diagram showing a transistor structure having an output signal to the back side, according to one embodiment of the present invention.

[0029] Figure 2D is a top view of a transistor structure corresponding to the circuit diagram in Figure 2C, according to one embodiment of the present invention, in which the source / drain regions of the merged transistor are connected to a common back contact.

[0030] [Figure 3] This figure shows a top view of Figure 2B relating to one embodiment of the present invention, along with the lines X, Y1, and Y2 on which the cross-sectional views of Figures 4A to 16C are based.

[0031] [Figure 4] Figure 4A is a first cross-sectional view corresponding to line X in Figure 3 after the formation of the inner spacer, according to one embodiment of the present invention.

[0032] Figure 4B is a second cross-sectional view corresponding to line Y1 in Figure 3 after the formation of the inner spacer, according to one embodiment of the present invention.

[0033] Figure 4C is a third cross-sectional view corresponding to line Y2 in Figure 3 after the formation of the inner spacer, according to one embodiment of the present invention.

[0034] [Figure 5] Figure 5A is a first cross-sectional view corresponding to line X in Figure 3 after patterning for protective spacer formation and back contact, according to one embodiment of the present invention.

[0035] Figure 5B is a second cross-sectional view corresponding to line Y1 in Figure 3 after patterning for protective spacer formation and back contact, according to one embodiment of the present invention.

[0036] Figure 5C is a third cross-sectional view corresponding to line Y2 in Figure 3 after patterning for protective spacer formation and back contact, according to one embodiment of the present invention.

[0037] [Figure 6] Figure 6A is a first cross-sectional view corresponding to line X in Figure 3, after removal of the organic planarization layer (OPL) and formation of a sacrificial layer, according to one embodiment of the present invention.

[0038] Figure 6B is a second cross-sectional view corresponding to line Y1 in Figure 3 after OPL removal and sacrificial layer formation, according to one embodiment of the present invention.

[0039] Figure 6C is a third cross-sectional view corresponding to line Y2 in Figure 3 after OPL removal and sacrificial layer formation, according to one embodiment of the present invention.

[0040] [Figure 7] Figure 7A is a first cross-sectional view corresponding to line X in Figure 3 after removal of the protective spacer and formation of the source / drain region, according to one embodiment of the present invention.

[0041] Figure 7B is a second cross-sectional view corresponding to line Y1 in Figure 3 after removal of the protective spacer and formation of the source / drain region, according to one embodiment of the present invention.

[0042] Figure 7C is a third cross-sectional view corresponding to line Y2 in Figure 3 after removal of the protective spacer and formation of the source / drain region, according to one embodiment of the present invention.

[0043] [Figure 8] Figure 8A is a first cross-sectional view corresponding to line X in Figure 3, after the formation of an interlayer dielectric (ILD) layer and a replacement metal gate (RMG), according to one embodiment of the present invention.

[0044] Figure 8B is a second cross-sectional view corresponding to line Y1 in Figure 3 after ILD layer formation and RMG formation, according to one embodiment of the present invention.

[0045] Figure 8C is a third cross-sectional view corresponding to line Y2 in Figure 3 after the formation of the ILD layer and RMG, according to one embodiment of the present invention.

[0046] [Figure 9] Figure 9A is a first cross-sectional view corresponding to line X in Figure 3, after the formation of the middle-of-line (MOL) ILD layer and the source / drain contact, according to one embodiment of the present invention.

[0047] Figure 9B is a second cross-sectional view corresponding to line Y1 in Figure 3, after the formation of the MOL ILD layer and the source / drain contact, according to one embodiment of the present invention.

[0048] Figure 9C is a third cross-sectional view corresponding to line Y2 in Figure 3, after the formation of the MOL ILD layer and the source / drain contact, according to one embodiment of the present invention.

[0049] [Figure 10] Figure 10A is a first cross-sectional view corresponding to line X in Figure 3, after back-end-of-line (BEOL) interconnect formation and carrier wafer bonding, according to one embodiment of the present invention.

[0050] Figure 10B is a second cross-sectional view corresponding to line Y1 in Figure 3 after BEOL interconnect formation and carrier wafer bonding, according to one embodiment of the present invention.

[0051] Figure 10C is a third cross-sectional view corresponding to line Y2 in Figure 3 after BEOL interconnect formation and carrier wafer bonding, according to one embodiment of the present invention.

[0052] [Figure 11] Figure 11A is a first cross-sectional view corresponding to line X in Figure 3 after substrate removal, according to one embodiment of the present invention.

[0053] Figure 11B is a second cross-sectional view corresponding to line Y1 in Figure 3 after substrate removal, according to one embodiment of the present invention.

[0054] Figure 11C is a third cross-sectional view corresponding to line Y2 in Figure 3 after substrate removal, according to one embodiment of the present invention.

[0055] [Figure 12] Figure 12A is a first cross-sectional view corresponding to line X in Figure 3 after etching has been stopped and the silicon layer has been removed, according to one embodiment of the present invention.

[0056] Figure 12B is a second cross-sectional view corresponding to line Y1 in Figure 3 after etching has been stopped and the silicon layer has been removed, according to one embodiment of the present invention.

[0057] Figure 12C is a third cross-sectional view corresponding to line Y2 in Figure 3 after etching has been stopped and the silicon layer has been removed, according to one embodiment of the present invention.

[0058] [Figure 13] Figure 13A is a first cross-sectional view corresponding to line X in Figure 3 after the formation of the backside ILD layer and planarization, according to one embodiment of the present invention.

[0059] Figure 13B is a second cross-sectional view corresponding to line Y1 in Figure 3 after the formation of the backside ILD layer and planarization, according to one embodiment of the present invention.

[0060] Figure 13C is a third cross-sectional view corresponding to line Y2 in Figure 3 after the formation of the backside ILD layer and planarization, according to one embodiment of the present invention.

[0061] [Figure 14] Figure 14A is a first cross-sectional view corresponding to line X in Figure 3 after the removal of the sacrificial layer, according to one embodiment of the present invention.

[0062] Figure 14B is a second cross-sectional view corresponding to line Y1 in Figure 3 after the removal of the sacrificial layer, according to one embodiment of the present invention.

[0063] Figure 14C is a third cross-sectional view corresponding to line Y2 in Figure 3 after the removal of the sacrificial layer, according to one embodiment of the present invention.

[0064] [Figure 15] Figure 15A is a first cross-sectional view corresponding to line X in Figure 3 after back contact formation, according to one embodiment of the present invention.

[0065] Figure 15B is a second cross-sectional view corresponding to line Y1 in Figure 3 after back contact formation, according to one embodiment of the present invention.

[0066] Figure 15C is a third cross-sectional view corresponding to line Y2 in Figure 3 after back contact formation, according to one embodiment of the present invention.

[0067] [Figure 16] Figure 16A is a first cross-sectional view corresponding to line X in Figure 3 after the formation of the rear power rail and interconnect, according to one embodiment of the present invention.

[0068] Figure 16B is a second cross-sectional view corresponding to line Y1 in Figure 3 after the formation of the rear power rail and interconnect, according to one embodiment of the present invention.

[0069] Figure 16C is a third cross-sectional view corresponding to line Y2 in Figure 3 after the formation of the rear power rail and interconnect, according to one embodiment of the present invention.

[0070] [Figure 17] Figure 17A is a circuit diagram showing a transistor structure with rear-side power distribution according to one embodiment of the present invention.

[0071] Figure 17B is a top view of the transistor structure according to the circuit diagram of Figure 1A, which is an embodiment of the present invention, in which the source / drain regions of the merged transistor are connected to a common back contact.

[0072] Figure 17C is a cross-sectional view taken along line A in Figure 17B, relating to one embodiment of the present invention.

[0073] [Figure 18] This figure shows a top view of Figure 17B relating to one embodiment of the present invention, along with the lines X, Y1, and Y2 on which the cross-sectional views of Figures 19A to 31C are based.

[0074] [Figure 19] Figure 19A is a first cross-sectional view corresponding to line X in Figure 18 after the formation of the inner spacer, according to one embodiment of the present invention.

[0075] Figure 19B is a second cross-sectional view corresponding to line Y1 in Figure 18 after the formation of the inner spacer, according to one embodiment of the present invention.

[0076] Figure 19C is a third cross-sectional view corresponding to line Y2 in Figure 18 after the formation of the inner spacer, according to one embodiment of the present invention.

[0077] [Figure 20] Figure 20A is a first cross-sectional view corresponding to line X in Figure 18, after protective spacer formation, removal of bottom dielectric insulator (BDI), and silicon layer recess formation, according to one embodiment of the present invention.

[0078] Figure 20B is a second cross-sectional view corresponding to line Y1 in Figure 18, after protective spacer formation, BDI removal, and silicon layer recessing, according to one embodiment of the present invention.

[0079] Figure 20C is a third cross-sectional view corresponding to line Y2 in Figure 18, after protective spacer formation, BDI removal, and silicon layer recessing, according to one embodiment of the present invention.

[0080] [Figure 21] Figure 21A is a first cross-sectional view corresponding to line X in Figure 18 after sacrificial layer formation, according to one embodiment of the present invention.

[0081] Figure 21B is a second cross-sectional view corresponding to line Y1 in Figure 18 after the formation of the sacrificial layer, according to one embodiment of the present invention.

[0082] Figure 21C is a third cross-sectional view corresponding to line Y2 in Figure 18 after sacrificial layer formation, according to one embodiment of the present invention.

[0083] [Figure 22] Figure 22A is a first cross-sectional view corresponding to line X in Figure 18 after removal of the protective spacer and formation of the source / drain region, according to one embodiment of the present invention.

[0084] Figure 22B is a second cross-sectional view corresponding to line Y1 in Figure 18 after removal of the protective spacer and formation of the source / drain region, according to one embodiment of the present invention.

[0085] Figure 22C is a third cross-sectional view corresponding to line Y2 in Figure 18 after removal of the protective spacer and formation of the source / drain region, according to one embodiment of the present invention.

[0086] [Figure 23] Figure 23A is a first cross-sectional view corresponding to line X in Figure 18 after the formation of the ILD layer and RMG, according to one embodiment of the present invention.

[0087] Figure 23B is a second cross-sectional view corresponding to line Y1 in Figure 18 after the formation of the ILD layer and RMG, according to one embodiment of the present invention.

[0088] Figure 23C is a third cross-sectional view corresponding to line Y2 in Figure 18 after the formation of the ILD layer and RMG, according to one embodiment of the present invention.

[0089] [Figure 24] Figure 24A is a first cross-sectional view corresponding to line X in Figure 18 after MOL and BEOL interconnect formation and carrier wafer bonding, according to one embodiment of the present invention.

[0090] Figure 24B is a second cross-sectional view corresponding to line Y1 in Figure 18 after MOL and BEOL interconnect formation and carrier wafer bonding, according to one embodiment of the present invention.

[0091] Figure 24C is a third cross-sectional view corresponding to line Y2 in Figure 18 after MOL and BEOL interconnect formation and carrier wafer bonding, according to one embodiment of the present invention.

[0092] [Figure 25] Figure 25A is a first cross-sectional view corresponding to line X in Figure 18 after substrate removal, according to one embodiment of the present invention.

[0093] Figure 25B is a second cross-sectional view corresponding to line Y1 in Figure 18 after substrate removal, according to one embodiment of the present invention.

[0094] Figure 25C is a third cross-sectional view corresponding to line Y2 in Figure 18 after substrate removal, according to one embodiment of the present invention.

[0095] [Figure 26] Figure 26A is a first cross-sectional view corresponding to line X in Figure 18 after etching has been stopped and the silicon layer has been removed, according to one embodiment of the present invention.

[0096] Figure 26B is a second cross-sectional view corresponding to line Y1 in Figure 18 after etching has been stopped and the silicon layer has been removed, according to one embodiment of the present invention.

[0097] Figure 26C is a third cross-sectional view corresponding to line Y2 in Figure 18 after etching has been stopped and the silicon layer has been removed, according to one embodiment of the present invention.

[0098] [Figure 27] Figure 27A is a first cross-sectional view corresponding to line X in Figure 18 after the formation of the backside ILD layer and planarization, according to one embodiment of the present invention.

[0099] Figure 27B is a second cross-sectional view corresponding to line Y1 in Figure 18 after the formation of the backside ILD layer and planarization, according to one embodiment of the present invention.

[0100] Figure 27C is a third cross-sectional view corresponding to line Y2 in Figure 18 after the formation of the backside ILD layer and planarization, according to one embodiment of the present invention.

[0101] [Figure 28] Figure 28A is a first cross-sectional view corresponding to line X in Figure 18 after the removal of the sacrificial layer, according to one embodiment of the present invention.

[0102] Figure 28B is a second cross-sectional view corresponding to line Y1 in Figure 18 after the removal of the sacrificial layer, according to one embodiment of the present invention.

[0103] Figure 28C is a third cross-sectional view corresponding to line Y2 in Figure 18 after the removal of the sacrificial layer, according to one embodiment of the present invention.

[0104] [Figure 29] Figure 29A is a first cross-sectional view corresponding to line X in Figure 18 after back contact formation, according to one embodiment of the present invention.

[0105] Figure 29B is a second cross-sectional view corresponding to line Y1 in Figure 18 after back contact formation, according to one embodiment of the present invention.

[0106] Figure 29C is a third cross-sectional view corresponding to line Y2 in Figure 18 after back contact formation, according to one embodiment of the present invention.

[0107] [Figure 30] Figure 30A is a first cross-sectional view corresponding to line X in Figure 18 after the formation of the rear power rail and vias, according to one embodiment of the present invention.

[0108] Figure 30B is a second cross-sectional view corresponding to line Y1 in Figure 18 after the formation of the rear power rail and vias, according to one embodiment of the present invention.

[0109] Figure 30C is a third cross-sectional view corresponding to line Y2 in Figure 18 after the formation of the rear power rail and vias, according to one embodiment of the present invention.

[0110] [Figure 31] Figure 31A is a first cross-sectional view corresponding to line X in Figure 18 after the formation of the back interconnect, according to one embodiment of the present invention.

[0111] Figure 31B is a second cross-sectional view corresponding to line Y1 in Figure 18 after the formation of the back interconnect, according to one embodiment of the present invention.

[0112] Figure 31C is a third cross-sectional view corresponding to line Y2 in Figure 18 after the formation of the back interconnect, according to one embodiment of the present invention. [Modes for carrying out the invention]

[0113] Exemplary embodiments of the present invention can be described herein, along with exemplary apparatus, systems, and devices formed using exemplary methods for forming direct back-side contact structures to the input and output source / drain regions of a transistor. However, it should be understood that embodiments of the present invention are not limited to exemplary methods, apparatus, systems, and devices, but are instead more broadly applicable to other suitable methods, apparatus, systems, and devices.

[0114] It should be understood that the various features shown in the attached drawings are schematic diagrams and are not necessarily drawn to scale. Furthermore, the same or similar reference numerals are used throughout the drawings to indicate the same or similar features, elements, or structures, and therefore, a detailed description of the same or similar features, elements, or structures is not repeated in each of the drawings. In addition, the terms “exemplary” and “illustrative,” as used herein, mean “serving as an example, case, or illustration.” Any embodiment or design described herein as “exemplary” or “illustrative” should not be construed as being preferable or advantageous to other embodiments or designs.

[0115] Figure 1A shows circuit diagram 10 illustrating a transistor structure with backside power distribution. Figure 1B shows a top view of the transistor structure 12 relating to circuit diagram 10, where the source / drain regions of adjacent transistors are connected to a common backside contact DBC. Referring to circuit diagram 10, in a power gating circuit where the supply voltage (Vdd) input is gated for a local core power supply, the gate receives an enable signal (Enable_N). The supply voltage may also be referred to herein as the "drain voltage". The input source / drain region of the transistor receives the supply voltage (Vdd), and the output source / drain region corresponds to the local core power supply voltage (Vdd_core), which is supplied to the gate logic through the backside power delivery network (BSPDN).

[0116] Referring to Figure 1B, the transistor structure 12 includes two p-type transistors, each containing an active region (RX). Alternatively, the transistor structure 12 includes two n-type transistors. In either case, the two transistors have the same doping type. According to one embodiment, the input source / drain region of each transistor is connected to the supply voltage (Vdd) through a direct backside contact (DBC) to a conductive wire (e.g., a metal wire). The input source / drain region may optionally be connected to a front contact (CA1). Similarly, the output source / drain region of each transistor is connected to the core supply voltage (Vdd_core) through another direct backside contact (DBC) to another conductive wire. The output source / drain region is further connected to a front contact (CA2).

[0117] The schematic circuit diagram 18 in Figure 1E shows the source / drain regions of adjacent transistors connected to a common back contact. As shown in Figure 1E, the input source / drain region of each transistor is connected to the supply voltage (Vdd) through a direct back contact (DBC) including a conducted wire 19-1 that directly contacts the first back contact (BSCA1). The output source / drain region of each transistor is connected to the core supply voltage (Vdd_core) through another direct back contact (DBC) including another conducted wire 19-2 that directly contacts the second back contact (BSCA2). Conducted wires 19-1 and 19-2 are connected to the back metallization layer (BSM). x) are connected to different parts of the circuit, which may include, for example, a back-side power supply network, and conductive wires 19-1 and 19-2 may include back-side power rails. Similar to schematic 10 in Figure 1A, the core power supply voltage (Vdd_core) is supplied to the gate logic. As can be seen in Figure 1B, at least one common gate PC is connected across the two transistors, and this common gate PC supplies a common gate input (Enable_N). In addition, in Figure 1B, direct back-side contacts (DBC) self-align with the top and bottom edges of the active regions (RX) (e.g., source / drain regions) of each of the two transistors.

[0118] Figure 1C shows a schematic diagram 14 illustrating a transistor structure with output signals to the back side of a semiconductor device, and Figure 1D shows a top view of the transistor structure 16 corresponding to schematic diagram 14 in Figure 1C, where the source / drain regions of adjacent transistors are connected to a common back-side contact. As shown in schematic diagram 14 in Figure 1C, the inverter circuit includes a common gate input (IN) to the gates of two transistors. The input voltage of one of the transistors is the supply (drain) voltage (Vdd), and the input voltage of the other transistor in schematic diagram 14 is the source voltage (Vss). The outputs (OUT) of the two transistors in schematic diagram 14 are provided to the back side of the device.

[0119] Similar to transistor structure 12, transistor structure 16 includes two adjacent p-type transistors, each containing an active region (RX). Alternatively, transistor structure 16 includes two n-type transistors. In either case, the two transistors have the same doping type. Transistor structure 16 further includes a third transistor adjacent to the two transistors with the same doping type, the third transistor having a different doping type than the two transistors. For example, in the diagram in Figure 1D, the third transistor is an n-type transistor. However, if the first two transistors are n-type, then the third transistor will be a p-type transistor. Similar to transistor structure 12, according to one embodiment, the input source / drain region of each p-type transistor in transistor structure 16 is connected to the supply voltage (Vdd) through a direct back contact (DBC) to a conductive wire (e.g., a metal wire), and the output source / drain region of each p-type transistor is connected to the back metallization layer (BSM) through another direct back contact (DBC) to another conductive wire. x It is connected in common to a part of the transistor structure 16. The input source / drain region of the third transistor (n-type) in the transistor structure 16 is connected separately to the source voltage (Vss). In one embodiment, the output source / drain region of the third transistor is connected to the same back metallization layer (BSM) as the first and second transistors. x It is connected to a common part of the ) . In other words, each of the three transistors has the same source / drain output (OUT), the two p-type transistors have the same source / drain input (Vdd), and the third transistor (n-type) has a different source / drain input (Vss). Each conductive wire is connected to the back metallization layer (BSM). x) are connected to different parts of the transistor, which may include, for example, a back-side power supply network. Conductive wires may include, for example, back-side power rails. As can be seen in Figure 1D, at least one common gate PC is connected across the three transistors, and this common gate PC supplies a common gate input (IN). In addition, in Figure 1D, direct back-side contacts (DBC) self-align with the top and bottom edges of the active region (RX) (e.g., source / drain region) of each of the three transistors.

[0120] Circuit diagrams 20 and 24 in Figures 2A and 2C are the same as circuit diagrams 10 and 14 in Figures 1A and 1C, and are shown as references for transistor structures 22 and 26 in Figures 2B and 2D. Similar to transistor structures 12 and 16, transistor structures 22 and 26 correspond to circuit diagrams 20 and 24. Transistor structures 22 and 26 are similar to transistor structures 12 and 16, except that the source / drain regions of the merged transistors are connected to a common back contact. More specifically, the two transistors in transistor structure 22 are a merged transistor whose active region (RX) is continuous across the two transistors. Similarly, in transistor structure 26, the two transistors of the same type (p-type in this case) are a merged transistor whose active region (RX) is continuous across these two transistors. As a result of the differently configured active regions in transistor structures 22 and 26, in Figure 2B, the direct back contact (DBC) self-aligns with only one edge (either the top or bottom edge) of the active region (RX) (e.g., source / drain region) of the merged transistor. As can be seen, the front contacts CA1, CA2, CA1', and CA2' in transistor structures 22 and 26 are the same as the front contacts CA1, CA2, CA1', and CA2' in transistor structures 12 and 16. In transistor structures 22 and 26, the front contacts CA1, CA2, and CA1' may be omitted, while the front contact CA2' must be maintained because it is required to connect the output S / D region of a p-type transistor (e.g., pFET) to the output S / D region of an n-type transistor (e.g., nFET). The front contact CA2' must also be maintained in transistor structure 16. As described herein, in transistor structure 12, the input source / drain region may optionally be connected to the front contact portion (CA1), but the front contact portion CA2 is required in this embodiment. In other respects, transistor structures 22 and 26 are the same as transistor structures 12 and 16.

[0121] As used herein, “front side” or “first side” refers to the side on or above the first and second semiconductor substrates 101 and 103, and / or the side in front of the multilayer nanosheet / gate and channel layers of the transistor in the orientation shown in the cross-sectional view. As used herein, “back side” or “second side” refers to the side below the first and / or second semiconductor substrates 101 and 103, and / or the side behind the multilayer nanosheet / gate and channel layers of the transistor in the orientation shown in the cross-sectional view, and / or the side in the direction in the direction below or / or the side in the direction opposite to the “front side.”

[0122] Regarding the semiconductor structure 100, Figure 3 shows a top view of Figure 2B relating to one embodiment of the present invention, along with the lines X, Y1, and Y2 on which the cross-sectional views of Figures 4A to 16C are based. Referring to Figures 4A to 4C, the first and second semiconductor substrates 101 and 103 include, but are not limited to, semiconductor materials including silicon (Si), III-V, II-V compound semiconductor materials, or other similar semiconductor materials. In addition, multiple layers of semiconductor material can be used as the semiconductor material of the first and second semiconductor substrates 101 and 103. The first and second semiconductor substrates 101 and 103 may also be referred to as the first and second semiconductor substrates 101 and 103 in this specification. An etching stop layer 102 is formed on the first semiconductor substrate 101, for example, silicon oxide (SiO2). x )(where x is, for example, 2, 1.99, or 2.01), or may include silicon germanium (SiGe). A second semiconductor substrate 103, for example, containing the same semiconductor material as the first semiconductor substrate 101, or other similar semiconductor material, is formed on the etching stop layer 102.

[0123] As can be seen in Figures 4B and 4C, a portion of the second semiconductor substrate 103 is recessed to a lower height. A dielectric layer 104 is filled into the recessed portion of the second semiconductor substrate 103 to form multiple isolation regions (for example, shallow trench isolation (STI) regions). The dielectric layer 104 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), and combinations thereof, and is deposited using deposition techniques such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), radio-frequency CVD (RFCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam deposition (MBD), pulsed laser deposition (PLD), and / or liquid source misted chemical deposition (LSMCD).

[0124] According to one embodiment of the present invention, a dielectric layer 109 (also referred to as a bottom dielectric insulator (BDI) layer) is formed on a second semiconductor substrate 103. The dielectric layer 109 may include, for example, SiN, SiON, SiCN, BN, SiBCN, SiOCN, and combinations thereof, and is deposited using deposition techniques such as CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, and / or LSMCD.

[0125] Layers of silicon germanium (SiGe) and silicon (Si) are stacked alternately on a dielectric layer 109, so that a first SiGe layer is followed by a first Si layer on the first SiGe layer, followed by a second SiGe layer on the first Si layer, and so on. As can be understood, the SiGe and Si layers grow epitaxially. The stacked nanosheet layers of SiGe and Si layers are patterned into nanosheet stacks including SiGe layer 105 and Si layer 107, as shown in Figure 4A. Although three SiGe layers 105 and three Si layers 107 are shown, embodiments of the present invention are not necessarily limited to the number of layers 105, 107 shown, and more or fewer layers may exist in the same alternate configuration depending on design constraints. For ease of explanation, three nanosheet stacks are shown. However, the embodiments are not limited thereto, and more than three or fewer nanosheet stacks can be formed.

[0126] The SiGe layer 105 is also referred to herein as the sacrificial semiconductor layer, as the SiGe layer 105 is ultimately removed and replaced by a gate structure, as will be further described herein. Although SiGe is described as the sacrificial material for the SiGe layer 105 and Si is described as the nanosheet channel material for the Si layer 107, other materials may be used as long as the sacrificial semiconductor layer has the property of being selectively removable compared to the nanosheet channel material.

[0127] The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" refer to the growth of a semiconductor material (crystalline material) on the deposition surface of another semiconductor material (crystalline material), in which case the growing semiconductor material (crystal covering the layer) has substantially the same crystalline properties as the semiconductor material on the deposition surface (seed material). In the epitaxial deposition process, the chemical reactants provided by the source gas are controlled and system parameters are set so that the atoms to be deposited reach the deposition surface of the semiconductor substrate with enough energy to move around on the surface so that the atoms to be deposited are oriented to the crystalline arrangement of the atoms on the deposition surface. Thus, an epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which the epitaxially grown material is formed.

[0128] The epitaxial deposition process may employ a deposition chamber of a chemical vapor deposition type apparatus such as a rapid thermal chemical vapor deposition (RTCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), or low-pressure chemical vapor deposition (LPCVD) apparatus. Many different sources may be used for the epitaxial deposition of in situ-doped semiconductor materials. In some embodiments, the gas source for the deposition of the epitaxially formed semiconductor material may include silicon (Si) deposited from silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. In other examples, if the semiconductor material contains germanium, the germanium gas source may be selected from the group consisting of german, sigermann, halogermann, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. The temperature for epitaxial deposition is typically in the range of 450°C to 900°C. Generally, higher temperatures result in faster deposition, but faster deposition can lead to crystal defects and film cracking.

[0129] A dummy gate portion 111 is formed on the uppermost Si layer 107 and around the laminated nanosheet structure of the SiGe layer 105 and the Si layer 107. The dummy gate portion 111 includes, but is not limited to, an amorphous silicon (a-Si) layer. The dummy gate portion 111 is deposited using deposition techniques such as CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, LSMCD, sputtering and / or plating, followed by a planarization process such as chemical mechanical planarization (CMP), and lithography and etching steps to remove excess dummy gate material and pattern the deposited layer. A hard mask layer 120 is formed on the dummy gate portion 111. The hard mask portion includes, for example, a nitride such as SiN or other nitride material.

[0130] Referring to Figure 4A, due to germanium in the SiGe layer 105, the SiGe layer 105 can be selectively etched laterally relative to the Si layer 107 so that the sides of the SiGe layer 105 can be removed to create an empty area that will be filled by the inner spacer 113. The material of the inner spacer 113 may include, but is not limited to, nitrides such as SiN, SiON, SiCN, BN, SiBN, SiBCN, or SiOCN. The gate spacer 112 is positioned on a nanosheet stack on opposite lateral surfaces of the dummy gate portion 111. The gate spacer 112 is formed from the same or similar material as the inner spacer 113. The inner and gate spacers 113 and 112 can be formed by any suitable technique, such as deposition and subsequent directional etching. Deposition may include, but is not limited to, ALD or CVD. Directional etching may include, but is not limited to, reactive ion etching (RIE).

[0131] Referring to Figures 5A to 5C, protective spacers 115 are formed on the side surface of the nanosheet stack, which includes the Si layer 107, gate spacers 112, and inner spacers 113. The protective spacers 115 are formed from, for example, SiN. In an exemplary embodiment, the thickness of the protective spacers 115 is about 20 angstroms (about 2 nanometers). The protective spacers 115 can be formed by any suitable technique, such as deposition and subsequent directional etching. Deposition may include, but is not limited to, ALD or CVD. Directional etching may include, but is not limited to, RIE.

[0132] After the formation of the protective spacer 115, an organic planarization layer (OPL) 122 is formed on the hard mask layer 120 and between the nanosheet stacks on the dielectric layer 109. The OPL 122 contains, but is not limited to, an organic polymer containing C, H, and N. In one embodiment, the OPL material may be silicon (Si) free. According to one embodiment, the OPL material may be Si and fluorine (F) free. As defined herein, a material is atom-free if the level of atoms in the material is at or below the trace level detectable using analytical methods available in the art. Non-limiting examples of OPL materials include JSR HM8006, JSR HM8014, AZ UM10M2, Shin Etsu ODL 102, or other similar commercially available materials from vendors such as JSR, TOK, Sumitomo, Rohm & Haas, etc. The OPL 122 can be deposited, for example, by spin coating. Openings 123-1 and 123-2 are formed within the OPL122, corresponding to the locations where the rear source / drain contacts 160-1 and 160-2 (see Figures 15A to 16C) will be formed.

[0133] Openings 124-1 and 124-2 (e.g., trenches) are formed at locations where an etching process, such as RIE, is performed through openings 123-1 and 123-2 in the OPL122 to form back-side source / drain contacts 160-1 and 160-2 in the second semiconductor substrate 103. Openings 124-1 and 124-2 are formed by etching through a portion of the dielectric layer 109 and a portion of the second semiconductor substrate 103.

[0134] Referring to Figures 6A to 6C, OPL 122 is removed, and the openings 124-1 and 124-2 are filled with sacrificial placeholder layers 125-1 and 125-2 containing, for example, SiGe, a III-V semiconductor material, or other semiconductor material. OPL 122 is exfoliated using, for example, an oxygen plasma, a nitrogen / hydrogen plasma, or other carbon exfoliation process. OPL exfoliation minimizes or eliminates damage to the exposed layer. The sacrificial placeholder layers 125-1 and 125-2 are deposited in the openings 124-1 and 124-2 using deposition techniques such as CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, and / or LSMCD, followed by a planarization process such as CMP. The CMP process removes excess portions of the sacrificial placeholder layers 125-1 and 125-2 deposited on the dielectric layer 109. As can be seen in Figures 6A to 6C, the upper surfaces of the sacrificial placeholder layers 125-1 and 125-2 are coplanar with the upper surface of the dielectric layer 109.

[0135] Referring to Figures 7A to 7C, the protective spacer 115 is removed, for example, using an isotropic dry or wet etching process, and source / drain regions 130-1 and 130-2 are epitaxially grown between the nanosheet stacks. Source / drain regions 130-1 and 130-2 include epitaxial layers grown from the sides of the Si layer 107. The Si layer 107 will function as a nanosheet channel layer. As can be seen, source / drain regions 130-1 and 130-2 are formed on sacrificial placeholder layers 125-1 and 125-2.

[0136] Referring to Figures 8A to 8C, an interlayer dielectric (ILD) layer 135 is deposited on and around the source / drain regions 130-1 and 130-2. The ILD layer 135 is deposited using a deposition technique such as CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, and / or LSMCD, followed by a planarization process such as CMP to remove excess portions of the ILD layer 135 deposited on the hard mask layer 120 and gate spacer 112, and to remove portions of the hard mask layer 120 and gate spacer 112 to expose the dummy gate portion 111. The ILD layer 135 may contain, for example, SiOx, SiOC, SiOCN, or any other dielectric.

[0137] The dummy gate portion 111 is selectively removed to create an empty area where the gate structure will be formed in place of the dummy gate portion 111. Selective removal can be performed, for example, using high-temperature ammonia to remove a-Si. In addition, the SiGe layer 105 is selectively removed to create an empty area where the gate structure will be formed in place of the SiGe layer 105. The SiGe layer 105 is selectively removed relative to the Si layer 107. Selective removal can be performed, for example, using dry HCl etching.

[0138] After the removal of the dummy gate portion 111 and the SiGe layer 105, the Si layer 107 is suspended, and a gate region 132, including, for example, the gate and dielectric portion, is formed in the void left by the removal of the dummy gate portion 111 and the SiGe layer 105. In exemplary embodiments, each gate region 132 includes a gate dielectric layer such as a high-K dielectric layer containing, for example, but not limited to, HfO2 (hafnium oxide), ZrO2 (zirconium dioxide), hafnium zirconium oxide, Al2O3 (aluminum oxide), and Ta2O5 (tantalum oxide). Examples of high-k materials include, but are not limited to, metal oxides such as hafnium silicon oxynitride, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. According to one embodiment, the gate region 132 includes a metal gate portion including a work-function metal (WFM) layer, which is not necessarily limited, but in the case of a pFET, titanium nitride (TiN), tantalum nitride (TaN), or ruthenium (Ru), and in the case of an nFET, TiN, titanium aluminum nitride (TiAlN), titanium aluminum carbon nitride (TiAlCN), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum carbon nitride (TaAlCN), or lanthanum (La) doped TiN, TaN, which can be deposited on the gate dielectric layer. Each metal gate portion is deposited on the WFM layer and the gate dielectric layer and may further include a gate metal layer containing metals such as, but are not limited to, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, tantalum carbide, titanium carbide, magnesium tantalum carbide, or combinations thereof. It should be understood that various other materials may be used for the metal gate portion as desired.

[0139] Referring to Figures 9A to 9C, additional ILD material is deposited to form an additional ILD layer 135' on top of the ILD layer 135. Next, front source / drain contacts 140-1 and 140-2 are formed within the ILD layers 135 and 135'. When forming the front source / drain contacts 140-1 and 140-2, openings are formed through portions of the ILD layers 135 and 135'. The openings expose the portions of the source / drain regions 130-1 and 130-2 where the front source / drain contacts 140-1 and 140-2 will be formed. According to one embodiment, a mask is formed on a portion of the ILD layer 135', and the exposed portions of the ILD layers 135 and 135' corresponding to the locations where the openings will be formed are removed using, for example, a dry etching process using RIE or ion beam etching (IBE), a wet chemical etching process, or a combination of these etching processes. Dry etching may be performed using plasma. Such wet or dry etching processes include, for example, IBE by Ar / CHF3 chemical reactions.

[0140] A metal layer is deposited within the opening to form the front source / drain contacts 140-1 and 140-2. The metal layer includes, for example, a silicide layer such as Ni, Ti, NiPt, a metal adhesive layer such as TiN, and a conductive metal filling layer such as W, Al, Co, Ru, etc., and can be deposited using deposition techniques such as CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, LSMCD, sputtering and / or plating, followed by a planarization process such as chemical mechanical planarization (CMP) to remove excess portions of the metal layer from above the ILD layer 135'. The front source / drain contacts 140-1 and 140-2 are used in addition to the back source / drain contacts 160-1 and 160-2 to completely fix the source / drain regions 130-1 and 130-2.

[0141] The front source / drain contacts 140-1 and 140-2 contact the respective source / drain regions 130-1 and 130-2. The front source / drain contacts 140-1 and 140-2 penetrate the ILD layers 135 and 135' and land on and contact the corresponding source / drain regions 130-1 and 130-2.

[0142] Referring to Figures 10A to 10C, a front gate contact 142 is formed through the ILD layer 135' to land on and contact the corresponding gate region 132 (which may also be called the gate structure). The process and materials used to form the front gate contact 142 are the same as those used to form the front source / drain contacts 140-1 and 140-2. A front BEOL interconnect 145 is formed on the ILD layer 135' containing the front source / drain contacts 140-1 and 140-2 and the front gate contact 142. As can be seen, the front gate contact 142 contacts the front BEOL interconnect 145, while the front source / drain contacts 140-1 and 140-2 do not contact the front BEOL interconnect 145 and are not electrically connected to them. A carrier wafer 147 is bonded to the front BEOL interconnect 145. The front-side BEOL interconnect 145 includes various BEOL interconnect structures that can be electrically connected to the front-side gate contact 142. In alternative embodiments, one or more of the front-side source / drain contacts 140-1 and 140-2 may be electrically connected to the front-side BEOL interconnect 145. The carrier wafer 147 may be formed from a material similar to that of the first and second semiconductor substrates 101 and 103, and may be formed by covering the front-side BEOL interconnect 145 using a wafer bonding process such as a dielectric-dielectric junction.

[0143] Referring to Figures 11A to 11C, the semiconductor structure 100 may be “flipped” (e.g., rotated 180 degrees) using the carrier wafer 147 so that the structure is inverted. In addition, the first semiconductor substrate 101 is removed from the back surface of the semiconductor structure 100. The removal process, including etching of the first semiconductor substrate 101, is stopped at the etching stop layer 102 as shown in Figures 11A to 11C. For example, the first semiconductor substrate 101 is selectively etched with an etching solution that selectively etches silicon relative to the material of the etching stop layer 102 (e.g., SiO2 or SiGe).

[0144] Referring to Figures 12A to 12C, the etching stop layer 102 and the second semiconductor substrate 103 (e.g., silicon layer) are selectively removed from the semiconductor structure 100 with respect to the sacrificial placeholder layers 125-1 and 125-2 and the dielectric layer 104 (e.g., STI region). As shown in Figures 12A to 12C, the etching stop layer 102 is removed, followed by the removal of the second semiconductor substrate 103, where the dielectric layer 104, dielectric layer 109, and portions of the sacrificial placeholder layers 125-1 and 125-2 are exposed. The etching process for removing the etching stop layer 102 includes, for example, IBE by an Ar / CHF3 chemical reaction.

[0145] Referring to Figures 13A to 13C, a backside ILD layer 150 is deposited to fill the area previously occupied by the second semiconductor substrate 103. The backside ILD layer 150 is deposited using a deposition technique such as CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, and / or LSMCD, followed by a planarization process such as CMP to remove excess portions of the backside ILD layer 150 deposited on top of the sacrificial placeholder layers 125-1 and 125-2 and the dielectric layer 104, so that the backside ILD layer is coplanar with the surfaces of the sacrificial placeholder layers 125-1 and 125-2. After the CMP process, the surfaces of the sacrificial placeholder layers 125-1 and 125-2 are exposed. The backside ILD layer 150 may contain, for example, SiOx, SiOC, SiOCN, or some other dielectric material.

[0146] Referring to Figures 14A to 14C, the sacrificial placeholder layers 125-1 and 125-2 are selectively removed to expose the back surfaces of the source / drain regions 130-1 and 130-2. The sacrificial placeholder layers 125-1 and 125-2 are removed, for example, using a selective dry or wet etching process.

[0147] Referring to Figures 15A to 15C, the rear source / drain contacts 160-1 and 160-2 are formed in the openings left by the removal of the sacrificial placeholder layers 125-1 and 125-2 in the rear ILD layer 150. A metal layer is deposited within the opening to form the back source / drain contacts 160-1 and 160-2. The metal layer includes, for example, a silicide layer such as Ni, Ti, NiPt, a metal bonding layer such as TiN, and a conductive metal filling layer such as W, Al, Co, Ru, and can be deposited using deposition techniques such as CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, LSMCD, sputtering, and / or plating, followed by a planarization process such as chemical mechanical planarization (CMP) to remove excess portions of the metal layer from above the back ILD layer 150.

[0148] The back-side source / drain contacts 160-1 and 160-2 contact the back surfaces of the respective source / drain regions 130-1 and 130-2. The back-side source / drain contacts 160-1 and 160-2 penetrate the back-side ILD layer 150 and land on and contact the back surfaces of the corresponding source / drain regions 130-1 and 130-2.

[0149] Referring to Figures 16A to 16C, additional back ILD material is deposited on the back ILD layer 150 to form an additional back ILD layer 150'. Next, conductive wires 165-1 (Vdd) and 165-2 (Vdd core) are formed within the back ILD layer 150'. Conductive wires 165-1 and 165-2 are also referred to herein as back power rails. When forming conductive wires 165-1 and 165-2, openings are formed through a portion of the additional back ILD layer 150'. The openings expose the portions of the back source / drain contacts 160-1 and 160-2 on which conductive wires 165-1 and 165-2 will be formed.

[0150] Conductive wires 165-1 and 165-2, also referred to herein as power elements or back-side power rails, are formed within the additional back-side ILD layer 150' by forming trenches within the additional back-side ILD layer 150' and filling the trenches with a conductive material. The trenches are opened within the additional back-side ILD layer 150', respectively, using, for example, lithography and the subsequent RIE. Conductive wires 165-1 and 165-2 are formed within the trenches by filling the trenches with a conductive material, such as, for example, a conductive material containing tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, and / or copper. A liner layer (not shown), for example, containing titanium and / or titanium nitride, may be formed on the side and bottom surfaces of the trenches before filling the trenches with the conductive material. The deposition of conductive materials can be carried out using one or more deposition techniques, including but not limited to CVD, PECVD, PVD, ALD, MBD, PLD, LSMCD, and / or spin-on coating, followed by planarization using a planarization process such as CMP.

[0151] Conductive wire 165-1 transmits, for example, the supply or drain voltage (Vdd) to the source / drain region 130-1 (e.g., the input source / drain region) through the back source / drain contact 160-1. Conductive wire 165-2 transmits, for example, the core supply voltage (Vdd_core) to the source / drain region 130-2 (e.g., the output source / drain region) through the back source / drain contact 160-2.

[0152] As can be seen in Figures 16A to 16C, the back source / drain contact 160-1 contacts the source / drain region 130-1, and the conductive wire 165-1 is formed on and in contact with the back source / drain contact 160-1. The back source / drain contact 160-2 contacts the source / drain region 130-2, and the conductive wire 165-2 is formed on and in contact with the back source / drain contact 160-2. The back ILD layer 150 and the additional back ILD layer 150' fill the empty areas on the lateral surfaces of the back source / drain contacts 160-1 and 160-2, and on the lateral surfaces of the conductive wires 165-1 and 165-2. The back source / drain contacts 160-1 and 160-2 are adjacent to and in contact with the dielectric layer 104. Referring back to Figure 3, the back-side source / drain contacts 160-1 and 160-2 each self-align with one edge of the active region (e.g., source / drain regions 130-1 and 130-2).

[0153] A back-side power supply network (BSPDN) layer 170 (also referred to herein as a back-side interconnect) is formed on an additional back-side ILD layer 150' and conductive wires 165-1 and 165-2. The BSPDN layer 170 includes, but is not limited to, various BSPDN structures such as interconnects in the power supply path from a voltage regulator module (VRM) to the circuit. The interconnects may include, for example, power and ground planes on the circuit board, cables associated with the power supply, connectors, and capacitors. Back-side power supply prevents BEOL wiring congestion, resulting in benefits in power performance.

[0154] Figure 17A shows a circuit diagram 30 illustrating a transistor structure with backside power distribution. Circuit diagram 30 in Figure 17A is the same as circuit diagrams 10 and 20 in Figures 1A and 2A, and is shown as a reference for transistor structure 32 in Figure 17B. Similar to transistor structures 12 and 22, transistor structure 32 corresponds to circuit diagram 30. Transistor structure 32 is similar to transistor structure 22 except that the frontside source / drain contacts are omitted, the direct backside contacts (DBC) extend to self-align with multiple edges of the active region, and vias V1 and V2 connect the direct backside contacts (DBC) to conductive wires. More specifically, referring to Figure 17C, which is a cross-sectional view 34 cut along line A in Figure 17B, the DBC extends across the entire width of the active region (RX) (e.g., source / drain region), and via V2 connects the direct backside contacts (DBC) to the backside metallization layer (BSM) through conductive wires (e.g., power rails) (not shown). x Connect to ).

[0155] Regarding the semiconductor structure 200, Figure 18 shows a top view of Figure 17B relating to one embodiment of the present invention, along with the lines X, Y1, and Y2 on which the cross-sectional views of Figures 19A to 31C are based. The reference numerals in Figures 19A to 31C that are the same as those in Figures 4A to 16C (for example, starting with "2" instead of "1") indicate the same or similar elements as those in Figures 4A to 16C. For example, Figures 19A to 19C show the same processing and configuration for the semiconductor structure 200 as for the semiconductor structure 100 in Figures 4A to 4C. More specifically, the first and second semiconductor substrates 201 and 203 and the etching stop layer 202 are the same or similar as the first and second semiconductor substrates 101 and 103 and the etching stop layer 102.

[0156] Similar to the processes in Figures 4B and 4C, and Figures 19B and 19C, a portion of the second semiconductor substrate 203 is recessed to a lower height, and the dielectric layer 204 fills the recessed portion of the second semiconductor substrate 203 to form a plurality of isolation regions (e.g., shallow trench isolation (STI) regions). According to one embodiment of the present invention, a dielectric layer 209 (also referred to as a BDI layer) is formed on the second semiconductor substrate 203, similar to the dielectric layer 109. Similar to the SiGe layer 105 and the Si layer 107, the semiconductor structure 200 includes a nanosheet stack containing the SiGe layer 205 and the Si layer 207.

[0157] The semiconductor structure 200 further includes a dummy gate portion 211 formed on the uppermost Si layer 207 and around the stacked nanosheet configuration of the SiGe layer 205 and the Si layer 207. The dummy gate portion 211 is the same as or similar to the dummy gate portion 111 of the semiconductor structure 100. Similar to the hard mask layer 120, a hard mask layer 220 is formed on the dummy gate portion 211. Referring to Figure 19A, the semiconductor structure 200 includes gate spacers 212 and inner spacers 213, similar to the gate spacers 112 and inner spacers 113 of the semiconductor structure 100.

[0158] Referring to Figures 20A to 20C, a protective spacer 215 is formed on the side surface of the nanosheet stack, including the Si layer 207, gate spacer 212, and inner spacer 213, similar to the protective spacer 115. After the formation of the protective spacer 215, the exposed portion of the dielectric layer 209 and a portion of the second semiconductor substrate 203 beneath it are removed to form openings 224-1 and 224-2, corresponding to the locations where the back-side source / drain contacts 260-1 and 260-2 (see Figures 29A to 31C) will be formed. An etching process, such as RIE, is performed to form openings 224-1 and 224-2 (e.g., trenches) within the second semiconductor substrate 203. The openings 224-1 and 224-2 are formed by etching through a portion of the dielectric layer 209 and a portion of the second semiconductor substrate 203.

[0159] Referring to Figures 21A to 21C, the openings 224-1 and 224-2 are filled with sacrificial placeholder layers 225-1 and 225-2, which include, for example, SiGe, a III-V semiconductor material, or another semiconductor material. As can be seen in Figures 21B and 21C, the openings 224-1 and 224-2 and the corresponding sacrificial placeholder layers 225-1 and 225-2 are wider than the openings 124-1 and 124-2 of the semiconductor structure 100 and the corresponding sacrificial placeholder layers 125-1 and 125-2.

[0160] Referring to Figures 22A to 22C, the protective spacer 215 is removed, for example, using an isotropic dry or wet etching process, and source / drain regions 230-1 and 230-2 are epitaxially grown between the nanosheet stacks. Source / drain regions 230-1 and 230-2 include epitaxial layers grown from the sides of the Si layer 207. The Si layer 207 will function as a nanosheet channel layer. As can be seen, source / drain regions 230-1 and 230-2 are formed on the entire upper surface of the sacrificial placeholder layers 225-1 and 225-2.

[0161] Referring to Figures 23A to 23C, the ILD layer 235 is deposited to fill the source / drain regions 230-1 and 230-2 and the surrounding portions thereof. The ILD layer 235 contains the same or similar material as the ILD layer 135 and is deposited using the same or similar deposition technique as used for the ILD layer 135, followed by a planarization process such as CMP to remove the excess portion of the ILD layer 135 deposited on the hard mask layer 220 and gate spacer 212, and to remove portions of the hard mask layer 220 and gate spacer 212 to expose the dummy gate region 211. Similar to the RMG process discussed in relation to Figures 8A to 8C, the dummy gate region 211 and SiGe layer 205 are selectively removed and replaced with a gate region 232 (also referred to herein as the gate structure). The gate region 232 may be the same or similar as the gate region 132.

[0162] Referring to Figures 24A to 24C, additional ILD material is deposited to form an additional ILD layer 235' on top of the ILD layer 235. The semiconductor structure 200 does not include a front-side source / drain contact. Similar to the front-side gate contact 142, a front-side gate contact 242 is formed through the ILD layer 235' to land on and contact the corresponding gate region 232. The process and materials used to form the front-side gate contact 242 are the same as those used to form the front-side source / drain contacts 140-1 and 140-2 in the semiconductor structure 100. A front-side BEOL interconnect 245 is formed on the ILD layer 235' containing the front-side gate contact 242. As can be seen, the front-side gate contact 242 contacts the front-side BEOL interconnect 245. A carrier wafer 247 is bonded to the front-side BEOL interconnect 245. The front-side BEOL interconnect 245 includes various BEOL interconnect structures that can be electrically connected to the front-side gate contact 242. The carrier wafer 247 may be formed from a material similar to that of the first and second semiconductor substrates 201 and 203, and may be formed by covering the front-side BEOL interconnect 245 using a wafer bonding process such as a dielectric-dielectric junction.

[0163] Referring to Figures 25A to 25C, the semiconductor structure 200 may be “flipped” (e.g., rotated 180 degrees) using the carrier wafer 247 so that the structure is inverted. In addition, the first semiconductor substrate 201 is removed from the back surface of the semiconductor structure 200. The removal process, including etching of the first semiconductor substrate 201, is stopped at the etching stop layer 202 as shown in Figures 25A to 25C. For example, the first semiconductor substrate 201 is selectively etched with an etching solution that selectively etches silicon relative to the material of the etching stop layer 202 (e.g., SiO2 or SiGe).

[0164] Referring to Figures 26A to 26C, the etching stop layer 202 and the second semiconductor substrate 203 (e.g., silicon layer) are selectively removed from the semiconductor structure 200 with respect to the sacrificial placeholder layers 225-1 and 225-2 and the dielectric layer 204 (e.g., STI region). As shown in Figures 26A to 26C, the etching stop layer 202 is removed, followed by the removal of the second semiconductor substrate 203, where the dielectric layer 204, the dielectric layer 209, and portions of the sacrificial placeholder layers 225-1 and 225-2 are exposed. The etching process for removing the etching stop layer 202 includes, for example, IBE by an Ar / CHF3 chemical reaction.

[0165] Referring to Figures 27A to 27C, a backside ILD layer 250 is deposited to fill the area previously occupied by the second semiconductor substrate 203. The backside ILD layer 250 is formed from the same or similar materials and processes as those used to form the backside ILD layer 150 of the semiconductor structure 100. In an exemplary embodiment, the backside ILD layer 250 is coplanar with the surfaces of sacrificial placeholder layers 225-1 and 225-2. After the CMP process, the surfaces of sacrificial placeholder layers 225-1 and 225-2 are exposed.

[0166] Referring to Figures 28A to 28C, the sacrificial placeholder layers 225-1 and 225-2 are selectively removed to expose the back surfaces of the source / drain regions 230-1 and 230-2. The sacrificial placeholder layers 225-1 and 225-2 are removed, for example, using a selective dry or wet etching process.

[0167] Referring to Figures 29A to 29C, backside source / drain contacts 260-1 and 260-2 are formed in the openings left by the removal of sacrificial placeholder layers 225-1 and 225-2 in the backside ILD layer 250 and between the dielectric layers 204. To form the backside source / drain contacts 260-1 and 260-2, a metal layer is deposited in the opening. The metal layer includes, for example, a silicide layer such as Ni, Ti, NiPt, a metal adhesive layer such as TiN, and a conductive metal filling layer such as W, Al, Co, Ru, and can be deposited using deposition techniques such as CVD, PECVD, RFCVD, PVD, ALD, MBD, PLD, LSMCD, sputtering, and / or plating, followed by a planarization process such as CMP to remove excess portions of the metal layer from above the backside ILD layer 250 and / or dielectric layer 204.

[0168] The back-side source / drain contacts 260-1 and 260-2 contact the respective back surfaces of the source / drain regions 230-1 and 230-2. In an exemplary embodiment, the back-side source / drain contacts 260-1 and 260-2 extend across the entire width of the source / drain regions 230-1 and 230-2 and contact the entire back surface of the source / drain regions 230-1 and 230-2. Referring back to Figure 18, the back-side source / drain contacts 260-1 and 260-2 may self-align with multiple edges of the source / drain regions 230-1 and 230-2. The back-side source / drain contacts 260-1 and 260-2 penetrate the back-side ILD layer 250 and / or dielectric layer 204 to land on and contact the corresponding back surfaces of the source / drain regions 230-1 and 230-2.

[0169] Referring to Figures 30A to 30C, additional back ILD material is deposited on top of the back ILD layer 250 to form an additional back ILD layer 250'. Conductive wires 265-1 (Vdd) and 265-2 (Vdd core), and vias 266-1 and 266-2 are then formed within the back ILD layer 250'. Via 266-1 is formed between conductive wire 265-1 and back source / drain contact 260-1, and via 266-2 is formed between conductive wire 265-2 and back source / drain contact 260-2. Conductive wires 265-1 and 265-2 are also referred to herein as back power rails. Openings are formed through a portion of the additional back ILD layer 250' when forming conductive wires 265-1 and 265-2, and vias 266-1 and 266-2. The openings where vias 266-1 and 266-2 are formed expose the portions of the back-side source / drain contacts 260-1 and 260-2 where vias 266-1 and 266-2 will be formed. In some locations, conductive wires 265-1 and 265-2 are formed on vias 266-1 and 266-2, respectively, within the openings that expose the back-side surfaces of vias 266-1 and 266-2. In other locations, portions of conductive wires 265-1 and 265-1 are not formed and do not contact vias 266-1 and 266-2.

[0170] Conductive wires 265-1 and 265-2, also referred to herein as power elements or back-side power rails, are formed within the additional back-side ILD layer 250' by forming trenches within the additional back-side ILD layer 250' and filling the trenches with a conductive material. Similarly, vias 266-1 and 266-2 are formed within the additional back-side ILD layer 250' by forming trenches within the additional back-side ILD layer 250' and filling the trenches with a conductive material. The trenches are opened within the additional back-side ILD layer 250', for example, using lithography and subsequent RIE. Conductive wires 265-1 and 265-2, and vias 266-1 and 266-2 are formed within the trenches by filling the trenches with a conductive material, such as, for example, a conductive material including, but not limited to, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, and / or copper. Before filling the trench with conductive material, a liner layer (not shown) containing, for example, titanium and / or titanium nitride may be formed on the side and bottom surfaces of the trench. The deposition of the conductive material can be carried out using one or more deposition techniques, including, but not limited to, CVD, PECVD, PVD, ALD, MBD, PLD, LSMCD, and / or spin-on coating, followed by planarization using a planarization process such as CMP.

[0171] Conductive wires 265-1 and vias 266-1 transmit, for example, the supply or drain voltage (Vdd) to the source / drain region 230-1 (e.g., the input source / drain region) through the back source / drain contact 260-1. Conductive wires 265-2 and vias 266-2 transmit, for example, the core supply voltage (Vdd_core) to the source / drain region 230-2 (e.g., the output source / drain region) through the back source / drain contact 260-2.

[0172] As can be seen in Figures 30A to 30C, the back source / drain contact 260-1 contacts the source / drain region 230-1, and via 266-1 is formed on and contacts the back source / drain contact 260-1. The back source / drain contact 260-2 contacts the source / drain region 230-2, and via 266-1 is formed on and contacts the back source / drain contact 260-2. The back ILD layer 250 and the additional back ILD layer 250' fill the empty areas on the lateral surfaces of the back source / drain contacts 260-1 and 260-2, and on the lateral surfaces of the conductive wires 265-1 and 265-2, and within vias 266-1 and 266-2. The back source / drain contacts 260-1 and 260-2 are adjacent to and contact the dielectric layer 204. Referring back to Figure 18, the backside source / drain contacts 260-1 and 260-2 each self-align with multiple edges of the active region (e.g., source / drain regions 230-1 and 230-2).

[0173] Referring to Figures 31A to 31C, a BSPDN layer 270 (also referred to herein as a back interconnect) is formed on an additional back ILD layer 250' and conductive wires 265-1 and 265-2. The BSPDN layer 270 includes, but is not limited to, various BSPDN structures such as interconnects in the power supply path from the voltage regulator module (VRM) to the circuit. The interconnect may include, for example, power and ground planes on the circuit board, cables associated with the power supply, connectors, and capacitors. Back-of-line power supply prevents BEOL wiring congestion, resulting in power performance benefits.

[0174] The semiconductor devices and methods for forming them according to the above techniques can be employed in a variety of applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., mobile phones and smartphones), solid-state media storage devices, functional circuits, etc. Systems and hardware incorporating semiconductor devices are intended embodiments of the present invention. Given the teachings provided herein, those skilled in the art will be able to envision other implementations and applications of embodiments of the present invention.

[0175] In some embodiments, the techniques described above are used in relation to semiconductor devices that require or otherwise utilize CMOS, MOSFET, and / or FinFET technology, for example. In non-limiting examples, semiconductor devices may include, but are not limited to, CMOS, MOSFET, and FinFET devices and / or semiconductor devices using CMOS, MOSFET, and / or FinFET technology.

[0176] The various structures described above may be implemented in integrated circuits. The resulting integrated circuit chips may be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in single-chip packages (such as plastic carriers with leads fixed to a motherboard or other higher-level carriers) or multi-chip packages (such as ceramic carriers with either or both surface interconnects or embedded interconnects). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, e.g., a motherboard, or (b) a final product. The final product may be any product containing integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processors.

[0177] As described above, conventional methods unnecessarily employ through-vias from the back to the front of the semiconductor device to establish a connection from the back power rail to the source / drain region of the FET. This results in complex semiconductor manufacturing processes and structures that hinder size reduction and miniaturization. Exemplary embodiments advantageously provide a technique for forming an efficient connection to the back power supply by using direct back contacts. For example, the input source / drain regions of multiple transistors are commonly connected to a direct back contact, and the output source / drain regions of multiple transistors are commonly connected to another direct back contact. The back contacts are connected to the back power rail and self-align with the edges of the input and output source / drain regions. The transistors may have a common gate structure and the same doping type. In some embodiments, the back source / drain contacts may be formed on part or all of the surface of the source / drain region. In cases where the back source / drain contacts are formed on the entire surface of the source / drain region, vias may be formed between the back source / drain contacts and the back power rail.

[0178] The semiconductor structure may further include at least one gate structure common to the first and second transistors. The first and second transistors may have the same doping type. The semiconductor structure may further include a third transistor adjacent to the second transistor. The third transistor may have a different doping type than that of the first and second transistors.

[0179] It should be understood that the various layers, structures, and regions shown in the figures are schematic diagrams and not drawn to scale. In addition, for the sake of ease of explanation, one or more types of layers, structures, and regions commonly used to form semiconductor devices or structures may not be explicitly shown in a given figure. This does not imply that any layers, structures, and regions not explicitly shown are omitted from actual semiconductor structures. Furthermore, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps illustrated and described herein. In particular, with respect to semiconductor processing steps, it should be emphasized that the descriptions provided herein are not intended to encompass all processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, are intentionally omitted herein for the sake of brevity.

[0180] Furthermore, the same or similar reference numerals are used throughout the figures to indicate the same or similar features, elements, or structures, and therefore, detailed descriptions of the same or similar features, elements, or structures are not repeated for each figure. The terms “approximately” or “substantially,” when used herein with respect to thickness, width, percentage, range, temperature, time, and other process parameters, etc., should be understood to mean that they are close or approximate, but not exact. For example, when the terms “approximately” or “substantially,” as used herein, suggest that there is a small tolerance, such as ±5%, preferably less than 2%, or 1% or less, of the amount mentioned.

[0181] The above description provides various materials, dimensions, and processing parameters for different elements. Unless otherwise stated, such materials are given merely as examples, and the embodiments are not exclusively limited to the specific examples given. Similarly, unless otherwise stated, all dimensions and process parameters are given as examples, and the embodiments are not exclusively limited to the specific dimensions or ranges given.

[0182] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or to limit the disclosed embodiments. Many modifications and variations will become apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best describe the principles of the embodiments, their practical applications, or technical improvements to the art found in the market, or to enable other those skilled in the art to understand the embodiments disclosed herein.

Claims

1. It is a semiconductor structure, A first transistor having a first input source / drain region and a first output source / drain region, A second transistor having a second input source / drain region and a second output source / drain region, Equipped with, The first input source / drain region and the second input source / drain region are connected to the first source / drain contact. The first output source / drain region and the second output source / drain region are connected to the second source / drain contact. The first source / drain contact and the second source / drain contact are located on the same side of the semiconductor structure.

2. The semiconductor structure according to claim 1, wherein the same side of the semiconductor structure includes the back side of the semiconductor structure.

3. The semiconductor structure according to claim 2, wherein at least one edge of the first source / drain contact is self-aligned with at least one edge of the first input source / drain region.

4. The semiconductor structure according to claim 3, wherein at least one edge of the second source / drain contact is self-aligned with at least one edge of the second output source / drain region.

5. The semiconductor structure according to claim 2, wherein the first source / drain contact and the second source / drain contact are connected to a first wire and a second wire located on the back side of the semiconductor structure, respectively.

6. The semiconductor structure according to claim 5, wherein the first wire is in contact with the first source / drain contact, and the second wire is in contact with the second source / drain contact.

7. The semiconductor structure according to claim 1, further comprising at least one gate structure common to the first transistor and the second transistor.

8. The semiconductor structure according to claim 1, wherein the first transistor and the second transistor have the same doping type.

9. The semiconductor structure according to claim 8, further comprising a third transistor adjacent to the second transistor, wherein the third transistor has a doping type different from that of the first and second transistors.

10. It is a semiconductor structure, Multiple input source / drain regions connected to the first wire through the first contact, Multiple output source / drain regions connected to the second wire through the second contact, Equipped with, The first wire and the second wire are located on the same side of the semiconductor structure, which is a semiconductor structure.

11. The semiconductor structure according to claim 10, wherein the same side of the semiconductor structure includes the back side of the semiconductor structure.

12. The semiconductor structure according to claim 11, wherein the first contact and the second contact are located on the back side of the semiconductor structure.

13. The semiconductor structure according to claim 10, wherein the plurality of input source / drain regions and the plurality of output source / drain regions correspond to a merged transistor, and the merged transistor includes a first transistor and a second transistor.

14. The semiconductor structure according to claim 13, wherein the same side of the semiconductor structure includes the back sides of the first transistor and the second transistor.

15. The system further comprises a third transistor adjacent to the merged transistor, and at least one gate structure common to the merged transistor and the third transistor. The first transistor and the second transistor have the same doping type. The semiconductor structure according to claim 13, wherein the third transistor has a doping type different from the doping types of the first transistor and the second transistor.

16. It is a semiconductor structure, A first input source / drain region and a first output source / drain region, A second input source / drain region and a second output source / drain region, Equipped with, The first input source / drain region and the second input source / drain region are connected to the first source / drain contact. The first output source / drain region and the second output source / drain region are connected to the second source / drain contact. The first source / drain contact is connected to the first wire through the first via, and the second source / drain contact is connected to the second wire through the second via. The first source / drain contact, the second source / drain contact, the first wire, and the second wire are located on the same side of the semiconductor structure, wherein the semiconductor structure is a semiconductor structure.

17. The semiconductor structure according to claim 16, wherein the same side of the semiconductor structure includes the back side of the semiconductor structure.

18. The first input source / drain region and the first output source / drain region correspond to the first transistor, The second input source / drain region and the second output source / drain region correspond to the second transistor, The semiconductor structure according to claim 16, wherein the first transistor and the second transistor gate a voltage input for a core power supply.

19. It is a semiconductor structure, A plurality of transistors comprising a first transistor, a second transistor adjacent to the first transistor, and a third transistor adjacent to the second transistor, wherein the first transistor and the second transistor have the same doping type, and the third transistor has a doping type different from that of the first transistor and the second transistor. A gate structure common to the first transistor, the second transistor and the third transistor, A first input source / drain region and a first output source / drain region corresponding to the first transistor, A second input source / drain region and a second output source / drain region corresponding to the second transistor, Equipped with, The first input source / drain region and the second input source / drain region are connected to the first source / drain contact. A semiconductor structure in which the first output source / drain region and the second output source / drain region are connected to a second source / drain contact.

20. At least one edge of the first source / drain contact is self-aligned with at least one edge of the first input source / drain region, The semiconductor structure according to claim 19, wherein at least one edge of the second source / drain contact is self-aligned with at least one edge of the second output source / drain region.

21. The semiconductor structure according to claim 19, wherein the first source / drain contact and the second source / drain contact are located on the back side of the plurality of transistors and are connected to the first wire and the second wire, respectively, located on the back side of the plurality of transistors.

22. The semiconductor structure according to claim 21, wherein the first wire is in contact with the first source / drain contact, and the second wire is in contact with the second source / drain contact.

23. The steps include forming a first sacrificial layer and a second sacrificial layer within a semiconductor layer, A step of forming a plurality of first source / drain regions on the semiconductor layer, wherein at least one of the plurality of first source / drain regions is formed on the first sacrificial layer, A step of forming a plurality of second source / drain regions on the semiconductor layer, wherein at least one of the plurality of second source / drain regions is formed on the second sacrificial layer, The steps include replacing the first sacrificial layer with a first contact and replacing the second sacrificial layer with a second contact, The steps include forming a first wire on the first contact and forming a second wire on the second contact, Equipped with, The first wire and the second wire are located on the same side as the first and second contacts of the plurality of first and second source / drain regions, in a manner.

24. The method according to claim 23, further comprising the step of connecting the first and second wires to a rear-side power supply network.

25. At least one edge of the first contact is self-aligned with at least one edge of the at least one first source / drain region, The method according to claim 23, wherein at least one edge of the second contact is self-aligned with at least one edge of the at least one second source / drain region.

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