Method for forming an electronic device having a distorted transistor channel

Abstract

Embodiments of this disclosure provide methods for manufacturing electronic devices that satisfy the compressive stress requirements of PMOS transistors and the tensile stress requirements of NMOS transistors. Each P-metal stack and N-metal stack is formed on the upper surface of a channel located between the source and drain on a semiconductor substrate and comprises a nanosheet channel layer and trenches between each nanosheet channel layer, having at least one side defining a gate trench. Some embodiments include forming a work function layer within the channel and inducing strain in the work function layer within the channel. Some embodiments include forming a gate metal packed layer on each of the P-metal stacks and N-metal stacks and inducing strain in the gate metal packed layer within the channel. The gate metal packed layer covers at least one side of each of the P-metal stacks and N-metal stacks and fills the gate trench.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic device manufacturing, particularly to transistors. More specifically, embodiments of the present disclosure are directed to methods of manufacturing FinFETs and GAA devices having strained transistor channels.

Background Art

[0002]

[0002] Integrated circuits have evolved into complex devices that can house millions of transistors, capacitors, and resistors on a single chip. In the process of the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the feature size (i.e., the smallest component (or line) that can be fabricated using a manufacturing process) has decreased.

[0003]

[0003] A transistor is a circuit component or circuit element that is often formed on a semiconductor device. Depending on the circuit design, many transistors, in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, can also be formed on a semiconductor device. Integrated circuits incorporate planar field-effect transistors (FETs) in which current flows through a semiconductor channel between a source and a drain in response to a voltage applied to a control gate.

[0004]

[0004] As device dimensions shrink, the device feature size and materials are challenged to maintain switching speed without failure. Several new technologies have emerged that enable chip designers to continue to shrink the gate length. Dimension control of device structures is an important issue for current and future technology generations.

[0005]

[0005] For example, microelectronic field-effect transistors (e.g., complementary metal-oxide-semiconductor (CMOS) field-effect transistors) can be formed on a substrate and work together to perform various functions in a circuit. A CMOS transistor has a gate structure located on a channel region formed between the source region and the drain region of the transistor. The gate structure generally includes a gate electrode and a gate dielectric. The gate electrode is located on the gate dielectric and is used during operation to control the flow of charge carriers (i.e., current) in the channel region beneath the gate dielectric.

[0006]

[0006] Through the transition of transistor technology from planar FETs to FinFETs, inducing stress / strain in the transistor channel of GAA devices such as negative metal-oxide-semiconductor (NMOS) transistors and positive metal-oxide-semiconductor (PMOS) transistors remains a challenge. Electron mobility (in the case of NMOS transistors) and hole mobility (in the case of PMOS transistors) are thought to be increased by inducing stress (or strain) which alters the arrangement of silicon atoms in the crystal lattice within the transistor channel. For example, in PMOS transistors, holes move via bond coupling. Increasing hole mobility within the transistor channel and inducing compressive stress is thought to be achieved by reducing the longitudinal interatomic spacing. For example, in NMOS transistors, electrons move with drift and diffusion. Increasing electron mobility within the transistor channel and inducing tensile stress is thought to be achieved by increasing the longitudinal interatomic spacing.

[0007]

[0007] There are two conventional approaches to inducing stress in transistor channels: biaxial global straining and uniaxial local straining. In a typical biaxial spherical straining, strain can be induced by various processes by mechanically compressing and / or stretching the silicon crystal lattice. For example, biaxial global strain has been achieved by epitaxially growing a thin silicon (Si) layer on a relaxed silicon germanium (SiGe) substrate. Due to the lattice mismatch between Si and SiGe, the Si lattice undergoes biaxial tensile strain along the interface plane. Alternatively, biaxial global strain can be introduced after the wafer has been fully processed. This is achieved, for example, by thinning the wafer to less than 10 μm and transferring it to a polymer film. After the wafer is transferred, mechanically straining the Si film allows for uniaxial and biaxial strain parallel to the substrate surface without inducing defects (e.g., vacancies) in the Si layer. As long as the strain level remains within the elastic limit, the mechanically strained wafer can be safely bonded to the final substrate.

[0008]

[0008] One drawback of conventional global strain techniques is that such techniques induce only one type of strain, namely compressive stress / strain or tensile stress / strain, but not both. To address the shortcomings of conventional global strain techniques, uniaxial local strain treatments have been developed.

[0009]

[0009] In a typical uniaxial local strain treatment, silicon germanium (SiGe) is incorporated into the source and drain regions of a PMOS transistor, and silicon carbide (SiC) is incorporated into the source and drain regions of an NMOS transistor.

[0010]

[0010] However, inducing and / or maintaining strain in the transistor channels of GAA devices, particularly in the trenches between nanosheets due to spacing constraints, remains a challenge. In particular, for PMOS transistors, the compressive stress achieved by two conventional approaches to induce stress in the transistor channel is much higher than desired, measured in gigapascals, due to high electron mobility but low hole mobility. For NMOS transistors, the tensile stress achieved within the transistor channel by two conventional processes is undesirable due to the low electron mobility measured by Ron DIBL. Ron DIBL is an on-resistance versus drain-induced barrier drop plot, which is a metric for measuring transistor performance. A lower Ron at a constant DIBL means improved performance.

[0011]

[0011] Therefore, there is a need for improved methods for manufacturing electronic devices that satisfy the compressive stress requirements of PMOS transistors and the tensile stress requirements of NMOS transistors. [Overview of the project]

[0012]

[0012] One or more embodiments of the present disclosure relate to a method for manufacturing an electronic device. The method comprises forming a P-metal stack and an N-metal stack on a semiconductor substrate. Each of the P-metal stack and the N-metal stack is formed on the upper surface of a channel located between a source and a drain on the semiconductor substrate. Each of the P-metal stack and the N-metal stack includes a nanosheet channel layer and trenches between each nanosheet channel layer. The method further comprises forming a work function layer in the channels between the nanosheet channel layers in each trench and inducing strain in the work function layer within the channels. Each of the P-metal stack and the N-metal stack independently has compressive stress and tensile stress in the range of 1 gigapascal (GPa) to 2 GPa.

[0013]

[0013] Additional embodiments of the present disclosure relate to a method for manufacturing an electronic device. The method comprises forming a P-metal stack and an N-metal stack on a semiconductor substrate. Each of the P-metal stack and the N-metal stack is formed on the upper surface of a channel located between a source and a drain on the semiconductor substrate. Each of the P-metal stack and the N-metal stack includes a nanosheet channel layer and trenches between each nanosheet channel layer, and each of the P-metal stack and the N-metal stack has at least one side, the at least one side defining a gate trench, and a gate metal packed layer is formed on each of the P-metal stack and the N-metal stack to induce gate metal packed layer strain in the channel. The gate metal packed layer covers at least one side of each of the P-metal stack and the N-metal stack and fills the gate trench. The P-metal stack has a compressive stress in the range of -0.1 GPa to -3.1 GPa, and the N-metal stack has a tensile stress of 2 GPa or more.

[0014]

[0014] Further embodiments of the present disclosure relate to a method for manufacturing an electronic device. The method comprises forming a P-metal stack and an N-metal stack on a semiconductor substrate. Each of the P-metal stack and the N-metal stack is formed on the upper surface of a channel located between a source and a drain on the semiconductor substrate. Each of the P-metal stack and the N-metal stack includes nanosheet channel layers and trenches between each nanosheet channel layer, and each of the P-metal stack and the N-metal stack has at least one side, the at least one side defining a gate trench. The method further comprises forming a work function layer in the channels between the nanosheet channel layers in each trench, inducing strain in the work function layer in the channels, and heat treatment. The method further comprises forming a gate metal packed layer on each of the P-metal stack and the N-metal stack, and inducing strain in the gate metal packed layer in the channels. The gate metal packed layer covers at least one side of each of the P-metal stack and the N-metal stack and fills the gate trench.

[0015]

[0015] To enable a detailed understanding of the features of the Disclosure listed above, a more detailed description of the Disclosure, which has been briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the Disclosure, as the Disclosure may also permit other equally effective embodiments, and therefore should not be considered to limit the scope of the Disclosure.

[0016]

[0016] In the following attached drawings, where the same elements are indicated by the same reference numerals, the embodiments described herein are merely examples and not limiting. [Brief explanation of the drawing]

[0017] [Figure 1A] The following diagrams show process flow diagrams of methods for manufacturing electronic devices according to one or more embodiments of the present disclosure. [Figure 1B] The following diagrams show process flow diagrams of methods for manufacturing electronic devices according to one or more embodiments of the present disclosure. [Figure 1C] The following diagrams show process flow diagrams of methods for manufacturing electronic devices according to one or more embodiments of the present disclosure. [Figure 2A] The following are cross-sectional views of semiconductor substrates according to one or more embodiments of this disclosure. [Figure 2B] The following are cross-sectional views of semiconductor substrates according to one or more embodiments of this disclosure. [Figure 2C] The following are cross-sectional views of semiconductor substrates according to one or more embodiments of this disclosure. [Figure 2D] The following are cross-sectional views of semiconductor substrates according to one or more embodiments of this disclosure. [Figure 2E] This shows a cross-sectional view of the semiconductor substrate after a work function layer has been formed within the channel and work function layer strain has been induced. [Figure 2F] Another cross-sectional view of the semiconductor substrate after a work function layer has been formed within the channel and work function layer strain has been induced is shown. [Figure 2G]A cross-sectional view of a semiconductor substrate is shown after forming a work function layer and then forming a gate metal fill layer on the work function layer, inducing work function layer strain and gate metal fill layer strain in the channel. [Figure 3] A cluster tool according to one or more embodiments of the present disclosure is shown.

Embodiments for Carrying Out the Invention

[0018]

[0028] Before explaining some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or process steps described in the following description. The present disclosure can also implement other embodiments and can be practiced or carried out in various ways.

[0019]

[0029] As used herein, the term "about" means approximately or nearly and means a variation of up to ±15% of the numerical value in light of the recited numerical value or range. For example, values that differ by a difference of ±14%, ±10%, ±5%, ±2%, or ±1% satisfy the definition of about.

[0020]

[0030] As used in this specification and the appended claims, the term "substrate" or "wafer" refers to the surface or a portion of the surface on which processing acts. Also, when reference is made to a substrate, it will be understood by those skilled in the art that it may refer to only a portion of the substrate, unless otherwise explicitly stated in the context. In addition, when reference is made to deposition on a substrate, it can mean both a bare substrate and a substrate on which one or more films or features are deposited or formed on top.

[0021]

[0031] As used in this document, “substrate” refers to any substrate or material surface formed on a substrate on which a film treatment is performed during the manufacturing process. For example, substrate surfaces on which treatment may be performed include, depending on the application, silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. A substrate includes, but is not limited to, a semiconductor wafer. A substrate may be exposed to pretreatment processes for polishing, etching, reducing, oxidizing, hydroxylating, annealing, and / or baking the substrate surface. In addition to direct film treatment on the surface of the substrate itself, any of the disclosed film treatment steps may be performed on underlying layers formed on the substrate, as will be disclosed in more detail below, and the term “substrate surface” is intended to include such underlying layers as the context indicates. Therefore, for example, if a film / layer or partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0022]

[0032] The term "on" indicates direct contact between elements. The term "directly on" indicates direct contact between elements without any intervening elements.

[0023]

[0033] As used in this document and the attached claims, terms such as “precursor,” “reactant,” and “reactive gas” are interchangeable and refer to any gas species that can react with the substrate surface.

[0024]

[0034] As used in this document, “atomic layer deposition” or “periodic deposition” refers to the sequential exposure of two or more reactive compounds to a substrate surface in order to deposit a layer of material. The substrate or a portion of the substrate is exposed separately to two or more reactive compounds introduced into the reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to adhere to and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, different portions of the substrate surface, or material on the substrate surface, are exposed to two or more reactive compounds simultaneously such that no given point on the substrate is substantially exposed to multiple reactive compounds at the same time. As used in this document and in the appended claims, the term “substantially” as used in this context means, as understood by those skilled in the art, that a small portion of the substrate may be simultaneously exposed to multiple reactive gases by diffusion, and that this simultaneous exposure is unintentional.

[0025]

[0035] In one aspect of time-domain ALD processing, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas (such as argon) is introduced into the processing chamber to purge the reaction zone or to remove any residual reactive compounds or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the entire deposition process so that only the purge gas flows during the time delays between pulsed deliveries of the reactive compounds. The reactive compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either scenario, one cycle consists of the ALD process of pulsed delivery of compound A, purge gas, compound B, and purge gas. A cycle can begin with either compound A or compound B and continue each sequence of the cycle until a film of a predetermined thickness is obtained.

[0026]

[0036] One or more of the layers deposited on the substrate or the substrate surface are continuous. In this document, the term "continuous" refers to a layer that covers the entire exposed surface without gaps or bare spots that expose the material beneath the deposited layer. A continuous layer may have gaps or bare spots with a surface area of ​​less than approximately 15% or less than approximately 10% of the total surface area of ​​the layer.

[0027]

[0037] In an embodiment of the spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are supplied simultaneously to the reaction zone but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas supply device so that any given point on the substrate is exposed to the first and second reactive gases.

[0028]

[0038] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive wires, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of a substrate, such as a semiconductor substrate, exhibiting a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric interposed between the gate electrode in the semiconductor substrate and the channel region.

[0029]

[0039] As used herein, the term “field-effect transistor” or “FET” refers to a transistor that uses an electric field to control the electrical behavior of a device. A field-effect transistor is a voltage-controlled device whose current-transmitting ability changes when an electric field is applied. Field-effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by the voltage difference between the body and the gate of the device. The three terminals of an FET are the source (S) through which carriers enter the channel, the drain (D) through which carriers exit the channel, and the gate (G), which is the terminal that regulates the conductivity of the channel. Traditionally, the current entering the channel from the source (S) is denoted as IS, and the current entering the channel from the drain (D) is denoted as ID. The voltage between the drain and source is V DS It is called a gate (G) by applying a voltage to the drain (i.e., I D The current entering the channel can be controlled using this method.

[0030]

[0040] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a type of field-effect transistor (FET) used in integrated circuits and high-speed switching applications. MOSFETs have an insulated gate, and the voltage applied to it determines the device's conductivity. This ability to change conductivity in response to the applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the modulation of charge concentration by metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to MOS capacitors, MOSFETs include two additional terminals (source and drain), each connected to a separate, highly doped region separated by the body region. These regions can be p-type or n-type, but both are the same type and are the opposite type to the body region. The source and drain (unlike the body) are highly doped, and the doping type is followed by a "+" symbol.

[0031]

[0041] If the MOSFET is an n-channel or nMOS FET, the source and drain are the n+ region, and the body is the p-type substrate region. If the MOSFET is a p-channel or pMOS FET, the source and drain are the p+ region, and the body is the n-type substrate region. The source is so named because it is the source of charge carriers (electrons in the case of an n-channel, and holes in the case of a p-channel) flowing through the channel. Similarly, the drain is where charge carriers exit the channel.

[0032]

[0042] An nMOS FET consists of an n-type source / drain and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away from the gate. This allows for the formation of an n-type channel between the source and drain, and current is carried by electrons from the source to the drain through the induced n-type channel. Logic gates and other digital devices implemented using NMOS are said to have NMOS logic. NMOS has three operating modes called cutoff, triode, and saturation. Circuits with NMOS logic gates dissipate electrostatic force when the circuit is idling because DC current flows through the logic gate when the output is low.

[0033]

[0043] A pMOS FET consists of a p-type source / drain and an n-type substrate. When a positive voltage is applied between the source and gate (or a negative voltage between the gate and source), a p-type channel is formed between the source and drain with opposite polarity. Current is carried from the source to the drain by holes through the induced p-type channel. When the gate voltage is high, the PMOS does not conduct, and when the gate voltage is low, the PMOS conducts. Logic gates and other digital devices implemented using PMOS are said to have PMOS logic. PMOS technology is low-cost and has good noise immunity.

[0034]

[0044] In NMOS, the carriers are electrons, while in PMOS, the carriers are holes. When a high voltage is applied to the gate, NMOS conducts, but PMOS does not. Furthermore, when a low voltage is applied to the gate, NMOS does not conduct, but PMOS does. Because the electron carriers in NMOS move twice as fast as the hole carriers in PMOS, NMOS is considered faster than PMOS. However, PMOS devices are more resistant to noise than NMOS devices. In addition, NMOS can provide half the impedance offered by PMOS (with the same shape dimensions and operating conditions), so NMOS ICs will be smaller than PMOS ICs (providing the same functionality).

[0035]

[0045] As used herein, the term “Fin-field-effect transistor (FinFET)” refers to a substrate-built MOSFET transistor in which the gate is located on two, three, or four sides of the channel, or wrapped around the channel, forming a double-gate structure. FinFET devices are given the common name FinFET because the source / drain regions form “fins” on the substrate. FinFET devices have fast switching times and high current density.

[0036]

[0046] As used herein, the term “gate all around (GAA)” is used to refer to electronic devices such as transistors in which the gate material completely surrounds the channel region. The channel region of a GAA transistor may include nanowires or nanoslabs or nanosheets, rod-shaped channels, or other suitable channel configurations known to those skilled in the art.

[0037]

[0047] In one or more embodiments, after implementing the method described herein, the channel region of the GAA transistor has stresses ranging from high tensile stress (e.g., 1 gigapascal (GPa) or more) to compressive stress (e.g., negative GPa). In one or more specific embodiments, after implementing the method described herein, advantageously, the channel region of the N metal stack has high tensile stress (e.g., 1 gigapascal (GPa) or more), and the channel region of the P metal stack has compressive stress (e.g., negative GPa).

[0038]

[0048] In one or more embodiments, the channel region of the GAA device has a plurality of vertically spaced horizontal nanowires or horizontal bars, making the GAA transistor a stacked horizontal gate all-around (hGAA) transistor.

[0039]

[0049] As used herein, the term "nanowire" refers to a nanometer (10⁻¹⁰) -9 This refers to nanostructures having a diameter in units of meters. Nanowires can also be defined as structures with a length-to-width ratio greater than 1000. Alternatively, nanowires can be defined as structures whose thickness or diameter is limited to tens of nanometers or less, but whose length is not limited. Nanowires are used in transistors and some laser applications, and in one or more embodiments, they are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in logic CPUs, GPUs, MPUs, and transistors for volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term “nanosheet” refers to a two-dimensional nanostructure having a thickness in the range of about 0.1 nm to about 1000 nm, or 0.5 nm to 500 nm, or 0.5 nm to 100 nm, or 1 nm to 500 nm, or 1 nm to 100 nm, or 1 nm to 50 nm.

[0040]

[0050] Embodiments of this disclosure advantageously provide methods for manufacturing electronic devices that increase electron mobility (in NMOS transistors) and hole mobility (in PMOS transistors) by distorting the transistor channel. Some embodiments advantageously provide methods for manufacturing electronic devices that satisfy the compressive stress requirements of PMOS transistors and the tensile stress requirements of NMOS transistors. Embodiments of this disclosure address the challenges of conventional biaxial global straining and uniaxial local straining with novel integration schemes.

[0041]

[0051] The inventors have advantageously developed two independent processes for inducing stress / strain in the transistor channel to satisfy the compressive stress requirements of PMOS transistors and the tensile stress requirements of NMOS transistors.

[0042]

[0052] Forming a work function layer and inducing strain in the work function layer, as described herein, may be referred to as the “first strain induction process.” Forming a gate metal packed layer and inducing strain in the gate metal packed layer, as described herein, may be referred to as the “second strain induction process.” The symbols “first strain induction process” and “second strain induction process” are used for illustrative purposes only to describe the respective processes in the order shown in the figures. It should be understood that the processes developed by the inventors (the “first strain induction process” and the “second strain induction process”) may be implemented separately or together.

[0043]

[0053] Embodiments of this disclosure are illustrated by drawings showing devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of this disclosure. The illustrated processes are merely illustrative examples of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated uses. In one or more illustrated embodiments, unless otherwise specified, similar references indicate similar elements.

[0044]

[0054] Figures 1A, 1B, and 1C independently show process flow diagrams of methods for manufacturing electronic devices according to one or more embodiments of the present disclosure. Figure 1A shows Method 10. Figure 1B shows Method 50. Figure 1C shows Method 100.

[0045]

[0055] Figures 2A to 2B are cross-sectional views of an electronic device (e.g., a transistor such as a FinFET or GAA) 200 according to one or more embodiments. Figures 2A to 2C show the process flow for forming a P-metal stack and an N-metal stack on a semiconductor substrate.

[0046]

[0056] The electronic devices 200 shown in Figures 2E to 2G may be manufactured by the methods 10, 50, and 100 described herein.

[0047]

[0057] Referring to Figures 2A to 2G, in one or more embodiments, the electronic device 200 comprises a semiconductor substrate 202 having a top surface 203. The semiconductor substrate 202 can be any suitable substrate material. In one or more embodiments, the semiconductor substrate 202 includes semiconductor materials, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphate (InP), indium gallium arsenide (InGaAs), aluminum indium arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), other semiconductor materials, or any combination thereof. In one or more embodiments, the semiconductor substrate 202 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), or selenium (Se). While some examples of materials on which a semiconductor substrate 202 may be formed are described herein, the essence and scope of this disclosure includes any material that can serve as a basis on which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) may be constructed.

[0048]

[0058] In one or more embodiments, the semiconductor substrate 202 is a p-type or n-type substrate. In this specification, the term “n-type” refers to a semiconductor produced by doping an intrinsic semiconductor with an electron donor element during manufacturing. The term “n-type” derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. In this specification, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration greater than the electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers.

[0049]

[0059] In one or more embodiments, the source region 204a is located on the upper surface 203 of the semiconductor substrate 202. In one or more embodiments, the source region 204a has a source and a source contact (not shown). The drain region 204b is located on the upper surface 203 of the semiconductor substrate 202 opposite to the source region 204a. In one or more embodiments, the drain region 204b has a drain and a drain contact (not shown).

[0050]

[0060] In one or more embodiments, the source region 204a and / or the drain region 204b can be any suitable material known to those skilled in the art. In one or more embodiments, the source region 204a and / or the drain region 204b may have two or more layers. For example, the source region 204a and / or the drain region 204b may independently comprise three layers. In one or more embodiments, the source region 204a and the drain region 204b may independently comprise one or more of the following: copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorus (P), germanium (Ge), silicon (Si), aluminum (Al), or zirconium (Zr). In some embodiments, the source region 204a and drain region 204b include a silicon bottom layer having doped epi (e.g., SiGe, SiP, etc.), a second layer of silicon compounds which may include nickel (Ni), titanium (Ti), aluminum (Al), etc., and a third layer or top layer which may be, but not limited to, a metal such as cobalt, tungsten, or ruthenium. In some embodiments, the source region 204a and drain region 204b may be raised source / drain regions formed by EPI growth.

[0051]

[0061] In one or more embodiments, the source contact and / or drain contact may be independently selected from one or more of the following: nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In one or more embodiments, the formation of the source contact and / or drain contact may be carried out by any suitable process known to those skilled in the art, including, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0052]

[0062] In one or more embodiments, the channel 206 is located between the source 204a and the drain 204b. As shown in Figures 2F and 2G, the channel 206 comprises multiple nanosheets. The terms “channel 206,” “transistor channel 206,” “multiple nanosheets 206,” and “multiple nanosheet channel layer 206” may be used interchangeably herein. The channel 206 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the channel 206 comprises silicon (Si).

[0053]

[0063] Each of the methods described herein (for example, methods 10, 50, and 100) includes forming a P-metal stack and an N-metal stack on a semiconductor substrate (step 12 of method 10, step 52 of method 50, and step 110 of method 100).

[0054]

[0064] Each of the P-metal stack and the N-metal stack is formed on the upper surface 205 of a channel 206 located between a source 204a and a drain 204b on a semiconductor substrate 202. In some embodiments, forming each of the P-metal stack and the N-metal stack includes depositing an interface layer 210 on the upper surface 205 of the channel 206, depositing a high-dielectric-constant dielectric layer 212 on the interface layer 210, and depositing a dipole layer 214 on the high-dielectric-constant dielectric layer 212 to a predetermined thickness.

[0055]

[0065] Referring to Figures 1A-1C and 2A-2G, in some embodiments, the interface layer 210 is deposited on the upper surface 205 of the channel 206 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In one or more embodiments, the interface layer 210 includes a silicon oxide (SiOx) layer formed on doped or undoped silicon. In one or more embodiments, the interface layer 210 may be formed by etching and oxide formation on the surface. In one or more embodiments, the interface layer 210 has a thickness ranging from 1 Å to 10 Å.

[0056]

[0066] In some embodiments, a wet chemical technique is performed to form the interface layer 210. The wet chemical technique may be any suitable technique known to those skilled in the art. In some embodiments, the wet chemical technique includes a pre-cleaning process. In some embodiments, the pre-cleaning process includes using an SC-1 solution containing one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, the pre-cleaning process includes using an SC-1 solution that does not contain ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, after using the SC-1 solution, the pre-cleaning process includes etching off native oxides on the semiconductor substrate 202 using dilute hydrofluoric acid (dilute HF, e.g., dilute HF of 130:1) at a ratio greater than 100:1 to form a hydrophobic surface (i.e., the interface layer 210).

[0057]

[0067] In some embodiments, rapid heat treatment (RTP) is used to form the interface layer 210. RTP may be any suitable process known to those skilled in the art. In some embodiments, RTP is a thermal oxidation process in which a silicon oxide (SiOx) layer, for example, the interface layer 210, is grown on a semiconductor substrate 202.

[0058]

[0068] In some embodiments, the high dielectric constant dielectric layer 212 is deposited on the interface layer 210 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, the high dielectric constant dielectric layer 212 is deposited conformally by ALD.

[0059]

[0069] The high dielectric constant dielectric layer 212 contains one or more of the following: hafnium oxide (HfOx), hafnium zirconium oxide (HfZrOx), zirconium oxide (ZrOx), nitrogen-doped hafnium oxide (HfOx), nitrogen-doped hafnium zirconium oxide (HfZrOx), and nitrogen-doped zirconium oxide (ZrOx).

[0060]

[0070] The high dielectric layer 212 can have any suitable thickness. In some embodiments, the high dielectric layer 212 has a thickness in the range of 10 Å to 20 Å.

[0061]

[0071] In some embodiments, the dielectric layer 214 is deposited on the upper surface 213 of the high dielectric constant dielectric layer 212 using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0062]

[0072] In some embodiments, depositing the dipole layer 214 involves exposing the semiconductor substrate 202 to pulses of a metal-containing precursor and pulses of reactants by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In some embodiments, the semiconductor substrate 202 is purged after each pulse. In one or more specific embodiments, the dipole layer 214 is deposited by atomic layer deposition (ALD).

[0063]

[0073] In one or more embodiments, the dipole layer 214 is deposited by atomic layer deposition (ALD) at a temperature in the range of about 200°C to about 600°C. In one or more embodiments, the dipole layer 214 is deposited by atomic layer deposition (ALD) at a temperature of about 450°C or less.

[0064]

[0074] The dipole layer 214 may have any suitable thickness. In one or more embodiments, the dipole layer 214 has a thickness in the range of 1 Å to 10 Å, or in the range of 2 Å to 5 Å. In one or more specific embodiments, the dipole layer 214 has a thickness in the range of 3 Å to 4 Å. The dipole layer 214 may be deposited as a single layer or as a multilayer film.

[0065]

[0075] In some embodiments, the dipole layer 214 includes one or more of a metal layer, a metal oxide layer, or a metal nitride layer.

[0066]

[0076] In some embodiments, the metal-containing precursor used to form the dipole layer 214 includes one or more of the following: titanium (Ti), tantalum (Ta), aluminum (Al), niobium (Nb), antimony (Sb), tellurium (Te), germanium (Ge), gallium (Ga), lanthanum (La), yttrium (Y), strontium (Sr), scandium (Sc), or boron (B).

[0067]

[0077] In some embodiments, the reactants are hydrogen-containing reactants for forming a dipole layer 214 containing a pure metal layer. In some embodiments, the hydrogen-containing reactant used to form the dipole layer 214 is hydrogen (H2) or deuterium ( 2 Includes one or more of H).

[0068]

[0078] In some embodiments, the reactants are oxygen-containing reactants for forming a dipole layer 214 containing a metal oxide layer. In some embodiments, the oxygen-containing reactants used to form the dipole layer 214 include one or more of oxygen (O2), ozone (O3), or water (H2O).

[0069]

[0079] In some embodiments, the reactants are nitrogen-containing reactants for forming a dipole layer 214 containing a metal nitride layer.

[0070]

[0080] In some embodiments, the nitrogen-containing reactant used to form the dipole layer 214 is nitrogen (N2), ammonia (NH3), hydrazine (N2H4), co-flow of nitrogen radicals (N2*) and hydrogen radicals (H*), co-flow of nitrogen radicals (N2*) and hydrogen (H2) gas, or nitrogen radicals (N2) and deuterium ( 2 H) Includes one or more of the gas confluences.

[0071]

[0081] In some embodiments, the nitrogen-containing reactant used to form the dipole layer 214 comprises substituted or unsubstituted alkylhydrazines. In some embodiments, the alkylhydrazine comprises atoms ranging from 1 to 6 carbon atoms. In one or more embodiments, the alkylhydrazine is t-butylhydrazine. In some embodiments, the nitrogen-containing reactant comprises plasma. In some embodiments, the nitrogen-containing reactant comprises ammonia (NH3).

[0072]

[0082] Figures 2B, 2C, and 2E show N-metal stacks 240 and P-metal stacks 250. In one or more embodiments, the stack on the left is an N-metal stack 240, and the stack on the right is a P-metal stack 250. Those skilled in the art will recognize that either the left or right side may include either an N-metal stack 240 or a P-metal stack 250, and that this disclosure is not limited to the illustrated embodiments.

[0073]

[0083] In one or more embodiments, the channel 206 comprises an n-type material, and the dipole layer 214 comprises one or more of the following: lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), magnesium (Mg), scandium (Sc), strontium (Sr), yttrium (Y), zirconium (Zr), or cesium (Cs).

[0074]

[0084] In one or more embodiments, the channel 206 comprises a p-type material, and the dipole layer 214 comprises one or more of the following: aluminum (Al), titanium (Ti), gallium (Ga), germanium (Ge), selenium (Se), indium (In), tin (Sn), antimony (Sb), tellurium (Te), tantalum (Ta), tungsten (W), or molybdenum (Mo).

[0075]

[0085] This method involves annealing the P metal stack 250 and the N metal stack 240 at a temperature of 1000°C or less to drive metal atoms from the dipole layer and increase the density of the high dielectric constant layer (not shown). In some embodiments, this method includes annealing the P metal stack 250 and the N metal stack 240 at a temperature of 950°C or less. In some embodiments, the temperature is in the range of 500°C to 1000°C, including the range of 600°C to 1000°C, the range of 700°C to 1000°C, the range of 750°C to 950°C, or the range of 800°C to 900°C.

[0076]

[0086] In one or more embodiments, the dipole layer 214 on one or more of the P metal stacks 250 or N metal stacks 240 is removed by a selective etching process. In Figure 2C, for example, the dipole layer 214 is removed from both the P metal stack 250 and the N metal stack 240 by a selective etching process.

[0077]

[0087] The etching process may be any suitable etching process known to those skilled in the art. In some embodiments, the etching process includes a wet etching process or a dry etching process. In some embodiments, the etching process includes a wet etching process. In some embodiments, the wet etching process includes a pre-washing process. In some embodiments, the pre-washing process includes using one or more ammonium hydroxide (NH4OH) or water (H2O). In some embodiments, water (H2O) is deionized water (DI). In some embodiments, the pre-washing process includes using a DI:NH4OH ratio ranging from 100:1 DI:NH4OH to 5:1 DI:NH4OH.

[0078]

[0088] In some embodiments, the pre-cleaning process includes using either SC-1 solution or SC-2 solution. In one or more embodiments, SC-1 solution includes one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In one or more embodiments, SC-2 solution includes one or more of hydrochloric acid or hydrogen peroxide. Advantageously, it has been found that using either SC-1 solution or SC-2 solution selectively etches the deposited dipole layer 214 from one of the P-metal stacks or N-metal stacks without etching any portion of the interface layer 210.

[0079] Figure 2D shows another cross-sectional view of the semiconductor substrate 202 in Figure 2C. In Figure 2D, each of the multiple nanosheet channel layers 206 is encased by an interface layer 210 and a high dielectric constant dielectric layer 212 on the interface layer 210. Figure 2D shows trenches 208 between each of the multiple nanosheet channel layers 206. In one or more embodiments, there is a gate trench 255 on at least one side of the channel 206. In Figure 2D, for example, there are gate trenches 255 on both sides of the channel 206.

[0080]

[0090] Referring to Figures 1A and 2E-2F, Method 10 includes, in step 14, forming a work function layer 220 within the channel 206 (e.g., between nanosheet channel layers 206) and inducing strain in the work function layer within the channel 206. Figures 1A, 1C, and 2E-2G show at least the “first strain induction process”.

[0081]

[0091] In Figure 2F, all sides of the channel 206 are covered. Each of the multiple nanosheet channel layers 206 contains silicon (Si). In Figure 2F, each of the multiple nanosheet channel layers 206 is encased in an interface layer 210, a high dielectric constant dielectric layer 212 on the interface layer 210, and a work function layer 220 on the high dielectric constant dielectric layer 212. In one or more embodiments, there is a gate trench 255 on at least one side of the channel 206. In the illustrated embodiment of Figure 2F, for example, there are gate trenches 255 on both sides of the channel 206.

[0082]

[0092] The work function layer 220 can be formed by any suitable process known to those skilled in the art. The work function layer 220 can be formed by any suitable process on the N metal stack 240. In one or more embodiments, forming the work function layer 220 on the P metal stack 250 includes heat treatment. The processing parameters of the heat treatment can be optimized or modified based on the specific application.

[0083]

[0093] As used herein, the term “thermal treatment” refers to deposition techniques that do not involve the use of plasma. As used herein, the term “plasma” refers to a composition having ionically charged species, uncharged neutral species, and radical species. In one or more embodiments, the ionically charged species of the plasma are neutralized by optimizing the pressure within the processing chamber. In embodiments in which the ionically charged nuclei of the plasma are neutralized, the plasma contains a higher proportion of radicals and may be referred to as a “radical-based plasma” or “radical-based process.” In some embodiments, the radical-based plasma is generated by a remote plasma source. While not intended to be theoretically binding, it is thought that a radical-based plasma generated by a remote plasma source removes the ionically charged species from the plasma, resulting in a plasma containing a higher proportion of radicals.

[0084]

[0094] Radical-based plasmas may contain any radical species. In some embodiments, radical-based plasmas contain one or more nitrogen radicals (N2*) or hydrogen radicals (H*). The composition of the mixture of nitrogen radicals (N2*) and hydrogen radicals (H*) may include any suitable ratio of nitrogen radicals (N2*) to hydrogen radicals (H*), and this ratio may be optimized or modified based on the specific application.

[0085]

[0095] In one or more embodiments, after depositing the high dielectric constant dielectric layer 212, a work function layer 220 is formed within the channel 206 (for example, within the trench 208 between the nanosheet channel layers 206). Figures 2E and 2F show the work function layer 220 formed on the high dielectric constant dielectric layer 212.

[0086]

[0096] While not intended to be theoretically binding, in one or more embodiments, the dipole may have a threshold voltage (V) required for a particular application. t If the following conditions are met, the work function layer 220 can be considered replaceable with a pure midgap metallic material having adjustable stress.

[0087]

[0097] In one or more embodiments, the method further includes forming a titanium nitride (TiN) layer in one or more of the trenches 208 of the channel 206 (e.g., the channel 206 of the P metal stack 250) before forming the work function layer 220 (not shown).

[0088]

[0098] The work function layer 220 may contain any suitable metal known to those skilled in the art. The work function layer 220 may be formed by any suitable metal-containing precursor, including but not limited to organometallic precursors and / or metal halide precursors. In one or more embodiments, the metal-containing precursor includes, but is not limited to, molybdenum (Mo), tungsten (W), titanium (Ti), aluminum (Al), ruthenium (Ru), iridium (Ir), tantalum (Ta), niobium (Nb), vanadium (V), or rhenium (Re).

[0089]

[0099] In some embodiments, the work function layer 220 includes one or more P metals or N metals. In one or more embodiments, the work function layer 220 includes a P metal. In embodiments where the work function layer 220 includes a P metal, the P metal includes, for example, any suitable highly electronegative metal nitride material. In embodiments where the work function layer 220 includes a P metal, the P metal includes one or more molybdenum (Mo), molybdenum nitride (MoN), molybdenum oxynitride (MoON), or molybdenum carbonitride (MoCN).

[0090]

[0100] In some embodiments, the work function layer 220 includes an N metal. In embodiments where the work function layer 220 includes an N metal, the N metal includes, for example, any suitable electrocathode refractive metal. In some embodiments, the N metal includes titanium aluminum nitride (TiAlN).

[0091]

[0101] The work function layer 220 may have any suitable thickness. In one or more embodiments, the work function layer has a thickness in the range of 10 Å to 30 Å. In one or more embodiments, the work function layer has a thickness of 30 Å or less, or 20 Å or less.

[0092]

[0102] The P metal stack 250 and / or the N metal stack 240 may contain any suitable P metal, such as the P metal described herein. The P metal stack 250 and / or the N metal stack 240 may contain any suitable N metal, such as the N metal described herein.

[0093]

[0103] In one or more embodiments, the method further includes forming a titanium nitride (TiN) layer, a TiN layer having an amorphous silicon (a-Si) capping layer on top, or a titanium silicon nitride (TiSiN) layer in the trench 208 of the channel 206, for example in the channel 206 of the N metal stack 240, before forming a work function layer 220 (not shown).

[0094]

[0104] In one or more embodiments, the work function layer 220 on the N metal stack includes titanium aluminum nitride (TiAlN). In one or more embodiments, the work function layer 220 on the N metal stack includes titanium aluminum nitride (TiAlN) formed by heat treatment.

[0095]

[0105] It is advantageously known that the work function materials described in this book induce stress in the transistor channels 206 of the electronic device 200. As described herein, the strain of the work function layer from the “first strain induction treatment” is a high tensile stress. Advantageously, when the work function layer 220 is deposited within the channel 206 (e.g., between the nanosheet channel layers 206 in each trench 208) and strain of the work function layer is induced within the channel 206, each of the P metal stack 250 and N metal stack 240 independently has compressive and tensile stresses in the range of 1 gigapascal (GPa) to 2 GPa.

[0096]

[0106] Referring to Figures 1B and 2F, Method 50, in step 54, comprises forming a gate metal packing layer 260 on each of the P metal stack 250 and the N metal stack 240, and inducing strain in the gate metal packing layer within the channel 206, wherein the gate metal packing layer 260 covers at least one side of each of the P metal stack and the N metal stack and fills the gate trench 255.

[0097]

[0107] Referring to Figures 1C and 2G, Method 100 includes, in step 130, forming a gate metal packing layer 260 on the channel 206 (e.g., on each channel 206 of the P metal stack 250 and the N metal stack 240) and inducing strain in the gate metal packing layer within the channel 206. In one or more embodiments, the gate metal packing layer 260 covers at least one side of each of the channel 206 (e.g., each channel 206 of the P metal stack 250 and the N metal stack 240). In one or more embodiments, as shown in Figure 2G, for example, the gate metal packing layer 260 fills the gate trenches 255 on both sides of the channel 206. In some embodiments, the process of step 54 of Method 50 is the same as the process of step 130 of Method 100. Figures 1B, 1C, and 2G show at least the “second strain-inducing treatment.” As described herein, the strain in the gate metal-filled layer from the “second strain-inducing treatment” is compressive stress.

[0098]

[0108] In Figure 2G, all sides of the channel 206 are covered. Each of the multiple nanosheet channel layers 206 contains silicon (Si). In Figure 2G, each of the multiple nanosheet channel layers 206 is surrounded by an interface layer 210, a high dielectric constant dielectric layer 212 on the interface layer 210, a work function layer 220 on the high dielectric constant dielectric layer 212, and a gate metal packing layer 260 on the work function layer 220.

[0099]

[0109] In the embodiment shown in Figure 2G, for example, the gate metal packing layer 260 covers all sides of the channel 206 and fills the gate trenches 255 on both sides of the channel 206. In one or more embodiments, the gate metal packing layer 260 covers all sides of each of the P metal stacks 250 and N metal stacks 240. In one or more embodiments, the gate metal packing layer 260 is a continuous layer.

[0100]

[0110] In one or more embodiments, forming the gate metal packing layer 260 includes a post-treatment process or a plasma atomic layer deposition (PEALD) process following the heat treatment (as described herein).

[0101]

[0111] In embodiments in which forming the gate metal packed layer 260 involves a heat treatment and subsequent post-treatment, the post-treatment includes exposing the heat-deposited gate metal packed layer 260 to a plasma containing one or more of argon (Ar) or hydrogen (H2) at a plasma output ranging from 150 W to 800 W to form a treated gate metal packed layer. In some embodiments, the Ar plasma is flowed at a rate ranging from 0.5 standard liters / min (slm) to 6 slm. In some embodiments, the H2 plasma is flowed at a rate ranging from 6 slm to 10 slm.

[0102]

[0112] In one or more embodiments, the gate metal packing layer 260 is formed at a temperature in the range of 150°C to 500°C.

[0103]

[0113] In one or more embodiments, forming the gate metal packed layer 260 involves exposing the semiconductor substrate 202 to one or more molybdenum-containing precursors or tungsten-containing precursors. The molybdenum-containing precursor and / or tungsten-containing precursor may include any suitable precursor. In one or more embodiments, the molybdenum-containing precursor includes one or more molybdenum pentachloride (MoCl5) or molybdenum dichloride (MoO2Cl2). In one or more embodiments, the tungsten-containing precursor includes tungsten pentachloride (WCl5), tungsten hexafluoride (WF6), or tungsten oxychloride (WO2Cl2). x Cl y ) includes.

[0104]

[0114] Advantageously, when the gate metal packing layer 260 is formed, strain is induced in the gate metal packing layer within the channel 206. The P metal stack 250 advantageously has compressive stress (e.g., negative GPa) when the gate metal packing layer 260 is formed.

[0105]

[0115] In embodiments in which the gate metal packing layer 260 is formed by the method described herein, advantageously, the electronic device 200 satisfies the compressive stress requirements for a PMOS transistor and the tensile stress requirements for an NMOS transistor. In one or more embodiments, the P metal stack 250 has a compressive stress in the range of -0.1 GPa to -3.1 GPa, and the N metal stack 240 has a tensile stress of 2 GPa or more.

[0106]

[0116] In one or more embodiments, the compressive stress value of the P metal stack 250 varies based on the thickness of the gate metal packing layer 260. While not intended to be theoretically binding, it is assumed that the compressive stress of the P metal stack 250 increases as the thickness of the gate metal packing layer 260 increases.

[0107]

[0117] The gate metal packing layer 260 can be deposited to any appropriate thickness. In one or more embodiments, the gate metal packing layer 260 is deposited to a thickness of 30 Å or more, 50 Å or more, 100 Å or more, 150 Å or more, or 200 Å or more.

[0108]

[0118] In some embodiments, when the gate metal packing layer 260 is deposited by a heat treatment using MoO2Cl2, the P metal stack 250 has a compressive stress of -1.7 GPa at 35 Å and a compressive stress of -0.6 GPa at 150 Å.

[0109]

[0119] In some embodiments, the P metal stack 250 has a compressive stress of -0.8 GPa at 35 Å and a compressive stress of -0.1 GPa at 150 Å when the gate metal packing layer 260 is deposited by heat treatment using MoCl5.

[0110]

[0120] In some embodiments, when the gate metal packing layer 260 is deposited by a PEALD process using MoO2Cl2, the P metal stack 250 has a compressive stress of -1.8 GPa at 30 Å and a compressive stress of -1.0 GPa at 100 Å.

[0111]

[0121] In some embodiments, the P metal stack 250 has a compressive stress of -0.96 GPa at approximately 42 Å and a compressive stress of -0.86 GPa at 90 Å when the gate metal packed layer 260 is deposited by a PEALD process using MoCl5.

[0112]

[0122] In one or more embodiments, Method 100 includes forming a work function layer 220 ("first strain induction treatment") by depositing a work function layer 220 to a thickness of 30 Å or less, 20 Å or less, or 10 Å or less by heat treatment, and forming a gate metal filling layer 260 ("second strain induction treatment") by forming a gate metal filling layer 260 to a thickness of 30 Å or more, 50 Å to 100 Å or more, 150 Å or more, or 200 Å or more by the PEALD process.

[0113]

[0123] Further aspects of this disclosure relate to methods that are part of a gap-filling process. In some embodiments, such as Method 100, a work function layer 220 is deposited on all sides of the channel 206. In one or more embodiments, the work function layer 220 acts as a liner, and a gate metal packing layer 260 is deposited on the work function layer 220. In one or more embodiments, the work function layer 220 is deposited by heat treatment to a thickness of 30 Å or less, 20 Å or less, or 10 Å or less, and the gate metal packing layer 260 is deposited by PEALD treatment to a thickness of 30 Å or more, 50 Å or more, 100 Å or more, 150 Å or more, or 200 Å or more. Advantageously, it has been found that depositing the work function layer 220, as in Method 100, and subsequently depositing the gate metal packing layer 260 on the work function layer 220, advantageously induces compressive and tensile stresses that satisfy the compressive stress requirements of a PMOS transistor and the tensile stress requirements of an NMOS transistor, respectively.

[0114]

[0124] Additional embodiments of the present disclosure, as shown in Figure 3, relate to a processing tool (i.e., a cluster tool) 900 for forming the logic / memory devices and methods described. The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are positioned within the central transfer stations 921, 931 and are configured to move robot blades and wafers to each of the multiple sides.

[0115]

[0125] The cluster tool 900 comprises several processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also called processing stations, connected to central transfer stations 921 and 931. The various processing chambers provide separate processing areas isolated from adjacent processing stations. The processing chambers can be any suitable chamber, including, but are not limited to, pre-cleaning chambers, buffer chambers, transfer spaces, wafer orienters / degassing chambers, cryogenic cooling chambers, deposition chambers, annealing chambers, etching chambers, heat treatment chambers, plasma oxidation chambers, plasma nitriding chambers, atomic layer deposition (ALD) chambers, and plasma ALD (PEALD) chambers.

[0116]

[0126] In one or more embodiments, the ALD chamber includes a single chamber for depositing an interface layer on the upper surface of a channel, depositing a high dielectric constant dielectric layer on the interface layer, and depositing a dipole layer of a predetermined thickness on the high dielectric constant dielectric layer so as not to cause vacuum breakdown between steps.

[0117]

[0127] In one or more embodiments, the ALD chamber may include a single chamber for each of the following: depositing an interface layer on the upper surface of the channel; depositing a high dielectric constant layer on the interface layer; and depositing a dipole layer of a predetermined thickness on the high dielectric constant layer such that a vacuum break occurs during at least one of the steps.

[0118]

[0128] In one or more embodiments, a heat treatment chamber is used to form a work function layer 220. In one or more embodiments, a PEALD chamber is used to form a gate metal packed layer 260. In one or more embodiments, the heat treatment chamber and the PEALD chamber are connected so as not to cause vacuum breakage between their respective operations.

[0119]

[0129] In one or more embodiments, the heat treatment chamber and the PEALD chamber are separated such that a vacuum break exists between their respective operations.

[0120]

[0130] The specific arrangement of the processing chamber and its components can be modified depending on the cluster tool and should not be considered to limit the scope of this disclosure.

[0121]

[0131] In one or more embodiments, the cluster tool 900 includes a silicon dioxide (SiO2) chamber for depositing silicon dioxide (SiO2). The silicon dioxide (SiO2) deposition chamber in some embodiments includes an atomic layer deposition chamber, a plasma-enhanced atomic layer deposition chamber, or a space atomic layer deposition chamber. In one or more embodiments, the cluster tool 900 includes a pre-cleaning chamber connected to a central transfer station.

[0122]

[0132] In the embodiment shown in Figure 3, the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of the factory interface 950. The loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, but those skilled in the art will understand that this is merely a typical example of one possible configuration.

[0123]

[0133] The size and shape of the loading chamber 954 and the unloading chamber 956 may vary, for example, depending on the substrates being processed within the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette in which multiple wafers are arranged within the cassette.

[0124]

[0134] Robot 952 is located within the factory interface 950 and can move between the loading chamber 954 and the unloading chamber 956. Robot 952 can transfer wafers from a cassette in the loading chamber 954 to the load lock chamber 960 through the factory interface 950. Robot 952 can also transfer wafers from the load lock chamber 962 to a cassette in the unloading chamber 956 through the factory interface 950. As will be understood by those skilled in the art, the factory interface 950 may have multiple robots 952. For example, the factory interface 950 may have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960, and a second robot that transfers wafers between the load lock chamber 962 and the unloading chamber 956.

[0125]

[0135] The cluster tool 900 shown in Figure 3 has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 through load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 in which at least one robot 925 is located. The robot 925 is also called a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally located relative to the load lock chambers 960, 962, processing chambers 902, 904, 916, 918, and buffer chambers 922, 924. In some embodiments, the robot 925 is a multi-arm robot capable of independently moving multiple wafers at once. In one or more embodiments, the first transfer chamber 921 comprises two or more robotic wafer transfer mechanisms. The robot 925 within the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Each wafer is supported on a wafer transport blade located at the distal end of the first robotic mechanism.

[0126]

[0136] After processing the wafer in the first section 920, the wafer may pass through a pass-through chamber to the second section 930. For example, chambers 922, 924 may be unidirectional or bidirectional pass-through chambers. Pass-through chambers 922, 924 can be used, for example, to cool the wafer to a low temperature before processing in the second section 930, or to allow wafer cooling or post-processing before returning to the first section 920.

[0127]

[0137] The system controller 990 communicates with the first robot 925, the second robot 935, the first set of processing chambers 902, 904, 916, 918, and the second set of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 may be a computer including a central processing unit, memory, appropriate circuitry, and storage.

[0128]

[0138] The processing may generally be stored as a software routine in the memory of the system controller 990, and when executed by the processor, causes the processing chamber to execute the processing of the disclosure. The software routine may also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of this disclosure as described herein (e.g., methods 10, 50, and / or 100) may be executed in hardware. Thus, the processing may be implemented in software and executed using a computer system in hardware (e.g., application-specific integrated circuits, or other types of hardware implementations), or in a combination of software and hardware. When executed by the processor, the software routine converts a general-purpose computer into a dedicated computer (controller) that controls the chamber operation so that the process can be executed.

[0129]

[0139] Embodiments of this disclosure relate to non-temporary computer-readable media. In one or more embodiments, the non-temporary computer-readable media includes instructions, when executed by a controller of a processing chamber, that cause the processing chamber to perform any of the steps described herein. In one or more embodiments, the controller causes the processing chamber to perform the steps of Method 10. In one or more embodiments, the controller causes the processing chamber to perform the steps of Method 50. In one or more embodiments, the controller causes the processing chamber to perform the steps of Method 100.

[0130]

[0140] In one or more embodiments, the processing tool 900 includes: a central transfer station 921, 931 having at least one robot 925, 935 configured to move wafers; one or more rapid heat treatment (RTP) stations, separated plasma oxidation (DPO), or separated plasma nitriding (DPN) stations connected to the central transfer station; an atomic layer deposition (ALD) station connected to the central transfer station; a heat treatment heat station; a plasma amplification ALD (PEALD) station; an optional pre-cleaning station connected to the central transfer station; and at least one controller connected to one or more of the central transfer station, RTP station, DPO station, DPN station, ALD station, or optional pre-cleaning station. In one or more embodiments, at least one controller has at least one configuration selected from: a configuration for moving wafers between stations using a robot; a configuration for performing rapid heat treatment; a configuration for performing separation plasma treatment; a configuration for controlling the flow of oxidizing gas to an RTP station or DPO station; a configuration for controlling the flow of nitriding gas to an RTP station or DPN station; a configuration for depositing silicon oxide films by atomic layer deposition; a configuration for pre-cleaning wafers.

[0131]

[0141] Spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used here to describe the relationship between one element or feature shown in a drawing and another, for the sake of clarity. It will be understood that spatially relative terms are intended to encompass different orientations of a device in use or operation, in addition to the orientation shown in the drawing. Therefore, for example, if a device in a drawing is upside down, an element described as “below” or “beneath” another element or feature will be located “above” that other element or feature. Thus, the exemplary term “below” may encompass both above and below directions. Devices may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptions used in this document should be interpreted accordingly.

[0132]

[0142] In the context of describing the materials and methods discussed herein (particularly in the context of the following claims), the terms “a,” “an,” and “the,” as well as similar references, should be interpreted as covering both singular and plural forms, unless otherwise stated herein or unless the context clearly contradicts this interpretation. The enumeration of numerical ranges in this specification is intended merely as abbreviation for referring individually to each distinct value that falls within that range, unless otherwise noted herein, and each distinct value is incorporated into the specification as if it were individually enumerated herein. All methods described herein may be performed in any appropriate order unless otherwise indicated herein or unless it is clearly inconsistent with the context. Any and all examples or illustrative language provided herein (e.g., "such as") is intended merely to better describe the materials and methods and does not limit their scope unless otherwise specified in the claims. Nothing in this specification should be construed to indicate that any element not specified in the claims is essential to the implementation of the disclosed materials and methods.

[0133]

[0143] Throughout this document, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiment” means that a particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this disclosure. Therefore, expressions such as “in one or more embodiments,” “in a particular embodiment,” “in one embodiment,” or “in an embodiment” in various parts of this specification do not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, particular features, structures, materials, or properties are combined in any and appropriate manner.

[0134]

[0144] While the disclosures in this book are described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and uses of the disclosure. It will be apparent to those skilled in the art that various modifications and changes can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to include modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for manufacturing electronic devices, The method involves forming a P-metal stack and an N-metal stack on a semiconductor substrate, wherein each of the P-metal stack and the N-metal stack is formed on the upper surface of a channel located between the source and drain on the semiconductor substrate, and each of the P-metal stack and the N-metal stack includes a nanosheet channel layer and trenches between each nanosheet channel layer. A method comprising forming a work function layer in the channels between the nanosheet channel layers in each trench, and inducing work function layer strain in the channels, wherein each of the P metal stack and the N metal stack independently has compressive stress and tensile stress in the range of 1 gigapascal (GPa) to 2 GPa.

2. The method according to claim 1, wherein forming each of the P metal stack and the N metal stack comprises depositing an interface layer on the upper surface of the channel, depositing a high dielectric constant layer on the interface layer, and depositing a dipole layer on the high dielectric constant layer.

3. The method according to claim 2, wherein after depositing the high dielectric constant dielectric layer, the work function layer is formed in the channels between the nanosheet channel layers.

4. The method according to claim 1, further comprising forming a titanium nitride (TiN) layer in one or more of the trenches of the P metal stack before forming the work function layer.

5. The method according to claim 1, wherein forming the work function layer on the P metal stack includes heat treatment.

6. The method according to claim 5, wherein the work function layer includes one or more of molybdenum (Mo), molybdenum nitride (MoN), molybdenum oxynitride (MoON), or molybdenum carbonitride (MoCN).

7. The method according to claim 1, further comprising forming a titanium nitride (TiN) layer, a TiN layer having an amorphous silicon (a-Si) capping layer, or a titanium silicon nitride (TiSiN) layer in the trench of the N metal stack before forming the work function layer.

8. The method according to claim 1, wherein forming the work function layer on the N metal stack includes titanium aluminum nitride (TiAlN) formed by heat treatment.

9. A method for manufacturing electronic devices, The process involves forming a P-metal stack and an N-metal stack on a semiconductor substrate, Each of the P-metal stack and N-metal stack is formed on the upper surface of the channel located between the source and drain on the semiconductor substrate. Each of the P-metal stack and N-metal stack includes a nanosheet channel layer and trenches between each nanosheet channel layer. Each of the P metal stack and the N metal stack has at least one side that defines a gate trench, The method involves forming a gate metal packed layer on each of the P metal stack and the N metal stack, and inducing strain in the gate metal packed layer within the channel. The gate metal packing layer covers at least one side of each of the P metal stack and the N metal stack, filling the gate trench. The P metal stack has a compressive stress in the range of -0.1 GPa to -3.1 GPa. A method comprising the N metal stack having a tensile stress of 2 GPa or more.

10. The method according to claim 9, wherein forming the gate metal packed layer includes a post-treatment process or plasma atomic layer deposition (PEALD) treatment following a heat treatment.

11. The post-processing step involves heating the thermally deposited gate metal packing layer with argon (Ar) or hydrogen (H ２ The method according to claim 10, comprising exposing the treated gate metal packed layer to a plasma containing one or more of the following at a plasma output in the range of 150 W to 800 W.

12. The method according to claim 11, comprising flowing the Ar plasma in a range of 0.5 standard liters / minute (slm) to 6 slm.

13. The aforementioned H ２ The method according to claim 11, comprising flowing plasma in a range of 6 slm to 10 slm.

14. The method according to claim 10, wherein forming the gate metal packed layer includes exposing the semiconductor substrate to one or more molybdenum-containing precursors or tungsten-containing precursors.

15. The molybdenum-containing precursor is molybdenum pentachloride (MoCl ５ ) or molybdenum chloride dioxide (MoO ２ Cl ２ The method according to claim 14, comprising one or more of the following.

16. The gate metal filling layer is MoO ２ Cl ２ The method according to claim 14, wherein when deposited by the heat treatment using, the P metal stack has a compressive stress of -1.7 GPa at 35 Å and a compressive stress of -0.6 GPa at 150 Å.

17. The gate metal filling layer is MoCl ５ The method according to claim 14, wherein when deposited by the heat treatment using, the P metal stack has a compressive stress of -0.8 GPa at 35 Å and a compressive stress of -0.1 GPa at 150 Å.

18. When the gate metal fill layer is deposited by the PEALD process using MoO ２ Cl ２ the P metal stack has a compressive stress of -1.8 GPa at 30 Å and a compressive stress of -1.0 GPa at 100 Å, the method of claim 14.

19. The gate metal filling layer is MoCl ５ The method according to claim 14, wherein when deposited by the PEALD process using the P metal stack, the P metal stack has a compressive stress of -0.96 GPa at about 42 Å and a compressive stress of -0.86 GPa at 90 Å.

20. A method for manufacturing electronic devices, The process involves forming a P-metal stack and an N-metal stack on a semiconductor substrate, Each of the P-metal stack and N-metal stack is formed on the upper surface of the channel located between the source and drain on the semiconductor substrate. Each of the P-metal stack and N-metal stack includes a nanosheet channel layer and trenches between each nanosheet channel layer. Each of the P metal stack and the N metal stack has at least one side that defines a gate trench, The method involves forming a work function layer within the channels between each of the nanosheet channel layers in the trench, and inducing work function layer strain within the channels. The formation of the work function layer includes heat treatment, The method involves forming a gate metal packed layer on each of the P metal stack and the N metal stack, and inducing strain in the gate metal packed layer within the channel. The gate metal packing layer covers at least one side of each of the P metal stack and the N metal stack, filling the gate trench. The formation of the gate metal packed layer includes plasma atomic layer deposition (PEALD) processing, and the N metal stack has a tensile stress of 2 GPa or more. A method comprising the P metal stack having a compressive stress in the range of -0.1 GPa to -3.1 GPa.

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