Method for forming a microelectronic device including a stepped structure and related microelectronic devices

Abstract

A method for forming a microelectronic device is provided, comprising the step of forming a pre-stack structure on a source structure. The pre-stack structure comprises a vertically alternating sequence of insulating material and sacrificial material arranged in a pre-layer. The method further comprises the steps of forming a staircase structure having steps including at least some of the edges of the pre-layer of the pre-stack structure; forming an implantation region within an exposed portion of sacrificial material in the steps of the staircase structure; forming an opening that reaches the source structure through the pre-stack structure and extends within a horizontal region of the staircase structure; replacing a portion of the sacrificial material with a conductive structure; forming a strap structure containing conductive material in a location vacant by the implantation region and adjacent laterally to the conductive structure in the steps of the staircase structure; and forming a conductive contact within the opening. Additional methods and microelectronic devices are also disclosed.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of the filing date of U.S. Patent Application No. 18 / 621,738, filed Mar. 29, 2024, and further claims the benefit of U.S. Provisional Patent Application No. 63 / 499,306, filed May 1, 2023, under 35 U.S.C. § 119(e). The entire disclosure of each is incorporated herein by reference in its entirety.

[0002] In various embodiments, the present disclosure generally relates to the field of design and manufacture of microelectronic devices. More specifically, the present disclosure relates to methods of forming microelectronic devices (e.g., memory devices such as 3D NAND memory devices) including a stepped structure and related microelectronic devices.

Background Art

[0003] An ongoing goal in the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, including non - volatile memory devices such as NAND - type flash memory devices. One way to increase the memory density in non - volatile memory devices is to utilize a vertical memory array (also referred to as a “three - dimensional (3D) memory array”) architecture. Conventional vertical memory arrays include vertical memory strings that extend through openings in one or more conductive stack structures including layers of conductive and insulating structures. Each vertical memory string can be configured such that a plurality of memory cells stacked vertically are connected in series and at least one select device is coupled in series. Such a configuration allows for more switching devices (e.g., transistors) to be placed per unit die area (i.e., the length and width of the active surface) by building the array upward (e.g., vertically) on the die compared to a conventional planar (e.g., two - dimensional) transistor array structure.

[0004] A vertical memory array architecture generally involves electrical connections between the conductive structures of the layers of the memory device's conductive stack structure and access lines (e.g., word lines), allowing for the individual selection of memory cells in the vertical memory array for write, read, or erase operations. One way to form such electrical connections is to create a so-called "staircase" or "step" structure at the edges (e.g., horizontal edges) of the layers of the memory device's conductive stack structure. This staircase structure includes multiple "steps" that define contact areas for the conductive structures, and by placing conductive contact structures on top of these steps, electrical access to the conductive structures can be provided.

[0005] With advancements in vertical memory array technology, higher memory density is achieved by forming stacks containing more layers of conductive structures, resulting in the formation of additional stepped structures and / or additional steps within individual stepped structures. As the height of the stack increases to accommodate more memory cells within the vertical memory array, these stacks may become more susceptible to tipping or collapse during various process steps. For example, during the replacement gate process, when removing or after removing some of the layers that are replaced by conductive structures, the layers of the stack may collapse. If part of the stack collapses, the reliability of the vertical memory string may be reduced.

[0006] Furthermore, as the dimensions and spacing of conductive features decrease, multilayer wiring structures are used within memory devices to electrically connect the conductive features to each other. Memory devices have wiring structures at different layer levels, and these wiring structures are formed from electrically conductive materials, providing conductive paths within the memory device. As the dimensions and spacing of conductive features decrease further, parasitic (i.e., stray) capacitance between adjacent conductive features within the memory device increases. This increase in parasitic capacitance leads to increased power consumption and operational delays in the memory device. [Overview of the project]

[0007] Embodiments described herein include methods for forming microelectronic devices including a stepped structure and related microelectronic devices. In one embodiment described herein, the method for forming a microelectronic device includes the step of forming a pre-stack structure on a source structure, the pre-stack structure including a vertically alternating sequence of insulating material and sacrificial material arranged as pre-layers. The method further includes the steps of forming a stepped structure having steps including the ends of at least some of the pre-layers of the pre-stack structure, forming implant regions within the exposed portions of sacrificial material in the steps of the stepped structure, forming openings in the pre-stack structure that extend to the source structure in the horizontal region of the stepped structure, replacing some of the sacrificial material with a conductive structure, forming strap structures containing conductive material in the steps of the stepped structure adjacent laterally to the conductive structure and at a position left open by the implant regions, and forming conductive contacts containing conductive material in the openings.

[0008] In other embodiments described herein, a method for forming a microelectronic device includes the steps of forming a stack structure on a source layer comprising one or more conductive structures, wherein the stack structure comprises layers comprising an insulating material and additional insulating materials perpendicularly adjacent thereto. The method further includes the steps of forming a stepped structure within the stack structure having stepped portions including the lateral edges of the layers of the stack structure; forming a sacrificial material comprising at least one of boron and carbon within the exposed portions of the uppermost additional insulating material in the stepped portions of the stepped structure; forming openings within the stack structure and within the horizontal region of the stepped structure that penetrate the sacrificial material and extend to the source layer; removing the additional insulating material to form cell openings; removing the sacrificial material to form lateral openings communicating with the openings; forming conductive material within the cell openings and lateral openings; and forming conductive contacts within the openings and electrically coupling the conductive material to one or more conductive structures in the source layer via the conductive contacts.

[0009] In yet another embodiment described herein, the microelectronic device comprises a stack structure located above a source layer, the stack structure comprising layers in which conductive and insulating structures are alternately stacked vertically. The stack structure also comprises a stepped structure, the stepped structure having steps including the lateral edges of the layers. Furthermore, a conductive contact is provided within the horizontal region of the stepped structure, the conductive contact extending vertically through the stack structure to the source layer. Furthermore, a strap structure is provided within the horizontal region of the steps of the stepped structure, each strap structure directly interposed laterally between the conductive structure and the conductive contact of the layers of the stack structure, the strap structure being electrically coupled to a conductive feature in the source layer via the conductive contact. [Brief explanation of the drawing]

[0010] [Figure 1A] This is a simplified partial top view showing various steps of a method for forming a microelectronic device according to the embodiments of this disclosure. [Figure 1B] This is a simplified partial cross-sectional view showing various steps in a method for forming a microelectronic device according to an embodiment of the present disclosure. [Figure 1C] This is a simplified partial cross-sectional view showing various steps in a method for forming a microelectronic device according to an embodiment of the present disclosure. [Figure 1D] This is a simplified partial cross-sectional view showing various steps in a method for forming a microelectronic device according to an embodiment of the present disclosure. [Figure 1E] This is a simplified partial top view showing various steps of a method for forming a microelectronic device according to the embodiments of this disclosure. [Figure 1F] This is a simplified partial cross-sectional view showing various steps in a method for forming a microelectronic device according to an embodiment of the present disclosure. [Figure 1G] This is a simplified partial cross-sectional view showing various steps in a method for forming a microelectronic device according to an embodiment of the present disclosure. [Figure 1H]This is a simplified partial top view showing various steps of a method for forming a microelectronic device according to the embodiments of this disclosure. [Figure 1I] This is a simplified partial cross-sectional view showing various steps in a method for forming a microelectronic device according to an embodiment of the present disclosure. [Figure 2A] This is a simplified partial cross-sectional view showing a method for forming a microelectronic device according to another embodiment of the present disclosure. [Figure 2B] This is a simplified partial cross-sectional view showing a method for forming a microelectronic device according to another embodiment of the present disclosure. [Figure 2C] This is a simplified partial cross-sectional view showing a method for forming a microelectronic device according to another embodiment of the present disclosure. [Figure 2D] This is a simplified partial cross-sectional view showing a method for forming a microelectronic device according to another embodiment of the present disclosure. [Figure 3] This is a simplified partially cutaway perspective view of a microelectronic device according to an embodiment of the present disclosure. [Figure 4] This is a schematic block diagram of an electronic system according to an embodiment of the present disclosure. [Figure 5] This is a schematic block diagram of a processor-based system according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0011] The following description provides specific details, such as material composition, shape, and dimensions, to fully illustrate the embodiments of the disclosure. However, those skilled in the art should understand that the embodiments of the disclosure can be implemented without these specific details. In fact, the embodiments of the disclosure may be implemented in combination with conventional microelectronic device manufacturing techniques used in the industry. Furthermore, the following description does not constitute a complete process flow in the manufacture of microelectronic devices (e.g., memory devices such as NAND flash memory devices). The structures described below do not constitute complete microelectronic devices, and only the process operations and structures necessary to understand the embodiments of the disclosure are described in detail. Additional steps to form a complete microelectronic device from these structures can be carried out by conventional manufacturing techniques.

[0012] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are based on the main plane of the structure and are not necessarily defined by the Earth’s gravitational field. “Horizontal” or “lateral” means a direction substantially parallel to the main plane of the structure, and “vertical” or “longitudinal” means a direction substantially perpendicular to the main plane of the structure. The main plane of a structure is defined by a surface that has a relatively large area compared to the other faces of the structure. Referring to the drawings, “horizontal” or “lateral” may be perpendicular to the indicated “Z” axis and parallel to the indicated “X” axis and / or “Y” axis. Similarly, “vertical” or “longitudinal” may be parallel to the indicated “Z” axis and perpendicular to the indicated “X” and “Y” axes.

[0013] As used herein, the term “substantially” means, and includes, the extent to which a person skilled in the art can understand that a particular parameter, characteristic, or condition is met within an acceptable tolerance. For example, depending on the parameter, characteristic, or condition, “substantially met” may mean that the parameter, characteristic, or condition is met by at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or 100.0%.

[0014] As used herein, the terms “about” or “approximately” mean that a numerical value relating to a particular parameter includes both the numerical value itself and a variation that a person skilled in the art would understand to be within an acceptable range for that parameter. For example, “about” or “approximately” with respect to a particular numerical value may mean including additional values ​​within a range of 90.0% to 108.0%, such as 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1% of that numerical value.

[0015] As used herein, the "conductive material" means a material having electrical conductivity and includes those, for example, one or more of metals (tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), one or more of alloys (for example, Co-based alloys, Fe-based alloys, Ni-based alloys, Fe-Ni-based alloys, Co-Ni-based alloys, Fe-Co-based alloys, Co-Ni-Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel), one or more of conductive metal-containing materials (for example, conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), or one or more of semiconductor materials doped with conductivity (for example, polysilicon doped with conductivity, germanium (Ge) doped with conductivity, silicon germanium (SiGe) doped with conductivity). Further, the "conductive structure" means a structure formed from or including the conductive material and includes those.

[0016] As used herein, "insulative material" means a material that is electrically insulating, and includes, for example, one or more dielectric oxide materials (such as silicon oxide (SiOx), silicate glass phosphate, silicate glass borate, silicate glass borate, silicate glass fluoride, aluminum oxide (AlOx), hafnium oxide (HfOx), niobium oxide (NbOx), titanium oxide (TiOx), zirconium oxide (ZrOx), tantalum oxide (TaOx), magnesium oxide (MgOx), etc.), one or more dielectric nitride materials (e.g., silicon nitride (SiNy)), one or more dielectric oxynitride materials (e.g., silicon oxynitride (SiOxNy)), and one or more dielectric carbonate nitride materials (e.g., silicon carbonate nitride (SiOxCzNy)). The chemical formulas containing "x," "y," and "z" shown herein (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCzNy) represent materials containing, on average, "x" other elements, "y" other elements, and (where applicable) "z" further elements for every one atom of a given element (e.g., Si, Al, Hf, Nb, Ti). Since these chemical formulas do not represent the exact chemical structure but rather the relative atomic ratios, insulating materials may contain one or more stoichiometric compounds and / or one or more non-stoichiometric compounds. Furthermore, the values ​​of "x," "y," and "z" (where applicable) may be integers or non-integers. As used herein, "non-stoichiometric compounds" refer to and include chemical compounds whose elemental composition cannot be expressed in clear natural number ratios and which violate the law of constant composition. Additionally, "insulative structure" refers to and includes structures made of or formed with insulating materials.

[0017] As used herein, the term "sacrificial," when used with respect to a material or structure, means a material, structure, or a portion thereof that is formed during a manufacturing process but at least partially (e.g., substantially all) of which is removed before the completion of the manufacturing process, and includes the same.

[0018] Figures 1A - 1I are simplified partial top views (Figures 1A, 1E, and 1H) and simplified partial cross-sectional views (Figures 1B - 1D, 1F, 1G, and 1I) showing various process steps of a method of forming a microelectronic device (e.g., a memory device such as a three-dimensional (3D) NAND flash memory device) according to an embodiment of the present disclosure. Figure 1H shows an enlarged portion of a top view of a part of Figure 1G, and Figure 1I shows an enlarged portion of a cross-sectional view of box I in Figure 1G. Based on the following description, it will be readily understood by those skilled in the art that the methods and structures described herein, with reference to Figures 1A - 1I, can be used in the formation and configuration of various devices and electronic systems. The method of the present disclosure can be applied when it is desired to form a microelectronic device.

[0019] Referring to Figure 1A, the microelectronic device structure 100 may be formed to include a preliminary stack structure 102 (Figure 1B). The dielectric material 116 may optionally be formed above the preliminary stack structure 102 (e.g., in the Z direction). The microelectronic device structure 100 may comprise a stepped region 105 containing one or more stepped structures 120 (Figure 1B). The microelectronic device structure 100 may also comprise an array region adjacent to the stepped region 105 in the horizontal direction (e.g., in the X direction). For example, the array region may include a memory pillar structure (e.g., a cell pillar structure) that functions as a memory cell (e.g., a NAND memory cell string), the details of which will be further explained with reference to Figure 3. Features of the array region of the microelectronic device structure 100 may be formed during (e.g., substantially simultaneously with) the formation of the corresponding features of the stepped region 105. The opening 130 may be formed to extend vertically (e.g., in the Z direction) through one or more materials located on the stepped structure 120 within the stepped region 105. The preliminary stack structure 102 of the stepped region 105 will be described below in detail, along with additional components (e.g., structures, features). Figure 1B is a simplified partial cross-sectional view of the microelectronic device structure 100 along line BB shown in Figure 1A. Not all features shown in either Figure 1A or Figure 1B are shown in the other, in order to make the drawings and related descriptions clear and easy to understand.

[0020] Referring to Figure 1B, the preliminary stack structure 102 may be formed to include a sequence of insulating structures 104 and additional insulating structures 106 arranged alternately in the vertical direction (e.g., the Z direction), which are arranged as layers 108. Each layer 108 of the preliminary stack structure 102 may include a configuration in which at least one insulating structure 104 is arranged perpendicularly adjacent to at least one additional insulating structure 106. The insulating structures 104 may be stacked alternately with the additional insulating structures 106. The insulating structures 104 of the preliminary stack structure 102 may be formed from or containing an insulating material. In some embodiments, the insulating structures 104 may be formed from or containing silicon dioxide (SiO2).

[0021] The additional insulating structure 106 may be formed from, or containing, an additional insulating material that is different from, and has etching selectivity to, the insulating material of the insulating structure 104. For example, each of the additional insulating structures 106 may be formed from, or containing, a dielectric nitride material (e.g., SiNy) and / or an oxynitride material (e.g., SiOxNy). In some embodiments, the additional insulating structure 106 may be formed from, or containing, Si3N4. The additional insulating structure 106 may function as a sacrificial structure in the formation of the conductive structure described later.

[0022] In some embodiments, the number of layers 108 (e.g., number of stages) of the pre-stack structure 102 may range from 32 to 256 layers. In some embodiments, the pre-stack structure 102 may include 128 layers 108. However, the disclosure is not limited thereto, and the pre-stack structure 102 may include a different number of layers 108. Furthermore, in some embodiments, the pre-stack structure 102 is located above a deck structure consisting of additional layers 108 (including insulating structures 104 and additional insulating structures 106), and the deck structure may be separated from the pre-stack structure 102 by a dielectric material such as an inter-deck insulating material.

[0023] Continuing to refer to Figure 1B, the microelectronic device structure 100 may further include a source layer 110 located perpendicular to the preliminary stack structure 102 (e.g., in the Z direction). The source layer 110 may include, for example, a first conductive material 112 and a second conductive material 114. In some embodiments, the first conductive material 112 may include conductively doped silicon. In some such embodiments, the second conductive material 114 may be formed from or comprising one or more of the following materials: a metallic silicide material (e.g., tungsten silicide (WSix)), a metallic nitride material (e.g., tungsten nitride), and a metallic silicon nitride material (e.g., tungsten silicon nitride (WSixNy)). In some embodiments, the second conductive material 114 may include tungsten silicide.

[0024] The dielectric material 116, which may function as a masking material, may be positioned perpendicularly (e.g., in the Z direction) above the insulating structure 104 of the preliminary stack structure 102 and the top layer 108 of the additional insulating structure 106. The dielectric material 116 may include one or more of the materials described above with respect to the insulating structure 104 (e.g., SiO2).

[0025] In some embodiments, the source layer 110 may be formed to include one or more source structures 118 (e.g., source plates, source lines) extending horizontally within the horizontal region of the stepped region 105. The source structures 118 may be operationally associated with memory cell strings extending vertically within the memory array region of the microelectronic device structure 100, as described later. The source structures 118 may be formed from, or including, a first conductive material 112 and a second conductive material 114, and may be electrically isolated by an insulating material 119 from other parts of the first conductive material 112 and the second conductive material 114 (e.g., other parts used as conductive wiring structures 117 and / or conductive pad structures).

[0026] As shown in Figure 1B, the stepped structure 120 may be formed within the stepped region 105 of the pre-stack structure 102. The dielectric filler material 126 may be formed to fill at least one valley 124 (e.g., space, gap, groove, opening) located above the stepped structure 120 (e.g., in the Z direction). The dielectric filler material 126 may be formed from, or comprising, a material having etching selectivity for one or more of the dielectric material 116, the insulating structure 104, the additional insulating structure 106, and additional materials (e.g., additional insulating material, additional conductive material) formed in subsequent steps of the microelectronic device structure 100. In some embodiments, the dielectric filler material 126 may include an insulating material comprising one or more of the materials described above (e.g., SiO2) with respect to the insulating structure 104.

[0027] The stepped structure 120 may be formed to include steps 122 that include the ends (e.g., horizontal ends) of layers 108 of the insulating structure 104 and the additional insulating structure 106. For example, each step 122 may include the uppermost insulating structure 104a and the uppermost additional insulating structure 106a located above it. Figure 1B shows an example where two layers 108 of the insulating structure 104 and the additional insulating structure 106 correspond to one step 122 of the stepped structure 120, but the number of steps 122 of the stepped structure 120 may correspond to the number of layers 108, and one step 122 may correspond to one layer 108. The stepped structure 120 (and at least the valleys 124 defined by the stepped structure 120) may have a stepped cross-sectional shape in the ZY plane, as shown in Figure 1B. The stepped cross-sectional shape of the stepped structure 120 (and valley section 124) may be defined by the geometric configuration of the step 122 of the stepped structure 120.

[0028] To make the drawings and related explanations clear and easy to understand, Figure 1B shows only a specific number of steps 122 within the stepped structure 120. However, it should be understood that the stepped structure 120 may contain more steps 122 than those shown. For example, the stepped structure 120 may contain 8 or more steps 122, 16 or more steps 122, 32 or more steps 122, 64 or more steps 122, 128 or more steps 122, or 256 or more steps 122.

[0029] In some embodiments, the stepped structures 120 may form part of a stadium structure that includes opposing stepped structures 120, each stepped structure 120 having a step 122 defined by the horizontal end of a layer 108 of the pre-stack structure 102. In some such embodiments, a plurality of (e.g., two or more) stadium structures may be formed, each including one or more initial stepped structures, and positioned at substantially the same height (e.g., vertical position) from one another within the pre-stack structure 102. During the formation of the step 122 of the stepped structure 120, an initial stepped structure (e.g., configured substantially similarly to the stepped structure 120) may be formed at an upper position within the pre-stack structure 102 within the horizontal boundary (e.g., horizontal region) of the stepped region 105 of the microelectronic device structure 100, and conventional processes (e.g., conventional photolithography patterning processes, conventional material removal processes) and conventional process apparatus may be used for this formation. These processes and apparatus are not described in detail herein.

[0030] Subsequently, the microelectronic device structure 100 may be subjected to one or more additional material removal processes (e.g., one or more chopping processes) which increase the depth (e.g., in the Z direction) of the initial stepped structure relative to the upper surface of the pre-stack structure 102, thereby forming the stepped structure 120. The stepped structure 120 may be substantially the same as the initial stepped structure used to form the stepped structure 120, except that it is located in a relatively lower position within the microelectronic device structure 100 (e.g., within the pre-stack structure 102). The additional material removal processes may cause the lower boundary of the stepped structure 120 to be located at the same position as or below the lower boundary of the pre-stack structure 102.

[0031] Before forming the dielectric filler material 126, implant regions 128 may be formed within the uppermost additional insulating structure 106a of the preliminary stack structure 102. For example, the initial material (e.g., silicon nitride material) of the exposed portion of the uppermost additional insulating structure 106a in each step 122 of the stepped structure 120 may be implanted with boron, carbon, oxygen, gallium, or a combination thereof to form the implant regions 128. One or more process operations may be performed to form the implant regions 128 of the uppermost additional insulating structure 106a. For example, the initial material of the uppermost additional insulating structure 106a may be subjected to (e.g., exposed to) one or more processing operations that change the material composition of the uppermost additional insulating structure 106a. These processing operations may change the material composition of the exposed portion of the uppermost additional insulating structure 106a compared to the material composition of the remaining (e.g., unexposed) portion and the material composition of the additional insulating structure 106 located below (e.g., in the Z direction) the uppermost additional insulating structure 106a in the early stages of formation.

[0032] The material of the implant region 128 of the uppermost additional insulating structure 106a may be formed from, for example, one or more carbon-containing materials (e.g., carbon-doped silicon nitride, silicon carbonitride (SiCN)), boron-containing materials (e.g., boron-doped silicon nitride), or gallium-containing materials, or comprising these. In a non-limiting example, the material of the implant region 128 may be formed from, for example, one or more boron nitride (BNy), gallium nitride (GaN), oxynitride materials (e.g., SiOxNy), and carbonitride materials (e.g., SiOxCzNy). In some embodiments, the implant region 128 may include a boron-doped nitride material or a carbon-doped nitride material.

[0033] The implanted region 128 may exhibit etching selectivity for the dielectric material 116, the dielectric filler material 126, the insulating structure 104 of the pre-stack structure 102, and optionally additional insulating structures 106. As used herein, the term “selectively etchable” means, and includes, a material in which a particular material exhibits a higher etching rate in response to exposure to an etching chemical compared to other materials exposed to the same etching chemical. For example, such a material may exhibit an etching rate at least about three times, e.g., about five times, about ten times, about twenty times, or about forty times, that of other materials. Etching chemicals and etching conditions for selectively etching the desired material may be selected by those skilled in the art.

[0034] The implantation conditions and dopant concentration may be adjusted to obtain desired etching selectivity for the insulating structure 104 and other exposed materials with respect to the implanted region 128. For example, the implantation conditions may be set to achieve desired etching selectivity for the implanted region 128, thereby allowing the material of the implanted region 128 to be selectively removed in a material removal process used to remove the additional insulating structure 106 (including the remainder of the uppermost additional insulating structure 106a) of the pre-stacked structure 102. Thus, depending on the implantation conditions used to form the implanted region 128, the additional insulating structure 106 and the implanted region 128 may be removed sequentially in a single process operation. In yet another embodiment, the implanted region 128 exhibits etching selectivity for the additional insulating structure 106, in which case the additional insulating structure 106 and the implanted region 128 may be removed sequentially in multiple (e.g., two or more) process operations.

[0035] The implant region 128 may be formed within the uppermost layer 106a of the insulating structure 104 and the additional insulating structure 106, but not within the additional insulating structure 106 of the other layers 108 located below it (vertically). The implant region 128 may be formed above the uppermost insulating structure 104a in the vertical direction (e.g., Z direction) and in direct contact with it. After formation, the implant region 128 may extend horizontally (e.g., Y direction) to substantially cover the upper surface of the uppermost insulating structure 104a in each step 122. The remaining (e.g., unexposed) portion of the uppermost additional insulating structure 106a in each step 122 may be adjacent (e.g., laterally adjacent) to the implant region 128 and in physical contact with it. As shown in Figure 1B, the implant region 128 may be formed to include a sacrificial portion of dielectric material that is adjusted to be removed during subsequent process operations. As will be described later, the implant region 128 may be replaced by other materials (for example, the conductive material of the strap structure 166 (Figure 1G)).

[0036] Continuing to refer to Figure 1B, after the formation of the stepped structure 120, openings 130 (e.g., contact openings) may be formed to extend vertically through the pre-stack structure 102. In the formation of each opening 130, portions of the dielectric filler material 126, implant region 128, insulating structure 104, and additional insulating structure 106 may be removed in one or more material removal processes, for example, by exposing their respective materials to wet etching chemicals and / or dry etching chemicals. A portion of the material of the implant region 128 (e.g., its central portion) may be removed (e.g., etched) in one or more material removal processes, and as a result, the dimensions (e.g., width) of each opening 130 may be relatively smaller than the dimensions of the implant region 128 of the uppermost additional insulating structure 106a (e.g., the portion corresponding to the upper surface of step 122 of the stepped structure 120). Furthermore, the openings 130 may extend beyond the upper surface of step 122 of the stepped structure 120 and penetrate the material of the pre-stack structure 102.

[0037] Therefore, the opening 130 may be formed to extend from the upper surface of the dielectric filling material 126 to the source layer 110 located below the pre-stack structure 102. As shown in Figure 1B, the opening 130 extends completely through the entire vertical direction (e.g., the height direction) of the pre-stack structure 102. Therefore, the vertical height (e.g., the Z direction) of the opening 130 may be substantially the same (e.g., substantially the same height) regardless of the horizontal positional relationship of the steps 122 of the stepped structure 120. The manufacturing process can be simplified by forming the opening 130 across the entire vertical direction of the pre-stack structure 102 without varying its depth depending on the position of each step 122 of the stepped structure 120.

[0038] The first conductive material 112 of the source layer 110 may function as an etching stop material when removing the dielectric filler material 126, implant region 128, insulating structure 104 and additional insulating structure 106 to form the opening 130. In some such embodiments, the opening 130 may be terminated on or inside the first conductive material 112 in the processing step shown in Figure 1B. In other embodiments, the opening 130 may be terminated on or inside an insulating material located above the first conductive material 112. In yet another embodiment, the opening 130 may penetrate the first conductive material 112 and be terminated on or inside the second conductive material 114. As an example that is not limited, in the process step shown in Figure 1B, the opening 130 may be terminated on or inside the first conductive material 112 and then terminated on or inside the second conductive material 114 in the subsequent process of the microelectronic device structure 100. As will be described later, the opening 130 may be used to form a conductive contact (e.g., a conductive contact 164 (Figure 1G)) that comes into contact with a conductive contact structure (e.g., a strap structure 166 (Figure 1G)) of the stepped structure 120.

[0039] The horizontal dimension (e.g., width) of each opening 130 may be relatively smaller than the dimension of the upper surface (e.g., tread) of the step 122 of the stepped structure 120. For example, the width of the opening 130 may be in the range of about 100 nanometers (nm) to about 500 nm, for example, in the range of about 100 nm to about 150 nm, about 150 nm to about 250 nm, about 250 nm to about 350 nm, or about 350 nm to about 500 nm. However, the disclosure is not limited to these, and the width of the opening 130 may be a value different from the above range. In some embodiments, the width of the opening 130 may be selected and adjusted to affect the size and shape of one or more features formed within the microelectronic device structure 100, as described later.

[0040] Referring next to Figure 1C, before forming the material for the conductive contact 164 (Figure 1G) within the opening 130, the lateral portion of the additional insulating structure 106 (e.g., the portion in the X or Y direction) may be converted to another insulating material, thereby insulating the additional insulating structure 106 from the material for the conductive contact 164. For example, the initial material (e.g., the silicon nitride material of the additional insulating structure 106) may be oxidized to form the liner material 134 (e.g., the inner liner material, the inner insulating material). Thus, the liner material 134 may be directly adjacent (e.g., continuous) to the remainder of the additional insulating structure 106 in the lateral direction. In some such embodiments, the liner material 134 may be formed from, or containing, an oxide material having a different material composition from the remainder of the additional insulating structure 106. However, the use of other materials as the material for the liner material 134 may be considered, insofar as the liner material 134 exhibits etching selectivity with respect to the surrounding material.

[0041] By forming the liner material 134 within the recessed region, an insulating region 132 can be formed between the opening 130 and the remainder of the additional insulating structure 106. This results in the portion of the additional insulating structure 106 having the first material composition being relatively separated (e.g., insulated) from the opening 130 by the liner material 134 of the insulating region 132 having a second different material composition. Therefore, the process operation may be selected (e.g., facilitated, encouraged) to form the liner material 134 in the vicinity of the opening 130, thereby forming an insulating region 132 between the remainder of the horizontally adjacent additional insulating structure 106 and the material of the conductive contact 164 (Figure 1G) that is later formed within the opening 130.

[0042] Alternatively, a lateral portion of the additional insulating structure 106 may be selectively removed through the opening 130 to form a recessed area for forming an insulating region 132. In one example, the exposed portion of the additional insulating structure 106 may be exposed to an etching agent (e.g., a wet etching agent) through the opening 130, thereby selectively removing a portion of the additional insulating structure 106 relative to the insulating structure 104. In some embodiments, the additional insulating structure 106 may be exposed to phosphoric acid (H3PO4) to selectively remove a portion of the additional insulating structure 106 in the vicinity of the opening 130.

[0043] After selectively removing a portion of the additional insulating structure 106, the liner material 134 may be formed in a recessed area near the remainder of the additional insulating structure 106 without completely filling the opening 130. For example, the liner material 134 may be formed in a recessed area and effectively "close" (e.g., seal) a recessed area immediately adjacent to the opening 130. The liner material 134 may be formed to extend between vertically adjacent insulating structures 104 in the vicinity of the recessed area from which a portion of the additional insulating structure 106 has been removed, thereby allowing the liner material 134 to substantially fill a portion of the recessed area near the opening 130 in a vertical direction without completely filling the opening 130. The liner material 134 may be formed by conventional process equipment using one or more of the prior art methods, e.g., in-situ growth, CVD, ALD, and PVD. In some embodiments, the liner material 134 may be formed (e.g., deposited) using a single continuous ALD process or a single continuous CVD process.

[0044] The liner material 134 may be formed from or comprising one or more of the materials described above with respect to the insulating structure 104 (e.g., SiO2). For example, the liner material 134 may be formed from or comprising an insulating material that has etching selectivity with respect to one or more of the additional insulating structures 106 and implant regions 128. In some embodiments, the liner material 134 may be formed from or comprising a single high-quality silicon oxide material (e.g., ALD-SiOx). For example, the liner material 134 may be a substantially uniform and substantially conformal silicon oxide material (e.g., a substantially uniform and substantially conformal silicon dioxide material), in which case there are substantially no voids within the liner material 134. Alternatively, the liner material 134 may be formed from or comprising one or more of silicon oxycarbide (SiOxCy), silicon oxynitride (SiOxNy), silicon hydride oxycarbide (SiCxOyHz), or silicon oxycarbonitride (SiOxCyNz).

[0045] As shown in Figure 1C, one or more sides of the insulating region 132 (e.g., lateral side, horizontal side) may be in direct contact with the remaining sides of the additional insulating structure 106 of the pre-stack structure 102 along the interface 136 (e.g., vertical interface). The implant regions 128 may each have a lateral extension greater than the lateral extension (e.g., width in the Y direction) of the insulating region 132, as shown in Figure 1C. In yet another embodiment, the sides of the implant regions 128 may be substantially aligned with the sides of the insulating region 132, or some insulating regions 132 may each have a lateral extension greater than the lateral extension of the implant regions 128, provided that in each step 122 of the stepped structure 120, the implant regions 128 are separated from the insulating region 132 by the remainder of the uppermost additional insulating structure 106a.

[0046] Referring to Figure 1D, the remaining material of the implant region 128 (Figure 1C) of the uppermost additional insulating structure 106a may be optionally and selectively removed (e.g., excavated) to form a lateral opening 131 (e.g., a lateral recess) that communicates with (e.g., is continuous with) the opening 130. For example, at least a portion (e.g., substantially the entirety) of the implant region 128 located on step 122 of the stepped structure 120 may be removed to form a lateral opening 131. By removing the implant region 128, the lateral width of the opening 130 in the preliminary stack structure 102 is increased, and a lateral opening 131 is formed between the remaining uppermost additional insulating structure 106a and the dielectric filler material 126 at each step 122. In yet another embodiment, the remaining implant region 128 may remain in the stepped structure 120 at the processing step in Figure 1D and be removed (e.g., excavated) during a subsequent material removal step (e.g., a replacement gate processing step). Details of this case will be explained with reference to Figures 1E and 1F.

[0047] In some embodiments, the material of the implant region 128 (e.g., carbon-containing material, boron-containing material) may be removed by exposure to one or more etchants (e.g., wet etchants) through the opening 130. The wet etchants may include one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, aqua regia, or hydrogen peroxide. In some embodiments, the material of the implant region 128 may be removed using a phosphoric acid / acetic acid / nitric acid (PAN) etching solution. However, the disclosure is not limited thereto, and the material of the implant region 128 may be removed by other etchants and / or other material removal processes (e.g., gas phase removal processes, atomic layer removal processes). For example, the material of the implant region 128 may be removed by sequentially performing a self-limiting process of an atomic layer removal process to modify the surface of the material (e.g., implant region 128), and then selectively removing the modified surface material. In further embodiments, the material of the implant region 128 may be removed by a plasma etching process (e.g., an inductively coupled plasma (ICP) etching process) comprising one or more of hydrogen fluoride (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), and other materials. The material of the implant region 128 may optionally be exposed to hydrogen (H2), nitrogen (N2), oxygen (O2), argon (Ar), or a combination thereof. Alternatively, the material of the implant region 128 may be removed by exposure to one or more dry etching agents.

[0048] By forming the lateral opening 131, at least a portion (e.g., substantially) of the material of the implant region 128 located laterally adjacent to the opening 130 is removed. For example, after the formation of the lateral opening 131, substantially no implant region 128 may remain within the stepped structure 120. Alternatively, some of the material of the implant region 128 may remain within the lateral opening 131. The implant region 128 within the uppermost additional insulating structure 106a, located vertically adjacent (e.g., below) the dielectric filler material 126 and laterally surrounding the opening 130, may be designated as the location for forming the lateral opening 131. Thus, the lateral opening 131 may be partially defined by the dielectric filler material 126, the remainder of the uppermost additional insulating structure 106a, and the uppermost insulating structure 104a.

[0049] As shown in Figure 1D, the first sacrificial material 138 may optionally be formed within one or more openings 130 and lateral openings 131. In some embodiments, the first sacrificial material 138 may be conformally formed within the openings 130 and substantially continuous along the vertical dimensions (e.g., vertical height) of the pre-stack structure 102, as well as being formed within the lateral openings 131 and substantially continuous along the horizontal dimensions (e.g., width) of each step 122 of the stepped structure 120. In other embodiments, the first sacrificial material 138 may be non-conformally formed within the openings 130 and lateral openings 131. Thus, the first sacrificial material 138 may be formed so that its thickness varies (e.g., is non-uniform) throughout the openings 130 and lateral openings 131. Furthermore, the first sacrificial material 138 may be formed to include a portion that is divided (e.g., discontinuous), in which case the first sacrificial material 138 may be included in some areas of the opening 130 and the lateral opening 131, but not in other areas. In yet another embodiment, the first sacrificial material 138 may not be formed in the lateral opening 131, but only in the opening 130, as in the processing step in Figure 1D where the remainder of the implant region 128 remains within the stepped structure 120.

[0050] The first sacrificial material 138 may be formed from, or comprising, an insulating material such as a dielectric nitride material. For example, the material of the first sacrificial material 138 may comprise one or more of the materials described above with respect to the additional insulating structure 106 (e.g., Si3N4). In other embodiments, the first sacrificial material 138 may comprise a conductive material (e.g., polysilicon). For example, the first sacrificial material 138 may be formed to comprise amorphous silicon or polycrystalline silicon. In some such embodiments, the first sacrificial material 138 may be doped with one or more dopants, for example, at least one N-type dopant (e.g., one or more of arsenic, phosphorus, antimony, and bismuth) or at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium).

[0051] The first sacrificial material 138 may be in contact with one or more (e.g., each) of the dielectric filler material 126, the insulating structure 104 and additional insulating structure 106 of the pre-stack structure 102, the liner material 134 of the insulating region 132, and the first conductive material 112 of the source layer 110. Thus, the first sacrificial material 138 may be formed within the opening 130 to extend from the upper surface of the dielectric filler material 126 to the source layer 110 located below the pre-stack structure 102. The first sacrificial material 138 may terminate on or within the upper surface of the first conductive material 112. Furthermore, by forming the first sacrificial material 138 within the lateral opening 131, an additional portion of the uppermost additional insulating structure 106a located above the uppermost insulating structure 104a of the insulating structure 104 may be formed.

[0052] In some cases, voids 140 (e.g., gaps, seams) may be formed within the first sacrificial material 138 during the fabrication of the microelectronic device structure 100. The first sacrificial material 138 may contain one or more voids 140 when formed within an opening 130 having a high aspect ratio (HAR). Furthermore, voids 140 may also be formed within the first sacrificial material 138 within a lateral opening 131. For example, the first sacrificial material 138 may contain one or more voids 140 within the opening 130 and the lateral opening 131 due to the material formation process (e.g., non-conformal deposition) used to form its insulating material. In some cases, the voids 140 may be located in the central part of the opening 130 and the lateral opening 131, as well as at the intersection of the opening 130 and the lateral opening 131. Some openings 130 and lateral openings 131 may be substantially free of voids 140, and these openings 130 and lateral openings 131 may be substantially filled with the first sacrificial material 138. This is illustrated in the opening 130 and the corresponding lateral opening 131 shown on the left side of the microelectronic device structure 100 in Figure 1D.

[0053] The first sacrificial material 138 may be configured and positioned to prevent the material defining the opening 130 and the lateral opening 131 (e.g., dielectric filler material 126, insulating structure 104, liner material 134 of insulating region 132, first conductive material 112 of source layer 110) from being removed (e.g., excavated) during the subsequent material removal process of the pre-stack structure 102. By at least partially filling the opening 130 and the lateral opening 131 with the first sacrificial material 138, the formation of additional dielectric material (e.g., carbon-containing mask material) during subsequent process operations can also be substantially suppressed (e.g., blocked, prevented). After the first sacrificial material 138 has been formed, the microelectronic device structure 100 may optionally be subjected to a chemical mechanical polishing (CMP) process to remove any material located on the pre-stack structure 102 (e.g., additional portions of the first sacrificial material 138). Alternatively, if the first sacrificial material 138 is not formed during the processing step shown in Figure 1D, the opening 130 and the lateral opening 131 may remain open during subsequent process operations (e.g., replacement gate processing operations).

[0054] Referring next to Figure 1E, a slot 144 (also referred to herein as the “replacement gate slot”) may be formed through the preliminary stack structure 102 (Figure 1D) to allow for the replacement of an additional insulating structure 106 (Figure 1D) with the conductive structure, and for the selective removal of the first sacrificial material 138 (Figure 1D), if present. As most clearly shown in Figure 1F, the additional insulating structure 106 is at least partially (e.g., substantially) replaced with a conductive structure 152 containing the conductive material 168 via a so-called “replacement gate” or “gate last” process operation, thereby forming a stack structure 156 in which layers 158 of the conductive structure 152 are alternately stacked perpendicular to the insulating structure 104. The second sacrificial material 150 may optionally be formed within the opening 130 and the lateral opening 131, for example, in the area where the first sacrificial material 138 previously existed. The slot 144 may then be filled with the dielectric material 148. The formation of slot 144 and conductive structure 152 will be described in detail below, along with other components (e.g., structures, features) of the microelectronic device structure 100 in the processing stage shown in Figure 1E. Figure 1F is a simplified partial cross-sectional view of the microelectronic device structure 100 along line FF shown in Figure 1E. For clarity and ease of understanding of the drawings and related descriptions, some features shown in one of Figures 1E and 1F may not be shown in the other.

[0055] Referring together to Figures 1E and 1F, the slots 144 may be formed to extend vertically (e.g., in the Z direction) through the preliminary stack structure 102 (Figure 1D), and may also penetrate, for example, the dielectric filler material 126 and the insulating structure 104 and the layer 108 of the additional insulating structure 106 (Figure 1D). In forming each slot 144, the respective portions of the dielectric filler material 126, insulating structure 104, and additional insulating structure 106 may be removed by, for example, one or more material removal processes by exposing the corresponding materials to wet etching chemicals and / or dry etching chemicals.

[0056] Prior to forming the slot 144, the dielectric filler material 126 and a portion of the pre-stack structure 102 may be covered with additional dielectric material (e.g., additional portions of dielectric material 116) and / or mask material 154 (e.g., carbon-containing mask material), which may be configured and arranged to prevent the dielectric filler material 126 from being removed (e.g., excavated) during the material removal process of the dielectric filler material 126 and the pre-stack structure 102. For the sake of clarity and ease of understanding of the drawings and related descriptions, the slot 144 is shown to be formed after the formation of the first sacrificial material 138, but is not limited thereto, and the slot 144 may be formed before the formation of the first sacrificial material 138. For example, the slot 144 may be formed during (e.g. substantially simultaneously with) the formation of the opening 130.

[0057] The slot 144 may extend to the source layer 110, for example, the first conductive material 112. Alternatively, the slot 144 may terminate on or within an insulating material located above the first conductive material 112. The slot 144 may divide (e.g., partition) the microelectronic device structure 100 into block structures 146. Although only three slots 144 and two block structures 146 are shown in Figure 1E, the disclosure is not limited thereto. The microelectronic device structure 100 may include a plurality of (e.g., four, five, six, or eight) block structures 146, each block structure 146 being separated from adjacent block structures 146 in the lateral direction (e.g., the X direction) by a single slot 144. The slot 144 may divide the microelectronic device structure 100 into any desired number of block structures 146.

[0058] Referring to Figure 1F, the additional insulating structure 106 (see Figure 1D) may be selectively removed (e.g., removed / excavated) through the slot 144 (see Figure 1E). Furthermore, the first sacrificial material 138 may also be selectively removed through the slot 144. For example, the first sacrificial material 138 may be removed during (e.g. substantially simultaneously with) the removal of the additional insulating structure 106. In embodiments where an implant region 128 remains within the stepped structure 120 at the processing stage of Figure 1D, the remaining portion of the implant region 128 may be selectively removed through cell openings between the insulating structures 104 during (e.g. substantially simultaneously with) the removal of the additional insulating structure 106 and the first sacrificial material 138, thereby reducing costs and the number of steps performed.

[0059] Therefore, the material of the additional insulating structure 106 and implant region 128 of the preliminary stack structure 102 (e.g., boron-doped nitride material or carbon-doped nitride material) may be removed in a single processing step, and a lateral opening 131 may be formed (e.g., a reopening opening) when the cell opening between the insulating structures 104 is formed. In embodiments in which the implant region 128 exhibits etching selectivity for the additional insulating structure 106, the additional insulating structure 106 and implant region 128 are removed in multiple (e.g., two or more) processing steps. The space between adjacent insulating structures 104 in the vertical direction (e.g., Z direction) is filled with conductive material 168 to form a stack structure 156 including layers 158 of conductive structure 152 and insulating structure 104.

[0060] In some embodiments, the conductive material 168 of the conductive structure 152 includes tungsten (W). In another embodiment, the conductive material 168 of the conductive structure 152 includes polysilicon doped to impart conductivity. In yet another embodiment, the conductive material 168 is formed to include one or more of titanium, ruthenium, aluminum, and molybdenum. For each conductive structure 152, its conductive material 168 may be substantially homogeneous or substantially heterogeneous. In some embodiments, each conductive structure 152 is substantially homogeneous. In another embodiment, at least one conductive structure 152 is substantially heterogeneous.

[0061] At least one conductive structure 152 on the vertically (e.g., Z-direction) lower side of the stack structure 156 is used as at least one lower selection gate (e.g., source-side selection gate (SGS)) of the microelectronic device structure 100. In some embodiments, a single (e.g., only one) conductive structure 152 belonging to the vertically lowest layer 158 of the stack structure 156 is used as the lower selection gate (e.g., SGS) of the microelectronic device structure 100. Furthermore, a conductive structure 152 on the vertically (e.g., Z-direction) upper side of the stack structure 156 is used as an upper selection gate (e.g., drain-side selection gate (SGD)). In some embodiments, horizontally adjacent conductive structures 152 (e.g., conductive structures separated from each other by slots) belonging to the vertically uppermost layer 158 of the stack structure 156 are used as the upper selection gate (e.g., SGD) of the microelectronic device structure 100. In some embodiments, multiple (e.g., 2, 4, 5, or 6) conductive structures 152 are used as upper selection gates (e.g., SGDs) of the microelectronic device structure 100.

[0062] When forming the conductive material 168 of the conductive structure 152, additional portions of the conductive material 168 may optionally be formed within the opening 130 and the lateral opening 131 to form the second sacrificial material 150. In this case, the opening 130 and the lateral opening 131 are not completely filled. For example, the conductive material 168 of the second sacrificial material 150 is formed during the formation of the conductive structure 152 through the slot 144 (see Figure 1E) and the cell opening between the insulating structure 104. Thus, the second sacrificial material 150 has substantially the same material composition as the conductive structure 152 (e.g., the conductive material 168).

[0063] As shown in Figure 1F, the second sacrificial material 150 may include a first portion 150a within the opening 130 and a second portion 150b within the lateral opening 131. For example, the first portion 150a extends vertically (e.g., in the Z direction) within the opening 130, and the second portion 150b extends horizontally (e.g., in the X or Y direction) within the lateral opening 131. The second sacrificial material 150 is formed as a substantially continuous material within the opening 130 and the lateral opening 131, as shown in Figure 1F. In another embodiment, the second sacrificial material 150 is formed in a shape with varying thickness (e.g., non-uniform) across one or more of the openings 130 and the lateral opening 131. Furthermore, the second sacrificial material 150 may be formed to include divided (e.g., discontinuous) portions, in which case the second sacrificial material 150 is included in some areas of the opening 130 and the lateral opening 131, but not in other areas.

[0064] The second sacrificial material 150 may, in some cases, contain additional voids (e.g., gaps or seams) within it. In some embodiments, the second sacrificial material 150 (e.g., first portion 150a) is formed on the vertical side surface of the dielectric filler material 126, and additional portions of the second sacrificial material 150 (e.g., second portion 150b) are not formed within the lateral opening 131, as shown in the example of the lateral opening 131 shown on the left side of the microelectronic device structure 100 in Figure 1F. Since the uppermost additional insulating structure 106a in each step 122 (see Figure 1D) is laterally adjacent to the lateral opening 131 (e.g., at the same height), in the processing steps of Figures 1E and 1F, one of the conductive structures 152 (e.g., the uppermost conductive structure 152a) may partially define the lateral opening 131.

[0065] The second sacrificial material 150 may or may not remain within the microelectronic device structure 100. For example, the remainder of the conductive material 168 in the first portion 150a of the second sacrificial material 150 may remain on the vertical sides of the dielectric filler material 126 and on the material of the stack structure 156, but the conductive material 168 of the second portion 150b may not remain within the lateral opening 131. In some embodiments, the remainder of the conductive material 168 of the second portion 150b of the second sacrificial material 150 that remains within the lateral opening 131 is removed using one or more material removal processes. If there is a remainder of dielectric material (e.g., high-K dielectric material 172 (see Figure 1I)) within the lateral opening 131, these are also removed using additional material removal processes (e.g., wet etching).

[0066] Furthermore, the features of the array region of the microelectronic device structure 100 may be formed during (e.g., substantially simultaneously with) the formation of the corresponding features of the stepped region 105, as described above in relation to Figure 1A. For example, after forming the conductive structures 152 of the stacked structure 156 within the stepped region 105 and the array region, the ends of the conductive structures 152 adjacent to the slots 144 in the array region are set back (e.g., laterally) relative to the ends of the insulating structures 104, and conductive rails are formed adjacent to the conductive structures 152 in the layer 158. The conductive rails are formed horizontally adjacent (e.g., horizontally positioned) to at least the conductive structures 152 within the recessed regions. By setting back the ends of the conductive structures 152 and forming conductive rails within these recessed regions, the electrical resistance of the microelectronic device structure 100 can be reduced.

[0067] In some embodiments, the remainder of the conductive material 168 of the second portion 150b of the second sacrificial material 150 is removed from the lateral opening 131 in the stepped region 105 during a material removal process to form a recessed region of the conductive structure 152 in the array region. For example, the material removal process to remove the second portion 150b of the second sacrificial material 150 (e.g., the conductive material 168) may be carried out during (e.g., substantially simultaneously with) a material removal process to set back the end of the conductive structure 152 adjacent to the slot 144 in the array region. Thus, the lateral dimension (e.g., width) of the lateral opening 131 may be substantially the same as the lateral dimension of the recessed region of the conductive structure 152 in the array region. In a non-limiting example, the lateral dimensions of each lateral opening 131 and the recessed region of the conductive structure 152 may be in the range of about 20 nm to about 50 nm, respectively.

[0068] While the second sacrificial material 150 and the conductive material 168 of the conductive structure 152 are being formed, the upper region of the opening 130 remains open, and the second sacrificial material 150 may not substantially fill the opening 130 and the lateral opening 131. In some embodiments, so-called "punch-through" etching is performed to remove a portion of the second sacrificial material 150 and the first conductive material 112, exposing a portion of the underlying second conductive material 114. In other embodiments, a portion of the insulating material on the second sacrificial material 150 and the first conductive material 112 is removed, exposing a portion of the underlying first conductive material 112.

[0069] As shown in Figure 1F, one or more sides of the insulating region 132 (e.g., horizontal or transverse sides) may be in direct contact with the sides of the conductive structure 152 of the stack structure 156 along the interface 160 (e.g., vertical interface). The presence of the liner material 134 forms an insulating region 132 between the conductive contact 164 (see Figure 1G) and the conductive structure 152, and the conductive structure 152 is isolated (e.g., separated) from the conductive contact 164 by the insulating region 132. After forming the second sacrificial material 150 and the conductive material 168 of the conductive structure 152 of the stack structure 156, the slot 144 (see Figure 1E) is filled with dielectric material 148 (see Figure 1E).

[0070] The dielectric material 148 is formed from or comprising an insulating material. For example, the dielectric material 148 is formed from or comprising one or more of the following: dielectric oxide materials (e.g., one or more of SiOx, silicate glass phosphate, silicate glass borate, silicate glass borate, silicate glass fluorine, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, and MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), and at least one dielectric carbonate nitride material (e.g., SiOxCzNy). The material composition of the dielectric material 148 may be substantially the same as the material composition of one or more of the dielectric filler material 126 and the insulating structure 104 of the stack structure 156, or it may be different from the material composition of the dielectric filler material 126 and the insulating structure 104. In some embodiments, the dielectric material 148 is formed from or containing SiO2.

[0071] Next, referring to Figure 1G, the conductive filler material 162 is formed within the opening 130 (see Figure 1F), and conductive contacts 164 are formed. After formation, each conductive contact 164 extends vertically, completely penetrating the stack structure 156, without terminating on the step 122 of the stepped structure 120, as shown in Figure 1G. For example, the conductive contact 164 extends vertically (e.g., in the Z direction) from the uppermost vertical boundary of the dielectric filler material 126 (e.g., at the height of the uppermost layer 158 of the stack structure 156) to the uppermost vertical boundary of the second conductive material 114, or a position below that. In some embodiments, the stepped structure 120 substantially does not include conductive contacts formed to terminate on its step 122.

[0072] As shown in Figure 1G, the presence of the liner material 134 within the recessed region creates an insulating region 132 between the conductive contact 164 and the additional conductive structures 152 located below each uppermost conductive structure 152a. As a result, the additional conductive structures 152 are isolated (e.g., separated) from the conductive contact 164 by the insulating region 132.

[0073] At least some of the conductive contacts 164 may have a different geometric shape (e.g., one or more different dimensions or shapes) and / or different horizontal spacing from at least some of the other conductive contacts 164. On the other hand, each conductive contact 164 may have a substantially identical geometric shape (e.g., identical dimensions and shape) and horizontal spacing (e.g., in the Y direction) to all the other conductive contacts 164. For example, the height (e.g., in the Z direction) of each conductive contact 164 of the microelectronic device structure 100 may be substantially the same as the height of the other conductive contacts 164.

[0074] Each conductive contact 164 of the microelectronic device structure 100 may be formed to extend through the entire vertical direction of the stack structure 156 and terminate at a single location, thereby substantially reducing (e.g., substantially preventing) damage within the stepped structure 120 during manufacturing. Thus, by having the conductive contacts 164 extend through the entire vertical direction of the stack structure 156 and terminate at a single location (e.g., on or inside the source layer 110), it is not necessary to extend the conductive contacts 164 to different depths of the individual steps 122, simplifying the manufacturing process. In contrast, in conventional microelectronic device structures, the conductive contacts are formed to terminate (e.g., land) on the upper surface of each step of the stepped structure, resulting in uneven height of the conductive contacts throughout the stepped structure.

[0075] In some cases, damage may occur within the stepped structure during the manufacturing of conventional microelectronic device structures. In particular, damage to the layer material (so-called "clipping") can cause defects and may adversely affect the performance of the memory device. Furthermore, misaligned conductive contacts terminating on the upper surface of individual steps of the stepped structure may be prone to bridging (e.g., short circuits or electrical connections) between adjacent portions of the conductive structure 152. In addition, terminating conductive contacts at different depths of the steps of the stepped structure in conventional microelectronic device structures may result in so-called "over-etching" or "under-etching" during the manufacturing process. Therefore, each conductive contact 164 of the microelectronic device structure 100 may be formed to extend through the entire vertical direction of the stack structure 156 and terminate at a single location, thereby substantially reducing (e.g., substantially preventing) damage within the stepped structure 120 during manufacturing.

[0076] During the formation of the conductive contact 164, its conductive filler material 162 may also substantially fill the lateral opening 131 (see Figure 1F), forming a strap structure 166. The conductive contact 164 may be integral and continuous (e.g., a single unit) with the strap structure 166. The strap structure 166 protrudes horizontally outward from the conductive contact 164. The conductive filler material 162 of the strap structure 166 is in contact with the dielectric filler material 126, the insulating structure 104 (e.g., the uppermost insulating structure 104a), and the conductive material 168 of the conductive structure 152 of the stack structure 156. After the conductive contact 164 and the strap structure 166 are formed, the microelectronic device structure 100 is subjected to a CMP process to remove sacrificial material outside the boundary of the opening 130 (see Figure 1F).

[0077] In some embodiments, the conductive filler material 162 of the conductive contact 164 and the strap structure 166 is formed adjacent to the remainder of the second sacrificial material 150 present in the opening 130 (see Figure 1F) and the lateral opening 131 (see Figure 1F). For example, the conductive filler material 162 may substantially fill the remainder of the opening 130 and the lateral opening 131 and be at least partially (e.g., substantially) laterally surrounded by the second sacrificial material 150. In another embodiment, the second sacrificial material 150 is substantially removed before forming the conductive filler material 162 of the conductive contact 164 and the strap structure 166. In such embodiments, the conductive filler material 162 substantially fills the opening 130 and contacts the dielectric filler material 126, the liner material 134 of the insulating region 132, the insulating structure 104 of the stack structure 156, and the first conductive material 112 and second conductive material 114 of the source layer 110. Therefore, the conductive contact 164 is formed to extend from the upper surface of the dielectric filler material 126 to the source layer 110 located below the stack structure 156. The conductive contact 164 may be terminated on or inside the second conductive material 114, or on or inside the first conductive material 112. In such embodiments, the conductive contact 164 is formed to self-align with the underlying conductive material (e.g., the first conductive material 112) using a so-called "assisted self-alignment" process.

[0078] The conductive contact 164 and the strap structure 166 are each formed from or comprising a conductive material (e.g., conductive filler material 162). In non-limiting examples, the conductive contact 164 and the strap structure 166 are formed from or comprising one or more of polysilicon, tungsten, titanium, titanium nitride, or other materials. In some embodiments, the conductive filler material 162 is formed from or comprising polysilicon. In such embodiments, the conductive filler material 162 is doped with one or more dopants, for example, at least one N-type dopant (e.g., one or more of arsenic, phosphorus, antimony, and bismuth) or at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In another embodiment, the conductive filler material 162 of the conductive contact 164 and the strap structure 166 is formed from or comprising tungsten. The conductive filler material 162 may have substantially the same material composition as the second sacrificial material 150 and the conductive material 168 of the conductive structure 152 of the stack structure 156, or it may have a different material composition.

[0079] The strap structure 166 can be considered as part of the conductive contact 164 (for example, a portion that extends horizontally outward). For example, as shown in Figure 1G, the conductive contact 164 includes a first portion 164a that is electrically connected to the source layer 110, for example, its second conductive material 114, without being electrically connected to all the conductive structures 152 located below (for example, in the Z direction) each of the individual steps 122 of the stepped structure 120. The conductive contact 164 may also separately include a second portion 164b (corresponding to one of the strap structures 166) that is electrically connected to the first portion 164a and one of the conductive materials 168 of the conductive structure 152. For example, the uppermost conductive structure 152a of the conductive structures 152 forming each step 122 may be configured as the contact area of ​​the second portion 164b of each conductive contact 164. The size and position of the first part 164a correspond to the size and position of the opening 130 (see Figure 1F), and the size and position of the second part 164b correspond to the size and position of the lateral opening 131 (see Figure 1F).

[0080] Therefore, each conductive contact 164 can be configured to facilitate electrical connection between the source layer 110 and the uppermost conductive structure 152a that forms each step 122 of the stepped structure 120. Furthermore, the strap structure 166 of at least one conductive contact 164 may be vertically offset from the strap structure 166 of at least one other conductive contact 164. By forming conductive contacts 164 to facilitate electrical connection between the source layer 110 and the conductive structure 152, the number of support structures (e.g., support pillars) within the stepped region 105 can be reduced. For example, by achieving electrical connection between the source layer 110 and the conductive structure 152 via conductive contacts 164, it is not necessary to form complex conductive paths on the stack structure 156, and support structures can be formed near the conductive contacts 164. Therefore, compared to the configuration of conventional microelectronic device structures, a stepped structure 120 can be provided that has more steps 122 within a given region of the microelectronic device structure 100. In this way, by providing conductive contacts 164 (including its first portion 164a and second portion 164b) within the stepped structure 120, congestion in the conductive path above the stack structure 156 can be reduced. As a result, the spacing between conductive features in the conductive path above the stack structure 156 can be increased, and parasitic (e.g., unwanted) capacitance between adjacent conductive features can be reduced during use and operation of the microelectronic device structure 100.

[0081] By forming the strap structure 166 during the formation of the conductive contact 164, the manufacturing process can be simplified and costs can be reduced. The strap structure 166 (e.g., its conductive filler material 162) can be formed during the formation of the conductive contact 164 (e.g., substantially simultaneously) using a single continuous CVD process or a single continuous PVD process. For example, it can be formed without using the ALD process used in the gate replacement process. Furthermore, the methods and structures of this disclosure can reduce the risk of damage during device formation, improve yield, and reduce current leakage (e.g., that may result from undesirable damage) compared to conventional methods, conventional structures, and conventional devices.

[0082] Figure 1H shows an enlarged portion of a top view of a part of Figure 1G, according to an embodiment of the microelectronic device structure 100 shown in Figure 1G. For clarity and ease of understanding of the drawings and related descriptions, the surrounding materials, including the dielectric filler material 126, are not shown in Figure 1H. The strap structure 166 may laterally surround and physically contact a portion of the conductive contact 164 (e.g., a first portion 164a) at the height of the uppermost conductive structure 152a in each step 122 of the stepped structure 120. Thus, a second portion 164b of an individual conductive contact 164 (also referred to herein as a strap structure 166) may be located in the horizontal vicinity of its first portion 164a and may at least partially (e.g., substantially) surround it. The first portion 164a and the second portion 164b of the conductive contact 164 may have substantially identical material composition, with no clearly distinguishable physical interface between them. Alternatively, the first portion 164a and the second portion 164b may have different material compositions, in which case the material composition of the strap structure 166 is different from the material composition of the conductive contact 164. In some embodiments, the material composition of the strap structure 166 is substantially the same as the material composition of the conductive structure 152 of the stack structure 156, and the material composition of the conductive contact 164 is different from the material compositions of the strap structure 166 and the conductive structure 152. The uppermost conductive structure 152a of the conductive structure 152 is located in the horizontal vicinity of the strap structure 166 (e.g., in direct contact) and may at least partially (e.g., substantially) surround it. The strap structure 166 is directly interposed laterally between the conductive contact 164 and the uppermost conductive structure 152a of the stack structure 156.

[0083] The conductive contact 164 may have a substantially circular horizontal cross-sectional shape, as shown in the top view of Figure 1H. However, the disclosure is not limited thereto. In non-limiting examples, in other embodiments, the conductive contacts 164 may individually have a substantially rectangular (e.g., substantially square) cross-sectional shape, or another elongated cross-sectional shape (e.g., an elliptical cross-sectional shape).

[0084] As shown in Figure 1H, the conductive contact 164 and the strap structure 166 may each be located at the horizontal center within the horizontal region of each step 122 of the stepped structure 120 (see Figure 1G), but other configurations are also possible. The lateral dimension of step 122 (e.g., the second width W2 in the Y direction) may be relatively larger than the lateral dimension of the conductive contact 164 (including its first portion 164a and second portion 164b) (e.g., the first width W1 or diameter in the Y direction). As a non-limiting example, the first width W1 may be in the range of about 300 nm to about 1000 nm (e.g., 1 μm), for example, about 300 nm to about 400 nm, about 400 nm to about 500 nm, about 500 nm to about 600 nm, about 600 nm to about 700 nm, about 700 nm to about 800 nm, about 800 nm to about 900 nm, or about 900 nm to about 1000 nm. However, this disclosure is not limited thereto, and the first width W1 may be a value other than those described above.

[0085] In some embodiments, the second width W2 is in the range of about 1.5 to about 2.5 times the first width W1 of the conductive contact 164 at the lateral boundary of the second portion 164b at the height position of the upper conductive structure 152a. In some embodiments, the second width W2 is at least about 2.0 times the first width W1. For example, the second width W2 may be in the range of about 600 nm to about 1200 nm (e.g., 1.2 μm), more specifically in the range of about 600 nm to about 800 nm, about 800 nm to about 1000 nm, or about 1000 nm to about 1200 nm. However, this disclosure is not limited to these values, and the second width W2 may be other values. In some embodiments, the second width W2 may be substantially the same size as the first width W1. In another embodiment, the second width W2 is set so that the lateral boundary of the second portion 164b of the conductive contact 164 does not extend laterally beyond the step 122 at the height position of the upper conductive structure 152a, thereby reducing or preventing the conductive contact 164 from electrically short-circuiting with other conductive structures 152 of the stack structure 156. The second width W2 is set so that the conductive contact 164 does not extend laterally beyond the lateral boundary of the step 122.

[0086] Figure 1I shows a magnified portion of box I in Figure 1G, illustrating an embodiment of the microelectronic device structure 100 of Figure 1G. For clarity and ease of understanding of the drawings and related descriptions, surrounding materials such as dielectric filler material 126 are not shown in Figure 1I. As shown in Figure 1I, the conductive structure 152 may comprise a conductive liner material 170 positioned adjacent to the insulating structure 104 and a conductive material 168 in contact with the conductive liner material 170. Furthermore, the conductive structure 152 may include a high-dielectric constant (High-K) dielectric material 172 in contact with the insulating structure 104 and the conductive liner material 170. The conductive liner material 170 is interposed perpendicularly between the conductive material 168 and the insulating structure 104, and the high-dielectric constant dielectric material 172 is interposed perpendicularly between the conductive liner material 170 and the insulating structure 104. In Figure 1I, for ease of understanding, the conductive liner material 170 and the high dielectric constant dielectric material 172 are shown only within a portion of the space between vertically adjacent insulating structures 104, but it should be understood that the microelectronic device structure 100 may also include these materials within additional (e.g., all) of the space between vertically adjacent insulating structures 104. The conductive structure 152 is positioned in a location corresponding to the location of the additional insulating structure 106 (see Figure 1D) that was removed via slot 144 (see Figure 1E).

[0087] As shown in Figure 1I, the lateral side of the strap structure 166 is adjacent to and physically in contact with the lateral side of the uppermost conductive structure 152a along the interface 174 (e.g., the vertical interface), thereby improving metal-to-metal contact between them. The high dielectric constant dielectric material 172 is not formed within the lateral opening 131 (see Figure 1F) of the strap structure 166, but is formed adjacent to the conductive structure 152. Forming the high dielectric constant dielectric material 172 adjacent to the conductive structure 152 without forming it within the lateral opening 131 facilitates the formation of the strap structure 166. This eliminates the need to remove a portion of the high dielectric constant dielectric material 172 from the lateral side of the uppermost conductive structure 152a before forming the conductive filler material 162 of the strap structure 166, significantly reducing (e.g., substantially preventing) damage to the surrounding material within the stepped structure 120 (e.g., the uppermost insulating structure 104a).

[0088] Since the strap structure 166 is formed laterally adjacent to and in direct contact with the uppermost conductive structure 152a, the conductive liner material 170 and the high dielectric constant dielectric material 172 are not laterally interposed between the strap structure 166 and the uppermost conductive structure 152a. Therefore, the strap structure 166 is formed directly adjacent to (e.g., in the X or Y direction) the uppermost conductive structure 152a of each step 122. In some such embodiments, only the outer side surface of each strap structure 166 is in physical contact with any of the conductive structures 152 of the stack structure 156. Alternatively, at least one material (e.g., the conductive liner material 170) may be horizontally interposed between the strap structure 166 and the uppermost conductive structure 152a. In either case, the strap structure 166 is formed directly adjacent to the uppermost conductive structure 152a.

[0089] The conductive liner material 170 (if formed) surrounding the conductive structure 152 is formed comprising, for example, one or more seed materials from which a conductive material 168 can be formed, and including this material. The conductive liner material 170 may be formed from, for example, one or more of the following materials: at least one metal (e.g., titanium, tantalum), at least one metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), or at least one other material. In some embodiments, the conductive liner material 170 is formed from, and includes, titanium nitride (TiNx). The high dielectric constant dielectric material 172 may be formed from, for example, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, a combination thereof, or a combination of silicon dioxide and one or more of these. In some embodiments, the high dielectric constant dielectric material 172 is formed from hafnium-doped silicon dioxide, where the ratio of hafnium to silicon is controlled to obtain the desired etching selectivity of the high dielectric constant dielectric material 172.

[0090] Each conductive contact 164 extends completely vertically through the stack structure 156 (see Figure 1G), so that the conductive contact 164 passes through the step 122 of the stepped structure 120 and does not terminate on its upper surface. As shown in Figure 1I, the liner material 134 within the insulating region 132 is horizontally interposed between the conductive contact 164 and an additional conductive structure 152 located below the uppermost conductive structure 152a, thereby isolating the additional conductive structure 152 from the conductive contact 164 by the insulating region 132. For example, the conductive contact 164 is configured to extend through the dielectric filler material 126 and individually contact the uppermost conductive structure 152a and the step 122 of the stepped structure 120, respectively, but not contact the additional conductive structure 152 below it. Each step 122 is individually contacted (e.g., physically or electrically) via the corresponding second portion 164b of the conductive contact 164 (also described as one of the strap structures 166). The second portion 164b of each conductive contact 164 is configured (e.g., dimensionally and shaped) to maximize (e.g., enlarge) the contact area with the contact region of the uppermost conductive structure 152a along the interface 174.

[0091] In some embodiments, the conductive liner material 170 and / or the high dielectric constant dielectric material 172 are maintained (e.g., remain) in the vicinity (e.g., above or below) of the uppermost conductive structure 152a at each step 122 of the stepped structure 120. In other embodiments, the stepped structure 120 does not have the conductive liner material 170 and the high dielectric constant dielectric material 172 in the vicinity of the uppermost conductive structure 152a, and the dielectric filler material 126 is directly adjacent (e.g., adjacent horizontally or vertically) to the conductive material 168 of the uppermost conductive structure 152a. When the conductive liner material 170 and the high dielectric constant dielectric material 172 are present, they surround a portion of the uppermost conductive structure 152a from both the lateral (e.g., X or Y direction) and vertical (e.g., Z direction) directions. The uppermost conductive structure 152a is positioned to vertically overlap (e.g., directly overlap) above the uppermost insulating structure 104a. Therefore, the strap structure 166 is adjacent to (e.g., in direct contact with) the uppermost insulating structure 104a in a vertical direction, and the strap structure 166 extends laterally over a portion of the uppermost insulating structure 104a in each step 122 of the stepped structure 120.

[0092] As shown in Figure 1I, the conductive structure 152 located below the uppermost conductive structure 152a is separated from the first portion 164a of the conductive contact 164 by a distance D1 in the Y direction by an insulating region 132. In non-limiting examples, the distance D1 may be in the range of about 20 nm to about 100 nm, for example, in the range of about 20 nm to about 40 nm, about 40 nm to about 60 nm, about 60 nm to about 80 nm, or about 80 nm to about 100 nm. In some embodiments, the distance D1 is about 80 nm, which corresponds to the horizontal width of the liner material 134 within the insulating region 132 in the Y direction. Furthermore, the horizontal width of the liner material 134 may vary along the vertical height of each conductive structure 152.

[0093] The conductive material 168 of the uppermost conductive structure 152a has a first thickness T1 (e.g., height) in the vertical direction, the value of which is in the range of about 10 nm to about 30 nm, for example, about 10 nm to about 15 nm, about 15 nm to about 20 nm, about 20 nm to about 25 nm, or about 25 nm to about 30 nm. The second portion 164b of the conductive contact 164 (also described herein as the strap structure 166) each has a second thickness T2 (e.g., height) in the vertical direction, the value of which is in the range of about 10 nm to about 40 nm, for example, about 10 nm to about 15 nm, about 15 nm to about 20 nm, about 20 nm to about 25 nm, or about 25 nm to about 40 nm. However, the disclosure is not limited to these, and the first thickness T1 and the second thickness T2 may differ from those described above. In some embodiments, the second thickness T2 is in the range of about 15 nm to about 20 nm, which corresponds to the thickness of the implant region 128 (see Figure 1C), but other thicknesses may also be considered. In embodiments where the conductive liner material 170 and the high dielectric constant dielectric material 172 are present in the vicinity of the uppermost conductive structure 152a (e.g., above or below it), the second thickness T2 of the strap structure 166 may be relatively larger than the first thickness T1 of the conductive material 168 of the uppermost conductive structure 152a. In some embodiments, the second thickness T2 is about 2 nm to about 4 nm larger than the first thickness T1. On the other hand, when the stepped structure 120 does not have the conductive liner material 170 and the high dielectric constant dielectric material 172 in the vicinity of the uppermost conductive structure 152a, the second thickness T2 is substantially the same as (e.g., substantially equal to) the first thickness T1.

[0094] The second thickness T2 of the strap structure 166 is adjusted to a desired value selected at least in part based on the design requirements of the microelectronic device structure 100. In particular, the shapes of the conductive contacts 164 and the strap structure 166 are configured to enlarge the contact area with the uppermost conductive structure 152a in each step 122. For example, the size, shape, and orientation of the strap structure 166 are designed to increase the surface area available for contact with the uppermost conductive structure 152a. As a result, the RC (resistance-capacitance product) of the conductive contacts 164 and the strap structure 166 is improved, which may allow for a reduction in the operating speed (e.g., write time) of the device including the microelectronic device structure 100, leading to improved performance. Furthermore, the presence of a high dielectric constant dielectric material 172 in the vicinity of the uppermost conductive structure 152a reduces parasitic (e.g., stray) capacitance between adjacent conductive features during use and operation of the microelectronic device structure 100.

[0095] The lateral dimensions (e.g., third width W3, diameter in the Y direction) of the liner material 134 of the insulating region 132 are relatively smaller than the lateral dimensions (e.g., fourth width W4, diameter in the Y direction) of the strap structure 166, where this fourth width W4 corresponds to the first width W1 of the individual conductive contacts 164 (see Figure 1H). In some embodiments, the third width W3 of the liner material 134 of the insulating region 132 is in the range of about 120 nm to about 500 nm, for example, about 120 nm to about 200 nm, about 200 nm to about 300 nm, about 300 nm to about 400 nm, or about 400 nm to about 500 nm. Therefore, the conductive structure 152 is separated from the conductive contact 164 by distances ranging from approximately 20 nm to approximately 100 nm in the Y direction, for example, from approximately 20 nm to approximately 40 nm, from approximately 40 nm to approximately 60 nm, from approximately 60 nm to approximately 80 nm, or from approximately 80 nm to approximately 100 nm.

[0096] The fourth width W4 of the strap structure 166 is in the range of about 300 nm to about 1000 nm, for example, about 300 nm to about 400 nm, about 400 nm to about 500 nm, about 500 nm to about 600 nm, about 600 nm to about 700 nm, about 700 nm to about 800 nm, about 800 nm to about 900 nm, or about 900 nm to about 1000 nm. Thus, the uppermost conductive structure 152a in each step 122 is separated from the conductive contact 164 by a distance in the Y direction of about 20 nm to about 120 nm, for example, about 20 nm to about 40 nm, about 40 nm to about 60 nm, about 60 nm to about 80 nm, about 80 nm to about 100 nm, or about 100 nm to about 120 nm. In another embodiment, the third width W3 is substantially the same as the fourth width W4 (for example, substantially equal).

[0097] In another embodiment, the third width W3 is relatively larger than the fourth width W4, and therefore at least some (e.g., all) of the insulating regions 132 have a lateral dimension greater than the lateral dimension of the strap structure 166. For example, the uppermost conductive structure 152a in each step 122 is separated from the conductive contact 164 by a distance in the Y direction ranging from about 10 nm to about 50 nm. The high dielectric constant dielectric material 172 may be formed adjacent to the conductive structure 152 and not within the lateral opening 131 of the strap structure 166 (see Figure 1F), so the high dielectric constant dielectric material 172 is separated from the conductive contact 164 by a distance in the Y direction ranging from about 10 nm to about 50 nm.

[0098] As those skilled in the art will understand, according to additional embodiments of the present disclosure, the features and feature configurations described above in relation to Figures 1A to 1I can be adapted to the design requirements of different microelectronic devices (e.g., different memory devices) depending on the desired electrical performance characteristics. As a non-limiting example, according to additional embodiments of the present disclosure, Figures 2A to 2D are simplified partial cross-sectional views of a method for forming a microelectronic device structure having a configuration different from that of microelectronic device structure 100. In the following description and accompanying drawings, functionally similar features (e.g., structures, devices) are denoted by similar reference numerals. To avoid redundancy, detailed descriptions of all features shown in Figures 2A to 2D are omitted here. Rather, unless otherwise specifically described below, features denoted by previously described reference numerals are understood to be substantially the same as those previously described.

[0099] Figure 2A is a simplified partial cross-sectional view of a microelectronic device structure 100' (a memory device such as a 3D NAND flash memory device). In the processing step shown in Figure 2A, the microelectronic device structure 100' may be substantially the same as the microelectronic device structure 100 in the processing step shown in Figure 1F. In the processing step shown in Figure 2B, the microelectronic device structure 100' may be substantially the same as the microelectronic device structure 100 in the processing step shown in Figure 1G. Figure 2C shows another embodiment of the microelectronic device structure 100' in the processing step of Figure 2B. Figure 2D shows an enlarged portion of the cross-sectional view of box D in Figure 2B.

[0100] The microelectronic device structure 100' shown in Figure 2A includes a stack structure 156 and an opening 130 that extends vertically through the dielectric filler material 126 and the material of the stack structure 156 after the substitution gate processing step. The stack structure 156 of the microelectronic device structure 100' may be formed as a series of layers (arranged in layer 158) of insulating structures 104 and conductive structures 152 arranged alternately in the vertical direction (e.g., the Z direction). The stack structure 156 is formed vertically on top of a source layer 110 containing a first conductive material 112 and a second conductive material 114. The microelectronic device structure 100' includes a stepped structure 120 including a step 122 and a dielectric filler material 126 arranged thereon. The dielectric material 116 may optionally be formed vertically above the stack structure 156. As shown in Figure 2A, the microelectronic device structure 100' may be configured to form an insulating region 132 which includes a liner material 134 that is laterally adjacent to and in direct contact with the side surface of the conductive structure 152 via an interface 160.

[0101] The microelectronic device structure 100' may be formed to include a lateral opening 131 communicating with the opening 130, similar to the processing steps of the embodiments described above with reference to Figure 1F. However, as shown in Figure 2A, the material composition within the opening 130 and the lateral opening 131 may be modified to include additional materials, as described later, different from the configuration described above with reference to Figure 1F.

[0102] In the processing step shown in Figure 2A, the microelectronic device structure 100' may be formed to include a high-dielectric constant (High-K) dielectric material 172 in a position laterally adjacent to the dielectric filler material 126 and the materials of the stack structure 156. Furthermore, the conductive material 168 may be configured to be at least partially (e.g., substantially) surrounded by the high-dielectric constant dielectric material 172. For example, in the substitution gate processing step, when forming the high-dielectric constant dielectric material 172 within the cell openings between the insulating structures 104, it may also be formed within one or more of the openings 130 and the lateral openings 131 (e.g., each of them).

[0103] When forming the conductive material 168 and (optionally) conductive liner material 170 (see Figure 2D) within the cell opening to form the conductive structure 152, additional portions of the conductive material 168 and, if formed, the conductive liner material 170 may be formed within the opening 130. However, the opening 130 is not completely filled. Therefore, the opening 130 according to the embodiment in Figure 2A may be configured to include a high dielectric constant dielectric material 172, a conductive material 168, and (optionally) a conductive liner material 170 inside. Furthermore, as will be described later, the lateral opening 131 may also be configured to include a high dielectric constant dielectric material 172, a conductive material 168, and a conductive liner material 170 inside. For ease of understanding, only the conductive material 168 is shown as a material formed within the opening 130 and the lateral opening 131 in Figures 2A to 2C, but please understand that the conductive liner material 170 may also be optionally formed to facilitate the formation of the conductive material 168.

[0104] As shown in Figure 2A, the conductive material 168 within the opening 130 may be configured to include a first portion 168a (e.g., upper part), a second portion 168b (e.g., vertical part), and a third portion 168c (e.g., lower part). Thus, in the processing step shown in Figure 2A, the opening 130 is defined by the conductive material 168. To facilitate the formation of the high dielectric constant dielectric material 172 and the conductive material 168 within the opening 130, additional portions of the dielectric material 116 and / or additional mask material (e.g., mask material 154) may be configured and positioned to surround (e.g., seal) the opening 130 during the replacement gate processing step. For example, the upper region of the opening 130 may be closed during a material removal process to remove the additional insulating structure 106 (see Figure 1D) of the pre-stack structure 102 (see Figure 1D) or when forming the conductive structure 152.

[0105] The strap structure 166 according to the embodiment of Figure 2A may be formed in the lateral opening 131 at an earlier stage than the processing steps of the embodiment described above. For example, when forming the conductive material 168 used to form the conductive structure 152 of the stack structure 156, the strap structure 166 may be formed before the conductive filler material 162 (see Figure 2B) of the conductive contact 164 (see Figure 2B) is formed in the opening 130. Thus, the strap structure 166 may be formed during (e.g., substantially simultaneously with) the formation of the conductive structure 152 in the substitution gate processing step. In particular, the high dielectric constant dielectric material 172 and conductive material 168 of the strap structure 166 may be formed at the time of the formation of the conductive structure 152 via the cell opening between the slot 144 (see Figure 1E) and the insulating structure 104. The high dielectric constant dielectric material 172 may be substantially continuous across the cell opening of the conductive structure 152 and the entire lateral opening 131 of the strap structure 166. The strap structure 166 is formed from a conductive material 168 and may have a material composition substantially identical to that of the conductive structure 152. The conductive material 168 of the strap structure 166 and the conductive material 168 of the uppermost conductive structure 152a may have substantially the same material composition, and there may be no clearly distinguishable physical interface between the two.

[0106] Alternatively, in the processing step of Figure 2A, the central portion of the lateral opening 131 may remain open (e.g., unfilled). For example, the high dielectric constant dielectric material 172 and the conductive material 168 are formed in the opening 130 during the formation of the conductive structure 152, but do not completely fill the lateral opening 131, and the central portion of the lateral opening 131 may be filled by the conductive filler material 162 (see Figure 2B) when forming the conductive contact 164 (see Figure 2B). In such embodiments, the high dielectric constant dielectric material 172 and the conductive material 168 are formed in part of the lateral opening 131 during the formation of the materials in the opening 130 (e.g., substantially simultaneously), and then the conductive filler material 162 may be formed in the central portion of the lateral opening 131 during the processing step of Figure 2B when the conductive filler material 162 is formed in the central portion of the opening 130.

[0107] After the formation of the conductive material 168, the microelectronic device structure 100' is subjected to a CMP process to remove materials stacked on the stack structure 156 (e.g., additional portions of dielectric material 116 and mask material 154). Furthermore, during the CMP process, a portion of the conductive material 168 (e.g., first portion 168a) and a portion of the high dielectric constant dielectric material 172 in the upper region of the opening 130 is removed, thereby forming the opening 130 (e.g., a reopening). Subsequently, so-called punch-through etching is performed to remove additional portions of the conductive material 168 (e.g., third portion 168c) and additional portions of the high dielectric constant dielectric material 172, exposing a portion of the underlying second conductive material 114. Alternatively, a portion of the insulating material on the conductive material 168, high dielectric constant dielectric material 172, and first conductive material 112 is removed, exposing a portion of the underlying first conductive material 112.

[0108] Therefore, residual material adjacent to the lower region of the opening 130 may indicate that punch-through etching has been performed to remove additional portions of the conductive material 168 and the high dielectric constant dielectric material 172. Alternatively, the conductive material 168 (e.g., first portion 168a and third portion 168c) and the high dielectric constant dielectric material 172 may be selectively removed by exposing each material to an etching chemical, such as a wet etching solution or a dry etching gas. In one or more such material removal processes, optionally, portions (e.g., all) of each material along the lateral sides of the dielectric filler material 126 and the stack structure 156 defining the opening 130 may be removed.

[0109] Referring to Figure 2B, after the high dielectric constant dielectric material 172 and conductive material 168 are formed in the opening 130 (see Figure 2A) and the lateral opening 131 (see Figure 2A), the conductive filler material 162 is formed in the opening 130, forming the conductive contacts 164. After formation, each conductive contact 164 extends throughout the entire vertical direction of the stack structure 156 without terminating on the step 122 of the stepped structure 120, as shown in Figure 2B. The conductive filler material 162 of the conductive contacts 164 is formed laterally adjacent to (e.g., directly adjacent laterally to) the conductive material 168 of the strap structure 166. The conductive filler material 162 may or may not have substantially the same material composition as the conductive material 168 of the conductive structure 152 of the strap structure 166 and the stack structure 156. In embodiments where the central portion of the lateral opening 131 remains open (e.g., empty) during the processing stage of Figure 2A, the conductive filler material 162 is formed in the central portion of the lateral opening 131, forming the strap structure 166 during (e.g., substantially simultaneously with) the formation of the conductive contact 164. When formed within the lateral opening 131, the conductive filler material 162 of the strap structure 166 is laterally adjacent to one or more of the conductive material 168 and the high dielectric constant dielectric material 172, and is at least partially (e.g., substantially) surrounded by them.

[0110] As shown in Figure 2B, the high dielectric constant dielectric material 172 and the conductive material 168 may remain within the microelectronic device structure 100'. In this case, the high dielectric constant dielectric material 172 at least partially (e.g., substantially) surrounds the conductive material 168, and the conductive material 168 at least partially (e.g., substantially) surrounds the conductive filler material 162 of the conductive contact 164. In another embodiment, one or more (e.g., all of each) of the high dielectric constant dielectric material 172 and conductive material 168 initially formed within the opening 130 (see Figure 2A) and / or the lateral opening 131 (see Figure 2A) are removed, and the conductive filler material 162 of the conductive contact 164 is configured to contact the dielectric filler material 126 and the material of the stack structure 156, similar to the previous embodiment.

[0111] By forming the conductive material 168 within the opening 130, the upper region of the opening 130 (see Figure 2A) is restricted (e.g., substantially isolated) during the replacement gate processing operation, facilitating the formation of the strap structure 166 when forming the conductive structure 152 of the stack structure 156. Thus, the strap structure 166 is formed during the formation of the conductive structure 152, reducing costs and the number of steps performed. Because the opening 130 is restricted during the replacement gate processing operation using the conductive material 168, there is no need to form additional mask material to protect the material of the opening 130 in subsequent processing of the microelectronic device structure 100', thereby further reducing costs and the number of steps.

[0112] Referring to Figure 2C, the microelectronic device structure 100' is formed with a configuration that includes features (e.g., structure, materials) substantially similar to those (e.g., structure, materials) of the microelectronic device structure 100' up to the processing stage described in relation to Figure 2B. For example, the microelectronic device structure 100' in Figure 2C is formed with a stack structure 156 including layers 158 of conductive structures 152 arranged alternately perpendicular to an insulating structure 104. The conductive contact 164 each separately includes a first portion 164a electrically connected to the source layer 110 and a second portion 164b corresponding to a strap structure 166 electrically connected to the first portion 164a in each step 122 of the stepped structure 120.

[0113] The conductive contact 164 and the strap structure 166 are substantially the same as the conductive filler material 162 of the conductive contact 164, the conductive material 168 of the conductive structure 152 and the strap structure 166, and the high dielectric constant dielectric material 172 of the microelectronic device structure 100' up to the processing stage described in relation to Figure 2B, and are formed in substantially the same manner as them. Therefore, the method for forming the microelectronic device structure 100' up to the processing stage shown in Figure 2C is the same as the processing stage and features described above with respect to the formation of the microelectronic device structure 100' up to the processing stage described in relation to Figure 2B.

[0114] Additional processes (e.g., material formation processes) may be optionally used to form multiple thicknesses of the strap structure 166 shown in Figure 2C. In the embodiment of Figure 2B, the strap structure 166 is formed to have a substantially uniform (e.g., substantially constant) second thickness T2 (see Figure 2D) along its lateral dimension. On the other hand, in the embodiment of Figure 2C, the strap structure 166 is formed to have multiple (e.g., two or more) thicknesses along its lateral dimension. For example, a conductive pad structure 176 is provided on the tread surface of each step 122 of the stepped structure 120, and this conductive pad structure 176 includes a first portion 176a having a second thickness T2 and a second portion 176b having a third thickness T3 that is relatively greater than the second thickness T2 of the first portion 176a. In some embodiments, the second thickness T2 of the first portion 176a corresponds to the thickness of the conductive structure 152 (for example, in the range of about 15 nm to about 20 nm), and the third thickness T3 of the second portion 176b is in the range of about 1.5 to about 3 times (for example, about 2 times) the second thickness T2 of the first portion 176a. However, the disclosure is not limited thereto, and the second thickness T2 and the third thickness T3 may be different values ​​from those described above.

[0115] As shown in Figure 2C, the first portion 176a of the conductive pad structure 176 is laterally adjacent to (e.g., in direct contact with) the upper conductive structure 152a, and the second portion 176b is laterally adjacent to (e.g., in direct contact with) the first portion 176a. Each conductive contact 164 is laterally separated from the first portion 176a by a portion of the second portion 176b. Furthermore, in a certain step 122, the upper conductive structure 152a is laterally separated from the second portion 176b by the first portion 176a. On the other hand, there may also be a configuration in which the upper conductive structure 152a is laterally adjacent to (e.g., in direct contact with) the second portion 176b without the interposition of the first portion 176a. In some embodiments, the conductive pad structure 176 (including the first portion 176a and the second portion 176b) is configured to include the conductive filler material 162 of the conductive contact 164, but not the high dielectric constant dielectric material 172 and the conductive material 168 of the conductive structure 152. In another embodiment, the first portion 176a and a portion of the adjacent second portion 176b include the conductive material 168 of the upper conductive structure 152a, and an additional portion of the second portion 176b located at the end of step 122 includes the conductive filler material 162 of the conductive contact 164 (illustrated in the strap structure 166 on the right side of Figure 2C). In such embodiments, the first portion 176a and a portion of the adjacent second portion 176b include the high dielectric constant dielectric material 172.

[0116] The first portion 176a and the second portion 176b each form a substantially "L-shaped" structure of the strap structure 166 in each step 122. As shown in Figure 2C, the relatively thicker (e.g., having a third thickness T3) second portion 176b substantially surrounds the conductive contact 164. In some embodiments, the lateral end face of the second portion 176b and the lateral end face of the uppermost insulating structure 104a located below it are substantially perpendicular to each other (e.g., substantially coplanar). In another embodiment, the second portion 176b extends laterally beyond the horizontal boundary of at least one step 122 of the stepped structure 120 directly below it, and the lateral end face of the second portion 176b extends beyond the lateral end face of the uppermost insulating structure 104a, provided that the strap structure 166 is separated from other strap structures 166 in adjacent steps 122 by at least a predetermined distance (e.g., about 20 nm or more).

[0117] The multilayer thickness configuration of the conductive pad structure 176 is formed to substantially reduce (e.g., substantially prevent) damage within the stepped structure 120 during manufacturing. For example, before performing the gate replacement process, the additional insulating structure 106 (see Figure 1D) of the preliminary stack structure 102 (see Figure 1D) is formed on step 122 of the stepped structure 120 to include a dielectric pad structure (a so-called "mesa nitride film" structure) on top of the additional insulating structure 106 (e.g., a dielectric nitride structure). During the gate replacement process, these dielectric pad structures are also replaced with conductive material 168, thereby effectively increasing the thickness of a portion of the uppermost conductive structure 152a at step 122 of the stepped structure 120 and mitigating damage within the stepped structure 120. Furthermore, the shape of the strap structure 166, including the multilayer thickness configuration of the conductive pad structure 176, contributes to expanding the contact area with the conductive contact 164 at step 122. For example, the relatively large thickness of the second portion 176b of the conductive pad structure 176 can increase the surface area available for contact with the lateral side of the conductive contact 164. As a result, the RC value (product of resistance and capacitance) of the conductive contact 164 and the strap structure 166 is improved.

[0118] The conductive contact 164 and strap structure 166, including the conductive pad structure 176 in Figure 2C, are illustrated to be formed in substantially the same manner as the processing steps in Figures 2A and 2B for clarity and ease of understanding of the drawings and related descriptions. However, the conductive pad structure 176 of the conductive contact 164 and strap structure 166 in Figure 2C may be formed in substantially the same manner as the processing steps in Figures 1A to 1I. For example, the conductive pad structure 176 of the strap structure 166 may be formed to include the conductive filler material 162 formed when the conductive contact 164 is formed, but not the conductive material 168 and high dielectric constant dielectric material 172 formed when the conductive structure 152 is formed.

[0119] Figure 2D shows a magnified portion of box D in Figure 2B, and is an embodiment of the microelectronic device structure 100' of Figure 2B. For clarity and ease of understanding of the drawings and related descriptions, the surrounding materials, including the dielectric filler material 126, are not shown in Figure 2D. Similar to the previous embodiment, the conductive structure 152 in Figure 2D includes a conductive material 168 and may also optionally include one or more conductive liner materials 170 and high dielectric constant dielectric materials 172. Since the strap structure 166 is formed at the same time as the conductive structure 152, the strap structure 166 also includes a conductive material 168 and may also optionally include conductive liner materials 170 and high dielectric constant dielectric materials 172. For example, the high dielectric constant dielectric material 172 is positioned to at least partially (e.g., substantially) surround the conductive material 168 of the strap structure 166. The high dielectric constant dielectric material 172 may also at least partially (e.g., substantially) surround the conductive material 168 of the conductive contact 164 laterally.

[0120] In some embodiments, the high dielectric material 172 is formed with varying thickness (e.g., non-uniform) so that the conductive contacts 164 and strap structures 166 are only partially surrounded by the high dielectric material 172. In other embodiments, as shown in Figure 2D, a substantially continuous portion of the high dielectric material 172 is formed to surround the conductive material 168 of each conductive contact 164 and strap structure 166. For example, at least a large portion (e.g., more than 50%, preferably about 75%, about 90%, or about 99%) of the conductive material 168 of each conductive contact 164 and strap structure 166 is substantially surrounded by the high dielectric material 172. The high dielectric material 172 may be configured to substantially (e.g., entirely) surround the strap structure 166 on three continuous surfaces, including the top, bottom, and outer lateral sides of the strap structure 166. The presence of the high dielectric constant dielectric material 172 adjacent to the uppermost conductive structure 152a and the strap structure 166 can reduce parasitic (e.g., stray) capacitance between adjacent conductive features during use and operation of the microelectronic device structure 100'.

[0121] As shown in Figure 2D, the sides of the conductive contact 164 (e.g., the lateral side) are adjacent to and in physical contact with the inner lateral side surfaces of the strap structure 166 in the lateral direction, improving metal-to-metal contact along the interface 178 (e.g., the vertical interface). Because the conductive contact 164 is formed in direct contact with the strap structure 166 in the lateral direction, the conductive liner material 170 and the high dielectric constant dielectric material 172 are not interposed between the conductive contact 164 and the strap structure 166 in the lateral direction (e.g., the horizontal direction). Therefore, a portion of the conductive contact 164 is formed in direct adjacency (e.g., in the X or Y direction) of the strap structure 166 in each step 122. In another embodiment, at least one material (e.g., the conductive liner material 170) may be interposed horizontally between the conductive contact 164 and the strap structure 166. In either case, the conductive contact 164 is formed in direct adjacency with the strap structure 166.

[0122] During the fabrication of the microelectronic device structure 100', a region 180 (e.g., a lateral seam) is formed within the conductive filler material 162 of the conductive contact 164 within the strap structure 166. Region 180 may arise from the material formation (e.g., deposition) process used to form the conductive filler material 162 of the conductive contact 164. For example, as shown in Figure 2D, region 180 may include a laterally extending seam within a portion (e.g., an intermediate portion) of the strap structure 166 adjacent to (e.g., substantially surrounding) the conductive contact 164. Region 180 may at least partially result from the formation of a portion of the conductive material 168 within the opening 130 of the conductive contact 164 (see Figure 2A) when forming the conductive material 168 of the conductive structure 152. As a result of the conductive material 168 being formed before the conductive filler material 162 of the conductive contact 164 is formed, the region 180 of the conductive filler material 162 may have a shape that protrudes horizontally outward from adjacent portions of the conductive filler material 162 within the conductive contact 164 (for example, portions that extend vertically).

[0123] One or more of the high dielectric constant dielectric material 172 and the conductive liner material 170 may be interposed vertically between the uppermost conductive structure 152a and the uppermost insulating structure 104a. Furthermore, one or more of the high dielectric constant dielectric material 172 and the conductive liner material 170 may be interposed horizontally between the conductive contact 164 and the insulating structure 104 (e.g., the uppermost insulating structure 104a) located vertically directly below the strap structure 166, and may also be interposed horizontally between the conductive contact 164 and the dielectric filling material 126 located vertically directly above the strap structure 166.

[0124] As shown in Figure 2D, the first portion 164a and the second portion 164b of the conductive contact 164 may be configured to have different material compositions. Therefore, the material composition of the strap structure 166 corresponding to the second portion 164b may be different from the material composition of the conductive contact 164 (e.g., the first portion 164a). The conductive filler material 162 of the conductive contact 164 may be formed directly adjacent to the conductive material 168 of the strap structure 166. Alternatively, in an embodiment in which the conductive filler material 162 is formed in the central portion of the lateral opening 131 (see Figure 2A) during the formation of the conductive contact 164 to form the strap structure 166, the conductive contact 164 and the strap structure 166 may each be configured to include the conductive filler material 162 in their central portions.

[0125] Similar to the embodiments described above, the second thickness T2 of the strap structure 166, which includes the conductive liner material 170 and the high dielectric constant dielectric material 172, may be configured to be relatively larger than the first thickness T1 of the conductive material 168. Since the strap structure 166 shown in Figure 2D is formed during the formation of the conductive structure 152, both the first thickness T1 of the conductive material 168 and the second thickness T2 of the strap structure 166 are substantially uniform (e.g., substantially constant) along the lateral dimensions of the strap structure 166.

[0126] As shown in Figure 2D, the lateral dimensions (e.g., width) of the individual conductive contacts 164, including the first portion 164a and the second portion 164b, are substantially identical (e.g., substantially equal) to the second width W2 of step 122. Thus, the strap structure 166 is perpendicularly adjacent to (e.g., in direct contact with) the uppermost insulating structure 104a, and the strap structure 166 extends laterally across the entire uppermost insulating structure 104a in each step 122 of the stepped structure 120. As a non-limiting example, the width of the conductive contacts 164 is in the range of approximately 600 nm to approximately 1200 nm, for example, approximately 600 nm to approximately 800 nm, approximately 800 nm to approximately 1000 nm, or approximately 1000 nm to approximately 1200 nm. The third width W3 of the liner material 134 in the insulating region 132 is relatively smaller than the additional width of the strap structure 166 corresponding to the second width W2 of step 122. Therefore, the strap structure 166 has a relatively large area in each step 122 of the stepped structure 120 of the microelectronic device structure 100' compared to the configuration of conventional microelectronic device structures. As a result, the RC (resistance-capacitance product) of the conductive contacts 164 and the strap structure 166 is improved, which can contribute to improved performance of the device including the microelectronic device structure 100'. In addition, the presence of the high dielectric constant dielectric material 172 adjacent to the uppermost conductive structure 152a can reduce parasitic capacitance (e.g., stray capacitance) between adjacent conductive features during use and operation of the microelectronic device structure 100'.

[0127] Figure 3 is a simplified partial cutaway perspective view showing a portion of a microelectronic device 201 (a memory device such as a dual-deck 3D NAND flash memory device) including a microelectronic device structure 200. The microelectronic device structure 200 is substantially similar to the microelectronic device structures 100, 100' after the processing steps described above in relation to Figures 1G and 2B. As shown in Figure 3, the microelectronic device structure 200 has a stepped structure 220 (e.g., including the stepped structure 120 in Figures 1G and 2B) that defines a contact area for directly connecting a conductive contact 206 (e.g., corresponding to the conductive contact 164 in Figures 1G and 2B) to a conductive layer 205 (e.g., a conductive layer, conductive plate, corresponding to the conductive structure 152 in Figures 1G and 2B). The microelectronic device structure 200 includes a vertical string 207 of memory cells 203 connected in series. The vertical string 207 extends perpendicularly (e.g., in the Z direction) to and orthogonal to the data line 202, source layer 204 (e.g., source layer 110 in Figures 1G and 2B), conductive layer 205, first selection gate 208 (e.g., upper selection gate, drain-side selection gate (SGD)), selection line 209, and second selection gate 210 (e.g., lower selection gate, source-side selection gate (SGS)). The microelectronic device 201 comprises a plurality of blocks 232 (e.g., block structure 146 in Figure 1E), which are spaced apart from each other horizontally (e.g., in the X direction) and partitioned by slot structures 230 (e.g., slot 144 in Figure 1E) filled with dielectric material 148 (Figure 1E).

[0128] Conductive contacts 213 and additional conductive contacts 211 may electrically connect components to each other, as shown in the figure. For example, selection line 209 is electrically connected to first selection gate 208. The microelectronic device 201 may further include a control unit 212 below the horizontal region of the memory array, which includes the vertical strings 207 of memory cells 203. The control unit 212 includes control logic devices configured to control various operations of other features of the microelectronic device 201 (e.g., the vertical strings 207 of memory cells 203). In a non-limiting example, the control unit 212 may include a charge pump (e.g., V CCPThe control unit 212 may include one or more (e.g., all) chip / deck control circuits, such as a charge pump (VNEGWL charge pump, DVC2 charge pump), a delay-locked loop (DLL) circuit (e.g., a ring oscillator), a Vdd regulator, a driver (e.g., a string driver), a decoder (e.g., a local deck decoder, a column decoder, a row decoder), a sense amplifier (e.g., an EQ amplifier, an ISO amplifier, an NMOS sense amplifier (NSA), a PMOS sense amplifier (PSA)), a repair circuit (e.g., a column repair circuit, a row repair circuit), an I / O device (e.g., a local I / O device), a memory test device, a MUX, an error detection and correction (ECC) device, a self-refresh / wear leveling device, and other chip / deck control circuits. The control unit 212 is electrically connected to, for example, data lines 202, a source layer 204, conductive contacts 206, a first selection gate 208, and a second selection gate 210. In some embodiments, the control unit 212 includes CMOS (complementary metal-oxide-semiconductor) circuitry. In such embodiments, the control unit 212 is characterized as a "CMOS under Array (CuA)" configuration, i.e., a configuration in which the CMOS circuits of the logic region are at least partially (e.g., substantially) located within the horizontal region of the memory array region of the microelectronic device, which includes the microelectronic device structures 100, 100'. The conductive filler material 162 (Figures 1G and 2B) of the conductive contact 164 (Figures 1G and 2B) and the conductive material of the strap structure 166 (Figures 1G and 2B) (e.g., conductive filler material 162, conductive material 168 (Figure 2D)) may be connected (e.g., electrically connected) to the logic circuits of the control unit 212 located below the source layer 204, while the additional conductive layer 205 below the steps of the stepped structure 220 is not connected to the logic circuits. Thus, the strap structure 166 is connected to conductive features in the source layer 204 (e.g., the logic circuits of the control unit 212) via the conductive contact 164.

[0129] The source structure 218 of the source layer 204 (for example, corresponding to the source structure 118 in Figure 1B) may be electrically isolated from other parts (for example, other parts that function as conductive wiring structures 217 (for example, corresponding to the conductive wiring structure 117 in Figure 1B)). The conductive wiring structure 217 electrically connects its components (for example, conductive contacts 206 and the source structure 218) to the circuit of the control unit 212.

[0130] The first selection gate 208 extends horizontally in a first direction (e.g., the Y direction) and connects to a first group of memory cells 203 in the vertical string 207 at its first end (e.g., the upper end). The second selection gate 210 is formed in a substantially planar configuration and connects to the vertical string 207 of memory cells 203 at a second opposite end (e.g., the lower end) of the vertical string 207.

[0131] A data line 202 (e.g., a bit line) extends horizontally in a second direction (e.g., the X direction) that forms an angle (e.g., a right angle) with respect to the first direction in which the first selection gate 208 extends. Each data line 202 is connected to the first end (e.g., the upper end) of a vertical string 207 belonging to a second group of vertical strings 207. The vertical strings 207 of the first group connected to each first selection gate 208 may share certain vertical strings 207 with the vertical strings 207 of the second group connected to each data line 202. Therefore, a specific vertical string 207 is selected at the intersection of a specific first selection gate 208 and a specific data line 202. Thus, the first selection gate 208 is used to select memory cells 203 included in the vertical strings 207.

[0132] Each conductive layer 205 (e.g., a word line plate; conductive structure 152 in Figures 1G and 2B) extends in a horizontal plane. The conductive layers 205 are stacked vertically, and each conductive layer 205 is connected to the vertical string 207 of all memory cells 203, the vertical string 207 of the memory cells 203 extending vertically through the stack of conductive layers 205. The conductive layer 205 can be connected to, or constitute, the control gate of the memory cell 203 to which it is connected. Each conductive layer 205 is connected to one memory cell 203 belonging to a particular vertical string 207 of the memory cell 203.

[0133] The first selection gate 208 and the second selection gate 210 perform the operation of selecting a vertical string 207 of a specific memory cell 203 between a specific data line 202 and the source layer 204. Thus, by operating (e.g., selecting) the appropriate first selection gate 208, second selection gate 210, and the conductive layer 205 connected to the specific memory cell 203, the specific memory cell 203 is selected and electrically connected to the data line 202.

[0134] The stepped structure 220 is configured to provide a direct electrical connection between the conductive contact 206 and the conductive layer 205. Thus, a particular conductive layer 205 is selected via the conductive contact 206 to which it is electrically connected. The data line 202 is electrically connected to the vertical string 207 via the conductive contact structure 234.

[0135] Accordingly, according to embodiments of the present disclosure, a method for forming a microelectronic device includes the step of forming a pre-stack structure on a source structure. The pre-stack structure includes a vertically alternating sequence of insulating material and sacrificial material arranged in a pre-stack. The method includes the steps of forming a stepped structure having steps including the edges of at least some of the pre-stacks of the pre-stack structure; forming an implant region within the exposed portion of sacrificial material in the steps of the stepped structure; forming an opening in the horizontal region of the stepped structure that penetrates the pre-stack structure and reaches the source structure; replacing some of the sacrificial material with a conductive structure; forming a strap structure containing conductive material laterally adjacent to the conductive structure in the steps of the stepped structure at a location left open by the implant region; and forming a conductive contact containing conductive material within the opening.

[0136] Furthermore, according to other embodiments of the present disclosure, a method for forming a microelectronic device includes the step of forming a stack structure on a source layer comprising one or more conductive structures. The stack structure comprises a plurality of layers, each comprising an insulating material and additional insulating material perpendicularly adjacent to the insulating material. The method includes the step of forming a stepped structure within the stack structure, the stepped structure having steps that include the lateral edges of the layers of the stack structure. Furthermore, the method includes the steps of forming a sacrificial material comprising one or both boron and carbon within the exposed portion of the uppermost additional insulating material in the steps, forming an opening that penetrates the stack structure and extends into the horizontal region of the stepped structure (the opening extends through the sacrificial material). The method also includes the steps of removing the additional insulating material to form a cell opening, removing the sacrificial material to form a lateral opening communicating with the opening, forming a conductive material within the cell opening and the lateral opening, and forming conductive contacts within the opening. The conductive material is electrically connected to one or more conductive structures in the source layer via the conductive contacts.

[0137] Furthermore, according to other embodiments of the present disclosure, a microelectronic device comprises a stack structure on a source layer. The stack structure includes a vertically alternating sequence of conductive and insulating structures arranged in multiple layers. The microelectronic device comprises a stepped structure provided within the stack structure, the stepped structure having steps including the lateral edges of the layers. The microelectronic device also includes conductive contacts provided within the horizontal region of the stepped structure, penetrating the stack structure vertically to reach the source layer, and strap structures provided within the horizontal region of each step of the stepped structure, directly interposed laterally between the conductive structure of each layer and the conductive contacts. The strap structures are electrically connected to conductive features in the source layer via the conductive contacts.

[0138] A microelectronic device (e.g., microelectronic device 201) including the microelectronic device structures of this disclosure (e.g., microelectronic device structures 100, 100', 200) may be incorporated into embodiments of the electronic systems of this disclosure. For example, Figure 4 is a schematic block diagram of an electronic system 303 according to an embodiment of this disclosure. The electronic system 303 may include, for example, a computer or its hardware components, a server or other network hardware components, a mobile phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a tablet with Wi-Fi or cellular communication capabilities (e.g., an iPad® or Surface® tablet), an e-reader, a navigation device, and the like. The electronic system 303 includes at least one memory device 305. The memory device 305 may include, for example, one embodiment of the microelectronic device structures described herein (e.g., microelectronic device structures 100, 100', 200) described herein in relation to Figures 1A to 2D and Figure 3, or one embodiment of the microelectronic device described herein in relation to Figure 3 (e.g., microelectronic device 201).

[0139] The electronic system 303 may further include at least one electronic signal processor device 307 (often referred to as a “microprocessor”). The electronic signal processor device 307 may optionally include one or more embodiments of the microelectronic devices and microelectronic device structures described herein. The electronic system 303 may further include one or more input devices 309 for a user to input information into the electronic system 303. Examples of input devices 309 include a mouse or other pointing device, a keyboard, a touchpad, buttons, an operating panel, etc. The electronic system 303 may further include one or more output devices 311 for outputting information (e.g., visual or auditory information) to the user. Examples of output devices 311 include a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input devices 309 and output devices 311 may constitute a single touchscreen device that can be used for both inputting information into the electronic system 303 and outputting visual information to the user. The input device 309 and the output device 311 may communicate electrically with one or more of the memory device 305 and the electronic signal processor device 307.

[0140] Referring to Figure 5, a processor-based system 400 is shown. The processor-based system 400 includes one or more of the microelectronic devices and microelectronic device structures described herein, which may be manufactured according to embodiments of the disclosure. The processor-based system 400 can be of various types, such as a computer, pager, mobile phone, personal organizer, control circuit, or other electronic device. The processor-based system 400 may include one or more processors 402, such as a microprocessor, which control system functions and processing of requests. The processors 402 and other subcomponents of the processor-based system 400 may include one or more of the microelectronic devices or microelectronic device structures described herein, which may be manufactured according to embodiments of the disclosure.

[0141] The processor-based system 400 may include a power supply 404 operably connected to the processor 402. For example, if the processor-based system 400 is a portable system, the power supply 404 may include one or more of a fuel cell, an energy recovery device, a primary battery, a replaceable battery, and a rechargeable battery. The power supply 404 may include an AC adapter, in which case the processor-based system 400 can be connected, for example, to a wall outlet. Alternatively, the power supply 404 may include a DC adapter, in which case the processor-based system 400 can be connected, for example, to a vehicle's cigarette lighter or vehicle power port.

[0142] Depending on the functions performed by the processor-based system 400, various other devices may be connected to the processor 402. For example, a user interface 406 may be connected to the processor 402. The user interface 406 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. A display device 408 may also be connected to the processor 402. The display device 408 may include LCD displays, SED displays, CRT displays, DLP displays, plasma displays, OLED displays, LED displays, three-dimensional projections, voice displays, or combinations thereof. Furthermore, an RF subsystem / baseband processor 410 may also be connected to the processor 402. The RF subsystem / baseband processor 410 may include an antenna connected to an RF receiver and an RF transmitter (not shown). Also, one or more communication ports 412 may be connected to the processor 402. The communication port 412 may be configured to connect to one or more peripheral devices 414 such as a modem, printer, computer, scanner, or camera, or to a network such as a local area network, remote area network, intranet, or the Internet.

[0143] The processor 402 controls the processor-based system 400 by executing software programs stored in memory. These software programs may include, for example, an operating system, database software, drawing software, word processing software, media editing software, or media playback software. Memory is connected to the processor 402 to facilitate the storage and execution of various programs. For example, the processor 402 may be connected to system memory 416. System memory 416 may include one or more of the following known memory types: spin-torque transfer magnetoresistive memory (STT-MRAM), magnetoresistive memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, or other known memory types. System memory 416 may also include volatile memory, non-volatile memory, or a combination thereof. System memory 416 is typically configured to have a large capacity to store dynamically loaded applications and data. In some embodiments, system memory 416 may include semiconductor devices such as one or more of the microelectronic devices and microelectronic device structures described herein.

[0144] The processor 402 may also be connected to non-volatile memory 418, but this does not necessarily imply that the system memory 416 is volatile. The non-volatile memory 418 may include one or more of the following: read-only memory (ROM) such as STT-MRAM, MRAM, EPROM, resistive read-only memory (RROM), and flash memory, and may be used in conjunction with the system memory 416. The capacity of the non-volatile memory 418 is typically set to be large enough to store the necessary operating system, application programs, and fixed data. Furthermore, the non-volatile memory 418 may include high-capacity memory such as disk drive memory, such as a hybrid drive, which includes resistive memory or other types of non-volatile solid-state memory. The non-volatile memory 418 may include microelectronic devices such as one or more of the microelectronic devices and microelectronic device structures described herein.

[0145] Some embodiments relating to this disclosure may be further characterized, without limitation, as shown below.

[0146] Embodiment 1: A method for forming a microelectronic device, comprising the following steps: forming a pre-stack structure on a source structure, the pre-stack structure having a stepped portion including the edge of at least a portion of the pre-stack structure, the pre-stack structure having a stepped portion including a vertically alternating sequence of insulating material and sacrificial material arranged in the pre-stack structure; forming an implant region within an exposed portion of sacrificial material in the stepped portion of the stepped structure; forming an opening that reaches the source structure through the pre-stack structure and extends within the horizontal region of the stepped structure; replacing a portion of the sacrificial material with a conductive structure; forming a strap structure containing a conductive material laterally adjacent to the conductive structure in the stepped portion of the stepped structure at a location vacated by the implant region; and forming a conductive contact containing a conductive material within the opening.

[0147] Embodiment 2: A method according to Embodiment 1, further comprising the step of forming a sacrificial nitride material in an opening, wherein the step of replacing a portion of the sacrificial material with a conductive structure includes the step of removing the sacrificial nitride material from the opening when removing the sacrificial material from the cell opening between insulating materials of the pre-stack structure.

[0148] Embodiment 3: A method according to Embodiment 1 or Embodiment 2, wherein the step of forming an implant region includes forming an implant region within the exposed portion of the uppermost sacrificial material in the step of a staircase structure, and not forming an implant region within additional sacrificial material located vertically below the uppermost sacrificial material.

[0149] Embodiment 4: A method according to any one of Embodiments 1 to 3, wherein the step of forming an implant region includes the step of injecting boron, carbon, oxygen, gallium, or a combination thereof into a nitride material of sacrificial material in the steps of a step structure.

[0150] Embodiment 5: A method according to any one of Embodiments 1 to 4, wherein the step of replacing a portion of the sacrificial material with a conductive structure includes, in a single process operation, the step of removing the sacrificial material of the pre-stack structure and the boron-doped or carbon-doped nitride material of the implant area.

[0151] Embodiment 6: A method according to any one of Embodiments 1 to 5, further comprising the step of forming a lateral opening communicating with an opening, each of which lateral openings is located at the height of one of the stepped portions, and the step of forming a conductive structure comprising forming a high dielectric constant dielectric material adjacent to the conductive structure, but not forming the high dielectric constant dielectric material within the lateral opening.

[0152] Embodiment 7: A method for forming a microelectronic device, comprising the following steps: forming a stack structure on a source layer comprising one or more conductive structures, wherein the stack structure comprises layers each comprising an insulating material and additional insulating materials perpendicularly adjacent thereto; forming a staircase structure within the stack structure, wherein the staircase structure has steps including the lateral edges of the layers of the stack structure; forming a sacrificial material comprising one or a combination thereof of boron and carbon within the uppermost layer of additional insulating material exposed at the steps; forming an opening that penetrates the stack structure to the source layer, extends within the horizontal region of the staircase structure, and further penetrates the sacrificial material; removing the additional insulating material to form a cell opening; removing the sacrificial material to form a lateral opening communicating with the opening; forming a conductive material within the cell opening and the lateral opening; and forming a conductive contact within the opening, wherein the conductive material is connected to one or more conductive structures on the source layer via the conductive contact.

[0153] Embodiment 8: A method according to Embodiment 7, further comprising the step of forming one or a combination thereof of a high dielectric constant dielectric material and a conductive liner material adjacent to an insulating material of a stack structure, wherein one or a combination thereof of the high dielectric constant dielectric material and the conductive liner material is interposed vertically between the insulating material and the conductive material of the stack structure, and horizontally between the conductive contact and the insulating material.

[0154] Embodiment 9: A method according to Embodiment 7 or Embodiment 8, wherein the step of forming a conductive material in a cell opening and a lateral opening includes the step of forming an additional portion of the conductive material in the opening.

[0155] Embodiment 10: A method according to any one of Embodiments 7 to 9, further comprising the steps of forming a dielectric material on a stack structure to seal an opening before forming a conductive material in the cell opening and the lateral opening, and forming a conductive material in the opening without completely filling the opening.

[0156] Embodiment 11: A method according to any one of Embodiments 7 to 10, wherein the step of forming a conductive contact includes the step of forming additional conductive material at a position directly adjacent laterally to the conductive material in a lateral opening.

[0157] Embodiment 12: A method according to any one of Embodiments 7 to 11, wherein the step of removing additional insulating material includes a step of substantially simultaneously removing the doped nitride material of the sacrificial material when forming a cell opening to form a lateral opening.

[0158] Embodiment 13: A microelectronic device comprising a stack structure, the stack structure being formed on a source layer and comprising a vertically alternating sequence of conductive and insulating structures arranged in stepped layers, further comprising a staircase structure, the staircase structure being formed within the stack structure and having stepped portions including the lateral edges of the layers, conductive contacts arranged within the horizontal region of the stack structure and extending vertically to reach the source layer, and a strap structure arranged within the horizontal region of the stepped portion of the staircase structure and directly interposed laterally between one of the conductive contacts and one conductive structure of the layers of the stack structure, wherein the strap structure is electrically connected to conductive features in the source layer via the conductive contacts.

[0159] Embodiment 14: A microelectronic device according to Embodiment 13, further comprising a high dielectric constant dielectric material adjacent to the insulating structure of the stack structure, wherein the high dielectric constant dielectric material substantially surrounds the strap structure on three consecutive sides.

[0160] Embodiment 15: A microelectronic device according to Embodiment 13 or Embodiment 14, wherein a strap structure substantially surrounds a conductive contact laterally, and the conductive material of the conductive structure of the stacked layers substantially surrounds each strap structure laterally.

[0161] Embodiment 16: A microelectronic device according to any one of Embodiments 13 to 15, wherein the conductive contact comprises a portion of the conductive material of a stacked conductive structure that at least partially surrounds additional conductive material laterally.

[0162] Embodiment 17: A microelectronic device according to any one of Embodiments 13 to 16, wherein the conductive contacts extend vertically through the stack structure from the top surface of the stack structure to an additional conductive structure in the source layer, and each conductive contact exhibits substantially the same vertical height.

[0163] Embodiment 18: A microelectronic device according to any one of Embodiments 13 to 17, wherein the strap structure includes a conductive pad structure on the steps of a staircase structure, the conductive pad structure includes a first portion laterally adjacent to the conductive structure and a second portion laterally adjacent thereto and relatively thicker, the second portion substantially laterally surrounding a conductive contact.

[0164] Embodiment 19: A microelectronic device according to any one of Embodiments 13 to 18, wherein the strap structure is arranged adjacent to one of the insulating structures of the layers of the stack structure in a perpendicular direction.

[0165] Embodiment 20: A microelectronic device according to any one of Embodiments 13 to 19, wherein the material composition of the strap structure is substantially the same as the material composition of the conductive structure of the stack structure, and the material composition of the conductive contacts is different from the material composition of each strap structure and conductive structure.

[0166] While specific embodiments have been described herein with reference to the drawings, those skilled in the art will understand and recognize that the embodiments included in this disclosure are not limited to those expressly shown and described herein. Rather, many additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments included in this disclosure, including those that may be claimed in the future, including legal equivalents. Furthermore, features of one disclosed embodiment combined with features of another disclosed embodiment are also included within the scope of this disclosure.

Claims

1. A method for forming a microelectronic device, comprising the following steps: A step of forming a pre-stack structure on a source structure, wherein the pre-stack structure includes a vertically alternating sequence of insulating material and sacrificial material arranged in a pre-layer, A step of forming a staircase structure having a stepped portion including the edge of at least a portion of the pre-stack structure, The process of forming an opening that reaches the source structure through the aforementioned pre-stack structure and extends within the horizontal region of the staircase structure, A process of replacing part of the sacrificial material with a conductive structure, A step of forming a strap structure containing a conductive material at a position adjacent laterally to a conductive structure in the step portion of a staircase structure, A step of forming a conductive contact containing a conductive material within an opening, A method that includes this.

2. A method according to claim 1, further comprising the step of forming a sacrificial nitride material in an opening, wherein the step of replacing a portion of the sacrificial material with a conductive structure includes removing the sacrificial nitride material from the opening when removing the sacrificial material from the cell opening between the insulating materials of the pre-stack structure.

3. A method according to claim 1 or claim 2, further comprising the step of forming an implant region within an exposed portion of sacrificial material in a step of a staircase structure, wherein the step of forming the implant region includes forming the implant region within an exposed portion of the uppermost sacrificial material in a step of a staircase structure, and not forming the implant region within additional sacrificial material located vertically below the uppermost sacrificial material.

4. A method according to claim 3, wherein the step of forming the implant region comprises injecting boron, carbon, oxygen, gallium, or a combination thereof into a sacrificial nitride material at the steps of a staircase structure.

5. A method according to claim 3, wherein the step of replacing a portion of the sacrificial material with a conductive structure includes removing the sacrificial material of the pre-stack structure and the boron-doped or carbon-doped nitride material of the implant region in a single process step.

6. A method according to claim 1 or claim 2, The process further includes forming a lateral opening that communicates with the opening, wherein each lateral opening is located at one height level of the step of the staircase structure. A method for forming a conductive structure, comprising forming a high-dielectric-constant dielectric material adjacent to the conductive structure, wherein the high-dielectric-constant dielectric material is not formed within a lateral opening.

7. A method according to claim 1, further comprising the step of forming a further sacrificial material containing one or both of boron and carbon within the exposed portion of the uppermost sacrificial material in the stepped portion.

8. A method according to claim 7, further comprising the step of forming one or more of a high dielectric constant dielectric material and a conductive liner material adjacent to an insulating material of a pre-stack structure, wherein one or more of the high dielectric constant dielectric material and the conductive liner material are interposed vertically between the conductive structure and the insulating material and horizontally between the conductive contact and the insulating material.

9. A method according to claim 7 or claim 8, further comprising the step of electrically connecting a strap structure to one or more conductive structures of a source structure via conductive contacts.

10. A method according to claim 7 or claim 8, Before forming the conductive structure, a step is made to form a dielectric material on the pre-stack structure to seal the openings, A step of forming a portion of the conductive material of the strap structure within the opening without completely filling the opening, Methods that further include the above.

11. A method according to claim 7 or claim 8, wherein the step of forming a conductive contact includes the step of forming an additional conductive material at a position directly adjacent laterally to the conductive material of the strap structure.

12. A method according to claim 7 or claim 8, further comprising the step of substantially simultaneously removing doped nitride material of additional sacrificial material when removing sacrificial material of a preliminary stack structure.

13. A microelectronic device, The stack structure is located on top of the source layer, and the stack structure has layers comprising a vertically alternating sequence of conductive and insulating structures arranged in layers. The stack structure includes a staircase structure, and the staircase structure has steps including the lateral edges of the layers. The structure comprises conductive contacts located within the horizontal region of the staircase structure and extending vertically through the stack structure to reach the source layer, The strap structure is located within the horizontal region of the step portion of the aforementioned staircase structure and is directly interposed laterally between one of the conductive structures and one of the conductive contacts in the layers of the stack structure, The strap structure is electrically connected to the conductive feature in the source layer via the conductive contact. Microelectronic devices.

14. A microelectronic device according to claim 13, further comprising a high dielectric constant dielectric material adjacent to an insulating structure of a stack structure, wherein the high dielectric constant dielectric material substantially surrounds three consecutive sides of the strap structure.

15. A microelectronic device according to claim 13, The strap structure substantially surrounds the conductive contacts laterally. The conductive material of the layered conductive structure in the stacked structure substantially surrounds each strap structure laterally. Microelectronic devices.

16. A microelectronic device according to any one of claims 13 to 15, wherein the conductive contact includes a portion of the conductive material of a stacked conductive structure, at least partially surrounding the additional conductive material laterally.

17. A microelectronic device according to any one of claims 13 to 15, wherein the conductive contacts extend vertically through the stack structure from the top surface of the stack structure to an additional conductive structure within the source layer, and each conductive contact has substantially the same vertical height.

18. A microelectronic device according to any one of claims 13 to 15, wherein the strap structure includes a conductive pad structure on the steps of a staircase structure, the conductive pad structure includes a first portion laterally adjacent to the conductive structure and a second portion laterally adjacent to the first portion and having a relatively larger thickness, substantially surrounding a conductive contact laterally.

19. A microelectronic device according to any one of claims 13 to 15, wherein the strap structure is individually perpendicularly adjacent to one of the insulating structures among the layers of the stack structure.

20. A microelectronic device according to any one of claims 13 to 15, wherein the material composition of the strap structure is substantially the same as the material composition of the conductive structure of the stack structure, and the material composition of the conductive contacts is different from the material composition of each strap structure and conductive structure.

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