Self-aligning contact structure and method for manufacturing the same

Abstract

Self-aligned contacts (SACs) and methods for manufacturing them are disclosed. In one embodiment, a field-effect transistor (FET) structure comprises a channel connecting a first source or drain (S / D) region to a second S / D region; a gate structure comprising a multilayer metal gate between gate spacers and positioned above the gate region that at least partially surrounds the channel; a self-aligned structure, also called a "hat," positioned above the gate structure and covering at least the multilayer metal gate and gate spacers; and a first S / D contact that is self-aligned to the hat and connected to the first S / D region. During manufacturing, a self-assembled monolayer (SAM) is used to precisely align the hat over the multilayer metal gate. The S / D contact is self-aligned to the hat even if the etching mask has overlay errors. The hat also shields the gate structure during etching.

Description

Technical Field

[0001] 1. Technical Field The present disclosure generally relates to semiconductor wafer processes, and more specifically, to self-aligned contact structures and methods of manufacturing the same.

[0002] 2. Description of Related Art As the size of semiconductor features is reduced, conventional manufacturing techniques may not have sufficient accuracy to avoid process errors resulting from feature misalignment. One example is the placement of source, drain, and gate contacts.

[0003] FIG. 1A shows a conventional contact structure. On an active substrate 100, one or more gate structures are fabricated as gate metal 102 between gate spacers 104. Source / drain (S / D) contacts 106 are formed by etching through dielectric oxide layer 108 to reach the active substrate 100. Properly aligned S / D contacts 106 are set at a distance 110 from the gate spacers as specified by the design rules.

[0004] FIG. 1B shows potential problems associated with the conventional contact structure. If the S / D contacts 106 are not properly aligned, for example due to misalignment of a photoresist mask, it results in contact between the gate spacers at point 112 of the S / D contacts 106, thereby increasing the parasitic capacitance between the source / drain and the gate. In severe cases, the S / D contacts 106 can create an electrical contact with the gate metal 102, resulting in a short circuit between the two terminals.

[0005] Figure 2A shows a conventional self-aligned contact (SAC). The active substrate 100, gate metal 102, and gate spacer 104 are substantially identical to the elements of similar number in Figures 1A and 1B, except that each gate structure also includes a hard mask 200 on top of the gate metal 102, and the S / D contact 202 fills the gap between the gate spacers 104, i.e., the S / D contact 202 is self-aligned on top of the gate structure.

[0006] Figure 2B illustrates potential problems associated with conventional SAC. Figure 2B shows the gate structure in more detail. In the example shown in Figure 2B, the gate structure includes a high-K dielectric 206 surrounding a work function metal (WFM) 208 surrounding a tungsten plug 210. The etching step in preparation for depositing the S / D contact 202 removes part of the hard mask 200 and gate spacer 104. If the hard mask 200 and gate spacer 104 are removed excessively, this allows the self-aligned S / D contact 202 to include additional metal 204 closer to the gate metal (i.e., WFM 208 and tungsten plug 210). Because the self-aligned S / D contact 202 is closer to the gate metal, this increases the parasitic capacitance between the S / D and the gate. Depending on how robust the hard mask 200 is, this capacitance can increase by more than 10%.

[0007] Figures 2C to 2E illustrate further potential problems associated with conventional SAC related to the etching step performed in preparation for the placement of the gate contact (GC) onto the gate metal 102. Figure 2C shows the result of an ideal etching process that generates a suitable recess depth and leaves a flat top surface for the high-K dielectric 206, WFM208, and tungsten plug 210. However, the actual etching result appears as shown in Figure 2D, showing “dishing” of the WFM208 and tungsten plug 210, resulting in a “horn” at the outer edge of the WFM208 when viewed in cross-section. The presence of the horn results in insufficient insulation against gate-contact short circuits (for example, due to the horn of the WFM208 being too close to the S / D contact at position 212). Worse still, the depth of the dishing effect and the height of the horn can vary based on the width and length of the particular gate structure, resulting in the resistance and capacitance values ​​of the gate WFM208 which can vary from FET to FET. Additional etching to remove the horns may result in the outcome shown in Figure 2E, and excessive etching, for example, could lead to damage to the WFM208 layer.

[0008] Therefore, conventional contacts typically require precise alignment of process layers, while self-aligning contacts typically require precise control of process steps. Thus, a better approach is needed that does not have the aforementioned drawbacks. [Overview of the Initiative]

[0009] The following provides a simplified overview of one or more embodiments disclosed herein. Therefore, this overview should not be considered a broad overview of all intended embodiments, nor should it be considered to identify the main or important elements of all intended embodiments, or to define the scope relevant to any particular embodiment. Accordingly, the sole purpose of this overview is to provide, in a simplified form, certain concepts relating to one or more embodiments of the mechanisms disclosed herein, prior to the detailed descriptions presented below.

[0010] In one embodiment, a field-effect transistor (FET) structure includes a channel connecting a first source or drain (S / D) region to a second S / D region; a gate structure disposed above a gate region that includes a multilayer metal gate between gate spacers and at least partially surrounds the channel; a self-aligning structure disposed above the gate structure and covering at least the multilayer metal gate and gate spacers; and a first S / D contact that is self-aligned to the self-aligning structure and connected to the first S / D region.

[0011] In one embodiment, a method for manufacturing an FET includes: providing a channel connecting a first S / D region to a second S / D region; providing a gate structure including a multilayer metal gate between gate spacers, positioned above a gate region that at least partially surrounds the channel, and embedded in a first oxide or dielectric (O / D) layer; providing a self-aligning structure positioned above the gate structure, covering at least the multilayer metal gate and gate spacers, and embedded in a second O / D layer positioned above the first O / D layer; and providing a first S / D contact that is self-aligned to the self-aligning structure and connected to the first S / D region.

[0012] Other purposes and advantages associated with the embodiments disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description.

[0013] By referring to the following detailed description, along with the accompanying drawings (where similar reference numbers represent similar parts) which are presented merely as examples and not to limit the disclosure, many aspects of this disclosure and their associated advantages will be better understood, and a more complete understanding thereof will be easily obtained. [Brief explanation of the drawing]

[0014] [Figure 1A] This diagram shows a conventional contact structure. [Figure 1B] This diagram shows the potential problems associated with conventional contact structures. [Figure 2A] This diagram shows a conventional self-aligning contact (SAC). [Figure 2B] This diagram shows the potential problems associated with conventional SAC (Structured Action Course). [Figure 2C] This figure shows further potential problems associated with conventional SAC. [Figure 2D] This figure shows further potential problems associated with conventional SAC. [Figure 2E] This figure shows further potential problems associated with conventional SAC. [Figure 3A] This is a cross-sectional view showing steps in a process for manufacturing a self-aligning contact structure according to an aspect of this disclosure. [Figure 3B] This is a cross-sectional view showing steps in a process for manufacturing a self-aligning contact structure according to an aspect of this disclosure. [Figure 3C] This is a cross-sectional view showing steps in a process for manufacturing a self-aligning contact structure according to an aspect of this disclosure. [Figure 3D] This is a cross-sectional view showing steps in a process for manufacturing a self-aligning contact structure according to an aspect of this disclosure. [Figure 3E] This is a cross-sectional view showing steps in a process for manufacturing a self-aligning contact structure according to an aspect of this disclosure. [Figure 3F] A cross-sectional view showing steps in a process for manufacturing a self-aligned contact structure according to an aspect of the present disclosure. [Figure 3G] A cross-sectional view showing steps in a process for manufacturing a self-aligned contact structure according to an aspect of the present disclosure. [Figure 3H] A cross-sectional view showing steps in a process for manufacturing a self-aligned contact structure according to an aspect of the present disclosure. [Figure 3I] A cross-sectional view showing steps in a process for manufacturing a self-aligned contact structure according to an aspect of the present disclosure. [Figure 3J] A cross-sectional view showing steps in a process for manufacturing a self-aligned contact structure according to an aspect of the present disclosure. [Figure 3K] A cross-sectional view showing steps in a process for manufacturing a self-aligned contact structure according to an aspect of the present disclosure. [Figure 4] A flowchart of an exemplary process associated with the manufacture of a FET according to an aspect of the present disclosure. [Figure 5] A diagram showing an exemplary mobile device according to some examples of the present disclosure. [Figure 6] A diagram showing various electronic devices that can be integrated with any of the foregoing integrated devices or semiconductor devices according to various examples of the present disclosure.

[0015] According to convention, features shown in the drawings may not be drawn to scale. Thus, the dimensions of the features shown may be arbitrarily enlarged or reduced for clarity. According to convention, some of the drawings are simplified for clarity. Thus, the drawings may not depict all components of a particular device or method. Further, like reference numerals indicate like features throughout this specification and the figures.

Mode for Carrying Out the Invention

[0016] Self-aligned contacts (SACs) and methods for manufacturing them are disclosed. In one embodiment, a field-effect transistor (FET) structure comprises a channel connecting a first source or drain (S / D) region to a second S / D region; a gate structure comprising a multilayer metal gate between gate spacers and positioned above the gate region that at least partially surrounds the channel; a self-aligned structure, also called a "hat," positioned above the gate structure and covering at least the multilayer metal gate and gate spacers; and at least one S / D contact that is self-aligned to the hat and connected to the S / D region. During manufacturing, a self-assembled monolayer (SAM) is used to precisely align the hat over the multilayer metal gate. The S / D contacts are self-aligned to the hat even if the etching mask has overlay errors. The hat also shields the gate structure during etching, thereby avoiding the need for a hard mask over the gate metal and the associated hard mask etching step.

[0017] The aspects of this disclosure are provided in the following description and related drawings, which cover various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of this disclosure. In addition, well-known elements of this disclosure are not described in detail or are omitted so as not to obscure the relevant details of this disclosure.

[0018] In this specification, the terms “exemplary” and / or “example” are used to mean “to serve as an example, case, or illustration.” Any aspect described herein as “exemplary” and / or “example” should not necessarily be construed as being preferable or advantageous to any other aspect. Similarly, the term “aspects of the disclosure” does not require that all aspects of the disclosure include the described features, advantages, or modes of operation.

[0019] Those skilled in the art will understand that the information and signals described below may be represented using any of a variety of different techniques and methods. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the following description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof, depending in part on the particular application, desired design, corresponding technology, etc.

[0020] Furthermore, many embodiments are described, for example, in terms of sequences of actions to be performed by elements of a computing device. It will be recognized that the various actions described herein can be performed by specific circuits (e.g., application-specific integrated circuits, ASICs), by program instructions executed by one or more processors, or a combination of both. In addition, the sequence(s) of actions described herein, when executed, can be considered to be fully embodied in any form of non-temporary computer-readable storage medium that stores a corresponding set of computer instructions that cause or instruct the relevant processors of the device to perform the functions described herein. Thus, the various embodiments of this disclosure can be embodied in several different forms, all of which are intended to fall within the scope of the claimed subject matter. In addition, for each of the embodiments described herein, any corresponding form of such embodiment may be described herein, for example, as “logic configured to perform” the described actions.

[0021] Figures 3A to 3K are cross-sectional views illustrating steps in a process for manufacturing a self-aligned contact structure according to an aspect of the present disclosure. As shown in Figure 3A, the process begins with a structure 300 including a substrate 302 on which a finFET 304 is constructed, using, for example, a replacement metal gate (RMG) process. The finFET 304 is surrounded by a shallow trench isolation (STI) layer 306 and covered by an inter-layer dielectric (ILD) layer 308. The gate structure 310 is separated by an epitaxial (EPI) source / drain (S / D) region 312. In the examples shown in Figures 3A to 3K, each gate structure 310 includes a set of gate spacers 314 with a metal gate (MG) structure 316 between them. In the example shown in Figure 3A, the MG structure 316 includes a high-K dielectric 318 surrounding a work function metal (WFM) 320 (e.g., titanium nitride or tantalum nitride) surrounding a tungsten plug 322, but other substitutional metal gate (RMG) structures may also be used. In particular, unlike the conventional SAC shown in Figure 2A, the gate structure 310 in Figure 3A does not include a hard mask between gate spacers 314 that must be etched later to expose the MG structure 316. Figure 3A shows an exemplary cross-section after a chemical / mechanical polishing (CMP) step.

[0022] Figure 3B shows the result of forming a self-assembled monolayer (SAM) 324 on the MG structure 316 portion of the gate structure 310. As shown in enlarged figure 326, the SAM is a repeating series of molecules having a head group shown as a circle, a long tail portion, and a functional group represented by the letter "R". The head group is formed by selective growth by chemiadsorption (e.g., sulfur onto a metal contact). The long tail portion is formed by (CC) nIt may contain alkanethiols with chains. The functional group R provides chemical inhibition against atomic layer deposition (ALD). SAM324 can be deposited by electroless deposition (ELD) or physical vapor deposition (PVD). SAM324 is later removed, for example, by H2 / N2 ashing or thermal desorption. In the example shown in Figure 3B, SAM324 is deposited on the MG structure 316 but not on the ILD layer 308.

[0023] Figure 3C shows the deposition of layer 328, for example, in some embodiments, AlO X Alternatively, the results are shown after selective ALD of another dielectric, or in other embodiments, after the deposition of SiO2 or another oxide. Selective deposition of layer 328 around SAM 324 forms trenches on the MG structure 316.

[0024] Figure 3D shows the result after SAM 324 has been removed (e.g., using H2 / N2 ashing or thermal desorption) and layer 328 has been trimmed so that the trench 329 is enlarged (dashed lines indicate the removed portion). In some embodiments, layer 328 is trimmed using an etching process such as inverse isotropic AlOx film etching, which generally has a higher etching rate in the horizontal sidewall direction than in the vertical direction. Because SAM 324 bonds only to the MG structure 316 and is therefore a self-aligning process, the use of SAM 324 avoids any overlay errors that may occur in conventional photolithography processes.

[0025] Figure 3E shows the deposition of a bilayer film containing a first layer 330 and a second layer 332, and the results after another CMP step. The bilayer film reduces parasitic capacitance. Exemplary bilayer films include, but are not limited to, SiN on SiO2, AlN on SiN, and SiC on SiN. A structure containing the first layer 330 and the second layer 332 together is referred to herein as a self-aligned structure 334. The self-aligned structure 334 self-aligns with the gate structure 310 and, in some embodiments, extends over the gate structure 310. In some embodiments, the sides of the self-aligned structure 334 extend horizontally to the outer edge of the gate spacer 314. In some embodiments, such as the example shown in Figure 3E, the sides of the self-aligned structure 334 extend slightly beyond the outer edge of the gate spacer 314 and slightly overhang from the EPI S / D region 312. The self-aligning structure 334 not only constrains the final position of the S / D contact but also protects the upper surface of the gate structure 310, for which the self-aligning structure 334 may also be referred to herein as the "hat" 334.

[0026] Figure 3F shows the result after depositing a metal drain (MD) photoresist (PR) layer 336 with holes 338 in preparation for etching through layer 328 and ILD layer 308 to expose the S / D region 312. Ideally, all holes 338 are centered over the S / D region 312, but a left or right shift of the overlay may prevent the holes 338 from being perfectly aligned over their respective S / D region 312. An example of this is shown in Figure 3F, where the central hole 338 is aligned over the lower S / D region 312 (representing, for example, the ideal case), but the left and right holes 338 are not aligned over their respective S / D region 312 (representing, for example, the left or right shift of the overlay), and instead have some offset error, as shown as e1 and e2 in Figure 3F. These offset errors are undesirable, but are shown in this example for illustrative purposes only.

[0027] Figure 3G shows the results after the etching step in preparation for MD deposition, where the contact holes or trenches 340 expose the S / D regions 312. Note that despite the fact that some holes 338 in the MDPR layer 336 were not perfectly aligned over their respective S / D regions 312, the hats 334 acted as an additional etching mask to self-align the contact holes or trenches 340 over the S / D regions 312 below. Furthermore, the presence of the hats 334 protected the tops of the gate structures 310 (e.g., gate spacers 314 and MG structures 316) from erosion during the etching step. Even such erosion of the gate spacers 314 would increase the parasitic capacity between the gate contacts and drain contacts, allowing the contact metal to be deposited later to be close enough to the MG structures 316.

[0028] Figure 3H shows the results after removal of the MDPR layer 328, deposition of the contact metal 342, and another CMP step. In some embodiments, the deposition of the contact metal 342 includes a TaN liner and ALD of cobalt or molybdenum or tungsten metal.

[0029] Figure 3I shows the results after the deposition of the ILD layer 344, the photolithography process for etching the ILD layer 344 and one or more hats 334, and the process for generating the S / D vias 346 and gate vias 348. Note that the gate vias 348 do not have a hard mask between the gate spacers 314 and therefore did not require an etching step to form recesses through the hard mask, thus creating contact with the gate structure 310. In some embodiments, the S / D vias 346 and gate vias 348 are generated by selective growth of tungsten followed by another CMP process. In some embodiments, the ILD layer 344 may include an oxide ILD layer. In some embodiments, the ILD layer 344 may include a dielectric layer. In some embodiments, the ILD layer 344 may include an oxide layer positioned above the dielectric layer to provide additional self-alignment of the vias.

[0030] Figure 3J shows the results after the processes of depositing the oxide IMD layer 350 and the metal layer 352. In some embodiments, the metal layer 352 may contain copper from a single damascene process. As shown in Figure 3J, the use of the hat 334 results in a self-aligned S / D contact 342 that does not penetrate the gate structure 310, and a gate contact that does not require a hard cap whose recess must be precisely etched later, thus overcoming the weaknesses of conventional contacts and SACs.

[0031] The techniques shown in Figures 3A to 3J can be applied to many different transistor architectures, including but not limited to planar FETs, fin FETs, and gate-all-around (GAA) FET designs.

[0032] Figure 3K is a cross-sectional view showing the result of fabricating a GAA FET 354 using a process for manufacturing a self-aligned contact structure according to an aspect of the present disclosure. The GAA FET 354 has a plurality of channels 356 separated from the gate by a dielectric material or oxide 358.

[0033] It will be understood that the aforementioned manufacturing processes are provided merely as general examples of some aspects of the present disclosure and do not limit the scope of the present disclosure or the attached claims. Furthermore, many details of manufacturing processes known to those skilled in the art may be omitted or combined in the abstract process portion to facilitate understanding of the various aspects disclosed without detailed descriptions of each detail and / or all possible process variations.

[0034] Figure 4 is a flowchart of an exemplary process 400 associated with the manufacture of an FET according to an aspect of this disclosure. In some aspects, the FET includes a planar FET, a finned FET, or a gate-all-around (GAA) FET.

[0035] As shown in Figure 4, process 400 may include providing a channel in block 410 that connects a first source or drain (S / D) region to a second S / D region. In some embodiments, at least one of the first S / D region or the second S / D region includes an epitaxial layer.

[0036] As further shown in Figure 4, process 400 may include providing a gate structure in block 420 that includes a multilayer metal gate between gate spacers, positioned above a gate region that at least partially encloses a channel, and embedded within a first oxide or dielectric (O / D) layer. In some embodiments, the multilayer metal gate structure includes a high-K dielectric layer that at least partially encloses a work function metal layer.

[0037] As further shown in Figure 4, process 400 may include providing a self-aligning structure in block 430 that is positioned above the gate structure, covers at least the multilayer metal gate and gate spacer, and is embedded within a second O / D layer positioned above the first O / D layer. In some embodiments, providing a self-aligning structure positioned above the gate structure, covering at least the multilayer metal gate and gate spacer, and embedded within a second O / D layer includes forming a self-assembled monolayer (SAM) layer on top of the multilayer metal gate, selectively depositing the second O / D layer above the first O / D layer but not above the multilayer metal gate to form a gate trench within the second O / D layer, removing the SAM layer from the gate trench, and forming a self-aligning structure within the gate trench. In some embodiments, forming a self-aligning structure within the gate trench includes forming a bilayer within the gate trench. In some embodiments, forming a two-layer film involves placing a first layer, comprising silicon nitride (SiN) or silicon dioxide (SiO2), within a gate trench, and placing a second layer, comprising aluminum nitride (AlN) or silicon carbide (SiC), above the first layer.

[0038] As further shown in Figure 4, process 400 may include providing a first S / D contact in block 440 that is self-aligned to a self-aligned structure and connected to a first S / D region. In some embodiments, providing a first S / D contact that is self-aligned to a self-aligned structure and connected to a first S / D region includes etching a second O / D layer above the first S / D region to form a trench having sides partitioned by the outer edge of the self-aligned structure, and depositing S / D contact material in the trench.

[0039] In some embodiments, the process 400 further includes providing a second S / D contact that is self-aligned to a self-aligning structure and connected to a second S / D region.

[0040] In some embodiments, process 400 further includes providing gate contacts connected to a multilayer metal gate through etched holes via a self-aligning structure.

[0041] In some embodiments, the process 400 further includes providing a third O / D layer positioned above the second O / D layer.

[0042] In some embodiments, process 400 further includes providing at least one of S / D vias connected to a first S / D contact through a third O / D layer, or gate contacts connected to a multilayer metal gate through a self-aligned structure, and gate vias connected to the gate contact through a third O / D layer. In some embodiments, providing the third O / D layer includes providing an upper oxide layer and a lower dielectric layer.

[0043] Process 400 may include additional implementations, such as any single implementation or any combination of implementations, as described below and / or elsewhere in this specification with respect to one or more other processes. Figure 4 shows an exemplary block of Process 400, but in some implementations, Process 400 may include additional blocks, fewer blocks, different blocks, or differently configured blocks in addition to those shown in Figure 4. Additionally or alternatively, two or more blocks of Process 400 may be executed in parallel.

[0044] Figure 5 shows an exemplary mobile device according to several examples of the present disclosure. Referring hereto to Figure 5, a block diagram of a mobile device configured according to an exemplary embodiment is depicted, the whole being designated as mobile device 500. In some embodiments, mobile device 500 may be configured as a wireless communication device. As shown, mobile device 500 includes a processor 502. The processor 502 is shown to include an instruction pipeline 504, a buffer processing unit (BPU) 506, a branch instruction queue (BIQ) 508, and a throttle 510, as is well known in the art. Other well known details of these blocks (e.g., counters, entries, confidence fields, weighted sums, comparators, etc.) are omitted from this figure of processor 502 for clarity. The processor 502 may be communicably coupled to memory 512 via a link, which may be a die-to-die link or a chip-to-chip link. The mobile device 500 also includes a display 514 and a display controller 516, the display controller 516 being coupled to the processor 502 and the display 514.

[0045] In some embodiments, Figure 5 may include a coder / decoder (CODEC) 518 (e.g., an audio and / or voice CODEC) coupled to a processor 502, a speaker 520 and a microphone 522 coupled to the CODEC 518, and a wireless antenna 526 and a wireless controller circuit 524 coupled to the processor 502 (which may include a modem, radio frequency (RF) circuit, filter, etc., which may be implemented using one or more flip-chip devices as disclosed herein).

[0046] In certain embodiments where one or more of the aforementioned blocks exist, the processor 502, display controller 516, memory 512, CODEC 518, and wireless controller circuit 524 may be contained within a system-in-package device or system-on-chip device, which may be implemented in whole or in part using the techniques disclosed herein. The input device 528 (e.g., a physical or virtual keyboard), power supply 530 (e.g., a battery), display 514, input device 528, speaker 520, microphone 522, wireless antenna 526, and power supply 530 may be outside the system-on-chip device and may be coupled to components of the system-on-chip device such as interfaces or controllers.

[0047] While Figure 5 shows a mobile device, it should be noted that the processor 502 and memory 512 may also be integrated into set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), stationary data units, computers, laptops, tablets, communication devices, mobile phones, or other similar devices.

[0048] Figure 6 shows various electronic devices that can be integrated with either the aforementioned integrated devices or semiconductor devices, as illustrated by various examples of the present disclosure. For example, the mobile phone device 602, the laptop computer device 604, and the stationary terminal device 606 may each be generally considered user equipment (UE) and may include, for example, device 600 as described herein. The device may be, for example, an integrated circuit, die, integrated device, integrated device package, integrated circuit device, device package, integrated circuit (IC) package, or package-on-package device as described herein. The mobile phone device 602, the laptop computer device 604, and the stationary terminal device 606 shown in Figure 6 are merely illustrative examples. Other electronic devices may also include, but are not limited to, a group of devices (e.g., electronic devices) that include mobile devices, handheld personal communication system (PCS) units, portable data units such as personal information terminals, global positioning system (GPS) devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in automobiles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0049] In the detailed explanation above, it will be seen that in the examples, different features are grouped together. This form of disclosure should not be understood as an intention that the exemplary clauses have more features than are explicitly stated within each clause. Rather, the various aspects of this disclosure may contain fewer features than all the features of the individual exemplary clauses disclosed. Accordingly, the following clauses should be considered incorporated into the explanation, and each clause may be valid on its own as a separate example. Each dependent clause may refer within itself to a specific combination with one of the other clauses, but the aspects (singular or plural) of that dependent clause are not limited to that specific combination. It will be understood that other exemplary clauses may also include combinations of aspects (singular or plural) of dependent clauses with the subject matter of any other dependent or independent clause, or any combination of features with other dependent and independent clauses. The various aspects disclosed herein explicitly include certain combinations (e.g., contradictory aspects such as defining an element as both an electrical insulator and an electrical conductor) unless it is explicitly stated or easily inferred that such combinations are not intended. Furthermore, even if a clause is not directly subordinate to an independent clause, it is intended that the nature of the clause may be included in any other independent clause.

[0050] Implementation examples are described in the following numbered sections. Clause 1. A field-effect transistor (FET) structure comprising: a channel connecting a first source or drain (S / D) region to a second S / D region; a gate structure including a multilayer metal gate between gate spacers and positioned above a gate region that at least partially surrounds the channel; a self-aligning structure positioned above the gate structure and covering at least the multilayer metal gate and gate spacers; and a first S / D contact that is self-aligned to the self-aligning structure and connected to the first S / D region.

[0051] Clause 2. The FET structure according to Clause 1, further comprising a second S / D contact that is self-aligned to a self-aligning structure and connected to a second S / D region.

[0052] Clause 3. The FET structure according to Clause 1 or 2, further comprising gate contacts connected to a multilayer metal gate through a self-aligning structure.

[0053] Clause 4. The FET structure according to any one of Clauses 1 to 3, wherein at least one of the first S / D region and the second S / D region includes an epitaxial layer.

[0054] Clause 5. An FET structure according to any one of Clauses 1 to 4, wherein the multilayer metal gate includes a high-K dielectric layer that at least partially surrounds the work function metal layer.

[0055] Clause 6. An FET structure according to any one of Clauses 1 to 5, wherein the self-aligned structure includes a bilayer film.

[0056] Clause 7. The FET structure according to Clause 6, wherein the bilayer film comprises silicon nitride (SiN) disposed on silicon dioxide (SiO2), aluminum nitride (AlN) disposed on SiN, or silicon carbide (SiC) disposed on SiN.

[0057] Clause 8. An FET structure as described in any of Clauses 1 to 7, at least partially surrounded by a shallow trench isolation (STI) layer.

[0058] Clause 9. An FET structure according to any one of Clauses 1 to 8, wherein the gate structure is embedded in a first oxide or dielectric (O / D) layer.

[0059] Clause 10. The FET structure according to Clause 9, wherein the self-aligned structure is embedded in a second O / D layer located above a first O / D layer.

[0060] Clause 11. The FET structure according to Clause 10, further comprising a third O / D layer positioned above the second O / D layer.

[0061] Clause 12. The FET structure according to Clause 11, further comprising at least one of the following: an S / D via connected to a first S / D contact through a third O / D layer, or a gate contact connected to a multilayer metal gate through a self-aligning structure and a gate via connected to the gate contact through a third O / D layer.

[0062] Clause 13. FET structures as described in any of Clauses 1 to 12, including planar FETs, finned FETs, or gate-all-around (GAA) FETs.

[0063] Clause 14. A method for manufacturing a field-effect transistor (FET) structure, comprising: providing a channel connecting a first source or drain (S / D) region to a second S / D region; providing a gate structure comprising a multilayer metal gate between gate spacers, positioned above a gate region at least partially surrounding the channel, and embedded in a first oxide or dielectric (O / D) layer; providing a self-aligning structure positioned above the gate structure, covering at least the multilayer metal gate and gate spacers, and embedded in a second O / D layer positioned above the first O / D layer; and providing a first S / D contact that is self-aligned to the self-aligning structure and connected to the first S / D region.

[0064] Clause 15. The method according to Clause 14, wherein at least one of the first S / D region or the second S / D region includes an epitaxial layer.

[0065] Clause 16. The method according to Clause 14 or 15, wherein the multilayer metal gate structure includes a high-K dielectric layer that at least partially surrounds the work function metal layer.

[0066] Clause 17. The method according to any one of Clauses 14 to 16, wherein providing a self-aligning structure positioned above a gate structure, covering at least a multilayer metal gate and gate spacer, and embedded within a second O / D layer, comprises forming a self-assembled monolayer (SAM) layer above a multilayer metal gate, selectively depositing a second O / D layer above a first O / D layer but not above a multilayer metal gate to form a gate trench within the second O / D layer, removing the SAM layer from the gate trench, and forming a self-aligning structure within the gate trench.

[0067] Clause 18. The method according to Clause 17, wherein forming a self-aligning structure within a gate trench includes forming a bilayer film within a gate trench.

[0068] Clause 19. The method according to Clause 18, wherein forming a two-layer film comprises placing a first layer comprising silicon nitride (SiN) or silicon dioxide (SiO2) in a gate trench, and placing a second layer comprising SiN, aluminum nitride (AlN), or silicon carbide (SiC) above the first layer.

[0069] Clause 20. The method according to any one of Clauses 14 to 19, comprising etching a second O / D layer above the first S / D region to form a trench having sides partitioned by the outer edge of the self-aligning structure, and depositing S / D contact material within the trench.

[0070] Clause 21. The method according to any one of Clauses 14 to 20, further comprising providing a second S / D contact that is self-aligned to a self-aligning structure and connected to a second S / D area.

[0071] Clause 22. The method according to any one of Clauses 14 to 21, further comprising providing a gate contact connected to a multilayer metal gate through etched holes through a self-aligning structure.

[0072] Clause 23. The method according to any one of Clauses 14 to 22, further comprising providing a third O / D layer positioned above a second O / D layer.

[0073] Clause 24. The method according to Clause 23, further comprising providing at least one of the following: an S / D via connected to a first S / D contact through a third O / D layer, or a gate contact connected to a multilayer metal gate through a self-aligning structure and a gate via connected to the gate contact through a third O / D layer.

[0074] Clause 25. The method described in any of Clauses 14 to 24, wherein the FET includes a planar FET, a finned FET, or a gate-all-around (GAA) FET.

[0075] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, electric current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0076] Furthermore, those skilled in the art will understand that various exemplary logic blocks, modules, circuits, and algorithmic steps described in relation to the embodiments disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly demonstrate this hardware-software compatibility, various exemplary components, blocks, modules, circuits, and steps have been outlined above in relation to their functions. Whether such functions are implemented as hardware or executed as software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functions in various ways with respect to each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0077] Various exemplary logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or run using general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, individual gate or transistor logic, individual hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0078] The methods, sequences, and / or algorithms described in relation to the embodiments disclosed herein may be embodied directly in hardware, in software modules executed by a processor, or in a combination of the two. The software modules may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal (e.g., a UE). Alternatively, the processor and storage medium may reside in the user terminal as separate components.

[0079] In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted via computer-readable media as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, including any media that facilitate the transfer of computer programs from one location to another. Storage media may be any available media accessible by a computer. Such computer-readable media, but not limited to examples, may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other media accessible by a computer that can be used to carry or store desired program code in the form of instructions or data structures. Furthermore, any connection may appropriately be referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of a medium. As used herein, disks and discs include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray® discs, where a disc typically reproduces data magnetically, and a disc optically reproduces data using a laser. Combinations of the above should also be considered within the scope of computer-readable media.

[0080] While the above disclosures represent exemplary aspects of the Disclosure, it should be noted that various changes and modifications can be made to this Specified without departing from the scope of the Disclosure as defined by the appended claims. The functions, steps, and / or actions of the method claims in the aspects of the Disclosure described herein do not need to be performed in any particular order. Furthermore, elements of the Disclosure may be described or claimed in the singular, but the plural is intended unless a limitation to the singular is explicitly stated. [Explanation of symbols]

[0081] 100 Active boards 102 Gate Metal 104 Gate Spacer 106 S / D Contact 108 Dielectric Oxide Layer 110 distance 112 points 200 Hard Masks 202 S / D Contact 202 Self-aligning S / D contact 204 Metal 206 High-K dielectrics 210 Tungsten Plug 212 positions 300 Structure 302 circuit board 308 ILD layer 310 Gate Structure 312 S / D area 314 Gate Spacer 316 Metal Gate (MG) Structure 318 High-K dielectrics 320 Work function of metals (WFM) 322 Tungsten Plug 324 Self-assembled monolayer (SAM) 326 Enlarged View 328 MDPR layer 329 Trench 330 First layer 332 Second Layer 334 Self-aligned structure 336 MDPR layer 338 Halls 340 Trench 342 Contact Metal 344 ILD layer 346 S / D Via 348 Gate Beer 350 Oxide IMD layer 352 Metal layer 356 channels 358 Oxides 500 mobile devices 502 Processors 504 Instruction Pipeline 510 Slotra 512 memory 514 displays 516 Display Controller 518 Decoder 520 speakers 522 Microphone 524 Wireless Controller Circuit 526 Wireless Antenna 528 Input Devices 530 Power supply 600 devices 602 Mobile phone devices 604 Laptop Computer Devices 606 Stationary terminal devices

Claims

1. A field-effect transistor (FET) structure, A channel connecting a first source or drain (S / D) region to a second S / D region, A gate structure comprising a multilayer metal gate between gate spacers and positioned above a gate region that at least partially surrounds the channel, A self-aligning structure positioned above the gate structure and covering at least the multilayer metal gate and the gate spacer, A first S / D contact, which is self-aligned with the self-aligning structure and connected to the first S / D region, A field-effect transistor (FET) structure that includes [the specified feature].

2. The FET structure according to claim 1, further comprising a second S / D contact that is self-aligned with the self-aligning structure and connected to the second S / D region.

3. The FET structure according to claim 1, further comprising a gate contact connected to the multilayer metal gate through the self-aligning structure.

4. The FET structure according to claim 1, wherein at least one of the first S / D region and the second S / D region includes an epitaxial layer.

5. The FET structure according to claim 1, wherein the multilayer metal gate includes a high-K dielectric layer that at least partially surrounds the work function metal layer.

6. The FET structure according to claim 1, wherein the self-aligning structure includes a two-layer film.

7. The aforementioned two-layer film, Silicon dioxide (SiO ２ Silicon nitride (SiN), placed on top of ) Aluminum nitride (AlN) placed on top of SiN, or Silicon carbide (SiC) placed on top of SiN, The FET structure according to claim 6, including the above.

8. The FET structure according to claim 1, which is at least partially surrounded by a shallow trench insulating (STI) layer.

9. The FET structure according to claim 1, wherein the gate structure is embedded in a first oxide or dielectric (O / D) layer.

10. The FET structure according to claim 9, wherein the self-aligning structure is embedded in a second O / D layer positioned above the first O / D layer.

11. The FET structure according to claim 10, further comprising a third O / D layer disposed above the second O / D layer.

12. An S / D via connected to the first S / D contact through the third O / D layer, A gate contact connected to the multilayer metal gate through the self-aligning structure and a gate via connected to the gate contact through the third O / D layer, The FET structure according to claim 11, further comprising at least one of the above.

13. The FET structure according to claim 1, comprising a planar FET, a finned FET, or a gate-all-around (GAA) FET.

14. A method for manufacturing a field-effect transistor (FET) structure, To provide a channel that connects a first source or drain (S / D) region to a second S / D region, To provide a gate structure comprising a multilayer metal gate between gate spacers, positioned above a gate region that at least partially surrounds the channel, and embedded within a first oxide or dielectric (O / D) layer, To provide a self-aligning structure that is positioned above the gate structure, covers at least the multilayer metal gate and the gate spacer, and is embedded in a second O / D layer positioned on top of the first O / D layer, To provide a first S / D contact that is self-aligned with the self-aligning structure and connected to the first S / D region, Methods that include...

15. The method according to claim 14, wherein at least one of the first S / D region or the second S / D region includes an epitaxial layer.

16. The method according to claim 14, wherein the multilayer metal gate structure includes a high-K dielectric layer that at least partially surrounds the work function metal layer.

17. To provide the self-aligning structure, which is positioned above the gate structure, covers at least the multilayer metal gate and the gate spacer, and is embedded within the second O / D layer, Forming a self-assembled monolayer (SAM) on top of the multilayer metal gate, The second O / D layer is selectively deposited above the first O / D layer but not above the multilayer metal gate, thereby forming a gate trench within the second O / D layer. Removing the SAM layer from the gate trench, Forming the self-aligning structure within the gate trench, The method according to claim 14, including the method described in claim 14.

18. The method according to claim 17, wherein forming the self-aligning structure within the gate trench includes forming a two-layer film within the gate trench.

19. Forming the aforementioned two-layer film Within the gate trench, a first layer is provided, which is silicon nitride (SiN) or silicon dioxide (SiO ２ ) including the first layer, A second layer is placed above the first layer, the second layer comprising SiN, aluminum nitride (AlN), or silicon carbide (SiC). The method according to claim 18, including the method described in claim 18.

20. To provide the first S / D contact which is self-aligned with the self-aligning structure and connected to the first S / D region, To form a trench having a side surface demarcated by the outer edge of the self-aligning structure, the second O / D layer above the first S / D region is etched, Depositing S / D contact material in the trench, The method according to claim 14, including the method described in claim 14.

21. The method according to claim 14, further comprising providing a second S / D contact that is self-aligned to the self-aligning structure and connected to the second S / D region.

22. The method according to claim 14, further comprising providing a gate contact connected to the multilayer metal gate through a hole etched through the self-aligning structure.

23. The method according to claim 14, further comprising providing a third O / D layer disposed above the second O / D layer.

24. An S / D via connected to the first S / D contact through the third O / D layer, A gate contact connected to the multilayer metal gate through the self-aligning structure and a gate via connected to the gate contact through the third O / D layer, The method according to claim 23, further comprising providing at least one of the following.

25. The method according to claim 14, wherein the FET includes a planar FET, a finned FET, or a gate-all-around (GAA) FET.

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