Semiconductor structure and method for manufacturing the same

Abstract

A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure comprises: bit lines extending in a first direction and spaced apart in a second direction, the first direction intersecting the second direction; shield lines located between two adjacent bit lines, extending in a first direction and alternately arranged with the bit lines in the second direction; active pillars located on the bit lines and arranged in an array in the first and second directions; and a bit line contact structure located between the bit lines and the active pillars, connecting the bit lines and the active pillars, wherein the width of the bit line contact structure in the second direction is smaller than the width of the bit lines and the active pillars in the second direction.

Description

Technical Field

[0001] This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on April 15, 2024, with the application number 202410452734.7 and the invention title "Semiconductor Structure and Its Manufacturing Method", and all the contents of the Chinese patent application are incorporated herein by reference.

[0002] This application relates to the field of integrated circuit technology, and particularly to semiconductor structures and their manufacturing methods.

Background Art

[0003] With the development of dynamic random access memory (DRAM) technology, the size of memory cells has become increasingly smaller, and its array architecture has evolved from 8F 2 to 6F 2 and further to 4F 2 (F: the minimum pattern size achievable under certain process conditions).

[0004] However, in the structure of 4F 2 design, how to minimize the transistor area of a single array region and pursue a higher chip area utilization rate remains an urgent issue to be solved.

Summary of the Invention

Problems to be Solved by the Invention

[0005] In view of the above, this application provides a semiconductor structure and its manufacturing method that can reduce the volume of the device and the difficulty of the manufacturing process.

Means for Solving the Problems

[0006] In one aspect, this application provides a semiconductor structure based on several embodiments, and the semiconductor structure is An array of active pillars arranged in a first direction and a second direction, wherein the first direction intersects with the second direction, Bit lines extending in a first direction, spaced apart in a second direction, and connected to active pillars arranged along the first direction, A shielding line is located between two adjacent bit lines, extends in a first direction, and is arranged alternately with the bit lines in a second direction. A bit line contact structure is located between a bit line and an active pillar and connects the bit line and the active pillar, wherein the width of the bit line contact structure in a second direction is smaller than the width of the bit line and the active pillar in the second direction.

[0007] In some embodiments, the bit line contact structure is connected to two adjacent active pillars in the second direction.

[0008] In some embodiments, the width of the shield wire in the third direction is greater than or equal to the width of the bit wire in the third direction, and the third direction intersects the first and second directions.

[0009] In some embodiments, the width of the bit line decreases as the bit line extends toward the bit line contact structure.

[0010] In some embodiments, the semiconductor structure is further, A bit line protection layer located on the side of the bit line away from the bit line contact structure of the bit line, A bit line isolation layer located between two adjacent bit lines, wherein the shield line comprises a bit line isolation layer located within the bit line isolation layer, The materials of the bit line protection layer and the bit line separation layer are different.

[0011] In some embodiments, the bit wire comprises at least one layer of metallic material. The shield wire includes at least one layer of metallic material.

[0012] In some embodiments, the semiconductor structure is further, The device includes a shield wire barrier layer, the shield wire barrier layer covering the shield wire layer.

[0013] In some embodiments, a gap exists between the bit line separation layer and the shielding wire.

[0014] In some embodiments, the cross-sectional shape of the shield wire perpendicular to the first direction is conical, elongated, elliptical, star-shaped, or other suitable shape.

[0015] In some embodiments, the semiconductor structure is further, Word lines extending in the second direction and spaced apart in the first direction, wherein the word lines are connected to the active pillar in the second direction, The system includes a memory structure connected to the active pillar and located at one end of the active pillar away from the bit line.

[0016] In another aspect, the present application further provides a method for manufacturing a semiconductor structure based on several embodiments, the method being The invention involves forming an active pillar, wherein the active pillar is arranged in an array in a first direction and a second direction, and the first direction intersects the second direction. The process involves forming a bit line, wherein the bit line extends in a first direction, is spaced apart in a second direction, and is connected to active pillars arranged along the first direction. The shielding wire is formed such that it is located between two adjacent bit lines, extends in a first direction, and is arranged alternately with the bit lines in a second direction. Forming a bit line contact structure, wherein the bit line contact structure connects the bit line and the active pillar, and the width of the bit line contact structure in the second direction is smaller than the widths of the bit line and the active pillar in the second direction, and

[0017] In some embodiments, forming the bit line includes Providing a substrate, the substrate having a first surface and a second surface in a third direction, the third direction intersecting the first direction and the second direction, and Forming bit line isolation trenches by performing patterning etching on the first surface, the size of the bottom of the bit line isolation trenches being larger than the size of the top of the bit line isolation trenches, the bit line isolation trenches extending along the first direction and being arranged at intervals in the second direction, and Filling the bit line isolation trenches to form a bit line isolation layer, and Polishing the second surface to expose the bit line isolation layer, and etching the substrate using the bit line isolation layer as a mask to form bit line trenches, and Filling the bit line trenches with at least one layer of metal material to form the bit line, and Forming a bit line protection layer on the bit line, the material of the bit line protection layer being different from that of the bit line isolation layer, and

[0018] In some embodiments, forming the shield line includes Using the bit line protection layer as a mask layer on the second surface to etch the bit line isolation layer to form shield line trenches, the depth of the shield line trenches being greater than or equal to the depth of the bit line trenches, and Filling the shield line trenches with at least one layer of metal material to form the shield line.

[0019] In some embodiments, the bit line contact structure includes a metal silicide, and forming the metal silicide includes depositing a metal material layer at the bottom of the bit line trench and performing a heat treatment to form a metal silicide, or depositing a metal material layer at the bottom of the bit line isolation trench and performing a heat treatment to form a metal silicide.

[0020] In some embodiments, after filling the bit line isolation trench to form a bit line isolation layer, the method further includes forming a word line isolation trench by performing a patterning etch on the first surface, the depth of the word line isolation trench being smaller than the depth of the bit line isolation trench, and the word line isolation trenches extend along a second direction and are arranged at intervals in a first direction, and the active pillars are formed by the word line isolation trenches and the bit line isolation trenches, after forming the active pillars, the method further includes forming word lines in the word line isolation trenches, the word lines extending in the second direction and being arranged at intervals in the first direction, and the word lines being connected to the active pillars in the second direction, and forming a memory structure at one end of the active pillar away from the bit line.

Advantages of the Invention

[0021] The semiconductor structure and its manufacturing method provided by the present application have at least the following beneficial effects.

[0022] According to the semiconductor structure and manufacturing method provided in this application, by forming metal bit lines on the back surface of the wafer, the resistance of the bit lines can be reduced, and by forming metal shield lines between the bit lines, the coupling capacitance between adjacent bit lines can be reduced, thereby improving the stability of the device. By using different materials for the substrate, bit line isolation layer, and bit line protection layer, setting different etching selectivity ratios, and performing etching using a self-aligned etching process, the number of photomasks can be reduced, thereby reducing manufacturing costs. Furthermore, adjacent Active Pillar Since they can share a single bit line, the complexity of the device process can be reduced. [Brief explanation of the drawing]

[0023] [Figure 1a] This is an exemplary top view of a semiconductor structure according to several disclosed embodiments. [Figure 1b] This is a schematic diagram of the cross-sectional structure along the bit line direction. [Figure 1c] This is a schematic diagram of the cross-sectional structure along the direction of the word line. [Figure 2] This is a schematic diagram of the cross-sectional structure of a semiconductor structure along the Word line direction according to several embodiments of the present application. [Figure 3a] This is a schematic diagram of the cross-sectional structure of a semiconductor structure along the word line direction according to some other embodiments of the present application. [Figure 3b] This is a schematic diagram of the cross-sectional structure of a semiconductor structure along the word line direction according to some other embodiments of the present application. [Figure 3c] This is a schematic diagram of the cross-sectional structure of a semiconductor structure along the word line direction according to some other embodiments of the present application. [Figure 3d] This is a schematic diagram of the cross-sectional structure of a semiconductor structure along the word line direction according to some other embodiments of the present application. [Figure 3e] This is a schematic diagram of the cross-sectional structure of a semiconductor structure along the word line direction according to some other embodiments of the present application. [Figure 4a]This is a schematic diagram of the cross-sectional structure along the word line direction at each stage of the method for manufacturing a semiconductor structure according to several embodiments of the present invention. [Figure 4b] This is a schematic diagram of the cross-sectional structure along the word line direction at each stage of the method for manufacturing a semiconductor structure according to several embodiments of the present invention. [Figure 4c] This is a schematic diagram of the cross-sectional structure along the word line direction at each stage of the method for manufacturing a semiconductor structure according to several embodiments of the present invention. [Figure 4d] This is a schematic diagram of the cross-sectional structure along the word line direction at each stage of the method for manufacturing a semiconductor structure according to several embodiments of the present invention. [Figure 4e] This is a schematic diagram of the cross-sectional structure along the word line direction at each stage of the method for manufacturing a semiconductor structure according to several embodiments of the present invention. [Figure 4f] This is a schematic diagram of the cross-sectional structure along the word line direction at each stage of the method for manufacturing a semiconductor structure according to several embodiments of the present invention. [Figure 4g] This is a schematic diagram of the cross-sectional structure along the word line direction at each stage of the method for manufacturing a semiconductor structure according to several embodiments of the present invention. [Figure 4h] This is a schematic diagram of the cross-sectional structure along the word line direction at each stage of the method for manufacturing a semiconductor structure according to several embodiments of the present invention. [Figure 4i] This is a schematic diagram of the cross-sectional structure along the word line direction at each stage of the method for manufacturing a semiconductor structure according to several embodiments of the present invention. [Figure 4j] This is a schematic diagram of the cross-sectional structure along the word line direction at each stage of the method for manufacturing a semiconductor structure according to several embodiments of the present invention. [Figure 4k] This is a schematic diagram of the cross-sectional structure along the word line direction at each stage of the method for manufacturing a semiconductor structure according to several embodiments of the present invention. [Figure 4l] This is a schematic diagram of the cross-sectional structure along the word line direction at each stage of the method for manufacturing a semiconductor structure according to several embodiments of the present invention. [Figure 5a]This is a schematic diagram of the cross-sectional structure along the word line direction at each step of the method for manufacturing a semiconductor structure according to several other embodiments of the present invention. [Figure 5b] This is a schematic diagram of the cross-sectional structure along the word line direction at each step of the method for manufacturing a semiconductor structure according to several other embodiments of the present invention. [Figure 5c] This is a schematic diagram of the cross-sectional structure along the word line direction at each step of the method for manufacturing a semiconductor structure according to several other embodiments of the present invention. [Figure 5d] This is a schematic diagram of the cross-sectional structure along the word line direction at each step of the method for manufacturing a semiconductor structure according to several other embodiments of the present invention. [Figure 5e] This is a schematic diagram of the cross-sectional structure along the word line direction at each step of the method for manufacturing a semiconductor structure according to several other embodiments of the present invention. [Figure 5f] This is a schematic diagram of the cross-sectional structure along the word line direction at each step of the method for manufacturing a semiconductor structure according to several other embodiments of the present invention. [Modes for carrying out the invention]

[0024] To more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art have been briefly introduced above. Clearly, the drawings described above represent only a few embodiments of the present application, and those skilled in the art should understand that they can obtain other drawings based on these without any creative effort.

[0025] To facilitate understanding of this application, the application will be described more comprehensively below with reference to the relevant drawings. While the drawings show preferred embodiments of the application, it can be realized in a variety of different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosures more thorough and comprehensive.

[0026] Unless otherwise specified, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art. Terms used in this specification are solely for the purpose of describing specific embodiments and are not intended to limit this application.

[0027] To ensure understanding, when an element or layer is described as being "on top of," "adjacent to," or "connected to" another element or layer, it may be directly located on top of, adjacent to, or connected to another element or layer, or there may be intervening elements or layers. To ensure understanding, terms such as first, second, etc., can be used to describe various elements, components, regions, layers, doping types, and / or parts, and these elements, components, regions, layers, doping types, and / or parts are not limited by these terms. These terms are merely for distinguishing one element, component, region, layer, doping type, or part from another element, component, region, layer, doping type, or part. Thus, without departing from the teachings of this application, the first element, component, region, layer, doping type, or part described below may be referred to as the second element, component, region, layer, or part. For example, the first doped region may be called the second doped region, and similarly, the second doped region may be called the first doped region, and the first doped region and the second doped region are different doped regions.

[0028] For example, terms indicating spatial relationships, such as "above," may be used herein to describe the relationship between one element or feature and another shown in the drawings. To make it clear, in addition to the orientation shown in the drawings, terms indicating spatial relationships include different orientations of the device in use and operation. For example, if the device in the drawing is inverted, the element or feature described as "above" will be oriented "below" the other element or feature. Thus, the exemplary term "above" may include both upward and downward orientations. Furthermore, the device may include other orientations (e.g., a 90-degree rotation or other orientations), and the spatial descriptive terms used herein should be interpreted accordingly.

[0029] Where used herein, unless otherwise defined in context, the singular forms “1,” “one,” and “the said / the said” are intended to include the plural forms as well. Furthermore, where used herein, the terms “equip” and / or “include” mean that they identify the presence of the described features, integers, steps, actions, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, parts, and / or combinations thereof. Also, where used herein, the terms “and / or” include any of the associated items and all combinations thereof.

[0030] The embodiments of this application are described herein with reference to schematic cross-sectional views of ideal embodiments (and intermediate structures) of this application, and deformations of the illustrated shapes due to manufacturing techniques and / or tolerances may be expected. Accordingly, embodiments of this application should not be limited to specific shapes of the regions shown herein, but should include deviations of shape due to manufacturing techniques, etc. The regions shown in the drawings are generally illustrative, and these shapes do not represent the actual shapes of the regions of the device, nor do they limit the scope of this application.

[0031] Referring to Figure 1a, in some relevant embodiments, the semiconductor structure may include a plurality of bitlines (BL) 3, a plurality of wordlines (WL) 2, and a plurality of active pillars 4. The plurality of bitlines (BL) 3 may extend along a first direction (e.g., the X direction) and be arranged along a second direction (e.g., the Y direction). The plurality of wordlines (WL) 2 may extend along the second direction and be arranged along the first direction. The bitlines 3 and wordlines 2 intersect in space at the active pillars 4, and the plurality of active pillars 4 may extend along a third direction (e.g., the Z direction) perpendicular to the direction of the substrate 1 and be arranged in an array. During the production of the bitlines 3, first, as shown in Figure 1c, bitline isolation trenches 6 are formed and filled, and then, as shown in Figure 1b, wordline isolation trenches 5 are formed by etching, and the substrate is modified in the wordline isolation trenches by ion implantation, doping, or metal diffusion to form the bitlines 3. As the size of bit lines 3 decreases, the resistance of bit lines 3 increases, and at the same time, the distance between adjacent bit lines 3 also decreases, resulting in a corresponding coupling effect that has a significant impact on the performance of the semiconductor structure. Furthermore, during the process of forming bit lines 3, certain damage occurs to word line isolation trenches, memory contacts, and active pillars, which greatly limits the development of semiconductor structure manufacturing processes.

[0032] This application provides a semiconductor structure and a method for manufacturing the same that can reduce the volume of a device, the details of which will be described in subsequent examples.

[0033] In one embodiment, the present application provides semiconductor structures according to several embodiments.

[0034] Referring to Figure 2, in some embodiments, the semiconductor structure may comprise a plurality of bit lines 3, a plurality of active pillars 4, a plurality of shielding lines 16, and a bit line contact structure 10. Here, the plurality of bit lines 3 extend in a first direction (e.g., the X direction) and are spaced apart in a second direction (e.g., the Y direction), with the first direction intersecting the second direction. The plurality of shielding lines 16 are located between two adjacent bit lines 3, extend in the first direction, and are arranged alternately with the bit lines 3 in the second direction. The plurality of active pillars 4 extend in a third direction (e.g., the Z direction) away from the bit lines 3 and are arranged in an array in the first and second directions. The bit line contact structure 10 is located between the bit lines 3 and the active pillars 4, connecting the bit lines 3 and the active pillars 4, and the width of the bit line contact structure 10 in the second direction is smaller than the width of the bit lines and active pillars in the second direction.

[0035] In the semiconductor structure provided in the above embodiment, the shield wire 16 is located between adjacent bit wires 3 and is arranged alternately with the bit wires in the second direction. Therefore, the shield wire 16 can reduce the coupling effect between two adjacent bit wires 3 and provide stability to the semiconductor structure. Since the width of the bit wire contact structure 10 in the second direction is smaller than the width of the bit wires 3 and active pillars 4 in the second direction, the width of the bit wires 3 in the second direction can be increased, reducing the resistance of the bit wires 3 while also reducing the difficulty of manufacturing the bit wires 3.

[0036] Referring to Figures 2 and 3a, in some embodiments, one bit line contact structure can be connected to one active pillar 4, and one bit line contact structure 10 can also be connected to two adjacent active pillars 4 in a second direction. Referring to Figure 2, two adjacent active pillars 4 share one bit line contact structure 10 and one bit line 3, which reduces the density of bit lines, increases the integration density and increases the spacing between bit lines, and at the same time increases the width of bit lines 3, reduces the resistance of bit lines 3, and improves the performance of the device.

[0037] Continuing to refer to Figure 2, in some embodiments, the width D1 of the shield wire 16 in the third direction (e.g., the Z direction) is greater than or equal to the width D2 of the bit wire 3 in the third direction (e.g., the Z direction), and the width D1 of the shield wire 16 in the third direction (e.g., the Z direction) must exceed the width D2 of the bit wire 3 in the third direction (e.g., the Z direction). Optionally, the width D1 of the shield wire 16 in the third direction (e.g., the Z direction) must exceed the sum of the widths of the bit wire 3 and the bit wire contact structure 10 in the third direction (e.g., the Z direction). In this way, the shield wire 16 can completely shield the coupling effect between adjacent bit wires 3 and improve the performance of the device.

[0038] Continuing to refer to Figure 2, in some embodiments, the width of the bit wire 3 in the second direction (e.g., the Y direction) decreases as the bit wire extends toward the bit wire contact structure, which can be understood as the bit wire exhibiting an inverted trapezoidal shape. This reduces the resistance of the bit wire 3 and also reduces the difficulty of the manufacturing process of the bit wire 3.

[0039] Continuing to refer to Figure 2, in some embodiments, the semiconductor structure may include a bit line protection layer 14 and a bit line isolation layer 8. The bit line protection layer 14 is located on the side of the bit line 3 away from the bit line contact structure 10, extends along a first direction (e.g., X), and is arranged in a second direction (e.g., Y). The bit line isolation layer 8 is located between two adjacent bit lines 3 and insulates and isolates adjacent bit lines from each other. The materials of the bit line protection layer 14 and the bit line isolation layer 8 are not particularly limited. For example, the material of the bit line protection layer 14 may include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and silicon carbonitride, or combinations thereof. The material of the bit line isolation layer 8 may include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and silicon carbonitride, or combinations thereof. However, the materials of the bit line separation layer 8 and the bit line protection layer 14 must be different. For example, the bit line protection layer 14 may be silicon nitride, and the bit line separation layer may be silicon oxide. This allows the bit line separation layer 8 to be etched using a self-alignment method, with the bit line protection layer 14 acting as a mask. separation Layer 8 can be selectively etched, thereby reducing the difficulty of the process and saving costs.

[0040] Continuing to refer to Figures 2 and 3c, in some embodiments, the bit line 3 and the shield line 16 may each be a single layer or multiple layers. For example, in Figure 3c, the bit line 3 includes a first bit line material layer 301 and a second bit line material layer 302, and the positional relationship between the first bit line material layer 301 and the second bit line material layer 302 is not particularly limited. As an example, the first bit line material layer 301 and the second bit line material layer 302 can employ structures such as lamination, encirclement, and partial encirclement. The shield line 16 may include a first shield line material layer 1601 and a second shield line material layer 1602, and the positional relationship between the first shield line material layer 1601 and the second shield line material layer 1602 is not particularly limited. As an example, the first shield line material layer 1601 and the second shield line material layer 1602 can employ structures such as lamination, encirclement, and partial encirclement. The materials of the bit wire 3 and the shield wire 16 are not particularly limited. For example, the material of the bit wire 3 may include, for instance, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the bit wire 3 may include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or a combination thereof. The material of the shield wire 16 may include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the shield wire 16 may include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof. Since the bit wire 3 and the shield wire 16 contain at least one metallic material layer, the resistance of the bit wire 3 and the shield wire 16 can be reduced, improving device performance.

[0041] Continuing to refer to Figure 2, in some embodiments, the semiconductor structure may include a DC bias power supply (DC bias), and the DC bias and the shield wire 16 are connected via a connector (not shown) to supply a stable voltage to the shield wire 16, causing the shield wire 16 to form a conductive barrier, thereby reducing or eliminating the impact on the other bit wire when one of two adjacent bit wires 3 is powered or the power supply is interrupted.

[0042] Referring to Figure 3b, in some embodiments, at least a portion of the shield wire 16 and the bit wire isolation layer 8 are not in complete contact, and a gap 17 exists between the shield wire 16 and the bit wire isolation layer 8, and the relative position of the gap 17 with respect to the shield wire 16 and the bit wire isolation layer 8 is not particularly limited. For example, the gap 17 may be located at the bottom of the shield wire, on one side wall, or partially surrounding the shield wire, and the size and shape of the gap 17 are not particularly limited. For example, the gap may be spherical, teardrop-shaped, short tube-shaped, ellipsoidal, elongated, or other suitable shape. Since the dielectric constant of air is 1.001 and close to the dielectric constant of vacuum, both the gap 17 and the bit wire isolation layer 8 exert a low dielectric constant effect, lowering the overall dielectric constant, thereby reducing parasitic capacitance and avoiding capacitive coupling effects between bit wires 3 and adjacent bit wires 3, thereby reducing the influence of parasitic capacitance on the device's performance parameters.

[0043] Referring to Figure 3d, in some embodiments, the cross-sectional shape of the shield wire 16 perpendicular to the first direction may be irregular, for example, conical, elongated, elliptical, star-shaped, or other suitable shape. The shield wire is formed in the bit wire separation layer 8, and the size of the shield wire 16 is influenced by the material of the bit wire separation layer 8 and the etching capability of the equipment. The irregular structure of the shield wire 16 can expand the process window and reduce manufacturing costs.

[0044] Referring to Figure 3e, in some embodiments, a shield wire barrier layer 18 can be provided above the shield wire 16, which can cover the shield wire 16 to protect it from damage in subsequent processes. The material of the shield wire barrier layer 18 is not limited and may be the same as or different from the material of the bit wire protection layer 14.

[0045] Continuing to refer to Figures 2 and 3a-3e, in some embodiments, the semiconductor structure further includes word lines 2, memory contacts 9 at one end of the active pillar, a memory structure 11, and subsequent wiring and protective layers (not shown) located on the memory structure 11. Specifically, the word lines 2 extend along a second direction and are arranged in a first direction, surrounding the active pillar 4 and controlling the charge transfer of the active pillar 4 on one, both, or three sides of the active pillar. The material of the word lines is not particularly limited, and as an example, the material of the word lines 2 may include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, Word line 2 may include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof.

[0046] Memory contact 9 is the bit line contact of the active pillar 4. structure It is located at one end away from 10 and connects the active pillar 4 and the memory structure 11. The material of the memory contact 9 is not particularly limited, and as an example, the material of the memory contact 9 may include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof, which can reduce the contact resistance between the active pillar 4 and the memory structure 11.

[0047] The memory structure 11 may be a capacitor structure including an upper electrode plate and a lower electrode plate, and a high-k dielectric material located between the upper electrode plate and the lower electrode plate, or it may be a variable resistance memory structure that switches between two resistance states by an electric pulse applied to the memory element. For example, the variable resistance memory structure may include a phase change material whose crystalline state changes depending on the amount of current, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0048] In another aspect, the present invention further provides a method for manufacturing a semiconductor structure according to several embodiments. To more clearly illustrate the method for manufacturing a semiconductor structure in some embodiments of the present invention, some embodiments of the present invention can be understood below by referring to Figures 1 to 3.

[0049] Figures 4a to 4l show intermediate steps of a method for manufacturing a semiconductor memory device according to several embodiments.

[0050] Referring to Figure 4a, a substrate 1 is provided, which has a first surface and a second surface facing each other in a third direction (for example, the Z direction), and an initial bit line separation trench 601 is formed by patterning etching on the first surface.

[0051] Specifically, in some embodiments, the material of the substrate 1 is not particularly limited. For example, the material of the substrate 1 may include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III / V or II / VI semiconductor materials.

[0052] In some embodiments, forming the initial bit line isolation trench 601 by patterning etching may include forming a mask layer on the first surface of the substrate 1, wherein the mask layer comprises one, two, or more material layers, depositing a photoresist layer, and etching the mask layer and the substrate 1 after exposure and development to form the initial bit line isolation trench 601. The etching method can be dry etching, wet etching, or a combination of both, and is not particularly limited thereto. Referring to Figures 2 and 3a, one row of active pillars 4 may be connected to one row of bit lines 3, or two adjacent rows of active pillars 4 may share one row of bit lines 3. By having two adjacent rows of active pillars 4 share one bit line in this way, the space between adjacent bit lines can be reduced, thereby reducing the device volume, making the internal layout of the semiconductor structure more rational, and thereby effectively improving the memory density of the semiconductor structure. In this embodiment, an example is adopted in which two rows of active pillars 4 share one bit line 3, and the initial bit line separation trenches 601 that are formed are spaced twice as far apart, that is, between adjacent initial bit line separation trenches 601 interval This corresponds to a distance of twice the active pillar 4 and one bit line isolation trench 6, which allows for an expansion of the process window and improves the stability of device performance.

[0053] Referring to Figure 4b, in some embodiments, the mask layer that was not removed by etching is modified, and its size is bitten. separationThe width of the trench 6 is adjusted to match the width of the exposed unetched substrate, or the width of the exposed unetched substrate is adjusted to match the width of the active pillar 4. The specific width is not limited and can be set according to process requirements, for example, it can be any width between 10 nm and 40 nm. A sidewall protection layer 7 is deposited in the initial bit line separation trench 601 and on the first surface of the substrate and on the surface of the mask layer that was not etched off on the first surface of the substrate. The sidewall protection layer 7 protects the surface of the first surface of the substrate and the surface of the mask layer that was not etched off on the first surface of the substrate from being damaged in subsequent process steps. The sidewall protection layer 7 is etched to open the sidewall protection layer at the bottom of the initial bit line separation trench 601, and then the first bit line separation trench 602 is formed using co-directional etching. Co-directional etching can be dry etching, wet etching, or a mixture of both, and is not particularly limited thereto. Because etching in the same direction was used, the width of the first bit line separation trench 602 in the second direction was greater than the width of the initial bit line separation trench 601 in the second direction, and a portion of the substrate on both sides of the first bit line separation trench 602 was removed by etching.

[0054] Referring to Figure 4c, in some embodiments, insulating material is filled into the initial bit line separation trench 601 and the first bit line separation trench 602, and a planarization process is performed to expose the mask layer that has not been removed by etching. Specifically, in some embodiments, the insulating material may include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and silicon carbonitride, or a combination thereof, and the material of the insulating material is different from the material of the mask layer. The deposition method may include, but is not limited to, chemical vapor deposition, fluid chemical vapor deposition, atomic layer deposition, spin coating, and high-strength deposition, or a combination thereof. The unremoved mask layer is selectively etched, the materials of the mask layer and the bit line separation layer 8 are different, and etching can be done by a self-alignment method without using a photomask, the etching method may be dry etching, wet etching or a mixture of the two, thereby modifying the mask layer and matching its size to the bit line separation trench 6, and the pattern of the second bit line separation trench 603 is formed by removing the mask layer.

[0055] Referring to Figure 4d, in some embodiments, the second bit line isolation trench 603 is formed based on the pattern of the second bit line isolation trench 603 formed in the above steps, and the second bit line isolation trench 603 extends along a first direction and is located between adjacent first bit line isolation trenches 602, and is spaced apart from the first bit line isolation trenches 602 in a second direction. Because the first bit line isolation trenches 602 and the second bit line isolation trenches 603 are spaced apart and formed in steps, when manufacturing the first bit line isolation trenches 602 and the second bit line isolation trenches 603 individually, the distance between adjacent bit line isolation trenches 602 is increased, the process window is increased, and the stability of the device is improved.

[0056] Referring to Figure 4e, in some embodiments, a bit line contact is located at the bottom of the second bit line separation trench 603. structure10 is formed, memory contact 9 is formed at the top of the active pillar, bit line contact structure 10 is located at the bottom of the second bit line separation trench 603 and is connected to the substrates on both sides, and in the second direction it is in contact with the adjacent first bit line separation trench 602. Specifically, a sidewall protective layer is formed on the surface of the second bit line separation trench 603 and the substrate to prevent subsequent processes from damaging or affecting the substrate, the protective layer on the bottom of the second bit line separation trench 603 and the substrate surface is removed by etching to expose the substrate, and bit line contact is made by an appropriate method such as depositing and diffusing a high-concentration doping material by ion implantation, or depositing a metallic material to carry out a metal silicide reaction. structure 10 and memory contact 9 are formed, and bit line contact structure 10 and the memory contact 9 may be formed in stages or simultaneously, and there are no particular limitations thereon. The material of the memory contact 9 is not particularly limited, and as an example, the material of the memory contact 9 may include at least one of the following: doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof. Bit wire contact structure The 10 materials are not particularly limited; for example, bit wire contacts. structure The 10 materials may include at least one of the following: doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof.

[0057] Referring to Figure 4f, in some embodiments, an insulating material is filled into the second bit line separation trench 603 to form a bit line separation layer 8, and a planarization process is performed to separate the bit lines. layer Number 8 extends along the first direction and is arranged at intervals along the second direction.

[0058] Referring to Figures 1b and 4g, in some embodiments, a word line isolation trench 5 is formed by patterning etching on the first surface of the substrate, and an active pillar 4 is formed in the word line isolation trench 5 and the bit line isolation trench 6. Word lines 2 are formed within the word line isolation trench 5, and the word lines 2 extend along a second direction and are arranged in a first direction, and the word lines surround the active pillar 4 and are located on one side, both sides or three sides of the active pillar, thereby controlling the charge transfer of the active pillar 4. The material of the word lines is not particularly limited, and as an example, the material of the word lines 2 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, Word line 2 may include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof.

[0059] A memory structure 11 is formed on the memory contact 9, and subsequent wiring is formed on the memory structure 11 (not shown). The memory structure 11 may be a capacitor structure consisting of an upper electrode plate, a lower electrode plate, and a high-k dielectric material located between the upper and lower electrode plates, or it may be a variable resistance memory structure that can be switched between two resistance states by an electric pulse applied to the memory element. For example, the variable resistance memory structure may include a phase change material whose crystalline state changes according to the amount of current, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0060] Referring to Figure 4h, in some embodiments, the substrate is inverted, and the second surface of the substrate is thinned by a polishing process to make the bit line separation layer 8 an etching stop layer.

[0061] Referring to Figure 4i, in some embodiments, the bit line separation layer 8 and the substrate material are different, and the substrate material can be removed by selective etching using a self-alignment process to form the bit line trench 12. The self-alignment process can reduce the number of exposures and thus reduce process costs.

[0062] Referring to Figure 4j, in some embodiments, a bit wire material layer 13 is deposited in a bit wire trench 12. The material of the bit wire material is not particularly limited, and as an example, the bit wire material layer 13 may include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof.

[0063] Referring to Figure 4k, in some embodiments, the bit wire material layer 13 is etched back to form the bit wire 3, a bit wire protection layer 14 is formed on the bit wire 3, and a planarization treatment is performed on the bit wire protection layer 14 using a polishing process. Specifically, the bit wire 3 is formed by removing a portion of the bit wire material layer 13 by etching using a selective etching method so that the bit wire material layer 13 is formed only within the bit wire trench 12. Dry etching may be used, wet etching may be used, or a mixture of the two may be used. The bit wire protection layer 14 is deposited on the bit wire 3, and the material of the bit wire protection layer 14 may include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and silicon carbonitride, or combinations thereof, and the material of the bit wire protection layer 14 is different from the material of the bit wire separation layer 8.

[0064] Referring to Figure 4l, in some embodiments, the bit line isolation layer 8 is etched to form a shield line trench 15 in the bit line isolation layer 8. Specifically, because the bit line isolation layer 8 and the bit line protection layer 14 are made of different materials, a portion of the bit line isolation layer 8 can be removed by etching using a self-aligned etching method to form a shield line trench 15. Dry etching may be used, wet etching may be used, or a mixture of the two may be used. In some embodiments, a trench of a certain depth is first formed using dry etching, and then wet etching is performed in the same direction at the bottom of the trench to increase the width of the trench bottom and form trenches of different shapes, thereby preventing disconnection due to the trench bottom being too small to fill with shield line material. By using a self-aligned etching process, the number of photolithography steps is reduced, manufacturing costs are lowered, and device stability is improved.

[0065] As can be seen from the steps above, the wider the bit line isolation layer 8 in the second direction, the larger the process window of the shield line trench 15, and the greater the depth of the shield line trench 15 in the third direction. Since the bottom of the shield line trench 15 is lower than the lowest plane of the bit line 3 in the third direction, the subsequently formed bit line shield line 16 can protect the bit line 3 from signal interference from adjacent bit lines. In some embodiments, the bottom of the shield line trench 15 is the bit line contact. structure By lowering the height below the lowest plane in the third direction of 10, the stability of the device can be improved. The shape of the shield wire trench 15 is not particularly limited, and as an example, the cross-sectional shape of the shield wire trench 15 in the second direction may be conical, elongated, elliptical, star-shaped, or other suitable shape.

[0066] Continuing to refer to Figures 2 and 3a to 3e, a conductive material is deposited in the shield wire trench 15 to form a shield wire 16. In some embodiments, the shield wire 16 may consist of one layer or multiple layers. For example, in Figure 3c, the shield wire 16 may include a first shield wire material layer 1601 and a second shield wire material layer 1602. The positional relationship between the first shield wire material layer 1601 and the second shield wire material layer 1602 is not particularly limited. As an example, the first shield wire material layer 1601 and the second shield wire material layer 1602 can employ structures such as lamination, encirclement, and semi-encirclement. The material of the shield wire 16 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof. For example, the shield wire 16 may include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof. The shield wire 16 includes at least one metallic material layer, which can reduce the resistance of the shield wire 16 and improve device performance.

[0067] Continuing to refer to Figure 3b, in some embodiments, at least a portion of the shield wire 16 and the bit wire isolation layer 8 are not in complete contact, and there is a gap 17 between the shield wire 16 and the bit wire isolation layer 8. The relative position of the gap 17 between the shield wire 16 and the bit wire isolation layer 8 is not particularly limited. For example, the gap 17 may be located at the bottom of the shield wire, on one side wall, or partially surrounding the shield wire. The size and shape of the gap 17 are also not particularly limited. For example, the gap may be spherical, teardrop-shaped, short tube-shaped, ellipsoidal, elongated, or other suitable shape. Since the dielectric constant of air is 1.001, which is close to the dielectric constant of vacuum, the gap 17 and the bit wire isolation layer 8 together exert a low dielectric constant effect, lowering the overall dielectric constant. This reduces parasitic capacitance, avoids the generation of capacitive coupling effects between bit wires 3 and adjacent bit wires 3, and reduces the influence of parasitic capacitance on the device's performance parameters.

[0068] Continuing to refer to Figure 3d, in some embodiments, the cross-sectional shape of the shield wire 16 in the third direction may be an irregular structure, for example, conical, elongated, elliptical, star-shaped, or other suitable shape. The shield wire is formed in the bit wire separation layer 8, and the size of the shield wire 16 is affected by the material of the bit wire separation layer 8 and the etching capability of the equipment. By making the shield wire 16 an irregular structure, the process window can be enlarged and the manufacturing process cost can be reduced.

[0069] Continuing to refer to Figure 3e, in some embodiments, a shield wire barrier layer 18 can be provided on top of the shield wire 16, which covers the shield wire 16 and protects it from damage in subsequent processes, and the material of the shield wire barrier layer 18 is not limited to that of the bit wire protection layer 14 and may be the same as or different from that of the bit wire protection layer 14.

[0070] Continuing to refer to Figure 2, in some embodiments, the width D1 of the shield wire 16 in the third direction (e.g., the Z direction) is greater than or equal to the width D2 of the bit line 3 in the third direction (e.g., the Z direction), and the width D1 of the shield wire 16 in the third direction (e.g., the Z direction) must exceed the width D2 of the bit line 3 in the third direction (e.g., the Z direction). Optionally, the width D1 of the shield wire 16 in the third direction (e.g., the Z direction) must exceed the sum of the widths of the bit line 3 and the bit line contact structure 10 in the third direction (e.g., the Z direction). In this way, the shield wire 16 can completely shield the coupling effect between adjacent bit lines 3 and improve the performance of the device.

[0071] Continuing to refer to Figure 2, in some embodiments, the semiconductor structure may include a DC bias power supply (DC bias), the DC bias and the shield wire 16 are connected via a connector (not shown), and by applying a stable voltage to the shield wire 16, a conductive barrier is formed on the shield wire 16, thereby reducing or eliminating the impact on the other when power is supplied to or interrupted on one of two adjacent bit lines 3.

[0072] Figures 5a to 5f show intermediate steps in a method for manufacturing a semiconductor memory device according to several other embodiments. For simplicity of explanation, parts that overlap with those described with reference to Figures 4a to 4l are summarized or omitted. For reference, Figure 5a shows the intermediate steps following Figure 4d.

[0073] Referring to Figure 5a, in some embodiments, the second bit line separation trench 603 is directly filled, and the material used to fill the second bit line separation trench 603 is not particularly limited and may be the same as or different from the material used to fill the first bit line separation trench 602. Planarization is performed to expose or partially fill the first surface of the substrate 1 to expose the tops of the active pillars 4, and memory contacts 9 are formed at the tops of the active pillars. Specifically, the memory contacts 9 are formed by appropriate methods such as depositing and diffusing a high-concentration doping material by ion implantation, or depositing a metallic material and performing a metal silicide reaction. The material of the memory contacts 9 is not particularly limited, and as an example, the material of the memory contacts 9 may include at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof.

[0074] Referring to Figures 1b and 5b, in some embodiments, word line isolation trenches 5 are formed by patterning etching on the first surface of the substrate, and active pillars 4 are formed in the word line isolation trenches 5 and bit line isolation trenches 6. Word lines 2 are formed in the word line isolation trenches, and the word lines 2 extend along a second direction and are arranged in a first direction, and the word lines surround the active pillars 4 and are located on one side, both sides or three sides of the active pillars, thereby controlling the charge transfer of the active pillars 4. The material of the word lines is not particularly limited, and as an example, the material of word lines 2 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, Word line 2 may include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof.

[0075] A memory structure 11 is formed on the memory contact 9, and subsequent wiring (not shown) is formed on the memory structure 11. The memory structure 11 may be a capacitor structure including an upper electrode plate and a lower electrode plate, and a high-k dielectric material located between the upper electrode plate and the lower electrode plate, or it may be a variable resistance memory structure that switches between two resistance states by an electric pulse applied to the memory element. For example, the variable resistance memory structure may include a phase change material whose crystalline state changes according to the amount of current, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0076] Referring to Figures 5c and 5d, in some embodiments, the substrate is inverted, the second surface of substrate 1 is thinned, a planarization process is performed, and the first bit line separation layer 8 is used as the etching stop layer.

[0077] Referring to Figure 5e, in some embodiments, the bit line separation layer 8 and the substrate material are different, and the substrate material can be removed by selective etching using a self-alignment process to form the bit line trench 12. The self-alignment process can reduce the number of exposures and thus reduce process costs.

[0078] Referring to Figure 5f, in some embodiments, a bit wire contact is located at the bottom of the bit wire trench 12. structure 10 is formed, and bit wire contact is made by appropriate methods such as depositing and diffusing a high-concentration doping material by ion implantation, or depositing a metallic material and carrying out a metal silicide reaction. structure Forms 10, bit wire contact structure The 10 materials are not particularly limited; for example, bit wire contacts. structure The 10 materials may include at least one of the following: doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, and combinations thereof.

[0079] Next, the bit line 3 and shield line 16 are formed with reference to Figures 4j to 4l. In this way, the semiconductor memory device described with reference to Figures 2 and 3a to 3e can be manufactured.

[0080] It should be noted that the methods for manufacturing semiconductor structures provided in the embodiments of this application can all be used to manufacture the corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structural embodiments can be interchanged and supplemented with each other without contradiction, allowing those skilled in the art to grasp the technical content of this application.

[0081] The various technical features in the above embodiments can be combined in any way, and for the sake of brevity, not all possible combinations of the technical features in the embodiments described above are described. However, as long as there is no inconsistency between these combinations of technical features, they should all be considered to fall within the scope described herein.

[0082] The above embodiments represent only a few embodiments of the present application, and while the descriptions are specific and detailed, they should not be understood as limitations on the scope of the patent of this application. Those skilled in the art will note that various modifications and changes can be made without departing from the spirit of this application, and these are also included within the scope of protection. Therefore, the scope of protection of this application should be based on the attached claims. [Explanation of Symbols]

[0083] 1 circuit board 2 Word lines 3-bit line 4 Active Pillars 5 Word Line Separation Trench 6-bit line isolation trench 601 Initial bit line isolation trench 602 First bit line isolation trench 603 Second bit line isolation trench 7. Sidewall protective layer 8-bit line isolation layer 9 Memory Contacts 10-bit line contact structure 11. Memory Structure 12-bit wire trench 13-bit wire material layer 301-bit line, first material layer 302-bit line second material layer 14-bit line protection layer 15 Shielded wire trench 16 Shielded wire 1601 Shielding wire first material layer 1602 Shielding wire second material layer 17 gaps 18 Shielded wire barrier layer

Claims

1. It is a semiconductor structure, Active pillars (4) arranged in an array in a first direction and a second direction, wherein the first direction intersects with the second direction, Bit lines (2) extending in a first direction and arranged at intervals in a second direction, wherein the bit lines (2) are connected to active pillars (4) arranged along the first direction, A shield line (16) is located between two adjacent bit lines (2), extends in a first direction, and is arranged alternately with the bit lines (2) in a second direction. A semiconductor structure comprising: a bit line contact structure (10) located between the bit line (2) and the active pillar (4), connecting the bit line (2) and the active pillar (4), wherein the width of the bit line contact structure (10) in the second direction is smaller than the width of the bit line (2) and the active pillar (4) in the second direction.

2. The bit line contact structure (10) is connected to two adjacent active pillars (4) in the second direction. The semiconductor structure according to claim 1.

3. The width of the shield wire (16) in the third direction is greater than or equal to the width of the bit wire (2) in the third direction, and the third direction intersects with the first direction and the second direction. The semiconductor structure according to claim 1 or 2.

4. The width of the bit line (2) in the second direction decreases as the bit line (2) extends toward the bit line contact structure (10). The semiconductor structure according to claim 3.

5. The aforementioned semiconductor structure further, The side of the bit line (2) away from the bit line contact structure (10) The bit line protection layer (14) located at, A bit line isolation layer (8) located between two adjacent bit lines (2), wherein the shield line (16) is located within the bit line isolation layer (8), and comprises the bit line isolation layer (8), The materials of the bit line protection layer (14) and the bit line separation layer (8) are different. The semiconductor structure according to any one of claims 1 to 3.

6. The bit wire (2) comprises at least one layer of metal material, The shield wire (16) includes at least one layer of metal material. The semiconductor structure according to any one of claims 1 to 3.

7. The aforementioned semiconductor structure further, The shield wire barrier layer (18) is provided, and the shield wire barrier layer (18) covers the shield wire (16). The semiconductor structure according to any one of claims 4 to 6.

8. A gap (17) exists between the bit line separation layer (8) and the shield wire (16). The semiconductor structure according to any one of claims 1 to 7.

9. The cross-sectional shape of the shield wire (16) perpendicular to the first direction is conical, elongated, elliptical, star-shaped, or other suitable shape. The semiconductor structure according to any one of claims 1 to 8.

10. The aforementioned semiconductor structure further, Word lines (2) extending in the second direction and spaced apart in the first direction, wherein the word lines (2) are connected to the active pillar (4) in the second direction, The system includes a memory structure (11) connected to the active pillar (4) and located at one end of the active pillar (4) away from the bit line (2), The semiconductor structure according to any one of claims 1 to 9.

11. A method for manufacturing a semiconductor structure, The method involves forming an active pillar (4), wherein the active pillar (4) is arranged in an array in a first direction and a second direction, and the first direction intersects the second direction. The method involves forming a bit line (2), wherein the bit line (2) extends in a first direction, is arranged at intervals in a second direction, and is connected to active pillars (4) arranged along the first direction. The shielding wire (16) is formed such that it is located between two adjacent bit lines (2), extends in the first direction, and is arranged alternately with the bit lines (2) in the second direction. A method for manufacturing a semiconductor structure, comprising forming a bit line contact structure (10), wherein the bit line contact structure (10) connects the bit line (2) and the active pillar (4), and the width of the bit line contact structure (10) in the second direction is smaller than the width of the bit line (2) and the active pillar (4) in the second direction.

12. Forming the aforementioned bit line (2) is The present invention provides a substrate (1) wherein the substrate (1) has a first surface and a second surface in a third direction, and the third direction intersects the first direction and the second direction. The first surface is formed by patterning etching, wherein the size of the bottom of the bit line separation trench (6) is larger than the size of the top of the bit line separation trench (6), and the bit line separation trench (6) extends along the first direction and is arranged at intervals in the second direction. The bit line separation trench (6) is filled to form a bit line separation layer (8), The second surface is polished to expose the bit line separation layer (8), and the substrate is etched using the bit line separation layer (8) as a mask to form a bit line trench (12). The bit wire (2) is formed by filling the bit wire trench (12) with at least one layer of metal material, The method involves forming a bit line protection layer (14) on the bit line (2), wherein the materials of the bit line protection layer (14) and the bit line separation layer (8) are different. A method for manufacturing a semiconductor structure according to claim 11.

13. Forming the aforementioned shield wire (16) The method involves etching the bit line separation layer (8) on the second surface using the bit line protection layer (14) as a mask layer to form a shield line trench (15), wherein the depth of the shield line trench (15) is greater than or equal to the depth of the bit line trench (12). This includes filling the shield wire trench (15) with at least one layer of metal material to form the shield wire (16), A method for manufacturing a semiconductor structure according to claim 11 or 12.

14. The bit wire contact structure (10) includes a metal silicide, and the formation of the metal silicide is A layer of metal material is deposited at the bottom of the bit wire trench (12), and heat treatment is performed to form a metal silicide, or This includes depositing a metal material layer at the bottom of the bit wire separation trench (6) and performing heat treatment to form a metal silicide. A method for manufacturing a semiconductor structure according to any one of claims 11 to 13.

15. After filling the bit line separation trench (6) and forming the bit line separation layer (8), the method for manufacturing the semiconductor structure is as follows: The method further includes forming a word line separation trench (5) by patterning etching on the first surface, wherein the depth of the word line separation trench (5) is less than the depth of the bit line separation trench (6), the bit line separation trench (6) extends along the second direction and is spaced apart in the first direction, and the active pillar (4) is formed by the word line separation trench (5) and the bit line separation trench (6). After forming the active pillar (4), the method for manufacturing the semiconductor structure is as follows: The method involves forming a word line (2) within the word line separation trench (5), wherein the word line (2) extends in the second direction, is spaced apart in the first direction, and is connected to the active pillar (4) in the second direction. The further includes forming a memory structure (11) at one end of the active pillar (4) away from the bit line (2), A method for manufacturing a semiconductor structure according to claim 12.

Images