Low-resistance stepped rivet contacts using metal-to-metal strap connections

Abstract

Methods, systems, and devices for low-resistance stepped rivet contacts using intermetallic strap connections are described. The described techniques provide the use of metallic materials that adhere to dielectric materials when deposited via chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes and connect to word line contacts. For example, a strap can be formed between a layer of conductive material and a word line contact that at least partially penetrates the stack of layers and is filled with such metallic material. Such techniques can support the connection between the word line contact and the conductive material layer without the use of liner material and can reduce the resistance of the connection.

Description

Technical Field

[0001] Cross-reference This patent application claims priority to U.S. Patent Application No. 18 / 654,618, filed May 3, 2024, by Clampitt et al. and titled "LOW RESISTANCE STAIRCASE RIVET CONTACT USING METAL-TO-METAL STRAP CONNECTION", and U.S. Provisional Patent Application No. 63 / 465,663, filed May 11, 2023, by Clampitt et al. and titled "LOW RESISTANCE STAIRCASE RIVET CONTACT USING METAL-TO-METAL STRAP CONNECTION", each of which has been assigned to the assignee of this application and the entire contents of each are hereby expressly incorporated by reference herein.

[0002] The following relates to one or more systems for memory, including low resistance staircase rivet contacts using metal-to-metal strap connections.

Background Art

[0003] Memory devices are widely used in devices such as computers, user devices, wireless communication devices, cameras, and digital displays to store information. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, often one of the states represented by logic 1 or logic 0. In some embodiments, a single memory cell can support two or more states, and any one of these can be stored. To access the stored information, the memory device can read out (e.g., sense, detect, acquire, identify) the state from the memory cell. To store information, the memory device can write (e.g., program, set, assign) a state to the memory cell.

[0004] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive random-access RAM (RRAM), flash memory, phase-change memory (PCM), self-selecting memory, chalcogenide memory technology, negative OR (NOR) memory devices, and negative AND (NAND) memory devices. Memory cells can be described in terms of volatile or non-volatile configurations. Non-volatile memory cells can maintain their stored logical state for a long time even without an external power supply. Volatile memory cells can lose their stored state when disconnected from an external power supply. [Brief explanation of the drawing]

[0005] [Figure 1] This specification presents an example of a memory array supporting low-resistance stepped rivet contacts using metal-to-metal strap connections as disclosed in this specification. [Figure 2] A top view of an example of a memory array supporting low-resistance stepped rivet contacts using metal-to-metal strap connections as disclosed herein is shown. [Figure 3A] A side view is shown of an example of a memory array supporting low-resistance stepped rivet contacts using metal-to-metal strap connections as disclosed herein. [Figure 3B] A side view is shown of an example of a memory array supporting low-resistance stepped rivet contacts using metal-to-metal strap connections as disclosed herein. [Figure 4] This specification provides an example of a layout that supports low-resistance stepped rivet contacts using metal-to-metal strap connections. [Figure 5] This specification provides an example of a layout that supports low-resistance stepped rivet contacts using metal-to-metal strap connections. [Figure 6]This specification provides an example of a layout that supports low-resistance stepped rivet contacts using metal-to-metal strap connections. [Figure 7] A block diagram of a manufacturing system supporting low-resistance stepped rivet contacts using metal-to-metal strap connections as disclosed herein is shown. [Figure 8] This flowchart shows one or more methods for supporting a low-resistance stepped rivet contact using metal-to-metal strap connections as disclosed herein. [Modes for carrying out the invention]

[0006] A memory device may include one or more arrays of memory cells and support circuits formed on a substrate for manipulating and accessing the memory cells. For example, a memory device may include one or more memory arrays with multiple levels of memory cells, where a level can refer to a plane above the substrate, possibly parallel to the substrate (e.g., horizontal). In some cases, such an architecture may include access circuits formed from one or more levels. For example, a stack of materials may be formed, with dielectric materials and metallic materials (e.g., used for word lines) arranged alternately, and the layers may be accessible through contact cavities (e.g., penetrating the stack of materials). In some examples, metallic material may be filled into the contact cavities during a process step in which portions of dielectric material between word lines or on the upper surface of the material stack may be exposed. Metallic materials (e.g., tungsten) may not be able to adhere directly to the surface of dielectric materials (e.g., oxide materials). If metallic material is deposited directly onto a surface that includes exposed portions of dielectric material, portions of metallic material that do not adhere to the dielectric material may cause contamination of other portions of the material stack. Therefore, a liner material (e.g., TiN) may be deposited in front of the metal material to help it adhere to the material stack. However, the use of such a liner material can increase the resistance between the contact and the word line, as some of the liner material will separate the metal material of the contact from the metal material of the word line.

[0007] To help reduce resistance at wordline contacts, a different metallic material (e.g., molybdenum or another suitable metal) can be deposited in the contact cavity without depositing a liner material (e.g., to adhere to an oxide material). In some cases, a strap may be formed in the layers associated with the contact cavity by converting the sacrificial material to a different sacrificial material, which may support the separate etching of the sacrificial material of the wordline contact and other layers of the strap. For example, a first set of layers corresponding to a metallic material (e.g., layers for wordline contacts) may be formed initially from a sacrificial material (e.g., SiN). In some cases, a cavity may be formed that exposes a layer of sacrificial material, and the exposed sacrificial material may be converted to another sacrificial material (e.g., SiCN). By converting the exposed layer, other layers of the sacrificial material can be etched independently of the exposed layer (e.g., pulled back from the cavity). The exposed layer of the different sacrificial material (e.g., the strap) may then be filled with a different metallic material (e.g., molybdenum) through the contact cavity or slit (e.g., used to excavate and fill the wordline structure). In some cases, such techniques can help reduce resistance between the contact material and the wordline material.

[0008] First, the features of this disclosure will be described in relation to memory devices and arrays with reference to Figures 1, 2, 3A, and 3B. The features of this disclosure will be described in relation to layouts with reference to Figures 4-6. These and other features of this disclosure are further illustrated and described by apparatus diagrams and flowcharts relating to low-resistance stepped rivet contacts using metal-to-metal strap connections, which will be described with reference to Figures 7 and 8.

[0009] Figure 1 shows an example of a memory device 100 supporting a low-resistance stepped rivet contact using a metal-to-metal strap connection according to an example disclosed herein. In some examples, the memory device 100 may be referred to as, or include, a memory die, a memory chip, or an electronic memory device. The memory device 100 may be operable to provide a location for storing information (e.g., physical memory addresses) that may be used by a system (e.g., a host device coupled to the memory device 100 for writing or reading information).

[0010] The memory device 100 may include one or more memory cells 105, each of which may be programmable to store a different logical state (e.g., one programmed from a set of two or more possible states). For example, a memory cell 105 may be configured to store one bit of digital logic at a time (e.g., logic 0 or logic 1). In some examples, a memory cell 105 (e.g., a multilevel memory cell 105) may be operable to store two or more bits of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some examples, the memory cells 105 may be arranged in an array.

[0011] The memory cell 105 can store logical states using configurable materials, which may also be called memory elements, storage elements, memory storage elements, material elements, material memory elements, material parts, or polarity write material parts. The configurable materials of the memory cell 105 may refer to chalcogenide-based storage components. For example, chalcogenide storage elements may be used in other architectures, such as phase-change memory cells, threshold memory cells, or self-selection memory cells.

[0012] In some examples, the material for the memory cell 105 may be a chalcogenide material or other alloy containing selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some examples, a chalcogenide material mainly containing selenium (Se), arsenic (As), and germanium (Ge) may be called a SAG alloy. In some examples, a SAG alloy may also contain silicon (Si), and such a chalcogenide material may be called a SiSAG alloy. In some embodiments, the SAG alloy may contain silicon (Si) or indium (In), or a combination thereof, and such a chalcogenide material may be called a SiSAG alloy or an InSAG alloy, respectively, or a combination thereof. In some embodiments, the chalcogenide material may also contain additional elements such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each of which exists in atomic or molecular form.

[0013] In some examples, memory cell 105 may be an example of a phase-change memory cell. In such examples, the material used in memory cell 105 may be alloy-based (such as the alloys listed above), and it may be operated to change to a different physical state (e.g., undergo a phase change) during the normal operation of memory cell 105. For example, a phase-change memory cell 105 may be associated with a relatively disordered atomic configuration (e.g., a relatively amorphous state) and a relatively ordered atomic configuration (e.g., a relatively crystalline state). The relatively disordered atomic configuration may correspond to a first logical state (e.g., the RESET state, logic 0), and the relatively ordered atomic configuration may correspond to a second logical state (e.g., a different logical state from the first logical state, the SET state, logic 1).

[0014] In some cases (e.g., for threshold selection of memory cell 105, for self-selection of memory cell 105), some or all of the set of logical states supported by memory cell 105 may be associated with the relatively disordered atomic structure of the chalcogenide material (e.g., an amorphous material may be capable of operating to store different logical states). In some cases, the memory element of memory cell 105 may be an example of a self-selecting memory element. In such cases, the material used in memory cell 105 may be alloy-based (e.g., one of the alloys mentioned above) and may be capable of operating to change to different physical states during the normal operation of memory cell 105. For example, a self-selecting or threshold-selecting memory cell 105 may have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state may correspond to a first logical state (e.g., RESET state, logic 0), and the low threshold voltage state may correspond to a second logical state (e.g., a different logical state from the first logical state, SET state, logic 1).

[0015] During a write operation (e.g., a programming operation) of the self-selecting memory cell 105 or threshold-selecting memory cell 105, the polarity used in the write operation may affect the behavior or characteristics of the material of the memory cell 105, such as the threshold characteristics (e.g., threshold voltage) (e.g., determine, set, program). The difference between the threshold characteristics of the material of the memory cell 105 for different logical states stored by the material of the memory cell 105 (e.g., the difference between the threshold voltage when the material is storing logical state "0" and when it is storing logical state "1") may correspond to the read window of the memory cell 105.

[0016] The memory device 100 may include access lines arranged in a pattern, such as a grid-like pattern (e.g., row lines 115, each extending along the exemplary x-direction, and column lines 125, each extending along the exemplary y-direction). The access lines may be formed of one or more conductive materials. In some examples, the row lines 115 or parts thereof may be called word lines. In some examples, the column lines 125 or parts thereof may be called digit lines or bit lines. References to access lines or their analogues are interchangeable without impairing understanding. Memory cells 105 may be located at the intersections of access lines such as the row lines 115 and column lines 125. In some examples, memory cells 105 may also be located along the exemplary z-direction (e.g., addressed), for example, in an implementation of a set of memory cells 105 located at different levels along the exemplary z-direction (e.g., layers, decks, planes, tiers). In some examples, the memory device 100 including memory cells 105 at different levels may be supported by access lines, decoders, and other supporting circuits in configurations different from those illustrated.

[0017] Operations such as read and write operations can be performed on the memory cell 105 by activating access lines, such as one or more row lines 115 or column lines 125, among other access lines associated with the alternative configuration. For example, by activating row lines 115 and column lines 125 (by applying voltage to row lines 115 or column lines 125), the memory cell 105 becomes accessible along their intersection. In various two-dimensional or three-dimensional configurations, the intersection of row lines 115 and column lines 125 in particular, among other access lines, is sometimes referred to as the address of the memory cell 105. In some examples, the access lines may be conductive lines coupled to the memory cell 105 and may be used to perform access operations to the memory cell 105. In some examples, the memory device 100 may perform operations in response to commands that may be issued by a host device coupled to the memory device 100, or commands that may be generated by the memory device 100 (e.g., a local memory controller 150).

[0018] Access to the memory cell 105 may be controlled via one or more decoders, such as a row decoder 110 or a column decoder 120, among several other examples. For example, the row decoder 110 may receive a row address from the local memory controller 150 and activate a row line 115 based on the received row address. The column decoder 120 may receive a column address from the local memory controller 150 and activate a column line 125 based on the received column address.

[0019] The sense component 130 may be operable to detect the state of the memory cell 105 (e.g., material state, resistance state, threshold state) and determine the logical state of the memory cell 105 based on the detected state. The sense component 130 may include one or more sense amplifiers to transform (e.g., amplify) the signals generated by accessing the memory cell 105 (e.g., signals from column line 125 or other access lines). The sense component 130 can compare the signals detected from the memory cell 105 with references 135 (e.g., reference voltage, reference charge, reference current). The detected logical state of the memory cell 105 may be provided as an output of the sense component 130 (e.g., to input / output component 140) and can indicate the detected logical state to another component of the memory device 100 or a host device coupled to the memory device 100.

[0020] The local memory controller 150 can control access to the memory cell 105 via various components (e.g., row decoder 110, column decoder 120, sense component 130, etc.). In some examples, one or more of the row decoder 110, column decoder 120, and sense component 130 may be located in the same place as the local memory controller 150. The local memory controller 150 may be able to receive information (e.g., commands, data) from one or more different controllers (e.g., an external memory controller associated with the host device, another controller associated with the memory device 100), convert that information into a signaling scheme that the memory device 100 can use, perform one or more operations on the memory cell 105, and transmit data from the memory device 100 to the host device based on the performance of one or more operations. The local memory controller 150 can generate row address signals and column address signals to activate access lines such as the target row line 115 and the target column line 125. The local memory controller 150 can also generate and control various signals (e.g., voltage, current) used during the operation of the memory device 100. In general, the amplitude, shape, or duration of the applied signals described herein may be variable and may vary depending on the various operations described when operating the memory device 100.

[0021] The local memory controller 150 may be operable to perform one or more access operations on one or more memory cells 105 of the memory device 100. Examples of access operations may include, in particular, write operations, read operations, refresh operations, precharge operations, or activation operations. In some examples, the access operations may be performed or otherwise conditioned by the local memory controller 150 in response to an access command (e.g., from a host device). The local memory controller 150 may be operable to perform other access operations not described herein or other operations related to the operation of the memory device 100 that are not directly related to accessing the memory cells 105.

[0022] In some cases, the access operation to one or more memory cells 105 may be performed via a word line contact that extends through a stack of materials to contact one or more word lines. For example, the stack of materials may include a staircase structure, where each step of the staircase corresponds to a respective layer of conductive material and a respective contact opening. In some cases, the connection between the contact opening and the conductive material layer may be achieved by depositing a metal material that extends between the layer and the contact opening. However, the metal material may be deposited on a dielectric material, and some metal materials (e.g., tungsten) may flake off or otherwise become non - adherent to the dielectric material. In such cases, a liner material may be deposited between the metal material and the dielectric material, which may increase the resistance between the metal material in the contact opening and the layer of conductive material.

[0023] To support a low - resistance connection between the metal material in the contact opening and the layer of conductive material, a metal material that adheres to the dielectric material without using a liner material can be used. For example, the strip that extends between the contact opening and the conductive layer may be filled with molybdenum or other metal materials that adhere to the dielectric material when deposited by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0024] In addition to the applicability to the memory systems described herein, the technique of low-resistance stepped rivet contacts using an intermetallic strap connection may generally be implemented to improve the performance (including games) of various electronic devices and systems. In some electronic device applications, including games and other high-performance applications, relatively high processing requirements may be associated, while there is also the advantage that the user experience is improved by relatively fast response times. Therefore, it may be desirable to improve the processing speed, shorten the response time, or otherwise improve the performance of the electronic device. By implementing the techniques described herein, it becomes possible to improve the performance of the electronic device by improving the density of the memory array, which may in particular improve the computing power and efficiency.

[0025] The memory device 100 can include any amount of non-transitory computer-readable media that support low-resistance stepped rivet contacts using an intermetallic strap connection. For example, the local memory controller 150, row decoder 110, column decoder 120, sense component 130, or input / output component 140, or any combination thereof, can include or have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) for performing the functions described herein by the memory device 100. For example, such instructions may cause the memory device 100 to perform one or more related functions described herein when executed by the memory device 100.

[0026] Figures 2, 3A, and 3B show an example of a memory array 200 supporting low-resistance stepped rivet contacts using intermetallic strap connections according to an example disclosed herein. The memory array 200 may be included in a memory device 100 and shows an example of a three-dimensional arrangement of memory cells 105 accessible by various conductive structures (e.g., access lines). Figure 2 shows a top section view (e.g., section AA) of the memory array 200 with respect to the section AA shown in Figures 3A and 3B. Figure 3A shows a side section view (e.g., section BB) of the memory array 200 with respect to the section BB shown in Figure 2. Figure 3B shows a side section view (e.g., section CC) of the memory array 200 with respect to the section CC shown in Figure 2. The section views may be examples of section views of the memory array 200 with some aspects (e.g., dielectric structures) omitted for clarity. The elements of the memory array 200 may be described with respect to the x, y, and z directions as shown in Figures 2, 3A, and 3B, respectively. Some elements in Figures 2, 3A, and 3B are labeled with numerical markers, while other corresponding elements, although understood to be the same or similar, are left unlabeled to enhance the visibility and clarity of the shown features. Furthermore, while the exemplary example of the memory array 200 shows several quantities of repeating elements, the techniques following the examples described herein may be applicable to any quantity of such elements, or to the ratio of quantities between one repeating element and another.

[0027] In the example of the memory array 200, the memory cells 105 and word lines 205 may be distributed along the z-direction according to levels 230 (e.g., decks, layers, planes, tiers, as shown in Figures 3A and 3B). In some examples, the z-direction may be orthogonal to the surface of the substrate (not shown) of the memory array 200 beneath the structure shown along the z-direction. While the exemplary example of the memory array 200 includes four levels 230, the memory array 200 according to the examples disclosed herein may include any number of one or more levels 230 along the z-direction (e.g., 64 levels, 128 levels).

[0028] Each word line 205 may be an example of a portion of an access line formed by one or more conductive materials (e.g., one or more metal parts, one or more metal alloy parts). As shown in the figure, the word line 205 may be formed in a comb structure including portions (e.g., projections, teeth) that extend along the y-direction through gaps (e.g., alternating gaps) between pillars 220. For example, as shown, the memory array 200 may contain two word lines 205 for each level 230 (e.g., according to odd word lines 205-a-n1 and even word lines 205-a-n2 for a given level n), and such word lines 205 of the same level 230 may be described as interleaved (e.g., a portion of odd word line 205-a-n1 protruding along the y-direction between portions of even word line 205-a-n2, or vice versa). In some examples, an odd word line 205 (e.g., level 230) may be associated with a first memory cell 105 located on a first side of a particular pillar 220 (e.g., along the x-direction), and an even word line (e.g., the same level 230) may be associated with a second memory cell 105 located on a second side of a particular pillar 220 (e.g., along the x-direction, opposite to the first memory cell 105). Thus, in some examples, a memory cell 105 at a given level 230 may be addressed (e.g., selected, activated) according to either an even word line 205 or an odd word line 205.

[0029] Each pillar 220 may be an example of a portion of an access line (e.g., a conductive pillar portion) formed by one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As shown in the figures, the pillars 220 can be arranged in a two-dimensional array (e.g., an xy-plane) having a first number of pillars 220 along a first direction (e.g., eight pillars, eight rows of pillars along the x direction) and a second number of pillars 220 along a second direction (e.g., five pillars, five rows of pillars along the y direction). While the exemplary memory array 200 includes a two-dimensional arrangement of eight pillars 220 along the x direction and five pillars 220 along the y direction, the memory array 200 according to the examples disclosed herein may include any number of pillars 220 along the x direction and any number of pillars 220 along the y direction. Furthermore, as illustrated, each pillar 220 may be coupled to each set of memory cells 105 (for example, one or more memory cells 105 for every level 230 along the z direction). The pillars 220 may have a cross-sectional area in the xy-plane extending along the z direction. Although the pillars 220 are illustrated with a circular cross-sectional area in the xy-plane, they may be formed in different shapes, such as having an elliptical, square, rectangular, polygonal, or other cross-sectional area in the xy-plane.

[0030] Each memory cell 105 may contain a chalcogenide material. In some examples, memory cell 105 may be an example of a threshold memory cell. Each memory cell 105 may be accessed (e.g., addressed, selected, etc.) according to the intersection of the word line 205 (e.g., level selection, which may include even or odd selection within level 230) and the pillar 220. For example, as illustrated, a selected memory cell 105-a at level 230-a-3 may be accessed according to the intersection of pillar 220-a-43 and word line 205-a-32.

[0031] The memory cell 105 can be accessed (e.g., written to, read from) by applying an access bias (e.g., an access voltage Vaccess, which may be a positive or negative voltage) to the memory cell 105. In some examples, the access bias can be applied by biasing a selected word line 205 with a first voltage (e.g., Vaccess / 2) and a selected pillar 220 with a second voltage (e.g., -Vaccess / 2) having the opposite sign to the first voltage. For the selected memory cell 105-a, the corresponding access bias (e.g., the first voltage) may be applied to word line 205-a-32, and the other unselected word lines 205 may be grounded (e.g., biased to 0V). In some examples, the word line bias may be provided by a word line driver (not shown) coupled to one or more of the word lines 205.

[0032] To apply the corresponding access bias (e.g., a second voltage) to the pillar 220, the pillar 220 can be configured to selectively couple with the sense line 215 (e.g., digit line, column line, access line extending along the y-direction) via each transistor 225 coupled (e.g., physically or electrically) between the pillar 220 and the sense line 215. In some examples, the transistor 225 may be a vertical transistor (e.g., a transistor with a channel along the z-direction, a transistor with a semiconductor junction along the z-direction) and may be formed on the substrate of the memory array 200 using various techniques (e.g., thin-film techniques). In some examples, the selected pillar 220, the selected sense line 215, or a combination thereof may be examples of the selected column line 125 (e.g., bit line) as described with reference to Figure 1.

[0033] Transistor 225 (e.g., the channel portion of transistor 225) may be activated by gate lines 210 (e.g., activation lines, selection lines, row lines, access lines extending along the x-direction) coupled to each gate of a set of transistors 225 (e.g., a set along the x-direction). In other words, each pillar 220 may have a first end (e.g., a lower end in the negative z-direction) configured to couple with an access line (e.g., a sense line 215). In some examples, the gate lines 210, transistors 225, or both may be considered components of the column decoder 120 (e.g., pillar decoder components). In some examples, selection of pillars 220 or sense lines 215 (e.g., bias application), or various combinations thereof, may be supported by the column decoder 120 or sense component 130, or both.

[0034] To apply the corresponding access bias (e.g., -Vaccess / 2) to pillar 220-a-43, the sense line 215-a-4 may be biased with the access bias, and the gate line 210-a-3 may be grounded (e.g., biased to 0V) or biased with an activation voltage. In the example where transistor 225 is an n-type transistor, if the gate line 210-a-3 is biased with a voltage relatively higher than the sense line 215-a-4, transistor 225-a may be activated (e.g., transistor 225-a operates in a conduction state), thereby coupling pillar 220-a-43 with the sense line 215-a-4 and biasing pillar 220-a-43 with the associated access bias. However, transistor 225 may include different channel types or operate according to different bias schemes to support various access operations.

[0035] In some examples, unselected pillars 220 of the memory array 200 may be electrically floating when transistor 225-a is activated, or coupled to another voltage source (e.g., ground, via a high-resistance path, via a leak path) to avoid voltage drift in pillar 220. For example, the ground voltage applied to gate line 210-a-3 may not activate other transistors coupled to gate line 210-a-3. This is because the ground voltage of gate line 210-a-3 may not be greater than the voltage of other sense lines 215 (e.g., which may be biased or floating with the ground voltage). Furthermore, other unselected gate lines 210, including gate line 210-a-5 shown in Figure 3A, may be biased to a voltage equal to or close to the access bias (e.g., -Vaccess / 2, or other negative biases, or biases relatively close to the access bias voltage) to prevent transistors 225 along the unselected gate lines 210 from being activated. Therefore, transistor 225-b coupled to gate line 210-a-5 can be deactivated (for example, operating in a non-conductive state), thereby isolating the voltage of sense line 215-a-4 from pillar 220, particularly pillar 220-a-45.

[0036] In a write operation, the memory cell 105 can be written to by applying a write bias (e.g., Vaccess=Vwrite, which can be a positive or negative voltage) to the memory cell 105. In some cases, the polarity of the write bias may affect (e.g., determine, set, program) the behavior or characteristics of the material of the memory cell 105, such as its threshold voltage. For example, applying a write bias of a first polarity may set the material of the memory cell 105 to a first threshold voltage, which may be associated with storing logical 0. Furthermore, applying a write bias of a second polarity (e.g., the opposite of the first polarity) may set the material of the memory cell to a second threshold voltage, which may be associated with storing logical 1. The difference between the threshold voltages of the material of the memory cell 105 for different logical states stored by the material of the memory cell 105 (e.g., the difference between the threshold voltages when the material is storing logical state "0" and when it is storing logical state "1") may correspond to the read window of the memory cell 105.

[0037] In a read operation, data can be read from memory cell 105 by applying a read bias (e.g., Vaccess = Vread, which can be a positive or negative voltage) to memory cell 105. In some examples, the logical state of memory cell 105 may be evaluated based on whether memory cell 105 reaches a threshold in the presence of the applied read bias. For example, such a read bias may raise memory cell 105 storing a first logical state (e.g., logical 0) to a threshold (e.g., allow current to flow, allow current exceeding the threshold current), and may not raise memory cell 105 storing a second logical state (e.g., logical 1) to a threshold (e.g., may not allow current to flow, may allow current below the threshold current).

[0038] In some examples, such techniques may be extended to memory architectures that support NAND memory cells. For example, memory cells 105 may be connected in a 3D NAND configuration. In such an example, pillar 220 may be an example of a string of memory cells 105, and multiple strings may form a block of memory cells 105 (e.g., a collection of pages of memory cells 105). In some examples, each string may contain a set of memory cells 105 connected in series (e.g., along the z-direction, the drain of one memory cell 105 in a string may be connected to the source of another memory cell 105 in the string). Each memory cell 105 in a string may be associated with a different word line 205, and as a result, the number of word lines 205 in the memory architecture may be equal to the number of memory cells 105 in a string. Thus, a string may contain memory cells 105 from multiple pages, and a page may contain memory cells 105 from multiple strings.

[0039] In some cases, access operations to one or more memory cells 105 may be performed via wordline contacts that extend through a stack of materials to contact one or more wordline gates. For example, the stack of materials may include a staircase structure, where each step of the staircase corresponds to a respective layer of conductive material and a respective contact opening. In some cases, metallic material may be filled into the contact openings during a process step in which a portion of the dielectric material between wordlines or on the upper surface of the material stack may be exposed. In some cases, the connection between the contact opening and the conductive material layer may be achieved by depositing metallic material extending between the layer and the contact opening. However, the metallic material may be deposited on top of the dielectric material, and some metallic materials (e.g., tungsten) may peel off or otherwise cease to adhere directly to the dielectric material. If the metallic material is deposited directly on a surface that includes an exposed portion of the dielectric material, the portion of the metallic material that does not adhere to the dielectric material may cause contamination of other parts of the material stack. In such cases, liner material may be deposited between the metallic material and the dielectric material, increasing the resistance between the metallic material and the conductive material layer at the contact opening.

[0040] To support low-resistance connections between the metal material of the contact opening and the conductive material layer, a metal material that adheres to the dielectric material without the use of a liner material can be used. For example, a strip extending between the contact opening and the conductive layer may be filled with molybdenum or other metal material that adheres to the dielectric material when deposited by a CVD or ALD process.

[0041] Figure 4 shows an example of layout 400 supporting a low-resistance stepped rivet contact using metal-to-metal strap connections according to various aspects of the present disclosure. Layout 400 can illustrate an example of a manufacturing operation of a first set of memory devices supporting metal-to-metal strap connections in a word line contact, as described herein. In some cases, layout 400 may include one or more layers of metal material 405 (e.g., the layers forming the word line 205 as described with reference to Figures 2, 3A, and 3B), one or more layers of dielectric material 410, the top layer of dielectric material 415, dielectric filler 420 (e.g., the same or different material as dielectric material 415 and dielectric material 410), one or more stepped contact pads 425, sacrificial material 430 corresponding to one or more straps of the word line contact, or any combination thereof. It should be noted that layout 400 can support any number of layers, any type of material, and various patterns of material, among other examples. Layout 400 may include a cross-sectional view of a memory device associated with a manufacturing operation of a first set.

[0042] In some examples, the first set of manufacturing operations may include forming a stack of material containing multiple layers. The multiple layers may alternate between a first material (e.g., dielectric material 410) and a second material (e.g., a first sacrificial material which is a dielectric material). In some cases, a stepped structure can be formed by cutting cavities (e.g., a first cavity) into the stack of material up to the layers in contact. For example, the first step 435-a of the step may be formed by cutting a cavity extending to layer 440-a of the material stack, and the second step 435-b of the step may be formed by cutting a cavity extending to layer 440-b of the material stack. In some cases, the cavity formed in each step 435 may expose a portion of the corresponding layer 440 (e.g., a layer of the first sacrificial material). Note that although layout 400 shows two steps of a stepped structure, any number of steps can be formed for any number of corresponding layers.

[0043] In some cases, the first set of manufacturing operations may include converting an exposed layer of a first sacrificial material through a first cavity to a different sacrificial material. For example, an operation may be performed on the exposed layer to convert the first sacrificial material of the exposed layer to a second sacrificial material (which may be sacrificial material 430). For example, the exposed layer of the first sacrificial material (e.g., SiN) may be injected (e.g., with carbon) to form the second sacrificial material (e.g., SiCN) within the portion of the layer 440 exposed by the cavity. In some cases, the first and second sacrificial materials may be etched using different chemicals (e.g., selectively etched). In some cases, after converting the exposed layer to the second sacrificial material (e.g., sacrificial material 430), the cavity may be filled with dielectric filler 420.

[0044] In some cases, the manufacturing operation of the first set may include cutting at least partially a second cavity within the filled first cavity to form a cavity 445 (e.g., a second cavity for forming wordline contacts for each step 435). For example, a cavity 445-a may be formed for step 435-a, and a cavity 445-b may be formed for step 435-b. In some examples, the cavity 445 may extend to the exposed layer of the corresponding step 435 (e.g., a top-down contact). For example, a cavity 445-a may extend to layer 440-a, and a cavity 445-b may extend to layer 440-b (e.g., terminating at the exposed layer).

[0045] In other examples, the cavity 445 may extend through the stack to the corresponding stepped contact pad 425 (e.g., a rivet contact). In such examples, an additional etching step (e.g., after the formation of the second cavity) can be performed to pull back one or more layers of the first sacrificial material that extend to the cavity 445. For example, in step 435-a, one or more layers of the first sacrificial material beneath layer 440-a may be etched to create a cavity between one or more layers and cavity 445-a (e.g., to prevent one or more layers from contacting the word line contact). In some cases, the cavity formed between one or more layers and cavity 445 may be filled with a dielectric material, which may be dielectric material 410 (e.g., the first material of the alternating layers).

[0046] In some examples, the first set of manufacturing instructions may include forming a slit (e.g., a third cavity) to support the extraction of a first sacrificial material from a stack of material. For example, the slit may be formed in a location excluding the first and second cavities (e.g., the space between step 435) and may be cut in a plane parallel or perpendicular to the cross-section shown by layout 400.

[0047] In some examples, the first set of manufacturing instructions may include excavating a first sacrificial material from a stack of material through a slit. For example, the first sacrificial material may be excavated to form a void corresponding to a layer of the first sacrificial material. In some cases, a second sacrificial material (e.g., one related to a contact strap) may not be excavated along with the first sacrificial material (e.g., due to different etching chemical properties).

[0048] In some examples, the first set of manufacturing instructions may include depositing metallic material 405 through slits into voids corresponding to layers of first sacrificial material. For example, depositing metallic material 405 can create word lines between layers of dielectric material 410. As a result of such operation, a material arrangement as shown in layout 400 may be achieved.

[0049] Figure 5 shows an example of layout 500 supporting low-resistance stepped rivet contacts using intermetallic strap connections according to various embodiments of the present disclosure. Layout 500 can illustrate an example of a second set of manufacturing operations for a memory device supporting intermetallic strap connections in wordline contacts, as described herein. In some cases, the second set of manufacturing operations may follow the first set of manufacturing operations described with reference to Figure 4 (for example, applying the second set of manufacturing operations to layout 400 may result in layout 500). Layout 500 may include one or more embodiments of layout 400, e.g., one or more layers of metallic material 405, one or more layers of dielectric material 410, a top layer of dielectric material 415, dielectric filler 420 (e.g., the same or different material as dielectric material 415 and dielectric material 410), stepped contact pads 425, or any combination thereof. It should be noted that layout 500 can support any number of layers, any type of material, and various patterns of material, among other examples. Layout 500 may include a cross-sectional view of a memory device associated with the second set of manufacturing operations.

[0050] Layout 500 may support a stepped structure of a memory device, which may include one or more steps 435 associated with one or more layers of metallic material 405, as illustrated with reference to Figure 4. For example, step 435-a may be associated with layer 440-a, and step 435-b may be associated with layer 440-b. In some cases, cavities 445-a and 445-b may be at least partially cut within steps 435-a and 435-b, respectively, and penetrate the stack to terminate with stepped contact pads 425 (such as rivets) or extend to the corresponding layer 440 (such as top-down contacts), which may be included in the manufacturing procedure of the first set, as illustrated with reference to Figure 4.

[0051] In some cases, a second set of manufacturing instructions may include excavating sacrificial material (e.g., sacrificial material 430 as described with reference to Figure 4) from one or more exposed layers. For example, the portion of layer 440-a overlapping step 435-a may contain sacrificial material, which may be a second sacrificial material (e.g., SiCN) converted from a first sacrificial material (e.g., SiN) by injection (e.g., carbon injection). In some cases, the etching chemical compositions of the first and second sacrificial materials may differ, and they may be etched separately. For example, one or more layers of the metallic material 405 may be initially filled with the first sacrificial material and then excavated separately from the exposed layers of the second sacrificial material. In some cases, the first sacrificial material may be excavated through a slit, which may be formed in a location excluding the step cavity and contact cavity (e.g., the space between steps 435), and may be cut in a plane parallel to or perpendicular to the cross-section shown by layout 500.

[0052] In some cases, a second sacrificial material may be excavated to form a void that connects to the corresponding cavity 445 (e.g., cavity 505-a and cavity 505-b). For example, the second sacrificial material may be excavated through the corresponding cavity 445 (e.g., as shown in layout 500) to form cavity 505-a and cavity 505-b. As another example, the second sacrificial material may be excavated through a slit and may be excavated before depositing the metallic material 505 (e.g., after excavating the first sacrificial material through the slit). For example, the second sacrificial material may be excavated after excavating the first sacrificial material from layer 440-a and before depositing the metallic material 405 in layer 440-a, and the metallic material 405 may be deposited in the exposed portion of layer 440-a (e.g., extending to the cavities 445-a on both sides).

[0053] Figure 6 shows an example of layout 600 supporting a low-resistance stepped rivet contact using intermetallic strap connections according to various embodiments of the present disclosure. Layout 600 can illustrate an example of a third set of manufacturing operations for a memory device supporting intermetallic strap connections in wordline contact, as described herein. In some cases, the third set of manufacturing operations may follow the second set of manufacturing operations described with reference to Figure 5 (for example, applying the third set of manufacturing operations to layout 500 may result in layout 600). Layout 600 may include one or more embodiments of layouts 400 and 500, e.g., one or more layers of metallic material 405 (e.g., the first metallic material), one or more layers of dielectric material 410, the top layer of dielectric material 415, dielectric filler 420 (e.g., the same or different material as dielectric material 415 and dielectric material 410), stepped contact pads 425, or any combination thereof, which may be examples of the corresponding embodiments described with reference to Figures 4 and 5. Furthermore, layout 600 may include a metallic material 605 (e.g., a second metallic material), a metallic material 610 (e.g., a third metallic material), a liner material 615, or any combination thereof. It should be noted that layout 600, in particular among other examples, can support any number of layers, any type of material, and various patterns of material. Layout 600 may include a cross-sectional view of a memory device associated with a third set of manufacturing operations.

[0054] In some cases, the manufacturing operation of a third set may include depositing metallic material 605 to form one or more contacts 620. For example, the metallic material 605 may be deposited in cavities corresponding to contacts 620-a and 620-b (e.g., cavities 445 as described with reference to Figures 4 and 5) and may be deposited using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. In some cases, the contacts 620 may extend through the stack and terminate at corresponding stepped contact pads 425 (e.g., rivet contacts). In other cases, the contacts 620 may extend through the stack and terminate at corresponding layers 425 (e.g., top-down contacts).

[0055] The metallic material 605 may be an example of a metallic material that can be deposited onto a dielectric material (e.g., an oxide material such as the dielectric material 410) using a CVD or ALD process. For example, some metallic materials (e.g., tungsten) may peel off or fail to adhere to the dielectric material 410 when deposited in contact with it. In such cases, a liner material (e.g., TiN) may be deposited between the metallic material and the dielectric material 410. However, such a technique may increase the resistance between the contact 620 and the corresponding layer 440 (e.g., due to the liner separating the direct connection). To reduce the resistance between the contact 620 and the corresponding layer 440, the metallic material 605 may be selected so that it is deposited onto the dielectric material 410 using a CVD or ALD process. For example, the metallic material 605 may be molybdenum (e.g., other metallic materials that can be deposited using a CVD or ALD process and adhere to the dielectric material 410 without the use of a resistance liner).

[0056] In some cases, the metallic material 605 may be in direct contact with the metallic material 405 (for example, to form a word line contact between the contact 620 and the corresponding layer 440). For example, a third set of manufacturing instructions may include filling portions of layer 440 exposed by the step cavity (e.g., a strap of layer 440 spanning the width of the cavity of step 435) using various techniques. In one example, the metallic material 605 may be filled into the strap as shown in layout 600. For example, as part of depositing the metallic material 605 to form contact 620-a and contact contact 620-b, the metallic material 605 may be deposited within each strap (e.g., extending to contact the metallic material 405 of layers 440-a and 440-b). In another example, the metallic material 405 may be filled into the strap. For example, as part of depositing the metallic material 405 through the slit (for example, after excavating a second sacrificial material through the slit, as described with reference to Figure 5), the metallic material 405 may be deposited within a strap of layer 440 (for example, extending to the corresponding contact 620). Such a technique (for example, filling the strap with metallic material 405 or metallic material 605) can reduce the resistance between each contact 620 and the corresponding layer 440.

[0057] In some examples, contact 620 may be filled with metallic material 605 (e.g., contact 655 may not have any other material). Furthermore, or alternatively, contact 620 may also be filled with metallic material 610 (e.g., a plug of metallic material 610 surrounded by metallic material 605), as shown in layout 600. For example, after depositing metallic material 605 within contact 620 (e.g., after covering the surface of contact 620), metallic material 610 may be deposited in the remaining space within contact 620. In some cases, liner material 615 may be deposited within contact 620 and placed between metallic material 605 and metallic material 610, as shown in layout 600. For example, liner material 615 (e.g., TiN) may be deposited after depositing metallic material 605 and before depositing metallic material 610, which can support a low-resistance contact (e.g., because the surface area of ​​liner material 615 is relatively large).

[0058] Figure 7 shows a block diagram 700 of a manufacturing system 720 supporting a low-resistance stepped rivet contact using intermetallic strap connections as described herein. Manufacturing system 720 may be an example of an embodiment of the manufacturing system described with reference to Figures 1 to 6. Manufacturing system 720 or various components thereof may be examples of means for performing various embodiments of the low-resistance stepped rivet contact using intermetallic strap connections as described herein. For example, manufacturing system 720 may include a stack-forming component 725, a cavity-forming component 730, a material-depositing component 735, a material-excavating component 740, an injection component 745, or any combination thereof. Each of these components can communicate with one another directly or indirectly (e.g., via one or more buses).

[0059] The stack forming component 725 may be configured as a means for forming a stack of material comprising a plurality of layers on a substrate, wherein the plurality of layers alternate between a first material and a second material, and the first material is a first dielectric material. The cavity forming component 730 may be configured as a means for forming a first cavity within the material stack, or otherwise may support such a means, the bottom of which exposes one of the plurality of layers of the second material. The material deposition component 735 may be configured as a means for filling the first cavity with the second dielectric material, or can otherwise support such a means. In some examples, the cavity forming component 730 may be configured as a means for forming a second cavity within the material stack, or otherwise may support such a means, the second cavity located in at least partially filled first cavities. In some examples, the cavity forming component 730 may be configured as a means for forming a third cavity within a stack of material, or may otherwise support such a means, the third cavity not comprising the first and second cavities. The material excavation component 740 may be configured as a means for excavating multiple layers of a second material through a third cavity to form voids corresponding to the second material, or may otherwise support such a means. In some examples, the material deposit component 735 may be configured as a means for depositing a first metallic material into multiple layers of voids through a third cavity, or may otherwise support such a means. In some examples, the material deposit component 735 may be configured as a means for depositing a second metallic material through a second cavity, or may otherwise support such a means, the second metallic material in contact with the first metallic material, and deposited using a chemical vapor deposition process or an atomic layer deposition process.

[0060] In some examples, the injection component 745 may be configured as a means of converting an exposed layer of a plurality of layers from a second material to a third material before forming a second cavity, or it may support such a means.

[0061] In some examples, the material excavation component 740 may be configured as a means for excavating a third material from an exposed layer through a third cavity before depositing a first metallic material in a void in a plurality of layers, or may otherwise support such a means, and depositing the first metallic material through the third cavity includes depositing the first metallic material in a void formed by excavating the third material from the exposed layer.

[0062] In some examples, the material excavation component 740 may be configured as a means for excavating a third material from an exposed layer through a second cavity, or may otherwise support such means, and depositing a second metallic material through a second cavity includes depositing the second metallic material in the void formed by excavating the third material from an exposed layer.

[0063] In some examples, the material deposition component 735 may be configured as a means for filling a second cavity with a third metallic material, or it may otherwise support such a means.

[0064] In some examples, the material deposition component 735 may be configured as a means for depositing a fourth material into the second cavity before filling the second cavity with a third metallic material, or may otherwise support such a means, with the fourth material located between the second and third metallic materials.

[0065] In some examples, the second metallic material contains molybdenum.

[0066] Figure 8 is a flowchart illustrating one or more methods 800 supporting low-resistance stepped rivet contacts using metal-to-metal strap connections according to examples disclosed herein. The operation of method 800 may be implemented by a manufacturing system or its components as described herein. For example, the operation of method 800 may be performed by a manufacturing system described with reference to Figures 1 to 7. In some examples, the manufacturing system may control the functional elements of the device to execute a set of instructions for performing the described functions. Additionally or alternatively, a wireless manufacturing system may perform embodiments of the described functions using dedicated hardware.

[0067] In 805, this method may involve forming a stack of materials on a substrate, the stack of materials comprising alternating layers of a first material and a second material, the first material being a first dielectric material. The operation of 805 may be performed according to the examples disclosed herein. In some examples, the operation of 805 may be performed by a stack-forming component 725, as described with reference to Figure 7.

[0068] In 810, this method may include forming a first cavity within a stack of material, the bottom of which exposes one of several layers of a second material. The operation of 810 may be performed according to the examples disclosed herein. In some examples, the operation of 810 may be performed by a cavity-forming component 730, as described with reference to Figure 7.

[0069] In 815, this method may include filling the first cavity with a second dielectric material. The operation of 815 may be performed according to the examples disclosed herein. In some examples, the operation of 815 may be performed by a material deposition component 735, as described with reference to Figure 7.

[0070] In 820, this method may include forming a second cavity within a stack of material, the second cavity being located within at least a partially filled first cavity. The operation of 820 may be performed according to the examples disclosed herein. In some examples, the operation of 820 may be performed by a cavity-forming component 730, as described with reference to Figure 7.

[0071] In 825, this method may include forming a third cavity within a stack of material, the third cavity not comprising the first and second cavities. The operation of 825 may be performed according to the examples disclosed herein. In some examples, the operation of 825 may be performed by a cavity-forming component 730, as described with reference to Figure 7.

[0072] In 830, this method may include excavating multiple layers of the second material through a third cavity to form voids corresponding to the second material. The operation of 830 may be performed according to the examples disclosed herein. In some examples, the operation of 830 may be performed by a material excavation component 740, as described with reference to Figure 7.

[0073] In 835, this method may include depositing a first metallic material in the voids of multiple layers through a third cavity. The operation of 835 may be carried out according to the examples disclosed herein. In some examples, the operation of 835 may be carried out by a material deposition component 735, as described with reference to Figure 7.

[0074] In 840, the method may include depositing a second metallic material through a second cavity, the second metallic material being in contact with the first metallic material, and being deposited using a chemical vapor deposition process or an atomic layer deposition process. The operation of 840 may be carried out according to the examples disclosed herein. In some examples, aspects of the operation of 840 may be carried out by a material deposition component 735, as described with reference to Figure 7.

[0075] In some embodiments, the apparatus described herein may perform methods such as method 800. The apparatus may include mechanisms, circuits, logic, means, or instructions (e.g., a non-temporary computer-readable medium storing instructions executable by a processor), or any combination thereof, for performing the following embodiments of the disclosure.

[0076] Embodiment 1: Forming a stack of material comprising a plurality of layers on a substrate, wherein the plurality of layers consist of alternating first and second materials, and the first material is a first dielectric material; forming the stack; forming a first cavity within the stack of material, wherein the bottom of the first cavity exposes one of the plurality of layers of the second material; forming the stack; filling the first cavity with a second dielectric material; forming a second cavity within the stack of material, wherein the second cavity is at least partially within the filled first cavity; forming the stack; and forming a third cavity within the stack of material, wherein the third A method, apparatus, or non-transient computer-readable medium comprising the operation, features, circuits, logic, means, or instructions for the deposition, which includes the operation, features, circuits, logic, means, or instructions, or any combination thereof, of the following: forming a cavity, which does not include the first cavity and the second cavity; excavating the plurality of layers of the second material through the third cavity to form voids corresponding to the second material; depositing the first metallic material in the voids of the plurality of layers through the third cavity; and depositing the second metallic material through the second cavity, wherein the second metallic material is in contact with the first metallic material and is deposited using a chemical vapor deposition process or an atomic layer deposition process.

[0077] Embodiment 2: The method, apparatus, or non-temporary computer-readable medium according to Embodiment 1, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for converting the exposed layer of the plurality of layers from the second material to the third material before forming the second cavity.

[0078] Embodiment 3: The method, apparatus, or non-temporary computer-readable medium of Embodiment 2, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for excavating, wherein the excavation includes excavating the third material of the exposed layer through a third cavity before depositing the first metallic material in the voids of the plurality of layers, and depositing the first metallic material through the third cavity, wherein the excavation includes depositing the first metallic material in the voids formed by excavating the third material of the exposed layer.

[0079] Embodiment 4: The method, apparatus, or non-temporary computer-readable medium of any embodiment 2 to 3, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for excavating the third material of the exposed layer through the second cavity, and depositing the second metallic material through the second cavity, which includes depositing the second metallic material in the void formed by excavating the third material of the exposed layer.

[0080] Embodiment 5: The method, apparatus, or non-temporary computer-readable medium of any embodiment 1 to 4, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for filling the second cavity with a third dielectric material.

[0081] Embodiment 6: The method, apparatus, or non-temporary computer-readable medium of Embodiment 5, further comprising depositing a fourth material in the second cavity before filling the second cavity with the third metallic material, wherein the fourth material is between the second metallic material and the third metallic material and further comprises operations, features, circuits, logic, means, or instructions, or any combination thereof, for the purpose of the deposit.

[0082] Embodiment 7: The method, apparatus, or non-temporary computer-readable medium according to any one of Embodiments 1 to 6, wherein the second metallic material comprises molybdenum.

[0083] It should be noted that the methods described herein describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and that other embodiments are also possible. Furthermore, two or more parts of the methods may be combined.

[0084] The apparatus is described. Below, an overview of the embodiments of the apparatus described herein is provided.

[0085] Embodiment 8: A stack of materials comprising a plurality of layers, wherein the plurality of layers consist of alternating first materials and second materials, the second materials comprising a first metallic material, the stack of materials comprising a cavity filled at least partially with a third material, the bottom of which is in contact with one of the plurality of layers of the second material, and a contact that at least partially penetrates the stack of materials and at least partially extends into the cavity, the contact comprising a second metallic material in contact with the first metallic material of the layer of the plurality of layers.

[0086] Embodiment 9: The apparatus according to Embodiment 8, wherein the contact is covered with the second metallic material.

[0087] Embodiment 10: The apparatus according to Embodiment 9, wherein the contact is at least partially filled with a third metallic material.

[0088] Embodiment 11: The apparatus according to Embodiment 10, wherein the contact is at least partially filled with a fourth material, the fourth material being located between the third material and the second metallic material.

[0089] Embodiment 12: The apparatus according to any one of Embodiments 8 to 11, wherein the contact extends through each of the multiple layers of the stack of the material.

[0090] Embodiment 13: The apparatus according to any one of Embodiments 8 to 12, wherein the contact partially penetrates the stack of the material and extends to the depth of the layer among the plurality of layers.

[0091] Embodiment 14: The apparatus according to any one of Embodiments 8 to 13, wherein the second metallic material comprises molybdenum.

[0092] Embodiment 15: The apparatus according to any one of Embodiments 8 to 14, wherein the first metal material of the layer among the plurality of layers forms a plurality of word lines, each coupled to each plurality of memory cells.

[0093] The information and signals described herein may be represented using any of a variety of different techniques and methods. For example, signaling data, instructions, commands, information, signals, bits, or symbols that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. In some drawings, signals may be shown as a single signal, but a signal may represent a bus of signals, and a bus may have a variety of bit widths.

[0094] The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to relationships between components that support the flow of signals between them. Components are considered to be in an electronic communication state (or conductive contact state, or connected state, or coupled state) with respect to each other if there is any conductive path between them that can support the flow of signals between them at any time. Conductive paths between components that are in an electronic communication state (or conductive contact state, or connected state, or coupled state) with respect to each other can be open or closed at any time, based on the operation of the device containing the connected components. Conductive paths between connected components may be direct conductive paths between components, or they may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some embodiments, the flow of signals between connected components may be temporarily interrupted by using one or more intermediate components, such as switches or transistors.

[0095] The term "coupling" (for example, "electrically coupled") can refer to a transition from an open-circuit relationship between components, where it is not currently possible for them to communicate signals through conductive paths, to a closed-circuit relationship, where it is possible for them to communicate signals through conductive paths. When a component, such as a controller, couples other components together, that component causes a change that allows signals to flow between the other components through conductive paths that were previously not permitted.

[0096] The term "isolated" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if an open circuit exists between them. For example, two components separated by a switch placed between them are isolated from each other when the switch is open. When a controller isolates two components, the controller makes a change that prevents signals from flowing between the components using conductive paths that previously allowed signals to flow.

[0097] As used herein, the terms “layer” or “level” refer to a layer or sheet of geometric structure (for example, on a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of the surface. For example, a layer or level may be a three-dimensional structure, such as a thin film, where two dimensions are greater than the third. Layers or levels may contain different elements, components, or materials. In some embodiments, a single layer or level may consist of two or more sublayers or sublevels.

[0098] Devices described herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some embodiments, the substrate is a semiconductor wafer. In other embodiments, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenide. Doping may be performed by ion implantation or by any other doping means during the initial formation or growth of the substrate.

[0099] The switching components or transistors discussed herein represent field-effect transistors (FETs) and may include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic elements via a conductive material, such as a metal. The source and drain may be conductive and may include highly doped, e.g., degenerate, semiconductor regions. The source and drain may be separated by a less doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be covered with an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET may result in a conductive channel. When a voltage above the transistor's threshold voltage is applied to the transistor gate, the transistor may enter an "on" or "activated" state. When a voltage lower than the transistor's threshold voltage is applied to the transistor gate, the transistor can enter an "off" or "deactivated" state.

[0100] The descriptions provided herein in relation to the accompanying drawings describe exemplary configurations and do not represent all embodiments that may be practiced or that fall within the claims. The term “exemplary” as used herein means “serving as an example, case, or illustration,” and not “preferred” or “advantageous over other examples.” Embodiments for carrying out the invention include specific details to facilitate understanding of the techniques described. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid ambiguity of the concepts of the embodiments described.

[0101] In the attached diagram, similar components or mechanisms may have the same reference label. Furthermore, various components of the same type may be distinguished by adding a second label after the reference label, followed by a dash, to differentiate similar components. If only the first reference label is used in the specification, the description may apply to any component of similar components having the same first reference label, regardless of the second reference label.

[0102] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If a function is implemented in software executed by a processor, the function may be stored or transmitted as one or more instructions or codes on a computer-readable medium. Other embodiments and representations are also within the scope of this disclosure and the accompanying claims. For example, due to the nature of the software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. The mechanism for implementing the function may also be physically located in various locations, including being distributed so that parts of the function are implemented in different physical locations.

[0103] For example, various exemplary blocks and modules described in connection with the disclosure herein may be implemented or run in general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, a processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented in a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working in conjunction with a DSP core, or any other such configuration).

[0104] Where used herein, including in the claims, “or” in a list of items (e.g., a list of items ending with a phrase such as “at least one of the following” or “one or more of the following”) indicates an inclusive list, for example, the list “at least one of A, B, or C” means A, or B, or C, or AB, or AC, or BC, or ABC (i.e., A and B and C). Also, where used herein, the phrase “based on” should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as “based on condition A” may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, where used herein, the phrase “based on” should be interpreted in the same way as the phrase “based at least partially on.”

[0105] Computer-readable media include both non-temporary computer storage media and communication media, and these include any media that facilitate the transfer of computer programs from one location to another. Non-temporary storage media can be any available media that can be accessed by a general-purpose or dedicated computer. Examples, but not limited to, of non-temporary computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD)ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-temporary media that can be used to transport or store desired program code means in the form of instructions or data structures, and that can be accessed by a general-purpose or dedicated computer, or a general-purpose or dedicated processor. Any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, discs (Disk and Disc) include CDs, laserdiscs, optical discs, digital multipurpose discs (DVDs), floppy disks, and Blu-ray discs, where a disc typically reproduces data magnetically, while a disc reproduces data optically using a laser. Any combination of the above is also included in the scope of computer-readable media.

[0106] The descriptions herein are provided to enable those skilled in the art to create or use this disclosure. Various modifications to this disclosure will be obvious to those skilled in the art, and the general principles defined herein can be applied to other modifications without departing from the scope of this disclosure. Thus, this disclosure should be recognized as having the broadest scope consistent with the principles and new features disclosed herein, and not limited to the examples and designs described herein.

Claims

1. The method involves forming a stack of materials on a substrate, wherein the multiple layers consist of alternating first and second materials, and the first material is a first dielectric material. The method involves forming a first cavity within the stack of the material, wherein the bottom of the first cavity exposes one of the plurality of layers of the second material. Filling the first cavity with the second dielectric material, The method involves forming a second cavity within the stack of the material, wherein the second cavity is at least partially located within the filled first cavity. The method involves forming a third cavity within the stack of the material, wherein the third cavity does not include the first cavity and the second cavity. Through the third cavity, the plurality of layers of the second material are excavated to form voids corresponding to the second material, The first metallic material is deposited in the gaps between the plurality of layers via the third cavity, The deposition of a second metallic material through the second cavity, wherein the second metallic material is in contact with the first metallic material, and is deposited using a chemical vapor deposition process or an atomic layer deposition process. Methods that include...

2. The method according to claim 1, further comprising converting the exposed layer among the plurality of layers from the second material to the third material before forming the second cavity.

3. The method according to claim 2, further comprising excavating the third material of the exposed layer through the third cavity before depositing the first metal material in the voids of the plurality of layers, wherein depositing the first metal material through the third cavity includes depositing the first metal material in the voids formed by excavating the third material of the exposed layer.

4. The method according to claim 2, further comprising excavating the third material of the exposed layer through the second cavity, and depositing the second metallic material through the second cavity, comprising depositing the second metallic material in the void formed by excavating the third material of the exposed layer.

5. The method according to claim 1, further comprising filling the second cavity with a third dielectric material.

6. The method according to claim 5, further comprising depositing a fourth material in the second cavity before filling the second cavity with the third metallic material, wherein the fourth material is located between the second metallic material and the third metallic material.

7. The method according to claim 1, wherein the second metal material comprises molybdenum.

8. A stack of materials comprising multiple layers, wherein the multiple layers consist of alternating first and second materials, the second material comprising a first metallic material, and the stack of materials comprising a cavity filled at least partially with a third material, the bottom of which is in contact with one of the multiple layers of the second material, and the stack of materials comprising the stack of materials, A contact that at least partially penetrates the stack of the material and at least partially extends into the cavity, wherein the contact includes a second metallic material that contacts the first metallic material of the layer among the plurality of layers, A device including a device.

9. The apparatus according to claim 8, wherein the contact is covered with the second metal material.

10. The apparatus according to claim 9, wherein the contact is at least partially filled with a third metallic material.

11. The apparatus according to claim 10, wherein the contact is at least partially filled with a fourth material, the fourth material being located between the third material and the second metallic material.

12. The apparatus according to claim 8, wherein the contact extends through each of the plurality of layers of the stack of the material.

13. The apparatus according to claim 8, wherein the contact partially penetrates the stack of material and extends to the depth of the layer among the plurality of layers.

14. The apparatus according to claim 8, wherein the second metal material contains molybdenum.

15. The apparatus according to claim 8, wherein the first metal material of the layer among the plurality of layers each forms a plurality of word lines coupled to each plurality of memory cells.

16. A stack of materials comprising a plurality of layers comprising a first material and a second material, wherein the second material comprises a first metallic material, and the stack of materials comprises a cavity filled at least partially with a third material, the bottom of which is in contact with one of the plurality of layers of the second material, A contact that at least partially penetrates the stack of the material and at least partially extends into the cavity, wherein the contact includes a second metallic material that contacts the first metallic material of the layer among the plurality of layers, A device including a device.

17. The apparatus according to claim 16, wherein the contact is covered with the second metallic material.

18. The apparatus according to claim 17, wherein the contact is at least partially filled with a third metallic material.

19. The apparatus according to claim 18, wherein the contact is at least partially filled with a fourth material, the fourth material being located between the third material and the second metallic material.

20. The apparatus according to claim 16, wherein the contact extends through each of the plurality of layers of the stack of the material.

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